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charset="utf-8" gpio32 pin group is missed for an7581 SoC. This patch add it. Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC") Signed-off-by: Mikhail Kshevetskiy --- drivers/pinctrl/mediatek/pinctrl-airoha.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/me= diatek/pinctrl-airoha.c index 995ba6175c95..805166223228 100644 --- a/drivers/pinctrl/mediatek/pinctrl-airoha.c +++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c @@ -539,6 +539,7 @@ static const int en7581_gpio28_pins[] =3D { 41 }; static const int en7581_gpio29_pins[] =3D { 42 }; static const int en7581_gpio30_pins[] =3D { 43 }; static const int en7581_gpio31_pins[] =3D { 44 }; +static const int en7581_gpio32_pins[] =3D { 45 }; static const int en7581_gpio33_pins[] =3D { 46 }; static const int en7581_gpio34_pins[] =3D { 47 }; static const int en7581_gpio35_pins[] =3D { 48 }; @@ -623,6 +624,7 @@ static const struct pingroup en7581_pinctrl_groups[] = =3D { PINCTRL_PIN_GROUP("gpio29", en7581_gpio29), PINCTRL_PIN_GROUP("gpio30", en7581_gpio30), PINCTRL_PIN_GROUP("gpio31", en7581_gpio31), + PINCTRL_PIN_GROUP("gpio32", en7581_gpio32), PINCTRL_PIN_GROUP("gpio33", en7581_gpio33), PINCTRL_PIN_GROUP("gpio34", en7581_gpio34), PINCTRL_PIN_GROUP("gpio35", en7581_gpio35), --=20 2.53.0 From nobody Mon Jun 8 05:29:11 2026 Received: from AS8PR04CU009.outbound.protection.outlook.com (mail-westeuropeazon11021083.outbound.protection.outlook.com [52.101.70.83]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1E7441AC45D; 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charset="utf-8" gpio32 pin group is missed for an7583 SoC. This patch add it. Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs") Signed-off-by: Mikhail Kshevetskiy --- drivers/pinctrl/mediatek/pinctrl-airoha.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/me= diatek/pinctrl-airoha.c index 805166223228..c0aed1b60792 100644 --- a/drivers/pinctrl/mediatek/pinctrl-airoha.c +++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c @@ -758,6 +758,7 @@ static const int an7583_gpio28_pins[] =3D { 30 }; static const int an7583_gpio29_pins[] =3D { 31 }; static const int an7583_gpio30_pins[] =3D { 32 }; static const int an7583_gpio31_pins[] =3D { 33 }; +static const int an7583_gpio32_pins[] =3D { 34 }; static const int an7583_gpio33_pins[] =3D { 35 }; static const int an7583_gpio34_pins[] =3D { 36 }; static const int an7583_gpio35_pins[] =3D { 37 }; @@ -836,6 +837,7 @@ static const struct pingroup an7583_pinctrl_groups[] = =3D { PINCTRL_PIN_GROUP("gpio29", an7583_gpio29), PINCTRL_PIN_GROUP("gpio30", an7583_gpio30), PINCTRL_PIN_GROUP("gpio31", an7583_gpio31), + PINCTRL_PIN_GROUP("gpio32", an7583_gpio32), PINCTRL_PIN_GROUP("gpio33", an7583_gpio33), PINCTRL_PIN_GROUP("gpio34", an7583_gpio34), PINCTRL_PIN_GROUP("gpio35", an7583_gpio35), --=20 2.53.0 From nobody Mon Jun 8 05:29:11 2026 Received: from AS8PR04CU009.outbound.protection.outlook.com (mail-westeuropeazon11021083.outbound.protection.outlook.com [52.101.70.83]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B4071F09AD; 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charset="utf-8" Pin 32 (gpio19) duplicate pinconf settings of pin 31. Fix it using a proper bit number in the configuration register. Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC") Signed-off-by: Mikhail Kshevetskiy --- drivers/pinctrl/mediatek/pinctrl-airoha.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/me= diatek/pinctrl-airoha.c index c0aed1b60792..14b235727736 100644 --- a/drivers/pinctrl/mediatek/pinctrl-airoha.c +++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c @@ -1798,7 +1798,7 @@ static const struct airoha_pinctrl_conf en7581_pinctr= l_pullup_conf[] =3D { PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(16)), PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(17)), PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(18)), - PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(18)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(19)), PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(20)), PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(21)), PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(22)), @@ -1915,7 +1915,7 @@ static const struct airoha_pinctrl_conf en7581_pinctr= l_pulldown_conf[] =3D { PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(16)), PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(17)), PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(18)), - PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(18)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(19)), PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(20)), PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(21)), PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(22)), @@ -2032,7 +2032,7 @@ static const struct airoha_pinctrl_conf en7581_pinctr= l_drive_e2_conf[] =3D { PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(16)), PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(17)), PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(18)), - PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(18)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(19)), PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(20)), PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(21)), PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(22)), @@ -2149,7 +2149,7 @@ static const struct airoha_pinctrl_conf en7581_pinctr= l_drive_e4_conf[] =3D { PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(16)), PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(17)), PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(18)), - PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(18)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(19)), PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(20)), PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(21)), PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(22)), --=20 2.53.0 From nobody Mon Jun 8 05:29:11 2026 Received: from AS8PR04CU009.outbound.protection.outlook.com (mail-westeuropeazon11021083.outbound.protection.outlook.com [52.101.70.83]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2651D220F2D; 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charset="utf-8" Pin 21 (gpio19) duplicate pinconf settings of pin 20. Fix it using a proper bit number in the configuration register. Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs") Signed-off-by: Mikhail Kshevetskiy --- drivers/pinctrl/mediatek/pinctrl-airoha.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/me= diatek/pinctrl-airoha.c index 14b235727736..34eef79d058f 100644 --- a/drivers/pinctrl/mediatek/pinctrl-airoha.c +++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c @@ -1851,7 +1851,7 @@ static const struct airoha_pinctrl_conf an7583_pinctr= l_pullup_conf[] =3D { PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(16)), PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(17)), PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(18)), - PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(18)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(19)), PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(20)), PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(21)), PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(22)), @@ -1968,7 +1968,7 @@ static const struct airoha_pinctrl_conf an7583_pinctr= l_pulldown_conf[] =3D { PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(16)), PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(17)), PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(18)), - PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(18)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(19)), PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(20)), PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(21)), PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(22)), @@ -2085,7 +2085,7 @@ static const struct airoha_pinctrl_conf an7583_pinctr= l_drive_e2_conf[] =3D { PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(16)), PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(17)), PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(18)), - PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(18)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(19)), PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(20)), PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(21)), PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(22)), @@ -2202,7 +2202,7 @@ static const struct airoha_pinctrl_conf an7583_pinctr= l_drive_e4_conf[] =3D { PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(16)), PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(17)), PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(18)), - PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(18)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(19)), PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(20)), PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(21)), PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(22)), --=20 2.53.0 From nobody Mon Jun 8 05:29:11 2026 Received: from AS8PR04CU009.outbound.protection.outlook.com (mail-westeuropeazon11021083.outbound.protection.outlook.com [52.101.70.83]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A62E8233933; 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charset="utf-8" phy4_led1 pin function maps led incorrectly. It uses the same map as phy3_led1. PHY{X} should map to LAN{N}_PHY_LED_MAP(X-1). Fixes: 579839c9548c ("pinctrl: airoha: convert PHY LED GPIO to macro") Signed-off-by: Mikhail Kshevetskiy --- drivers/pinctrl/mediatek/pinctrl-airoha.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/me= diatek/pinctrl-airoha.c index 34eef79d058f..9497f5110f61 100644 --- a/drivers/pinctrl/mediatek/pinctrl-airoha.c +++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c @@ -1622,13 +1622,13 @@ static const struct airoha_pinctrl_func_group phy3_= led1_func_group[] =3D { =20 static const struct airoha_pinctrl_func_group phy4_led1_func_group[] =3D { AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), }; 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charset="utf-8" phy4_led1 pin function maps led incorrectly. It uses the same map as phy3_led1. PHY{X} should map to LAN{N}_PHY_LED_MAP(X-1). Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs") Signed-off-by: Mikhail Kshevetskiy --- drivers/pinctrl/mediatek/pinctrl-airoha.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/me= diatek/pinctrl-airoha.c index 9497f5110f61..9be759f08b18 100644 --- a/drivers/pinctrl/mediatek/pinctrl-airoha.c +++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c @@ -1710,13 +1710,13 @@ static const struct airoha_pinctrl_func_group an758= 3_phy3_led1_func_group[] =3D { =20 static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[= ] =3D { AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), }; 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charset="utf-8" AN7581 have 47 valid GPIOs only (gpio0-gpio46), so gpio47 is a fiction. AN7583 have 49 valid GPIOs (gpio0-gpio48), so gpio48 is missed To fix an issue * create AN7583 specific pwm pin function, * remove gpio47 from AN7581 pwm pin function. Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs") Signed-off-by: Mikhail Kshevetskiy --- drivers/pinctrl/mediatek/pinctrl-airoha.c | 74 ++++++++++++++++++++++- 1 file changed, 72 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/me= diatek/pinctrl-airoha.c index 9be759f08b18..15a541724349 100644 --- a/drivers/pinctrl/mediatek/pinctrl-airoha.c +++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c @@ -906,7 +906,30 @@ static const char *const pwm_groups[] =3D { "gpio0", "= gpio1", "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45", - "gpio46", "gpio47" }; + "gpio46" }; +static const char *const an7583_pwm_groups[] =3D { "gpio0", "gpio1", + "gpio2", "gpio3", + "gpio4", "gpio5", + "gpio6", "gpio7", + "gpio8", "gpio9", + "gpio10", "gpio11", + "gpio12", "gpio13", + "gpio14", "gpio15", + "gpio16", "gpio17", + "gpio18", "gpio19", + "gpio20", "gpio21", + "gpio22", "gpio23", + "gpio24", "gpio25", + "gpio26", "gpio27", + "gpio28", "gpio29", + "gpio30", "gpio31", + "gpio36", "gpio37", + "gpio38", "gpio39", + "gpio40", "gpio41", + "gpio42", "gpio43", + "gpio44", "gpio45", + "gpio46", "gpio47", + "gpio48" }; static const char *const phy1_led0_groups[] =3D { "gpio33", "gpio34", "gpio35", "gpio42" }; static const char *const phy2_led0_groups[] =3D { "gpio33", "gpio34", @@ -1504,7 +1527,54 @@ static const struct airoha_pinctrl_func_group pwm_fu= nc_group[] =3D { AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG), AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG), AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG), +}; + +static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] =3D { + AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG), AIROHA_PINCTRL_PWM_EXT("gpio47", GPIO47_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio48", GPIO48_FLASH_MODE_CFG), }; =20 #define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \ @@ -1759,7 +1829,7 @@ static const struct airoha_pinctrl_func an7583_pinctr= l_funcs[] =3D { PINCTRL_FUNC_DESC("emmc", emmc), PINCTRL_FUNC_DESC("pnand", pnand), PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset), - PINCTRL_FUNC_DESC("pwm", pwm), + PINCTRL_FUNC_DESC("pwm", an7583_pwm), PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0), PINCTRL_FUNC_DESC("phy2_led0", an7583_phy2_led0), PINCTRL_FUNC_DESC("phy3_led0", an7583_phy3_led0), --=20 2.53.0 From nobody Mon Jun 8 05:29:11 2026 Received: from AS8PR04CU009.outbound.protection.outlook.com (mail-westeuropeazon11021083.outbound.protection.outlook.com [52.101.70.83]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 80D711A6803; Sun, 7 Jun 2026 00:17:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.70.83 ARC-Seal: i=2; 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charset="utf-8" gpio21 pin group refers to gpio22 pin, this is wrong. Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs") Signed-off-by: Mikhail Kshevetskiy --- drivers/pinctrl/mediatek/pinctrl-airoha.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/me= diatek/pinctrl-airoha.c index 15a541724349..9dce3ed6de17 100644 --- a/drivers/pinctrl/mediatek/pinctrl-airoha.c +++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c @@ -748,7 +748,7 @@ static const int an7583_gpio17_pins[] =3D { 19 }; static const int an7583_gpio18_pins[] =3D { 20 }; static const int an7583_gpio19_pins[] =3D { 21 }; static const int an7583_gpio20_pins[] =3D { 22 }; -static const int an7583_gpio21_pins[] =3D { 24 }; +static const int an7583_gpio21_pins[] =3D { 23 }; static const int an7583_gpio23_pins[] =3D { 25 }; static const int an7583_gpio24_pins[] =3D { 26 }; static const int an7583_gpio25_pins[] =3D { 27 }; --=20 2.53.0 From nobody Mon Jun 8 05:29:11 2026 Received: from AS8PR04CU009.outbound.protection.outlook.com (mail-westeuropeazon11021083.outbound.protection.outlook.com [52.101.70.83]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D77E280A5A; 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charset="utf-8" gpio22 pin group is missed, fix it. Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs") Signed-off-by: Mikhail Kshevetskiy --- drivers/pinctrl/mediatek/pinctrl-airoha.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/me= diatek/pinctrl-airoha.c index 9dce3ed6de17..e66b608c4803 100644 --- a/drivers/pinctrl/mediatek/pinctrl-airoha.c +++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c @@ -749,6 +749,7 @@ static const int an7583_gpio18_pins[] =3D { 20 }; static const int an7583_gpio19_pins[] =3D { 21 }; static const int an7583_gpio20_pins[] =3D { 22 }; static const int an7583_gpio21_pins[] =3D { 23 }; +static const int an7583_gpio22_pins[] =3D { 24 }; static const int an7583_gpio23_pins[] =3D { 25 }; static const int an7583_gpio24_pins[] =3D { 26 }; static const int an7583_gpio25_pins[] =3D { 27 }; @@ -828,6 +829,7 @@ static const struct pingroup an7583_pinctrl_groups[] = =3D { PINCTRL_PIN_GROUP("gpio19", an7583_gpio19), PINCTRL_PIN_GROUP("gpio20", an7583_gpio20), PINCTRL_PIN_GROUP("gpio21", an7583_gpio21), + PINCTRL_PIN_GROUP("gpio22", an7583_gpio22), PINCTRL_PIN_GROUP("gpio23", an7583_gpio23), PINCTRL_PIN_GROUP("gpio24", an7583_gpio24), PINCTRL_PIN_GROUP("gpio25", an7583_gpio25), --=20 2.53.0 From nobody Mon Jun 8 05:29:11 2026 Received: from AS8PR04CU009.outbound.protection.outlook.com (mail-westeuropeazon11021083.outbound.protection.outlook.com [52.101.70.83]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 900EF2874E6; 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charset="utf-8" phy1_led1 pin function wrongly refers to gpio1 instead of gpio11. Fix it. Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs") Signed-off-by: Mikhail Kshevetskiy --- drivers/pinctrl/mediatek/pinctrl-airoha.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/me= diatek/pinctrl-airoha.c index e66b608c4803..b73ab60d0065 100644 --- a/drivers/pinctrl/mediatek/pinctrl-airoha.c +++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c @@ -1754,7 +1754,7 @@ static const struct airoha_pinctrl_func_group an7583_= phy1_led1_func_group[] =3D { LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED1("gpio1", GPIO_LAN3_LED1_MODE_MASK, + AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), }; =20 --=20 2.53.0 From nobody Mon Jun 8 05:29:11 2026 Received: from AS8PR04CU009.outbound.protection.outlook.com (mail-westeuropeazon11021083.outbound.protection.outlook.com [52.101.70.83]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B4D82C08D0; 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charset="utf-8" pcm_spi_int, pcm_spi_cs2, pcm_spi_cs3, pcm_spi_cs4 pin groups are not defined, so pcm_spi function can't be applied to these groups. Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs") Signed-off-by: Mikhail Kshevetskiy --- drivers/pinctrl/mediatek/pinctrl-airoha.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/me= diatek/pinctrl-airoha.c index b73ab60d0065..bf5ebb31e635 100644 --- a/drivers/pinctrl/mediatek/pinctrl-airoha.c +++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c @@ -877,10 +877,8 @@ static const char *const pcm_spi_groups[] =3D { "pcm_s= pi", "pcm_spi_int", "pcm_spi_cs2_p156", "pcm_spi_cs2_p128", "pcm_spi_cs3", "pcm_spi_cs4" }; -static const char *const an7583_pcm_spi_groups[] =3D { "pcm_spi", "pcm_spi= _int", - "pcm_spi_rst", "pcm_spi_cs1", - "pcm_spi_cs2", "pcm_spi_cs3", - "pcm_spi_cs4" }; +static const char *const an7583_pcm_spi_groups[] =3D { "pcm_spi", + "pcm_spi_rst", "pcm_spi_cs1" }; static const char *const i2s_groups[] =3D { "i2s" }; static const char *const emmc_groups[] =3D { "emmc" }; static const char *const pnand_groups[] =3D { "pnand" }; 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charset="utf-8" Preparation step. Later the driver will be split on several SoC specific drivers and a common code. So it's better put them to a separate directory. No functional changes. Signed-off-by: Mikhail Kshevetskiy --- drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/airoha/Kconfig | 18 ++++++++++++++++++ drivers/pinctrl/airoha/Makefile | 4 ++++ .../{mediatek =3D> airoha}/pinctrl-airoha.c | 0 drivers/pinctrl/mediatek/Kconfig | 18 +----------------- drivers/pinctrl/mediatek/Makefile | 1 - 7 files changed, 25 insertions(+), 18 deletions(-) create mode 100644 drivers/pinctrl/airoha/Kconfig create mode 100644 drivers/pinctrl/airoha/Makefile rename drivers/pinctrl/{mediatek =3D> airoha}/pinctrl-airoha.c (100%) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 03f2e3ee065f..8b9b94ae9b33 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -678,6 +678,7 @@ config PINCTRL_RP1 Enable the gpio and pinctrl/mux driver for RaspberryPi RP1 multi function device. =20 +source "drivers/pinctrl/airoha/Kconfig" source "drivers/pinctrl/actions/Kconfig" source "drivers/pinctrl/aspeed/Kconfig" source "drivers/pinctrl/bcm/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index f7d5d5f76d0c..a61eecff0dad 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -65,6 +65,7 @@ obj-$(CONFIG_PINCTRL_UPBOARD) +=3D pinctrl-upboard.o obj-$(CONFIG_PINCTRL_ZYNQMP) +=3D pinctrl-zynqmp.o obj-$(CONFIG_PINCTRL_ZYNQ) +=3D pinctrl-zynq.o =20 +obj-y +=3D airoha/ obj-y +=3D actions/ obj-$(CONFIG_ARCH_ASPEED) +=3D aspeed/ obj-y +=3D bcm/ diff --git a/drivers/pinctrl/airoha/Kconfig b/drivers/pinctrl/airoha/Kconfig new file mode 100644 index 000000000000..fd84a04cb428 --- /dev/null +++ b/drivers/pinctrl/airoha/Kconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-only + +# For ARMv8 SoCs +config PINCTRL_AIROHA + tristate "Airoha AN7581/AN7583 pin control" + depends on OF + depends on ARM64 || COMPILE_TEST + depends on ARCH_AIROHA || COMPILE_TEST + select PINMUX + select GENERIC_PINCONF + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GPIOLIB + select GPIOLIB_IRQCHIP + select REGMAP_MMIO + help + Say yes here to support pin controller and gpio driver + on Airoha EN7581/AN7583 SoC. diff --git a/drivers/pinctrl/airoha/Makefile b/drivers/pinctrl/airoha/Makef= ile new file mode 100644 index 000000000000..009800406f5e --- /dev/null +++ b/drivers/pinctrl/airoha/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +# SoC Drivers +obj-$(CONFIG_PINCTRL_AIROHA) +=3D pinctrl-airoha.o diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/ai= roha/pinctrl-airoha.c similarity index 100% rename from drivers/pinctrl/mediatek/pinctrl-airoha.c rename to drivers/pinctrl/airoha/pinctrl-airoha.c diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kc= onfig index 4819617d9368..1fd09305c73f 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only menu "MediaTek pinctrl drivers" - depends on ARCH_MEDIATEK || ARCH_AIROHA || RALINK || COMPILE_TEST + depends on ARCH_MEDIATEK || RALINK || COMPILE_TEST =20 config EINT_MTK tristate "MediaTek External Interrupt Support" @@ -125,22 +125,6 @@ config PINCTRL_MT8127 default MACH_MT8127 select PINCTRL_MTK =20 -# For ARMv8 SoCs -config PINCTRL_AIROHA - tristate "Airoha EN7581 pin control" - depends on OF - depends on ARM64 || COMPILE_TEST - select PINMUX - select GENERIC_PINCONF - select GENERIC_PINCTRL_GROUPS - select GENERIC_PINMUX_FUNCTIONS - select GPIOLIB - select GPIOLIB_IRQCHIP - select REGMAP_MMIO - help - Say yes here to support pin controller and gpio driver - on Airoha EN7581 SoC. - config PINCTRL_MT2712 bool "MediaTek MT2712 pin control" depends on OF diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/M= akefile index ae765bd99965..6dc17b0c23f9 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -8,7 +8,6 @@ obj-$(CONFIG_PINCTRL_MTK_MOORE) +=3D pinctrl-moore.o obj-$(CONFIG_PINCTRL_MTK_PARIS) +=3D pinctrl-paris.o =20 # SoC Drivers -obj-$(CONFIG_PINCTRL_AIROHA) +=3D pinctrl-airoha.o obj-$(CONFIG_PINCTRL_MT7620) +=3D pinctrl-mt7620.o obj-$(CONFIG_PINCTRL_MT7621) +=3D pinctrl-mt7621.o obj-$(CONFIG_PINCTRL_MT76X8) +=3D pinctrl-mt76x8.o --=20 2.53.0 From nobody Mon Jun 8 05:29:11 2026 Received: from AS8PR04CU009.outbound.protection.outlook.com (mail-westeuropeazon11021083.outbound.protection.outlook.com [52.101.70.83]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 80BCA2D97BB; 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charset="utf-8" Let's move the definitions and declarations of structures required for Airoha SoC-specific pinctrl drivers to a common header. Later we'll have several SoC-specific drivers, so this step is necessary. No functional changes. Signed-off-by: Mikhail Kshevetskiy --- drivers/pinctrl/airoha/airoha-common.h | 479 ++++++++++++++++++++++++ drivers/pinctrl/airoha/pinctrl-airoha.c | 464 +---------------------- 2 files changed, 480 insertions(+), 463 deletions(-) create mode 100644 drivers/pinctrl/airoha/airoha-common.h diff --git a/drivers/pinctrl/airoha/airoha-common.h b/drivers/pinctrl/airoh= a/airoha-common.h new file mode 100644 index 000000000000..3d70002213bd --- /dev/null +++ b/drivers/pinctrl/airoha/airoha-common.h @@ -0,0 +1,479 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Author: Lorenzo Bianconi + * Author: Benjamin Larsson + * Author: Markus Gothe + */ + +#ifndef __AIROHA_COMMON_HEADER__ +#define __AIROHA_COMMON_HEADER__ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../core.h" +#include "../pinconf.h" +#include "../pinmux.h" + +#define PINCTRL_PIN_GROUP(id, table) \ + PINCTRL_PINGROUP(id, table##_pins, ARRAY_SIZE(table##_pins)) + +#define PINCTRL_FUNC_DESC(id, table) \ + { \ + .desc =3D PINCTRL_PINFUNCTION(id, table##_groups, \ + ARRAY_SIZE(table##_groups)),\ + .groups =3D table##_func_group, \ + .group_size =3D ARRAY_SIZE(table##_func_group), \ + } + +#define PINCTRL_CONF_DESC(p, offset, mask) \ + { \ + .pin =3D p, \ + .reg =3D { offset, mask }, \ + } + +/* MUX */ +#define REG_GPIO_2ND_I2C_MODE 0x0214 +#define GPIO_MDC_IO_MASTER_MODE_MODE BIT(14) +#define GPIO_I2C_MASTER_MODE_MODE BIT(13) +#define GPIO_I2S_MODE_MASK BIT(12) +#define GPIO_I2C_SLAVE_MODE_MODE BIT(11) +#define GPIO_LAN3_LED1_MODE_MASK BIT(10) +#define GPIO_LAN3_LED0_MODE_MASK BIT(9) +#define GPIO_LAN2_LED1_MODE_MASK BIT(8) +#define GPIO_LAN2_LED0_MODE_MASK BIT(7) +#define GPIO_LAN1_LED1_MODE_MASK BIT(6) +#define GPIO_LAN1_LED0_MODE_MASK BIT(5) +#define GPIO_LAN0_LED1_MODE_MASK BIT(4) +#define GPIO_LAN0_LED0_MODE_MASK BIT(3) +#define PON_TOD_1PPS_MODE_MASK BIT(2) +#define GSW_TOD_1PPS_MODE_MASK BIT(1) +#define GPIO_2ND_I2C_MODE_MASK BIT(0) + +#define REG_GPIO_SPI_CS1_MODE 0x0218 +#define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21) +#define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20) +#define GPIO_PCM_SPI_CS2_MODE_P156_MASK BIT(19) +#define GPIO_PCM_SPI_CS2_MODE_P128_MASK BIT(18) +#define AN7583_GPIO_PCM_SPI_CS2_MODE_MASK BIT(18) +#define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17) +#define GPIO_PCM_SPI_MODE_MASK BIT(16) +#define GPIO_PCM2_MODE_MASK BIT(13) +#define GPIO_PCM1_MODE_MASK BIT(12) +#define GPIO_PCM_INT_MODE_MASK BIT(9) +#define GPIO_PCM_RESET_MODE_MASK BIT(8) +#define GPIO_SPI_QUAD_MODE_MASK BIT(4) +#define GPIO_SPI_CS4_MODE_MASK BIT(3) +#define GPIO_SPI_CS3_MODE_MASK BIT(2) +#define GPIO_SPI_CS2_MODE_MASK BIT(1) +#define GPIO_SPI_CS1_MODE_MASK BIT(0) + +#define REG_GPIO_PON_MODE 0x021c +#define GPIO_PARALLEL_NAND_MODE_MASK BIT(14) +#define GPIO_SGMII_MDIO_MODE_MASK BIT(13) +#define GPIO_PCIE_RESET2_MASK BIT(12) +#define SIPO_RCLK_MODE_MASK BIT(11) +#define GPIO_PCIE_RESET1_MASK BIT(10) +#define GPIO_PCIE_RESET0_MASK BIT(9) +#define GPIO_UART5_MODE_MASK BIT(8) +#define GPIO_UART4_MODE_MASK BIT(7) +#define GPIO_HSUART_CTS_RTS_MODE_MASK BIT(6) +#define GPIO_HSUART_MODE_MASK BIT(5) +#define GPIO_UART2_CTS_RTS_MODE_MASK BIT(4) +#define GPIO_UART2_MODE_MASK BIT(3) +#define GPIO_SIPO_MODE_MASK BIT(2) +#define GPIO_EMMC_MODE_MASK BIT(1) +#define GPIO_PON_MODE_MASK BIT(0) + +#define REG_NPU_UART_EN 0x0224 +#define JTAG_UDI_EN_MASK BIT(4) +#define JTAG_DFD_EN_MASK BIT(3) + +#define REG_FORCE_GPIO_EN 0x0228 +#define FORCE_GPIO_EN(n) BIT(n) + +/* LED MAP */ +#define REG_LAN_LED0_MAPPING 0x027c +#define REG_LAN_LED1_MAPPING 0x0280 + +#define LAN4_LED_MAPPING_MASK GENMASK(18, 16) +#define LAN4_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n= )) + +#define LAN3_LED_MAPPING_MASK GENMASK(14, 12) +#define LAN3_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n= )) + +#define LAN2_LED_MAPPING_MASK GENMASK(10, 8) +#define LAN2_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n= )) + +#define LAN1_LED_MAPPING_MASK GENMASK(6, 4) +#define LAN1_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n= )) + +#define LAN0_LED_MAPPING_MASK GENMASK(2, 0) +#define LAN0_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n= )) + +/* CONF */ +#define REG_I2C_SDA_E2 0x001c +#define AN7583_I2C1_SCL_E2_MASK BIT(16) +#define AN7583_I2C1_SDA_E2_MASK BIT(15) +#define SPI_MISO_E2_MASK BIT(14) +#define SPI_MOSI_E2_MASK BIT(13) +#define SPI_CLK_E2_MASK BIT(12) +#define SPI_CS0_E2_MASK BIT(11) +#define PCIE2_RESET_E2_MASK BIT(10) +#define PCIE1_RESET_E2_MASK BIT(9) +#define PCIE0_RESET_E2_MASK BIT(8) +#define AN7583_MDIO_0_E2_MASK BIT(5) +#define AN7583_MDC_0_E2_MASK BIT(4) +#define UART1_RXD_E2_MASK BIT(3) +#define UART1_TXD_E2_MASK BIT(2) +#define I2C_SCL_E2_MASK BIT(1) +#define I2C_SDA_E2_MASK BIT(0) + +#define REG_I2C_SDA_E4 0x0020 +#define AN7583_I2C1_SCL_E4_MASK BIT(16) +#define AN7583_I2C1_SDA_E4_MASK BIT(15) +#define SPI_MISO_E4_MASK BIT(14) +#define SPI_MOSI_E4_MASK BIT(13) +#define SPI_CLK_E4_MASK BIT(12) +#define SPI_CS0_E4_MASK BIT(11) +#define PCIE2_RESET_E4_MASK BIT(10) +#define PCIE1_RESET_E4_MASK BIT(9) +#define PCIE0_RESET_E4_MASK BIT(8) +#define AN7583_MDIO_0_E4_MASK BIT(5) +#define AN7583_MDC_0_E4_MASK BIT(4) +#define UART1_RXD_E4_MASK BIT(3) +#define UART1_TXD_E4_MASK BIT(2) +#define I2C_SCL_E4_MASK BIT(1) +#define I2C_SDA_E4_MASK BIT(0) + +#define REG_GPIO_L_E2 0x0024 +#define REG_GPIO_L_E4 0x0028 +#define REG_GPIO_H_E2 0x002c +#define REG_GPIO_H_E4 0x0030 + +#define REG_I2C_SDA_PU 0x0044 +#define AN7583_I2C1_SCL_PU_MASK BIT(16) +#define AN7583_I2C1_SDA_PU_MASK BIT(15) +#define SPI_MISO_PU_MASK BIT(14) +#define SPI_MOSI_PU_MASK BIT(13) +#define SPI_CLK_PU_MASK BIT(12) +#define SPI_CS0_PU_MASK BIT(11) +#define PCIE2_RESET_PU_MASK BIT(10) +#define PCIE1_RESET_PU_MASK BIT(9) +#define PCIE0_RESET_PU_MASK BIT(8) +#define AN7583_MDIO_0_PU_MASK BIT(5) +#define AN7583_MDC_0_PU_MASK BIT(4) +#define UART1_RXD_PU_MASK BIT(3) +#define UART1_TXD_PU_MASK BIT(2) +#define I2C_SCL_PU_MASK BIT(1) +#define I2C_SDA_PU_MASK BIT(0) + +#define REG_I2C_SDA_PD 0x0048 +#define AN7583_I2C1_SDA_PD_MASK BIT(16) +#define AN7583_I2C1_SCL_PD_MASK BIT(15) +#define SPI_MISO_PD_MASK BIT(14) +#define SPI_MOSI_PD_MASK BIT(13) +#define SPI_CLK_PD_MASK BIT(12) +#define SPI_CS0_PD_MASK BIT(11) +#define PCIE2_RESET_PD_MASK BIT(10) +#define PCIE1_RESET_PD_MASK BIT(9) +#define PCIE0_RESET_PD_MASK BIT(8) +#define AN7583_MDIO_0_PD_MASK BIT(5) +#define AN7583_MDC_0_PD_MASK BIT(4) +#define UART1_RXD_PD_MASK BIT(3) +#define UART1_TXD_PD_MASK BIT(2) +#define I2C_SCL_PD_MASK BIT(1) +#define I2C_SDA_PD_MASK BIT(0) + +#define REG_GPIO_L_PU 0x004c +#define REG_GPIO_L_PD 0x0050 +#define REG_GPIO_H_PU 0x0054 +#define REG_GPIO_H_PD 0x0058 + +#define REG_PCIE_RESET_OD 0x018c +#define PCIE2_RESET_OD_MASK BIT(2) +#define PCIE1_RESET_OD_MASK BIT(1) +#define PCIE0_RESET_OD_MASK BIT(0) + +/* GPIOs */ +#define REG_GPIO_CTRL 0x0000 +#define REG_GPIO_DATA 0x0004 +#define REG_GPIO_INT 0x0008 +#define REG_GPIO_INT_EDGE 0x000c +#define REG_GPIO_INT_LEVEL 0x0010 +#define REG_GPIO_OE 0x0014 +#define REG_GPIO_CTRL1 0x0020 +#define REG_GPIO_CTRL2 0x0060 +#define REG_GPIO_CTRL3 0x0064 + +/* PWM MODE CONF */ +#define REG_GPIO_FLASH_MODE_CFG 0x0034 +#define GPIO15_FLASH_MODE_CFG BIT(15) +#define GPIO14_FLASH_MODE_CFG BIT(14) +#define GPIO13_FLASH_MODE_CFG BIT(13) +#define GPIO12_FLASH_MODE_CFG BIT(12) +#define GPIO11_FLASH_MODE_CFG BIT(11) +#define GPIO10_FLASH_MODE_CFG BIT(10) +#define GPIO9_FLASH_MODE_CFG BIT(9) +#define GPIO8_FLASH_MODE_CFG BIT(8) +#define GPIO7_FLASH_MODE_CFG BIT(7) +#define GPIO6_FLASH_MODE_CFG BIT(6) +#define GPIO5_FLASH_MODE_CFG BIT(5) +#define GPIO4_FLASH_MODE_CFG BIT(4) +#define GPIO3_FLASH_MODE_CFG BIT(3) +#define GPIO2_FLASH_MODE_CFG BIT(2) +#define GPIO1_FLASH_MODE_CFG BIT(1) +#define GPIO0_FLASH_MODE_CFG BIT(0) + +/* PWM MODE CONF EXT */ +#define REG_GPIO_FLASH_MODE_CFG_EXT 0x0068 +#define GPIO51_FLASH_MODE_CFG BIT(31) +#define GPIO50_FLASH_MODE_CFG BIT(30) +#define GPIO49_FLASH_MODE_CFG BIT(29) +#define GPIO48_FLASH_MODE_CFG BIT(28) +#define GPIO47_FLASH_MODE_CFG BIT(27) +#define GPIO46_FLASH_MODE_CFG BIT(26) +#define GPIO45_FLASH_MODE_CFG BIT(25) +#define GPIO44_FLASH_MODE_CFG BIT(24) +#define GPIO43_FLASH_MODE_CFG BIT(23) +#define GPIO42_FLASH_MODE_CFG BIT(22) +#define GPIO41_FLASH_MODE_CFG BIT(21) +#define GPIO40_FLASH_MODE_CFG BIT(20) +#define GPIO39_FLASH_MODE_CFG BIT(19) +#define GPIO38_FLASH_MODE_CFG BIT(18) +#define GPIO37_FLASH_MODE_CFG BIT(17) +#define GPIO36_FLASH_MODE_CFG BIT(16) +#define GPIO31_FLASH_MODE_CFG BIT(15) +#define GPIO30_FLASH_MODE_CFG BIT(14) +#define GPIO29_FLASH_MODE_CFG BIT(13) +#define GPIO28_FLASH_MODE_CFG BIT(12) +#define GPIO27_FLASH_MODE_CFG BIT(11) +#define GPIO26_FLASH_MODE_CFG BIT(10) +#define GPIO25_FLASH_MODE_CFG BIT(9) +#define GPIO24_FLASH_MODE_CFG BIT(8) +#define GPIO23_FLASH_MODE_CFG BIT(7) +#define GPIO22_FLASH_MODE_CFG BIT(6) +#define GPIO21_FLASH_MODE_CFG BIT(5) +#define GPIO20_FLASH_MODE_CFG BIT(4) +#define GPIO19_FLASH_MODE_CFG BIT(3) +#define GPIO18_FLASH_MODE_CFG BIT(2) +#define GPIO17_FLASH_MODE_CFG BIT(1) +#define GPIO16_FLASH_MODE_CFG BIT(0) + +#define REG_GPIO_DATA1 0x0070 +#define REG_GPIO_OE1 0x0078 +#define REG_GPIO_INT1 0x007c +#define REG_GPIO_INT_EDGE1 0x0080 +#define REG_GPIO_INT_EDGE2 0x0084 +#define REG_GPIO_INT_EDGE3 0x0088 +#define REG_GPIO_INT_LEVEL1 0x008c +#define REG_GPIO_INT_LEVEL2 0x0090 +#define REG_GPIO_INT_LEVEL3 0x0094 + +#define AIROHA_NUM_PINS 64 +#define AIROHA_PIN_BANK_SIZE (AIROHA_NUM_PINS / 2) +#define AIROHA_REG_GPIOCTRL_NUM_PIN (AIROHA_NUM_PINS / 4) + +/* PWM */ +#define AIROHA_PINCTRL_PWM(gpio, mux_val) \ + { \ + .name =3D (gpio), \ + .regmap[0] =3D { \ + AIROHA_FUNC_PWM_MUX, \ + REG_GPIO_FLASH_MODE_CFG, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size =3D 1, \ + } \ + +#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \ + { \ + .name =3D (gpio), \ + .regmap[0] =3D { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size =3D 1, \ + } \ + +#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \ + { \ + .name =3D (gpio), \ + .regmap[0] =3D { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_2ND_I2C_MODE, \ + (mux_val), \ + (mux_val), \ + }, \ + .regmap[1] =3D { \ + AIROHA_FUNC_MUX, \ + REG_LAN_LED0_MAPPING, \ + (map_mask), \ + (map_val), \ + }, \ + .regmap_size =3D 2, \ + } + +#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \ + { \ + .name =3D (gpio), \ + .regmap[0] =3D { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_2ND_I2C_MODE, \ + (mux_val), \ + (mux_val), \ + }, \ + .regmap[1] =3D { \ + AIROHA_FUNC_MUX, \ + REG_LAN_LED1_MAPPING, \ + (map_mask), \ + (map_val), \ + }, \ + .regmap_size =3D 2, \ + } + +#define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val) \ + airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP, \ + (pin), (val)) +#define airoha_pinctrl_get_pulldown_conf(pinctrl, pin, val) \ + airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN, \ + (pin), (val)) +#define airoha_pinctrl_get_drive_e2_conf(pinctrl, pin, val) \ + airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2, \ + (pin), (val)) +#define airoha_pinctrl_get_drive_e4_conf(pinctrl, pin, val) \ + airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4, \ + (pin), (val)) +#define airoha_pinctrl_get_pcie_rst_od_conf(pinctrl, pin, val) \ + airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD, \ + (pin), (val)) +#define airoha_pinctrl_set_pullup_conf(pinctrl, pin, val) \ + airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP, \ + (pin), (val)) +#define airoha_pinctrl_set_pulldown_conf(pinctrl, pin, val) \ + airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN, \ + (pin), (val)) +#define airoha_pinctrl_set_drive_e2_conf(pinctrl, pin, val) \ + airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2, \ + (pin), (val)) +#define airoha_pinctrl_set_drive_e4_conf(pinctrl, pin, val) \ + airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4, \ + (pin), (val)) +#define airoha_pinctrl_set_pcie_rst_od_conf(pinctrl, pin, val) \ + airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD, \ + (pin), (val)) + +struct airoha_pinctrl_reg { + u32 offset; + u32 mask; +}; + +enum airoha_pinctrl_mux_func { + AIROHA_FUNC_MUX, + AIROHA_FUNC_PWM_MUX, + AIROHA_FUNC_PWM_EXT_MUX, +}; + +struct airoha_pinctrl_func_group { + const char *name; + struct { + enum airoha_pinctrl_mux_func mux; + u32 offset; + u32 mask; + u32 val; + } regmap[2]; + int regmap_size; +}; + +struct airoha_pinctrl_func { + const struct pinfunction desc; + const struct airoha_pinctrl_func_group *groups; + u8 group_size; +}; + +struct airoha_pinctrl_conf { + u32 pin; + struct airoha_pinctrl_reg reg; +}; + +struct airoha_pinctrl_gpiochip { + struct gpio_chip chip; + + /* gpio */ + const u32 *data; + const u32 *dir; + const u32 *out; + /* irq */ + const u32 *status; + const u32 *level; + const u32 *edge; + + u32 irq_type[AIROHA_NUM_PINS]; +}; + +struct airoha_pinctrl_confs_info { + const struct airoha_pinctrl_conf *confs; + unsigned int num_confs; +}; + +enum airoha_pinctrl_confs_type { + AIROHA_PINCTRL_CONFS_PULLUP, + AIROHA_PINCTRL_CONFS_PULLDOWN, + AIROHA_PINCTRL_CONFS_DRIVE_E2, + AIROHA_PINCTRL_CONFS_DRIVE_E4, + AIROHA_PINCTRL_CONFS_PCIE_RST_OD, + + AIROHA_PINCTRL_CONFS_MAX, +}; + +struct airoha_pinctrl { + struct pinctrl_dev *ctrl; + + struct pinctrl_desc desc; + const struct pingroup *grps; + const struct airoha_pinctrl_func *funcs; + const struct airoha_pinctrl_confs_info *confs_info; + + struct regmap *chip_scu; + struct regmap *regmap; + + struct airoha_pinctrl_gpiochip gpiochip; +}; + +struct airoha_pinctrl_match_data { + const struct pinctrl_pin_desc *pins; + const unsigned int num_pins; + const struct pingroup *grps; + const unsigned int num_grps; + const struct airoha_pinctrl_func *funcs; + const unsigned int num_funcs; + const struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MA= X]; +}; + +#endif diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airo= ha/pinctrl-airoha.c index bf5ebb31e635..0b4bbcf08ec9 100644 --- a/drivers/pinctrl/airoha/pinctrl-airoha.c +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c @@ -5,290 +5,7 @@ * Author: Markus Gothe */ =20 -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../core.h" -#include "../pinconf.h" -#include "../pinmux.h" - -#define PINCTRL_PIN_GROUP(id, table) \ - PINCTRL_PINGROUP(id, table##_pins, ARRAY_SIZE(table##_pins)) - -#define PINCTRL_FUNC_DESC(id, table) \ - { \ - .desc =3D PINCTRL_PINFUNCTION(id, table##_groups, \ - ARRAY_SIZE(table##_groups)),\ - .groups =3D table##_func_group, \ - .group_size =3D ARRAY_SIZE(table##_func_group), \ - } - -#define PINCTRL_CONF_DESC(p, offset, mask) \ - { \ - .pin =3D p, \ - .reg =3D { offset, mask }, \ - } - -/* MUX */ -#define REG_GPIO_2ND_I2C_MODE 0x0214 -#define GPIO_MDC_IO_MASTER_MODE_MODE BIT(14) -#define GPIO_I2C_MASTER_MODE_MODE BIT(13) -#define GPIO_I2S_MODE_MASK BIT(12) -#define GPIO_I2C_SLAVE_MODE_MODE BIT(11) -#define GPIO_LAN3_LED1_MODE_MASK BIT(10) -#define GPIO_LAN3_LED0_MODE_MASK BIT(9) -#define GPIO_LAN2_LED1_MODE_MASK BIT(8) -#define GPIO_LAN2_LED0_MODE_MASK BIT(7) -#define GPIO_LAN1_LED1_MODE_MASK BIT(6) -#define GPIO_LAN1_LED0_MODE_MASK BIT(5) -#define GPIO_LAN0_LED1_MODE_MASK BIT(4) -#define GPIO_LAN0_LED0_MODE_MASK BIT(3) -#define PON_TOD_1PPS_MODE_MASK BIT(2) -#define GSW_TOD_1PPS_MODE_MASK BIT(1) -#define GPIO_2ND_I2C_MODE_MASK BIT(0) - -#define REG_GPIO_SPI_CS1_MODE 0x0218 -#define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21) -#define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20) -#define GPIO_PCM_SPI_CS2_MODE_P156_MASK BIT(19) -#define GPIO_PCM_SPI_CS2_MODE_P128_MASK BIT(18) -#define AN7583_GPIO_PCM_SPI_CS2_MODE_MASK BIT(18) -#define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17) -#define GPIO_PCM_SPI_MODE_MASK BIT(16) -#define GPIO_PCM2_MODE_MASK BIT(13) -#define GPIO_PCM1_MODE_MASK BIT(12) -#define GPIO_PCM_INT_MODE_MASK BIT(9) -#define GPIO_PCM_RESET_MODE_MASK BIT(8) -#define GPIO_SPI_QUAD_MODE_MASK BIT(4) -#define GPIO_SPI_CS4_MODE_MASK BIT(3) -#define GPIO_SPI_CS3_MODE_MASK BIT(2) -#define GPIO_SPI_CS2_MODE_MASK BIT(1) -#define GPIO_SPI_CS1_MODE_MASK BIT(0) - -#define REG_GPIO_PON_MODE 0x021c -#define GPIO_PARALLEL_NAND_MODE_MASK BIT(14) -#define GPIO_SGMII_MDIO_MODE_MASK BIT(13) -#define GPIO_PCIE_RESET2_MASK BIT(12) -#define SIPO_RCLK_MODE_MASK BIT(11) -#define GPIO_PCIE_RESET1_MASK BIT(10) -#define GPIO_PCIE_RESET0_MASK BIT(9) -#define GPIO_UART5_MODE_MASK BIT(8) -#define GPIO_UART4_MODE_MASK BIT(7) -#define GPIO_HSUART_CTS_RTS_MODE_MASK BIT(6) -#define GPIO_HSUART_MODE_MASK BIT(5) -#define GPIO_UART2_CTS_RTS_MODE_MASK BIT(4) -#define GPIO_UART2_MODE_MASK BIT(3) -#define GPIO_SIPO_MODE_MASK BIT(2) -#define GPIO_EMMC_MODE_MASK BIT(1) -#define GPIO_PON_MODE_MASK BIT(0) - -#define REG_NPU_UART_EN 0x0224 -#define JTAG_UDI_EN_MASK BIT(4) -#define JTAG_DFD_EN_MASK BIT(3) - -#define REG_FORCE_GPIO_EN 0x0228 -#define FORCE_GPIO_EN(n) BIT(n) - -/* LED MAP */ -#define REG_LAN_LED0_MAPPING 0x027c -#define REG_LAN_LED1_MAPPING 0x0280 - -#define LAN4_LED_MAPPING_MASK GENMASK(18, 16) -#define LAN4_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n= )) - -#define LAN3_LED_MAPPING_MASK GENMASK(14, 12) -#define LAN3_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n= )) - -#define LAN2_LED_MAPPING_MASK GENMASK(10, 8) -#define LAN2_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n= )) - -#define LAN1_LED_MAPPING_MASK GENMASK(6, 4) -#define LAN1_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n= )) - -#define LAN0_LED_MAPPING_MASK GENMASK(2, 0) -#define LAN0_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n= )) - -/* CONF */ -#define REG_I2C_SDA_E2 0x001c -#define AN7583_I2C1_SCL_E2_MASK BIT(16) -#define AN7583_I2C1_SDA_E2_MASK BIT(15) -#define SPI_MISO_E2_MASK BIT(14) -#define SPI_MOSI_E2_MASK BIT(13) -#define SPI_CLK_E2_MASK BIT(12) -#define SPI_CS0_E2_MASK BIT(11) -#define PCIE2_RESET_E2_MASK BIT(10) -#define PCIE1_RESET_E2_MASK BIT(9) -#define PCIE0_RESET_E2_MASK BIT(8) -#define AN7583_MDIO_0_E2_MASK BIT(5) -#define AN7583_MDC_0_E2_MASK BIT(4) -#define UART1_RXD_E2_MASK BIT(3) -#define UART1_TXD_E2_MASK BIT(2) -#define I2C_SCL_E2_MASK BIT(1) -#define I2C_SDA_E2_MASK BIT(0) - -#define REG_I2C_SDA_E4 0x0020 -#define AN7583_I2C1_SCL_E4_MASK BIT(16) -#define AN7583_I2C1_SDA_E4_MASK BIT(15) -#define SPI_MISO_E4_MASK BIT(14) -#define SPI_MOSI_E4_MASK BIT(13) -#define SPI_CLK_E4_MASK BIT(12) -#define SPI_CS0_E4_MASK BIT(11) -#define PCIE2_RESET_E4_MASK BIT(10) -#define PCIE1_RESET_E4_MASK BIT(9) -#define PCIE0_RESET_E4_MASK BIT(8) -#define AN7583_MDIO_0_E4_MASK BIT(5) -#define AN7583_MDC_0_E4_MASK BIT(4) -#define UART1_RXD_E4_MASK BIT(3) -#define UART1_TXD_E4_MASK BIT(2) -#define I2C_SCL_E4_MASK BIT(1) -#define I2C_SDA_E4_MASK BIT(0) - -#define REG_GPIO_L_E2 0x0024 -#define REG_GPIO_L_E4 0x0028 -#define REG_GPIO_H_E2 0x002c -#define REG_GPIO_H_E4 0x0030 - -#define REG_I2C_SDA_PU 0x0044 -#define AN7583_I2C1_SCL_PU_MASK BIT(16) -#define AN7583_I2C1_SDA_PU_MASK BIT(15) -#define SPI_MISO_PU_MASK BIT(14) -#define SPI_MOSI_PU_MASK BIT(13) -#define SPI_CLK_PU_MASK BIT(12) -#define SPI_CS0_PU_MASK BIT(11) -#define PCIE2_RESET_PU_MASK BIT(10) -#define PCIE1_RESET_PU_MASK BIT(9) -#define PCIE0_RESET_PU_MASK BIT(8) -#define AN7583_MDIO_0_PU_MASK BIT(5) -#define AN7583_MDC_0_PU_MASK BIT(4) -#define UART1_RXD_PU_MASK BIT(3) -#define UART1_TXD_PU_MASK BIT(2) -#define I2C_SCL_PU_MASK BIT(1) -#define I2C_SDA_PU_MASK BIT(0) - -#define REG_I2C_SDA_PD 0x0048 -#define AN7583_I2C1_SDA_PD_MASK BIT(16) -#define AN7583_I2C1_SCL_PD_MASK BIT(15) -#define SPI_MISO_PD_MASK BIT(14) -#define SPI_MOSI_PD_MASK BIT(13) -#define SPI_CLK_PD_MASK BIT(12) -#define SPI_CS0_PD_MASK BIT(11) -#define PCIE2_RESET_PD_MASK BIT(10) -#define PCIE1_RESET_PD_MASK BIT(9) -#define PCIE0_RESET_PD_MASK BIT(8) -#define AN7583_MDIO_0_PD_MASK BIT(5) -#define AN7583_MDC_0_PD_MASK BIT(4) -#define UART1_RXD_PD_MASK BIT(3) -#define UART1_TXD_PD_MASK BIT(2) -#define I2C_SCL_PD_MASK BIT(1) -#define I2C_SDA_PD_MASK BIT(0) - -#define REG_GPIO_L_PU 0x004c -#define REG_GPIO_L_PD 0x0050 -#define REG_GPIO_H_PU 0x0054 -#define REG_GPIO_H_PD 0x0058 - -#define REG_PCIE_RESET_OD 0x018c -#define PCIE2_RESET_OD_MASK BIT(2) -#define PCIE1_RESET_OD_MASK BIT(1) -#define PCIE0_RESET_OD_MASK BIT(0) - -/* GPIOs */ -#define REG_GPIO_CTRL 0x0000 -#define REG_GPIO_DATA 0x0004 -#define REG_GPIO_INT 0x0008 -#define REG_GPIO_INT_EDGE 0x000c -#define REG_GPIO_INT_LEVEL 0x0010 -#define REG_GPIO_OE 0x0014 -#define REG_GPIO_CTRL1 0x0020 - -/* PWM MODE CONF */ -#define REG_GPIO_FLASH_MODE_CFG 0x0034 -#define GPIO15_FLASH_MODE_CFG BIT(15) -#define GPIO14_FLASH_MODE_CFG BIT(14) -#define GPIO13_FLASH_MODE_CFG BIT(13) -#define GPIO12_FLASH_MODE_CFG BIT(12) -#define GPIO11_FLASH_MODE_CFG BIT(11) -#define GPIO10_FLASH_MODE_CFG BIT(10) -#define GPIO9_FLASH_MODE_CFG BIT(9) -#define GPIO8_FLASH_MODE_CFG BIT(8) -#define GPIO7_FLASH_MODE_CFG BIT(7) -#define GPIO6_FLASH_MODE_CFG BIT(6) -#define GPIO5_FLASH_MODE_CFG BIT(5) -#define GPIO4_FLASH_MODE_CFG BIT(4) -#define GPIO3_FLASH_MODE_CFG BIT(3) -#define GPIO2_FLASH_MODE_CFG BIT(2) -#define GPIO1_FLASH_MODE_CFG BIT(1) -#define GPIO0_FLASH_MODE_CFG BIT(0) - -#define REG_GPIO_CTRL2 0x0060 -#define REG_GPIO_CTRL3 0x0064 - -/* PWM MODE CONF EXT */ -#define REG_GPIO_FLASH_MODE_CFG_EXT 0x0068 -#define GPIO51_FLASH_MODE_CFG BIT(31) -#define GPIO50_FLASH_MODE_CFG BIT(30) -#define GPIO49_FLASH_MODE_CFG BIT(29) -#define GPIO48_FLASH_MODE_CFG BIT(28) -#define GPIO47_FLASH_MODE_CFG BIT(27) -#define GPIO46_FLASH_MODE_CFG BIT(26) -#define GPIO45_FLASH_MODE_CFG BIT(25) -#define GPIO44_FLASH_MODE_CFG BIT(24) -#define GPIO43_FLASH_MODE_CFG BIT(23) -#define GPIO42_FLASH_MODE_CFG BIT(22) -#define GPIO41_FLASH_MODE_CFG BIT(21) -#define GPIO40_FLASH_MODE_CFG BIT(20) -#define GPIO39_FLASH_MODE_CFG BIT(19) -#define GPIO38_FLASH_MODE_CFG BIT(18) -#define GPIO37_FLASH_MODE_CFG BIT(17) -#define GPIO36_FLASH_MODE_CFG BIT(16) -#define GPIO31_FLASH_MODE_CFG BIT(15) -#define GPIO30_FLASH_MODE_CFG BIT(14) -#define GPIO29_FLASH_MODE_CFG BIT(13) -#define GPIO28_FLASH_MODE_CFG BIT(12) -#define GPIO27_FLASH_MODE_CFG BIT(11) -#define GPIO26_FLASH_MODE_CFG BIT(10) -#define GPIO25_FLASH_MODE_CFG BIT(9) -#define GPIO24_FLASH_MODE_CFG BIT(8) -#define GPIO23_FLASH_MODE_CFG BIT(7) -#define GPIO22_FLASH_MODE_CFG BIT(6) -#define GPIO21_FLASH_MODE_CFG BIT(5) -#define GPIO20_FLASH_MODE_CFG BIT(4) -#define GPIO19_FLASH_MODE_CFG BIT(3) -#define GPIO18_FLASH_MODE_CFG BIT(2) -#define GPIO17_FLASH_MODE_CFG BIT(1) -#define GPIO16_FLASH_MODE_CFG BIT(0) - -#define REG_GPIO_DATA1 0x0070 -#define REG_GPIO_OE1 0x0078 -#define REG_GPIO_INT1 0x007c -#define REG_GPIO_INT_EDGE1 0x0080 -#define REG_GPIO_INT_EDGE2 0x0084 -#define REG_GPIO_INT_EDGE3 0x0088 -#define REG_GPIO_INT_LEVEL1 0x008c -#define REG_GPIO_INT_LEVEL2 0x0090 -#define REG_GPIO_INT_LEVEL3 0x0094 - -#define AIROHA_NUM_PINS 64 -#define AIROHA_PIN_BANK_SIZE (AIROHA_NUM_PINS / 2) -#define AIROHA_REG_GPIOCTRL_NUM_PIN (AIROHA_NUM_PINS / 4) +#include "airoha-common.h" =20 static const u32 gpio_data_regs[] =3D { REG_GPIO_DATA, @@ -326,93 +43,6 @@ static const u32 irq_edge_regs[] =3D { REG_GPIO_INT_EDGE3 }; =20 -struct airoha_pinctrl_reg { - u32 offset; - u32 mask; -}; - -enum airoha_pinctrl_mux_func { - AIROHA_FUNC_MUX, - AIROHA_FUNC_PWM_MUX, - AIROHA_FUNC_PWM_EXT_MUX, -}; - -struct airoha_pinctrl_func_group { - const char *name; - struct { - enum airoha_pinctrl_mux_func mux; - u32 offset; - u32 mask; - u32 val; - } regmap[2]; - int regmap_size; -}; - -struct airoha_pinctrl_func { - const struct pinfunction desc; - const struct airoha_pinctrl_func_group *groups; - u8 group_size; -}; - -struct airoha_pinctrl_conf { - u32 pin; - struct airoha_pinctrl_reg reg; -}; - -struct airoha_pinctrl_gpiochip { - struct gpio_chip chip; - - /* gpio */ - const u32 *data; - const u32 *dir; - const u32 *out; - /* irq */ - const u32 *status; - const u32 *level; - const u32 *edge; - - u32 irq_type[AIROHA_NUM_PINS]; -}; - -struct airoha_pinctrl_confs_info { - const struct airoha_pinctrl_conf *confs; - unsigned int num_confs; -}; - -enum airoha_pinctrl_confs_type { - AIROHA_PINCTRL_CONFS_PULLUP, - AIROHA_PINCTRL_CONFS_PULLDOWN, - AIROHA_PINCTRL_CONFS_DRIVE_E2, - AIROHA_PINCTRL_CONFS_DRIVE_E4, - AIROHA_PINCTRL_CONFS_PCIE_RST_OD, - - AIROHA_PINCTRL_CONFS_MAX, -}; - -struct airoha_pinctrl { - struct pinctrl_dev *ctrl; - - struct pinctrl_desc desc; - const struct pingroup *grps; - const struct airoha_pinctrl_func *funcs; - const struct airoha_pinctrl_confs_info *confs_info; - - struct regmap *chip_scu; - struct regmap *regmap; - - struct airoha_pinctrl_gpiochip gpiochip; -}; - -struct airoha_pinctrl_match_data { - const struct pinctrl_pin_desc *pins; - const unsigned int num_pins; - const struct pingroup *grps; - const unsigned int num_grps; - const struct airoha_pinctrl_func *funcs; - const unsigned int num_funcs; - const struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MA= X]; -}; - static struct pinctrl_pin_desc en7581_pinctrl_pins[] =3D { PINCTRL_PIN(0, "uart1_txd"), PINCTRL_PIN(1, "uart1_rxd"), @@ -1458,31 +1088,6 @@ static const struct airoha_pinctrl_func_group an7583= _pcie_reset_func_group[] =3D { }, }; =20 -/* PWM */ -#define AIROHA_PINCTRL_PWM(gpio, mux_val) \ - { \ - .name =3D (gpio), \ - .regmap[0] =3D { \ - AIROHA_FUNC_PWM_MUX, \ - REG_GPIO_FLASH_MODE_CFG, \ - (mux_val), \ - (mux_val) \ - }, \ - .regmap_size =3D 1, \ - } \ - -#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \ - { \ - .name =3D (gpio), \ - .regmap[0] =3D { \ - AIROHA_FUNC_PWM_EXT_MUX, \ - REG_GPIO_FLASH_MODE_CFG_EXT, \ - (mux_val), \ - (mux_val) \ - }, \ - .regmap_size =3D 1, \ - } \ - static const struct airoha_pinctrl_func_group pwm_func_group[] =3D { AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG), AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG), @@ -1577,42 +1182,6 @@ static const struct airoha_pinctrl_func_group an7583= _pwm_func_group[] =3D { AIROHA_PINCTRL_PWM_EXT("gpio48", GPIO48_FLASH_MODE_CFG), }; =20 -#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \ - { \ - .name =3D (gpio), \ - .regmap[0] =3D { \ - AIROHA_FUNC_MUX, \ - REG_GPIO_2ND_I2C_MODE, \ - (mux_val), \ - (mux_val), \ - }, \ - .regmap[1] =3D { \ - AIROHA_FUNC_MUX, \ - REG_LAN_LED0_MAPPING, \ - (map_mask), \ - (map_val), \ - }, \ - .regmap_size =3D 2, \ - } - -#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \ - { \ - .name =3D (gpio), \ - .regmap[0] =3D { \ - AIROHA_FUNC_MUX, \ - REG_GPIO_2ND_I2C_MODE, \ - (mux_val), \ - (mux_val), \ - }, \ - .regmap[1] =3D { \ - AIROHA_FUNC_MUX, \ - REG_LAN_LED1_MAPPING, \ - (map_mask), \ - (map_val), \ - }, \ - .regmap_size =3D 2, \ - } - static const struct airoha_pinctrl_func_group phy1_led0_func_group[] =3D { AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), @@ -2679,37 +2248,6 @@ static int airoha_pinctrl_set_conf(struct airoha_pin= ctrl *pinctrl, return 0; } =20 -#define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val) \ - airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP, \ - (pin), (val)) -#define airoha_pinctrl_get_pulldown_conf(pinctrl, pin, val) \ - airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN, \ - (pin), (val)) -#define airoha_pinctrl_get_drive_e2_conf(pinctrl, pin, val) \ - airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2, \ - (pin), (val)) -#define airoha_pinctrl_get_drive_e4_conf(pinctrl, pin, val) \ - airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4, \ - (pin), (val)) -#define airoha_pinctrl_get_pcie_rst_od_conf(pinctrl, pin, val) \ - airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD, \ - (pin), (val)) -#define airoha_pinctrl_set_pullup_conf(pinctrl, pin, val) \ - airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP, \ - (pin), (val)) -#define airoha_pinctrl_set_pulldown_conf(pinctrl, pin, val) \ - airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN, \ - (pin), (val)) -#define airoha_pinctrl_set_drive_e2_conf(pinctrl, pin, val) \ - airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2, \ - (pin), (val)) -#define airoha_pinctrl_set_drive_e4_conf(pinctrl, pin, val) \ - airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4, \ - (pin), (val)) -#define airoha_pinctrl_set_pcie_rst_od_conf(pinctrl, pin, val) \ - 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X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 8d891be1-7bce-4216-9a99-bee9de02ba58 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: /avq3veus4KA8LXLOv3G/jAYyRWaYXa+8ZoqikDCkpKW2isRB9zdNmYbR/Uph/2O4LG6Zf8AKn3Go5Gu1LHj6Mw+/QjTVMql6ZAEyOnTcrY= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MRWPR08MB11707 Content-Type: text/plain; charset="utf-8" Split combined an7581/an7583 source file on a * shared pinctrl code (pinctrl-airoha.c) * an7581 specific pinctrl driver (pinctrl-an7581.c) * an7583 specific pinctrl driver (pinctrl-an7583.c) No functional changes. Signed-off-by: Mikhail Kshevetskiy --- drivers/pinctrl/airoha/Kconfig | 22 +- drivers/pinctrl/airoha/Makefile | 5 +- drivers/pinctrl/airoha/airoha-common.h | 2 + drivers/pinctrl/airoha/pinctrl-airoha.c | 1928 +---------------------- drivers/pinctrl/airoha/pinctrl-an7581.c | 1148 ++++++++++++++ drivers/pinctrl/airoha/pinctrl-an7583.c | 1078 +++++++++++++ 6 files changed, 2253 insertions(+), 1930 deletions(-) create mode 100644 drivers/pinctrl/airoha/pinctrl-an7581.c create mode 100644 drivers/pinctrl/airoha/pinctrl-an7583.c diff --git a/drivers/pinctrl/airoha/Kconfig b/drivers/pinctrl/airoha/Kconfig index fd84a04cb428..08038a5b11c6 100644 --- a/drivers/pinctrl/airoha/Kconfig +++ b/drivers/pinctrl/airoha/Kconfig @@ -1,10 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-only +menu "Airoha pinctrl drivers" + depends on ARCH_AIROHA || COMPILE_TEST =20 -# For ARMv8 SoCs config PINCTRL_AIROHA - tristate "Airoha AN7581/AN7583 pin control" + tristate "Airoha pin control" depends on OF - depends on ARM64 || COMPILE_TEST depends on ARCH_AIROHA || COMPILE_TEST select PINMUX select GENERIC_PINCONF @@ -13,6 +13,20 @@ config PINCTRL_AIROHA select GPIOLIB select GPIOLIB_IRQCHIP select REGMAP_MMIO + imply PINCTRL_AIROHA_AN7581 + imply PINCTRL_AIROHA_AN7583 help Say yes here to support pin controller and gpio driver - on Airoha EN7581/AN7583 SoC. + on Airoha SoC. + +config PINCTRL_AIROHA_AN7581 + tristate "AN7581 pinctrl" + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_AIROHA + +config PINCTRL_AIROHA_AN7583 + tristate "AN7583 pinctrl" + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_AIROHA + +endmenu diff --git a/drivers/pinctrl/airoha/Makefile b/drivers/pinctrl/airoha/Makef= ile index 009800406f5e..eac0f376b590 100644 --- a/drivers/pinctrl/airoha/Makefile +++ b/drivers/pinctrl/airoha/Makefile @@ -1,4 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 =20 # SoC Drivers -obj-$(CONFIG_PINCTRL_AIROHA) +=3D pinctrl-airoha.o +obj-$(CONFIG_PINCTRL_AIROHA) +=3D pinctrl-airoha.o + +obj-$(CONFIG_PINCTRL_AIROHA_AN7581) +=3D pinctrl-an7581.o +obj-$(CONFIG_PINCTRL_AIROHA_AN7583) +=3D pinctrl-an7583.o diff --git a/drivers/pinctrl/airoha/airoha-common.h b/drivers/pinctrl/airoh= a/airoha-common.h index 3d70002213bd..611194725757 100644 --- a/drivers/pinctrl/airoha/airoha-common.h +++ b/drivers/pinctrl/airoha/airoha-common.h @@ -476,4 +476,6 @@ struct airoha_pinctrl_match_data { const struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MA= X]; }; =20 +int airoha_pinctrl_probe(struct platform_device *pdev); + #endif diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airo= ha/pinctrl-airoha.c index 0b4bbcf08ec9..9a77495e703f 100644 --- a/drivers/pinctrl/airoha/pinctrl-airoha.c +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c @@ -43,1851 +43,6 @@ static const u32 irq_edge_regs[] =3D { REG_GPIO_INT_EDGE3 }; =20 -static struct pinctrl_pin_desc en7581_pinctrl_pins[] =3D { - PINCTRL_PIN(0, "uart1_txd"), - PINCTRL_PIN(1, "uart1_rxd"), - PINCTRL_PIN(2, "i2c_scl"), - PINCTRL_PIN(3, "i2c_sda"), - PINCTRL_PIN(4, "spi_cs0"), - PINCTRL_PIN(5, "spi_clk"), - PINCTRL_PIN(6, "spi_mosi"), - PINCTRL_PIN(7, "spi_miso"), - PINCTRL_PIN(13, "gpio0"), - PINCTRL_PIN(14, "gpio1"), - PINCTRL_PIN(15, "gpio2"), - PINCTRL_PIN(16, "gpio3"), - PINCTRL_PIN(17, "gpio4"), - PINCTRL_PIN(18, "gpio5"), - PINCTRL_PIN(19, "gpio6"), - PINCTRL_PIN(20, "gpio7"), - PINCTRL_PIN(21, "gpio8"), - PINCTRL_PIN(22, "gpio9"), - PINCTRL_PIN(23, "gpio10"), - PINCTRL_PIN(24, "gpio11"), - PINCTRL_PIN(25, "gpio12"), - PINCTRL_PIN(26, "gpio13"), - PINCTRL_PIN(27, "gpio14"), - PINCTRL_PIN(28, "gpio15"), - PINCTRL_PIN(29, "gpio16"), - PINCTRL_PIN(30, "gpio17"), - PINCTRL_PIN(31, "gpio18"), - PINCTRL_PIN(32, "gpio19"), - PINCTRL_PIN(33, "gpio20"), - PINCTRL_PIN(34, "gpio21"), - PINCTRL_PIN(35, "gpio22"), - PINCTRL_PIN(36, "gpio23"), - PINCTRL_PIN(37, "gpio24"), - PINCTRL_PIN(38, "gpio25"), - PINCTRL_PIN(39, "gpio26"), - PINCTRL_PIN(40, "gpio27"), - PINCTRL_PIN(41, "gpio28"), - PINCTRL_PIN(42, "gpio29"), - PINCTRL_PIN(43, "gpio30"), - PINCTRL_PIN(44, "gpio31"), - PINCTRL_PIN(45, "gpio32"), - PINCTRL_PIN(46, "gpio33"), - PINCTRL_PIN(47, "gpio34"), - PINCTRL_PIN(48, "gpio35"), - PINCTRL_PIN(49, "gpio36"), - PINCTRL_PIN(50, "gpio37"), - PINCTRL_PIN(51, "gpio38"), - PINCTRL_PIN(52, "gpio39"), - PINCTRL_PIN(53, "gpio40"), - PINCTRL_PIN(54, "gpio41"), - PINCTRL_PIN(55, "gpio42"), - PINCTRL_PIN(56, "gpio43"), - PINCTRL_PIN(57, "gpio44"), - PINCTRL_PIN(58, "gpio45"), - PINCTRL_PIN(59, "gpio46"), - PINCTRL_PIN(61, "pcie_reset0"), - PINCTRL_PIN(62, "pcie_reset1"), - PINCTRL_PIN(63, "pcie_reset2"), -}; - -static const int en7581_pon_pins[] =3D { 49, 50, 51, 52, 53, 54 }; -static const int en7581_pon_tod_1pps_pins[] =3D { 46 }; -static const int en7581_gsw_tod_1pps_pins[] =3D { 46 }; -static const int en7581_sipo_pins[] =3D { 16, 17 }; -static const int en7581_sipo_rclk_pins[] =3D { 16, 17, 43 }; -static const int en7581_mdio_pins[] =3D { 14, 15 }; -static const int en7581_uart2_pins[] =3D { 48, 55 }; -static const int en7581_uart2_cts_rts_pins[] =3D { 46, 47 }; -static const int en7581_hsuart_pins[] =3D { 28, 29 }; -static const int en7581_hsuart_cts_rts_pins[] =3D { 26, 27 }; -static const int en7581_uart4_pins[] =3D { 38, 39 }; -static const int en7581_uart5_pins[] =3D { 18, 19 }; -static const int en7581_i2c0_pins[] =3D { 2, 3 }; -static const int en7581_i2c1_pins[] =3D { 14, 15 }; -static const int en7581_jtag_udi_pins[] =3D { 16, 17, 18, 19, 20 }; -static const int en7581_jtag_dfd_pins[] =3D { 16, 17, 18, 19, 20 }; -static const int en7581_i2s_pins[] =3D { 26, 27, 28, 29 }; -static const int en7581_pcm1_pins[] =3D { 22, 23, 24, 25 }; -static const int en7581_pcm2_pins[] =3D { 18, 19, 20, 21 }; -static const int en7581_spi_quad_pins[] =3D { 32, 33 }; -static const int en7581_spi_pins[] =3D { 4, 5, 6, 7 }; -static const int en7581_spi_cs1_pins[] =3D { 34 }; -static const int en7581_pcm_spi_pins[] =3D { 18, 19, 20, 21, 22, 23, 24, 2= 5 }; -static const int en7581_pcm_spi_int_pins[] =3D { 14 }; -static const int en7581_pcm_spi_rst_pins[] =3D { 15 }; -static const int en7581_pcm_spi_cs1_pins[] =3D { 43 }; -static const int en7581_pcm_spi_cs2_pins[] =3D { 40 }; -static const int en7581_pcm_spi_cs2_p128_pins[] =3D { 40 }; -static const int en7581_pcm_spi_cs2_p156_pins[] =3D { 40 }; -static const int en7581_pcm_spi_cs3_pins[] =3D { 41 }; -static const int en7581_pcm_spi_cs4_pins[] =3D { 42 }; -static const int en7581_emmc_pins[] =3D { 4, 5, 6, 30, 31, 32, 33, 34, 35,= 36, 37 }; -static const int en7581_pnand_pins[] =3D { 4, 5, 6, 7, 30, 31, 32, 33, 34,= 35, 36, 37, 38, 39, 40, 41, 42 }; -static const int en7581_gpio0_pins[] =3D { 13 }; -static const int en7581_gpio1_pins[] =3D { 14 }; -static const int en7581_gpio2_pins[] =3D { 15 }; -static const int en7581_gpio3_pins[] =3D { 16 }; -static const int en7581_gpio4_pins[] =3D { 17 }; -static const int en7581_gpio5_pins[] =3D { 18 }; -static const int en7581_gpio6_pins[] =3D { 19 }; -static const int en7581_gpio7_pins[] =3D { 20 }; -static const int en7581_gpio8_pins[] =3D { 21 }; -static const int en7581_gpio9_pins[] =3D { 22 }; -static const int en7581_gpio10_pins[] =3D { 23 }; -static const int en7581_gpio11_pins[] =3D { 24 }; -static const int en7581_gpio12_pins[] =3D { 25 }; -static const int en7581_gpio13_pins[] =3D { 26 }; -static const int en7581_gpio14_pins[] =3D { 27 }; -static const int en7581_gpio15_pins[] =3D { 28 }; -static const int en7581_gpio16_pins[] =3D { 29 }; -static const int en7581_gpio17_pins[] =3D { 30 }; -static const int en7581_gpio18_pins[] =3D { 31 }; -static const int en7581_gpio19_pins[] =3D { 32 }; -static const int en7581_gpio20_pins[] =3D { 33 }; -static const int en7581_gpio21_pins[] =3D { 34 }; -static const int en7581_gpio22_pins[] =3D { 35 }; -static const int en7581_gpio23_pins[] =3D { 36 }; -static const int en7581_gpio24_pins[] =3D { 37 }; -static const int en7581_gpio25_pins[] =3D { 38 }; -static const int en7581_gpio26_pins[] =3D { 39 }; -static const int en7581_gpio27_pins[] =3D { 40 }; -static const int en7581_gpio28_pins[] =3D { 41 }; -static const int en7581_gpio29_pins[] =3D { 42 }; -static const int en7581_gpio30_pins[] =3D { 43 }; -static const int en7581_gpio31_pins[] =3D { 44 }; -static const int en7581_gpio32_pins[] =3D { 45 }; -static const int en7581_gpio33_pins[] =3D { 46 }; -static const int en7581_gpio34_pins[] =3D { 47 }; -static const int en7581_gpio35_pins[] =3D { 48 }; -static const int en7581_gpio36_pins[] =3D { 49 }; -static const int en7581_gpio37_pins[] =3D { 50 }; -static const int en7581_gpio38_pins[] =3D { 51 }; -static const int en7581_gpio39_pins[] =3D { 52 }; -static const int en7581_gpio40_pins[] =3D { 53 }; -static const int en7581_gpio41_pins[] =3D { 54 }; -static const int en7581_gpio42_pins[] =3D { 55 }; -static const int en7581_gpio43_pins[] =3D { 56 }; -static const int en7581_gpio44_pins[] =3D { 57 }; -static const int en7581_gpio45_pins[] =3D { 58 }; -static const int en7581_gpio46_pins[] =3D { 59 }; -static const int en7581_pcie_reset0_pins[] =3D { 61 }; -static const int en7581_pcie_reset1_pins[] =3D { 62 }; -static const int en7581_pcie_reset2_pins[] =3D { 63 }; - -static const struct pingroup en7581_pinctrl_groups[] =3D { - PINCTRL_PIN_GROUP("pon", en7581_pon), - PINCTRL_PIN_GROUP("pon_tod_1pps", en7581_pon_tod_1pps), - PINCTRL_PIN_GROUP("gsw_tod_1pps", en7581_gsw_tod_1pps), - PINCTRL_PIN_GROUP("sipo", en7581_sipo), - PINCTRL_PIN_GROUP("sipo_rclk", en7581_sipo_rclk), - PINCTRL_PIN_GROUP("mdio", en7581_mdio), - PINCTRL_PIN_GROUP("uart2", en7581_uart2), - PINCTRL_PIN_GROUP("uart2_cts_rts", en7581_uart2_cts_rts), - PINCTRL_PIN_GROUP("hsuart", en7581_hsuart), - PINCTRL_PIN_GROUP("hsuart_cts_rts", en7581_hsuart_cts_rts), - PINCTRL_PIN_GROUP("uart4", en7581_uart4), - PINCTRL_PIN_GROUP("uart5", en7581_uart5), - PINCTRL_PIN_GROUP("i2c0", en7581_i2c0), - PINCTRL_PIN_GROUP("i2c1", en7581_i2c1), - PINCTRL_PIN_GROUP("jtag_udi", en7581_jtag_udi), - PINCTRL_PIN_GROUP("jtag_dfd", en7581_jtag_dfd), - PINCTRL_PIN_GROUP("i2s", en7581_i2s), - PINCTRL_PIN_GROUP("pcm1", en7581_pcm1), - PINCTRL_PIN_GROUP("pcm2", en7581_pcm2), - PINCTRL_PIN_GROUP("spi", en7581_spi), - PINCTRL_PIN_GROUP("spi_quad", en7581_spi_quad), - PINCTRL_PIN_GROUP("spi_cs1", en7581_spi_cs1), - PINCTRL_PIN_GROUP("pcm_spi", en7581_pcm_spi), - PINCTRL_PIN_GROUP("pcm_spi_int", en7581_pcm_spi_int), - PINCTRL_PIN_GROUP("pcm_spi_rst", en7581_pcm_spi_rst), - PINCTRL_PIN_GROUP("pcm_spi_cs1", en7581_pcm_spi_cs1), - PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7581_pcm_spi_cs2_p128), - PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7581_pcm_spi_cs2_p156), - PINCTRL_PIN_GROUP("pcm_spi_cs2", en7581_pcm_spi_cs2), - PINCTRL_PIN_GROUP("pcm_spi_cs3", en7581_pcm_spi_cs3), - PINCTRL_PIN_GROUP("pcm_spi_cs4", en7581_pcm_spi_cs4), - PINCTRL_PIN_GROUP("emmc", en7581_emmc), - PINCTRL_PIN_GROUP("pnand", en7581_pnand), - PINCTRL_PIN_GROUP("gpio0", en7581_gpio0), - PINCTRL_PIN_GROUP("gpio1", en7581_gpio1), - PINCTRL_PIN_GROUP("gpio2", en7581_gpio2), - PINCTRL_PIN_GROUP("gpio3", en7581_gpio3), - PINCTRL_PIN_GROUP("gpio4", en7581_gpio4), - PINCTRL_PIN_GROUP("gpio5", en7581_gpio5), - PINCTRL_PIN_GROUP("gpio6", en7581_gpio6), - PINCTRL_PIN_GROUP("gpio7", en7581_gpio7), - PINCTRL_PIN_GROUP("gpio8", en7581_gpio8), - PINCTRL_PIN_GROUP("gpio9", en7581_gpio9), - PINCTRL_PIN_GROUP("gpio10", en7581_gpio10), - PINCTRL_PIN_GROUP("gpio11", en7581_gpio11), - PINCTRL_PIN_GROUP("gpio12", en7581_gpio12), - PINCTRL_PIN_GROUP("gpio13", en7581_gpio13), - PINCTRL_PIN_GROUP("gpio14", en7581_gpio14), - PINCTRL_PIN_GROUP("gpio15", en7581_gpio15), - PINCTRL_PIN_GROUP("gpio16", en7581_gpio16), - PINCTRL_PIN_GROUP("gpio17", en7581_gpio17), - PINCTRL_PIN_GROUP("gpio18", en7581_gpio18), - PINCTRL_PIN_GROUP("gpio19", en7581_gpio19), - PINCTRL_PIN_GROUP("gpio20", en7581_gpio20), - PINCTRL_PIN_GROUP("gpio21", en7581_gpio21), - PINCTRL_PIN_GROUP("gpio22", en7581_gpio22), - PINCTRL_PIN_GROUP("gpio23", en7581_gpio23), - PINCTRL_PIN_GROUP("gpio24", en7581_gpio24), - PINCTRL_PIN_GROUP("gpio25", en7581_gpio25), - PINCTRL_PIN_GROUP("gpio26", en7581_gpio26), - PINCTRL_PIN_GROUP("gpio27", en7581_gpio27), - PINCTRL_PIN_GROUP("gpio28", en7581_gpio28), - PINCTRL_PIN_GROUP("gpio29", en7581_gpio29), - PINCTRL_PIN_GROUP("gpio30", en7581_gpio30), - PINCTRL_PIN_GROUP("gpio31", en7581_gpio31), - PINCTRL_PIN_GROUP("gpio32", en7581_gpio32), - PINCTRL_PIN_GROUP("gpio33", en7581_gpio33), - PINCTRL_PIN_GROUP("gpio34", en7581_gpio34), - PINCTRL_PIN_GROUP("gpio35", en7581_gpio35), - PINCTRL_PIN_GROUP("gpio36", en7581_gpio36), - PINCTRL_PIN_GROUP("gpio37", en7581_gpio37), - PINCTRL_PIN_GROUP("gpio38", en7581_gpio38), - PINCTRL_PIN_GROUP("gpio39", en7581_gpio39), - PINCTRL_PIN_GROUP("gpio40", en7581_gpio40), - PINCTRL_PIN_GROUP("gpio41", en7581_gpio41), - PINCTRL_PIN_GROUP("gpio42", en7581_gpio42), - PINCTRL_PIN_GROUP("gpio43", en7581_gpio43), - PINCTRL_PIN_GROUP("gpio44", en7581_gpio44), - PINCTRL_PIN_GROUP("gpio45", en7581_gpio45), - PINCTRL_PIN_GROUP("gpio46", en7581_gpio46), - PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0), - PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1), - PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2), -}; - -static struct pinctrl_pin_desc an7583_pinctrl_pins[] =3D { - PINCTRL_PIN(2, "gpio0"), - PINCTRL_PIN(3, "gpio1"), - PINCTRL_PIN(4, "gpio2"), - PINCTRL_PIN(5, "gpio3"), - PINCTRL_PIN(6, "gpio4"), - PINCTRL_PIN(7, "gpio5"), - PINCTRL_PIN(8, "gpio6"), - PINCTRL_PIN(9, "gpio7"), - PINCTRL_PIN(10, "gpio8"), - PINCTRL_PIN(11, "gpio9"), - PINCTRL_PIN(12, "gpio10"), - PINCTRL_PIN(13, "gpio11"), - PINCTRL_PIN(14, "gpio12"), - PINCTRL_PIN(15, "gpio13"), - PINCTRL_PIN(16, "gpio14"), - PINCTRL_PIN(17, "gpio15"), - PINCTRL_PIN(18, "gpio16"), - PINCTRL_PIN(19, "gpio17"), - PINCTRL_PIN(20, "gpio18"), - PINCTRL_PIN(21, "gpio19"), - PINCTRL_PIN(22, "gpio20"), - PINCTRL_PIN(23, "gpio21"), - PINCTRL_PIN(24, "gpio22"), - PINCTRL_PIN(25, "gpio23"), - PINCTRL_PIN(26, "gpio24"), - PINCTRL_PIN(27, "gpio25"), - PINCTRL_PIN(28, "gpio26"), - PINCTRL_PIN(29, "gpio27"), - PINCTRL_PIN(30, "gpio28"), - PINCTRL_PIN(31, "gpio29"), - PINCTRL_PIN(32, "gpio30"), - PINCTRL_PIN(33, "gpio31"), - PINCTRL_PIN(34, "gpio32"), - PINCTRL_PIN(35, "gpio33"), - PINCTRL_PIN(36, "gpio34"), - PINCTRL_PIN(37, "gpio35"), - PINCTRL_PIN(38, "gpio36"), - PINCTRL_PIN(39, "gpio37"), - PINCTRL_PIN(40, "gpio38"), - PINCTRL_PIN(41, "i2c0_scl"), - PINCTRL_PIN(42, "i2c0_sda"), - PINCTRL_PIN(43, "i2c1_scl"), - PINCTRL_PIN(44, "i2c1_sda"), - PINCTRL_PIN(45, "spi_clk"), - PINCTRL_PIN(46, "spi_cs"), - PINCTRL_PIN(47, "spi_mosi"), - PINCTRL_PIN(48, "spi_miso"), - PINCTRL_PIN(49, "uart_txd"), - PINCTRL_PIN(50, "uart_rxd"), - PINCTRL_PIN(51, "pcie_reset0"), - PINCTRL_PIN(52, "pcie_reset1"), - PINCTRL_PIN(53, "mdc_0"), - PINCTRL_PIN(54, "mdio_0"), -}; - -static const int an7583_pon_pins[] =3D { 15, 16, 17, 18, 19, 20 }; -static const int an7583_pon_tod_1pps_pins[] =3D { 32 }; -static const int an7583_gsw_tod_1pps_pins[] =3D { 32 }; -static const int an7583_sipo_pins[] =3D { 34, 35 }; -static const int an7583_sipo_rclk_pins[] =3D { 34, 35, 33 }; -static const int an7583_mdio_pins[] =3D { 43, 44 }; -static const int an7583_uart2_pins[] =3D { 34, 35 }; -static const int an7583_uart2_cts_rts_pins[] =3D { 32, 33 }; -static const int an7583_hsuart_pins[] =3D { 30, 31 }; -static const int an7583_hsuart_cts_rts_pins[] =3D { 28, 29 }; -static const int an7583_npu_uart_pins[] =3D { 7, 8 }; -static const int an7583_uart4_pins[] =3D { 7, 8 }; -static const int an7583_uart5_pins[] =3D { 23, 24 }; -static const int an7583_i2c0_pins[] =3D { 41, 42 }; -static const int an7583_i2c1_pins[] =3D { 43, 44 }; -static const int an7583_jtag_udi_pins[] =3D { 23, 24, 22, 25, 26 }; -static const int an7583_jtag_dfd_pins[] =3D { 23, 24, 22, 25, 26 }; -static const int an7583_pcm1_pins[] =3D { 10, 11, 12, 13, 14 }; -static const int an7583_pcm2_pins[] =3D { 28, 29, 30, 31, 24 }; -static const int an7583_spi_pins[] =3D { 28, 29, 30, 31 }; -static const int an7583_spi_quad_pins[] =3D { 25, 26 }; -static const int an7583_spi_cs1_pins[] =3D { 27 }; -static const int an7583_pcm_spi_pins[] =3D { 28, 29, 30, 31, 10, 11, 12, 1= 3 }; -static const int an7583_pcm_spi_rst_pins[] =3D { 14 }; -static const int an7583_pcm_spi_cs1_pins[] =3D { 24 }; -static const int an7583_emmc_pins[] =3D { 7, 8, 9, 22, 23, 24, 25, 26, 45,= 46, 47 }; -static const int an7583_pnand_pins[] =3D { 7, 8, 9, 22, 23, 24, 25, 26, 27= , 28, 29, 30, 31, 45, 46, 47, 48 }; -static const int an7583_gpio0_pins[] =3D { 2 }; -static const int an7583_gpio1_pins[] =3D { 3 }; -static const int an7583_gpio2_pins[] =3D { 4 }; -static const int an7583_gpio3_pins[] =3D { 5 }; -static const int an7583_gpio4_pins[] =3D { 6 }; -static const int an7583_gpio5_pins[] =3D { 7 }; -static const int an7583_gpio6_pins[] =3D { 8 }; -static const int an7583_gpio7_pins[] =3D { 9 }; -static const int an7583_gpio8_pins[] =3D { 10 }; -static const int an7583_gpio9_pins[] =3D { 11 }; -static const int an7583_gpio10_pins[] =3D { 12 }; -static const int an7583_gpio11_pins[] =3D { 13 }; -static const int an7583_gpio12_pins[] =3D { 14 }; -static const int an7583_gpio13_pins[] =3D { 15 }; -static const int an7583_gpio14_pins[] =3D { 16 }; -static const int an7583_gpio15_pins[] =3D { 17 }; -static const int an7583_gpio16_pins[] =3D { 18 }; -static const int an7583_gpio17_pins[] =3D { 19 }; -static const int an7583_gpio18_pins[] =3D { 20 }; -static const int an7583_gpio19_pins[] =3D { 21 }; -static const int an7583_gpio20_pins[] =3D { 22 }; -static const int an7583_gpio21_pins[] =3D { 23 }; -static const int an7583_gpio22_pins[] =3D { 24 }; -static const int an7583_gpio23_pins[] =3D { 25 }; -static const int an7583_gpio24_pins[] =3D { 26 }; -static const int an7583_gpio25_pins[] =3D { 27 }; -static const int an7583_gpio26_pins[] =3D { 28 }; -static const int an7583_gpio27_pins[] =3D { 29 }; -static const int an7583_gpio28_pins[] =3D { 30 }; -static const int an7583_gpio29_pins[] =3D { 31 }; -static const int an7583_gpio30_pins[] =3D { 32 }; -static const int an7583_gpio31_pins[] =3D { 33 }; -static const int an7583_gpio32_pins[] =3D { 34 }; -static const int an7583_gpio33_pins[] =3D { 35 }; -static const int an7583_gpio34_pins[] =3D { 36 }; -static const int an7583_gpio35_pins[] =3D { 37 }; -static const int an7583_gpio36_pins[] =3D { 38 }; -static const int an7583_gpio37_pins[] =3D { 39 }; -static const int an7583_gpio38_pins[] =3D { 40 }; -static const int an7583_gpio39_pins[] =3D { 41 }; -static const int an7583_gpio40_pins[] =3D { 42 }; -static const int an7583_gpio41_pins[] =3D { 43 }; -static const int an7583_gpio42_pins[] =3D { 44 }; -static const int an7583_gpio43_pins[] =3D { 45 }; -static const int an7583_gpio44_pins[] =3D { 46 }; -static const int an7583_gpio45_pins[] =3D { 47 }; -static const int an7583_gpio46_pins[] =3D { 48 }; -static const int an7583_gpio47_pins[] =3D { 49 }; -static const int an7583_gpio48_pins[] =3D { 50 }; -static const int an7583_pcie_reset0_pins[] =3D { 51 }; -static const int an7583_pcie_reset1_pins[] =3D { 52 }; - -static const struct pingroup an7583_pinctrl_groups[] =3D { - PINCTRL_PIN_GROUP("pon", an7583_pon), - PINCTRL_PIN_GROUP("pon_tod_1pps", an7583_pon_tod_1pps), - PINCTRL_PIN_GROUP("gsw_tod_1pps", an7583_gsw_tod_1pps), - PINCTRL_PIN_GROUP("sipo", an7583_sipo), - PINCTRL_PIN_GROUP("sipo_rclk", an7583_sipo_rclk), - PINCTRL_PIN_GROUP("mdio", an7583_mdio), - PINCTRL_PIN_GROUP("uart2", an7583_uart2), - PINCTRL_PIN_GROUP("uart2_cts_rts", an7583_uart2_cts_rts), - PINCTRL_PIN_GROUP("hsuart", an7583_hsuart), - PINCTRL_PIN_GROUP("hsuart_cts_rts", an7583_hsuart_cts_rts), - PINCTRL_PIN_GROUP("npu_uart", an7583_npu_uart), - PINCTRL_PIN_GROUP("uart4", an7583_uart4), - PINCTRL_PIN_GROUP("uart5", an7583_uart5), - PINCTRL_PIN_GROUP("i2c0", an7583_i2c0), - PINCTRL_PIN_GROUP("i2c1", an7583_i2c1), - PINCTRL_PIN_GROUP("jtag_udi", an7583_jtag_udi), - PINCTRL_PIN_GROUP("jtag_dfd", an7583_jtag_dfd), - PINCTRL_PIN_GROUP("pcm1", an7583_pcm1), - PINCTRL_PIN_GROUP("pcm2", an7583_pcm2), - PINCTRL_PIN_GROUP("spi", an7583_spi), - PINCTRL_PIN_GROUP("spi_quad", an7583_spi_quad), - PINCTRL_PIN_GROUP("spi_cs1", an7583_spi_cs1), - PINCTRL_PIN_GROUP("pcm_spi", an7583_pcm_spi), - PINCTRL_PIN_GROUP("pcm_spi_rst", an7583_pcm_spi_rst), - PINCTRL_PIN_GROUP("pcm_spi_cs1", an7583_pcm_spi_cs1), - PINCTRL_PIN_GROUP("emmc", an7583_emmc), - PINCTRL_PIN_GROUP("pnand", an7583_pnand), - PINCTRL_PIN_GROUP("gpio0", an7583_gpio0), - PINCTRL_PIN_GROUP("gpio1", an7583_gpio1), - PINCTRL_PIN_GROUP("gpio2", an7583_gpio2), - PINCTRL_PIN_GROUP("gpio3", an7583_gpio3), - PINCTRL_PIN_GROUP("gpio4", an7583_gpio4), - PINCTRL_PIN_GROUP("gpio5", an7583_gpio5), - PINCTRL_PIN_GROUP("gpio6", an7583_gpio6), - PINCTRL_PIN_GROUP("gpio7", an7583_gpio7), - PINCTRL_PIN_GROUP("gpio8", an7583_gpio8), - PINCTRL_PIN_GROUP("gpio9", an7583_gpio9), - PINCTRL_PIN_GROUP("gpio10", an7583_gpio10), - PINCTRL_PIN_GROUP("gpio11", an7583_gpio11), - PINCTRL_PIN_GROUP("gpio12", an7583_gpio12), - PINCTRL_PIN_GROUP("gpio13", an7583_gpio13), - PINCTRL_PIN_GROUP("gpio14", an7583_gpio14), - PINCTRL_PIN_GROUP("gpio15", an7583_gpio15), - PINCTRL_PIN_GROUP("gpio16", an7583_gpio16), - PINCTRL_PIN_GROUP("gpio17", an7583_gpio17), - PINCTRL_PIN_GROUP("gpio18", an7583_gpio18), - PINCTRL_PIN_GROUP("gpio19", an7583_gpio19), - PINCTRL_PIN_GROUP("gpio20", an7583_gpio20), - PINCTRL_PIN_GROUP("gpio21", an7583_gpio21), - PINCTRL_PIN_GROUP("gpio22", an7583_gpio22), - PINCTRL_PIN_GROUP("gpio23", an7583_gpio23), - PINCTRL_PIN_GROUP("gpio24", an7583_gpio24), - PINCTRL_PIN_GROUP("gpio25", an7583_gpio25), - PINCTRL_PIN_GROUP("gpio26", an7583_gpio26), - PINCTRL_PIN_GROUP("gpio27", an7583_gpio27), - PINCTRL_PIN_GROUP("gpio28", an7583_gpio28), - PINCTRL_PIN_GROUP("gpio29", an7583_gpio29), - PINCTRL_PIN_GROUP("gpio30", an7583_gpio30), - PINCTRL_PIN_GROUP("gpio31", an7583_gpio31), - PINCTRL_PIN_GROUP("gpio32", an7583_gpio32), - PINCTRL_PIN_GROUP("gpio33", an7583_gpio33), - PINCTRL_PIN_GROUP("gpio34", an7583_gpio34), - PINCTRL_PIN_GROUP("gpio35", an7583_gpio35), - PINCTRL_PIN_GROUP("gpio36", an7583_gpio36), - PINCTRL_PIN_GROUP("gpio37", an7583_gpio37), - PINCTRL_PIN_GROUP("gpio38", an7583_gpio38), - PINCTRL_PIN_GROUP("gpio39", an7583_gpio39), - PINCTRL_PIN_GROUP("gpio40", an7583_gpio40), - PINCTRL_PIN_GROUP("gpio41", an7583_gpio41), - PINCTRL_PIN_GROUP("gpio42", an7583_gpio42), - PINCTRL_PIN_GROUP("gpio43", an7583_gpio43), - PINCTRL_PIN_GROUP("gpio44", an7583_gpio44), - PINCTRL_PIN_GROUP("gpio45", an7583_gpio45), - PINCTRL_PIN_GROUP("gpio46", an7583_gpio46), - PINCTRL_PIN_GROUP("gpio47", an7583_gpio47), - PINCTRL_PIN_GROUP("gpio48", an7583_gpio48), - PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0), - PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1), -}; - -static const char *const pon_groups[] =3D { "pon" }; -static const char *const tod_1pps_groups[] =3D { "pon_tod_1pps", "gsw_tod_= 1pps" }; -static const char *const sipo_groups[] =3D { "sipo", "sipo_rclk" }; -static const char *const mdio_groups[] =3D { "mdio" }; -static const char *const an7583_mdio_groups[] =3D { "mdio" }; -static const char *const uart_groups[] =3D { "uart2", "uart2_cts_rts", "hs= uart", - "hsuart_cts_rts", "uart4", - "uart5" }; -static const char *const i2c_groups[] =3D { "i2c1" }; -static const char *const jtag_groups[] =3D { "jtag_udi", "jtag_dfd" }; -static const char *const pcm_groups[] =3D { "pcm1", "pcm2" }; -static const char *const spi_groups[] =3D { "spi_quad", "spi_cs1" }; -static const char *const pcm_spi_groups[] =3D { "pcm_spi", "pcm_spi_int", - "pcm_spi_rst", "pcm_spi_cs1", - "pcm_spi_cs2_p156", - "pcm_spi_cs2_p128", - "pcm_spi_cs3", "pcm_spi_cs4" }; -static const char *const an7583_pcm_spi_groups[] =3D { "pcm_spi", - "pcm_spi_rst", "pcm_spi_cs1" }; -static const char *const i2s_groups[] =3D { "i2s" }; -static const char *const emmc_groups[] =3D { "emmc" }; -static const char *const pnand_groups[] =3D { "pnand" }; -static const char *const pcie_reset_groups[] =3D { "pcie_reset0", "pcie_re= set1", - "pcie_reset2" }; -static const char *const an7583_pcie_reset_groups[] =3D { "pcie_reset0", "= pcie_reset1" }; -static const char *const pwm_groups[] =3D { "gpio0", "gpio1", - "gpio2", "gpio3", - "gpio4", "gpio5", - "gpio6", "gpio7", - "gpio8", "gpio9", - "gpio10", "gpio11", - "gpio12", "gpio13", - "gpio14", "gpio15", - "gpio16", "gpio17", - "gpio18", "gpio19", - "gpio20", "gpio21", - "gpio22", "gpio23", - "gpio24", "gpio25", - "gpio26", "gpio27", - "gpio28", "gpio29", - "gpio30", "gpio31", - "gpio36", "gpio37", - "gpio38", "gpio39", - "gpio40", "gpio41", - "gpio42", "gpio43", - "gpio44", "gpio45", - "gpio46" }; -static const char *const an7583_pwm_groups[] =3D { "gpio0", "gpio1", - "gpio2", "gpio3", - "gpio4", "gpio5", - "gpio6", "gpio7", - "gpio8", "gpio9", - "gpio10", "gpio11", - "gpio12", "gpio13", - "gpio14", "gpio15", - "gpio16", "gpio17", - "gpio18", "gpio19", - "gpio20", "gpio21", - "gpio22", "gpio23", - "gpio24", "gpio25", - "gpio26", "gpio27", - "gpio28", "gpio29", - "gpio30", "gpio31", - "gpio36", "gpio37", - "gpio38", "gpio39", - "gpio40", "gpio41", - "gpio42", "gpio43", - "gpio44", "gpio45", - "gpio46", "gpio47", - "gpio48" }; -static const char *const phy1_led0_groups[] =3D { "gpio33", "gpio34", - "gpio35", "gpio42" }; -static const char *const phy2_led0_groups[] =3D { "gpio33", "gpio34", - "gpio35", "gpio42" }; -static const char *const phy3_led0_groups[] =3D { "gpio33", "gpio34", - "gpio35", "gpio42" }; -static const char *const phy4_led0_groups[] =3D { "gpio33", "gpio34", - "gpio35", "gpio42" }; -static const char *const phy1_led1_groups[] =3D { "gpio43", "gpio44", - "gpio45", "gpio46" }; -static const char *const phy2_led1_groups[] =3D { "gpio43", "gpio44", - "gpio45", "gpio46" }; -static const char *const phy3_led1_groups[] =3D { "gpio43", "gpio44", - "gpio45", "gpio46" }; -static const char *const phy4_led1_groups[] =3D { "gpio43", "gpio44", - "gpio45", "gpio46" }; -static const char *const an7583_phy1_led0_groups[] =3D { "gpio1", "gpio2", - "gpio3", "gpio4" }; -static const char *const an7583_phy2_led0_groups[] =3D { "gpio1", "gpio2", - "gpio3", "gpio4" }; -static const char *const an7583_phy3_led0_groups[] =3D { "gpio1", "gpio2", - "gpio3", "gpio4" }; -static const char *const an7583_phy4_led0_groups[] =3D { "gpio1", "gpio2", - "gpio3", "gpio4" }; -static const char *const an7583_phy1_led1_groups[] =3D { "gpio8", "gpio9", - "gpio10", "gpio11" }; -static const char *const an7583_phy2_led1_groups[] =3D { "gpio8", "gpio9", - "gpio10", "gpio11" }; -static const char *const an7583_phy3_led1_groups[] =3D { "gpio8", "gpio9", - "gpio10", "gpio11" }; -static const char *const an7583_phy4_led1_groups[] =3D { "gpio8", "gpio9", - "gpio10", "gpio11" }; - -static const struct airoha_pinctrl_func_group pon_func_group[] =3D { - { - .name =3D "pon", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_PON_MODE_MASK, - GPIO_PON_MODE_MASK - }, - .regmap_size =3D 1, - }, -}; - -static const struct airoha_pinctrl_func_group tod_1pps_func_group[] =3D { - { - .name =3D "pon_tod_1pps", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - PON_TOD_1PPS_MODE_MASK, - PON_TOD_1PPS_MODE_MASK - }, - .regmap_size =3D 1, - }, { - .name =3D "gsw_tod_1pps", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GSW_TOD_1PPS_MODE_MASK, - GSW_TOD_1PPS_MODE_MASK - }, - .regmap_size =3D 1, - }, -}; - -static const struct airoha_pinctrl_func_group sipo_func_group[] =3D { - { - .name =3D "sipo", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, - GPIO_SIPO_MODE_MASK - }, - .regmap_size =3D 1, - }, { - .name =3D "sipo_rclk", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, - GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK - }, - .regmap_size =3D 1, - }, -}; - -static const struct airoha_pinctrl_func_group mdio_func_group[] =3D { - { - .name =3D "mdio", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GPIO_MDC_IO_MASTER_MODE_MODE, - GPIO_MDC_IO_MASTER_MODE_MODE - }, - .regmap[1] =3D { - AIROHA_FUNC_MUX, - REG_FORCE_GPIO_EN, - FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2), - FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2) - }, - .regmap_size =3D 2, - }, -}; - -static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] =3D= { - { - .name =3D "mdio", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_SGMII_MDIO_MODE_MASK, - GPIO_SGMII_MDIO_MODE_MASK - }, - .regmap[1] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_MDC_IO_MASTER_MODE_MODE, - GPIO_MDC_IO_MASTER_MODE_MODE - }, - .regmap_size =3D 2, - }, -}; - -static const struct airoha_pinctrl_func_group uart_func_group[] =3D { - { - .name =3D "uart2", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_UART2_MODE_MASK, - GPIO_UART2_MODE_MASK - }, - .regmap_size =3D 1, - }, { - .name =3D "uart2_cts_rts", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK, - GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK - }, - .regmap_size =3D 1, - }, { - .name =3D "hsuart", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, - GPIO_HSUART_MODE_MASK - }, - .regmap_size =3D 1, - }, - { - .name =3D "hsuart_cts_rts", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, - GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK - }, - .regmap_size =3D 1, - }, { - .name =3D "uart4", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_UART4_MODE_MASK, - GPIO_UART4_MODE_MASK - }, - .regmap_size =3D 1, - }, { - .name =3D "uart5", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_UART5_MODE_MASK, - GPIO_UART5_MODE_MASK - }, - .regmap_size =3D 1, - }, -}; - -static const struct airoha_pinctrl_func_group i2c_func_group[] =3D { - { - .name =3D "i2c1", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GPIO_2ND_I2C_MODE_MASK, - GPIO_2ND_I2C_MODE_MASK - }, - .regmap_size =3D 1, - }, -}; - -static const struct airoha_pinctrl_func_group jtag_func_group[] =3D { - { - .name =3D "jtag_udi", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_NPU_UART_EN, - JTAG_UDI_EN_MASK, - JTAG_UDI_EN_MASK - }, - .regmap_size =3D 1, - }, { - .name =3D "jtag_dfd", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_NPU_UART_EN, - JTAG_DFD_EN_MASK, - JTAG_DFD_EN_MASK - }, - .regmap_size =3D 1, - }, -}; - -static const struct airoha_pinctrl_func_group pcm_func_group[] =3D { - { - .name =3D "pcm1", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM1_MODE_MASK, - GPIO_PCM1_MODE_MASK - }, - .regmap_size =3D 1, - }, { - .name =3D "pcm2", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM2_MODE_MASK, - GPIO_PCM2_MODE_MASK - }, - .regmap_size =3D 1, - }, -}; - -static const struct airoha_pinctrl_func_group spi_func_group[] =3D { - { - .name =3D "spi_quad", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_SPI_QUAD_MODE_MASK, - GPIO_SPI_QUAD_MODE_MASK - }, - .regmap_size =3D 1, - }, { - .name =3D "spi_cs1", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_SPI_CS1_MODE_MASK, - GPIO_SPI_CS1_MODE_MASK - }, - .regmap_size =3D 1, - }, { - .name =3D "spi_cs2", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_SPI_CS2_MODE_MASK, - GPIO_SPI_CS2_MODE_MASK - }, - .regmap_size =3D 1, - }, { - .name =3D "spi_cs3", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_SPI_CS3_MODE_MASK, - GPIO_SPI_CS3_MODE_MASK - }, - .regmap_size =3D 1, - }, { - .name =3D "spi_cs4", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_SPI_CS4_MODE_MASK, - GPIO_SPI_CS4_MODE_MASK - }, - .regmap_size =3D 1, - }, -}; - -static const struct airoha_pinctrl_func_group pcm_spi_func_group[] =3D { - { - .name =3D "pcm_spi", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_SPI_MODE_MASK, - GPIO_PCM_SPI_MODE_MASK - }, - .regmap_size =3D 1, - }, { - .name =3D "pcm_spi_int", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_INT_MODE_MASK, - GPIO_PCM_INT_MODE_MASK - }, - .regmap_size =3D 1, - }, { - .name =3D "pcm_spi_rst", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_RESET_MODE_MASK, - GPIO_PCM_RESET_MODE_MASK - }, - .regmap_size =3D 1, - }, { - .name =3D "pcm_spi_cs1", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_SPI_CS1_MODE_MASK, - GPIO_PCM_SPI_CS1_MODE_MASK - }, - .regmap_size =3D 1, - }, { - .name =3D "pcm_spi_cs2_p128", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_SPI_CS2_MODE_P128_MASK, - GPIO_PCM_SPI_CS2_MODE_P128_MASK - }, - .regmap_size =3D 1, - }, { - .name =3D "pcm_spi_cs2_p156", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_SPI_CS2_MODE_P156_MASK, - GPIO_PCM_SPI_CS2_MODE_P156_MASK - }, - .regmap_size =3D 1, - }, { - .name =3D "pcm_spi_cs3", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_SPI_CS3_MODE_MASK, - GPIO_PCM_SPI_CS3_MODE_MASK - }, - .regmap_size =3D 1, - }, { - .name =3D "pcm_spi_cs4", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_SPI_CS4_MODE_MASK, - GPIO_PCM_SPI_CS4_MODE_MASK - }, - .regmap_size =3D 1, - }, -}; - -static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[] = =3D { - { - .name =3D "pcm_spi", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_SPI_MODE_MASK, - GPIO_PCM_SPI_MODE_MASK - }, - .regmap_size =3D 1, - }, { - .name =3D "pcm_spi_int", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_INT_MODE_MASK, - GPIO_PCM_INT_MODE_MASK - }, - .regmap_size =3D 1, - }, { - .name =3D "pcm_spi_rst", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_RESET_MODE_MASK, - GPIO_PCM_RESET_MODE_MASK - }, - .regmap_size =3D 1, - }, { - .name =3D "pcm_spi_cs1", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_SPI_CS1_MODE_MASK, - GPIO_PCM_SPI_CS1_MODE_MASK - }, - .regmap_size =3D 1, - }, { - .name =3D "pcm_spi_cs2", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - AN7583_GPIO_PCM_SPI_CS2_MODE_MASK, - AN7583_GPIO_PCM_SPI_CS2_MODE_MASK - }, - .regmap_size =3D 1, - }, { - .name =3D "pcm_spi_cs3", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_SPI_CS3_MODE_MASK, - GPIO_PCM_SPI_CS3_MODE_MASK - }, - .regmap_size =3D 1, - }, { - .name =3D "pcm_spi_cs4", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_SPI_CS4_MODE_MASK, - GPIO_PCM_SPI_CS4_MODE_MASK - }, - .regmap_size =3D 1, - }, -}; - -static const struct airoha_pinctrl_func_group i2s_func_group[] =3D { - { - .name =3D "i2s", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GPIO_I2S_MODE_MASK, - GPIO_I2S_MODE_MASK - }, - .regmap_size =3D 1, - }, -}; - -static const struct airoha_pinctrl_func_group emmc_func_group[] =3D { - { - .name =3D "emmc", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_EMMC_MODE_MASK, - GPIO_EMMC_MODE_MASK - }, - .regmap_size =3D 1, - }, -}; - -static const struct airoha_pinctrl_func_group pnand_func_group[] =3D { - { - .name =3D "pnand", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_PARALLEL_NAND_MODE_MASK, - GPIO_PARALLEL_NAND_MODE_MASK - }, - .regmap_size =3D 1, - }, -}; - -static const struct airoha_pinctrl_func_group pcie_reset_func_group[] =3D { - { - .name =3D "pcie_reset0", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_PCIE_RESET0_MASK, - GPIO_PCIE_RESET0_MASK - }, - .regmap_size =3D 1, - }, { - .name =3D "pcie_reset1", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_PCIE_RESET1_MASK, - GPIO_PCIE_RESET1_MASK - }, - .regmap_size =3D 1, - }, { - .name =3D "pcie_reset2", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_PCIE_RESET2_MASK, - GPIO_PCIE_RESET2_MASK - }, - .regmap_size =3D 1, - }, -}; - -static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group= [] =3D { - { - .name =3D "pcie_reset0", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_PCIE_RESET0_MASK, - GPIO_PCIE_RESET0_MASK - }, - .regmap_size =3D 1, - }, { - .name =3D "pcie_reset1", - .regmap[0] =3D { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_PCIE_RESET1_MASK, - GPIO_PCIE_RESET1_MASK - }, - .regmap_size =3D 1, - }, -}; - -static const struct airoha_pinctrl_func_group pwm_func_group[] =3D { - AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG), -}; - -static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] =3D { - AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio47", GPIO47_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio48", GPIO48_FLASH_MODE_CFG), -}; - -static const struct airoha_pinctrl_func_group phy1_led0_func_group[] =3D { - AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), -}; - -static const struct airoha_pinctrl_func_group phy2_led0_func_group[] =3D { - AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), -}; - -static const struct airoha_pinctrl_func_group phy3_led0_func_group[] =3D { - AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), -}; - -static const struct airoha_pinctrl_func_group phy4_led0_func_group[] =3D { - AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), -}; - -static const struct airoha_pinctrl_func_group phy1_led1_func_group[] =3D { - AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), -}; - -static const struct airoha_pinctrl_func_group phy2_led1_func_group[] =3D { - AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), -}; - -static const struct airoha_pinctrl_func_group phy3_led1_func_group[] =3D { - AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), -}; - -static const struct airoha_pinctrl_func_group phy4_led1_func_group[] =3D { - AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), -}; - -static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[= ] =3D { - AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), -}; - -static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[= ] =3D { - AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), -}; - -static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[= ] =3D { - AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), -}; - -static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[= ] =3D { - AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), -}; - -static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[= ] =3D { - AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), -}; - -static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[= ] =3D { - AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), -}; - -static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[= ] =3D { - AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), -}; - -static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[= ] =3D { - AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), -}; - -static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] =3D { - PINCTRL_FUNC_DESC("pon", pon), - PINCTRL_FUNC_DESC("tod_1pps", tod_1pps), - PINCTRL_FUNC_DESC("sipo", sipo), - PINCTRL_FUNC_DESC("mdio", mdio), - PINCTRL_FUNC_DESC("uart", uart), - PINCTRL_FUNC_DESC("i2c", i2c), - PINCTRL_FUNC_DESC("jtag", jtag), - PINCTRL_FUNC_DESC("pcm", pcm), - PINCTRL_FUNC_DESC("spi", spi), - PINCTRL_FUNC_DESC("pcm_spi", pcm_spi), - PINCTRL_FUNC_DESC("i2s", i2s), - PINCTRL_FUNC_DESC("emmc", emmc), - PINCTRL_FUNC_DESC("pnand", pnand), - PINCTRL_FUNC_DESC("pcie_reset", pcie_reset), - PINCTRL_FUNC_DESC("pwm", pwm), - PINCTRL_FUNC_DESC("phy1_led0", phy1_led0), - PINCTRL_FUNC_DESC("phy2_led0", phy2_led0), - PINCTRL_FUNC_DESC("phy3_led0", phy3_led0), - PINCTRL_FUNC_DESC("phy4_led0", phy4_led0), - PINCTRL_FUNC_DESC("phy1_led1", phy1_led1), - PINCTRL_FUNC_DESC("phy2_led1", phy2_led1), - PINCTRL_FUNC_DESC("phy3_led1", phy3_led1), - PINCTRL_FUNC_DESC("phy4_led1", phy4_led1), -}; - -static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] =3D { - PINCTRL_FUNC_DESC("pon", pon), - PINCTRL_FUNC_DESC("tod_1pps", tod_1pps), - PINCTRL_FUNC_DESC("sipo", sipo), - PINCTRL_FUNC_DESC("mdio", an7583_mdio), - PINCTRL_FUNC_DESC("uart", uart), - PINCTRL_FUNC_DESC("i2c", i2c), - PINCTRL_FUNC_DESC("jtag", jtag), - PINCTRL_FUNC_DESC("pcm", pcm), - PINCTRL_FUNC_DESC("spi", spi), - PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi), - PINCTRL_FUNC_DESC("emmc", emmc), - PINCTRL_FUNC_DESC("pnand", pnand), - PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset), - PINCTRL_FUNC_DESC("pwm", an7583_pwm), - PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0), - PINCTRL_FUNC_DESC("phy2_led0", an7583_phy2_led0), - PINCTRL_FUNC_DESC("phy3_led0", an7583_phy3_led0), - PINCTRL_FUNC_DESC("phy4_led0", an7583_phy4_led0), - PINCTRL_FUNC_DESC("phy1_led1", an7583_phy1_led1), - PINCTRL_FUNC_DESC("phy2_led1", an7583_phy2_led1), - PINCTRL_FUNC_DESC("phy3_led1", an7583_phy3_led1), - PINCTRL_FUNC_DESC("phy4_led1", an7583_phy4_led1), -}; - -static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] =3D { - PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK), - PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK), - PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK), - PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SCL_PU_MASK), - PINCTRL_CONF_DESC(4, REG_I2C_SDA_PU, SPI_CS0_PU_MASK), - PINCTRL_CONF_DESC(5, REG_I2C_SDA_PU, SPI_CLK_PU_MASK), - PINCTRL_CONF_DESC(6, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK), - PINCTRL_CONF_DESC(7, REG_I2C_SDA_PU, SPI_MISO_PU_MASK), - PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(0)), - PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(1)), - PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(2)), - PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(3)), - PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(4)), - PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(5)), - PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(6)), - PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(7)), - PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(8)), - PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(9)), - PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(10)), - PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(11)), - PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(12)), - PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(13)), - PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(14)), - PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(15)), - PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(16)), - PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(17)), - PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(18)), - PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(19)), - PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(20)), - PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(21)), - PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(22)), - PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(23)), - PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(24)), - PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(25)), - PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(26)), - PINCTRL_CONF_DESC(40, REG_GPIO_L_PU, BIT(27)), - PINCTRL_CONF_DESC(41, REG_GPIO_L_PU, BIT(28)), - PINCTRL_CONF_DESC(42, REG_GPIO_L_PU, BIT(29)), - PINCTRL_CONF_DESC(43, REG_GPIO_L_PU, BIT(30)), - PINCTRL_CONF_DESC(44, REG_GPIO_L_PU, BIT(31)), - PINCTRL_CONF_DESC(45, REG_GPIO_H_PU, BIT(0)), - PINCTRL_CONF_DESC(46, REG_GPIO_H_PU, BIT(1)), - PINCTRL_CONF_DESC(47, REG_GPIO_H_PU, BIT(2)), - PINCTRL_CONF_DESC(48, REG_GPIO_H_PU, BIT(3)), - PINCTRL_CONF_DESC(49, REG_GPIO_H_PU, BIT(4)), - PINCTRL_CONF_DESC(50, REG_GPIO_H_PU, BIT(5)), - PINCTRL_CONF_DESC(51, REG_GPIO_H_PU, BIT(6)), - PINCTRL_CONF_DESC(52, REG_GPIO_H_PU, BIT(7)), - PINCTRL_CONF_DESC(53, REG_GPIO_H_PU, BIT(8)), - PINCTRL_CONF_DESC(54, REG_GPIO_H_PU, BIT(9)), - PINCTRL_CONF_DESC(55, REG_GPIO_H_PU, BIT(10)), - PINCTRL_CONF_DESC(56, REG_GPIO_H_PU, BIT(11)), - PINCTRL_CONF_DESC(57, REG_GPIO_H_PU, BIT(12)), - PINCTRL_CONF_DESC(58, REG_GPIO_H_PU, BIT(13)), - PINCTRL_CONF_DESC(59, REG_GPIO_H_PU, BIT(14)), - PINCTRL_CONF_DESC(61, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK), - PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK), - PINCTRL_CONF_DESC(63, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK), -}; - -static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] =3D { - PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)), - PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)), - PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)), - PINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(3)), - PINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(4)), - PINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(5)), - PINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(6)), - PINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(7)), - PINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(8)), - PINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(9)), - PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(10)), - PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(11)), - PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(12)), - PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(13)), - PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(14)), - PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(15)), - PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(16)), - PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(17)), - PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(18)), - PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(19)), - PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(20)), - PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(21)), - PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(22)), - PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(23)), - PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(24)), - PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(25)), - PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(26)), - PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(27)), - PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(28)), - PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(29)), - PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(30)), - PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(31)), - PINCTRL_CONF_DESC(34, REG_GPIO_H_PU, BIT(0)), - PINCTRL_CONF_DESC(35, REG_GPIO_H_PU, BIT(1)), - PINCTRL_CONF_DESC(36, REG_GPIO_H_PU, BIT(2)), - PINCTRL_CONF_DESC(37, REG_GPIO_H_PU, BIT(3)), - PINCTRL_CONF_DESC(38, REG_GPIO_H_PU, BIT(4)), - PINCTRL_CONF_DESC(39, REG_GPIO_H_PU, BIT(5)), - PINCTRL_CONF_DESC(40, REG_GPIO_H_PU, BIT(6)), - PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, I2C_SCL_PU_MASK), - PINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_PU_MASK), - PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, AN7583_I2C1_SCL_PU_MASK), - PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, AN7583_I2C1_SDA_PU_MASK), - PINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, SPI_CLK_PU_MASK), - PINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_PU_MASK), - PINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK), - PINCTRL_CONF_DESC(48, REG_I2C_SDA_PU, SPI_MISO_PU_MASK), - PINCTRL_CONF_DESC(49, REG_I2C_SDA_PU, UART1_TXD_PU_MASK), - PINCTRL_CONF_DESC(50, REG_I2C_SDA_PU, UART1_RXD_PU_MASK), - PINCTRL_CONF_DESC(51, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK), - PINCTRL_CONF_DESC(52, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK), - PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, AN7583_MDC_0_PU_MASK), - PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, AN7583_MDIO_0_PU_MASK), -}; - -static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] =3D= { - PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK), - PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK), - PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK), - PINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SCL_PD_MASK), - PINCTRL_CONF_DESC(4, REG_I2C_SDA_PD, SPI_CS0_PD_MASK), - PINCTRL_CONF_DESC(5, REG_I2C_SDA_PD, SPI_CLK_PD_MASK), - PINCTRL_CONF_DESC(6, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK), - PINCTRL_CONF_DESC(7, REG_I2C_SDA_PD, SPI_MISO_PD_MASK), - PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(0)), - PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(1)), - PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(2)), - PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(3)), - PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(4)), - PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(5)), - PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(6)), - PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(7)), - PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(8)), - PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(9)), - PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(10)), - PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(11)), - PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(12)), - PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(13)), - PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(14)), - PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(15)), - PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(16)), - PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(17)), - PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(18)), - PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(19)), - PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(20)), - PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(21)), - PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(22)), - PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(23)), - PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(24)), - PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(25)), - PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(26)), - PINCTRL_CONF_DESC(40, REG_GPIO_L_PD, BIT(27)), - PINCTRL_CONF_DESC(41, REG_GPIO_L_PD, BIT(28)), - PINCTRL_CONF_DESC(42, REG_GPIO_L_PD, BIT(29)), - PINCTRL_CONF_DESC(43, REG_GPIO_L_PD, BIT(30)), - PINCTRL_CONF_DESC(44, REG_GPIO_L_PD, BIT(31)), - PINCTRL_CONF_DESC(45, REG_GPIO_H_PD, BIT(0)), - PINCTRL_CONF_DESC(46, REG_GPIO_H_PD, BIT(1)), - PINCTRL_CONF_DESC(47, REG_GPIO_H_PD, BIT(2)), - PINCTRL_CONF_DESC(48, REG_GPIO_H_PD, BIT(3)), - PINCTRL_CONF_DESC(49, REG_GPIO_H_PD, BIT(4)), - PINCTRL_CONF_DESC(50, REG_GPIO_H_PD, BIT(5)), - PINCTRL_CONF_DESC(51, REG_GPIO_H_PD, BIT(6)), - PINCTRL_CONF_DESC(52, REG_GPIO_H_PD, BIT(7)), - PINCTRL_CONF_DESC(53, REG_GPIO_H_PD, BIT(8)), - PINCTRL_CONF_DESC(54, REG_GPIO_H_PD, BIT(9)), - PINCTRL_CONF_DESC(55, REG_GPIO_H_PD, BIT(10)), - PINCTRL_CONF_DESC(56, REG_GPIO_H_PD, BIT(11)), - PINCTRL_CONF_DESC(57, REG_GPIO_H_PD, BIT(12)), - PINCTRL_CONF_DESC(58, REG_GPIO_H_PD, BIT(13)), - PINCTRL_CONF_DESC(59, REG_GPIO_H_PD, BIT(14)), - PINCTRL_CONF_DESC(61, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK), - PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK), - PINCTRL_CONF_DESC(63, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK), -}; - -static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] =3D= { - PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)), - PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)), - PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)), - PINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(3)), - PINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(4)), - PINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(5)), - PINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(6)), - PINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(7)), - PINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(8)), - PINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(9)), - PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(10)), - PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(11)), - PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(12)), - PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(13)), - PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(14)), - PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(15)), - PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(16)), - PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(17)), - PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(18)), - PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(19)), - PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(20)), - PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(21)), - PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(22)), - PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(23)), - PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(24)), - PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(25)), - PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(26)), - PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(27)), - PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(28)), - PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(29)), - PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(30)), - PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(31)), - PINCTRL_CONF_DESC(34, REG_GPIO_H_PD, BIT(0)), - PINCTRL_CONF_DESC(35, REG_GPIO_H_PD, BIT(1)), - PINCTRL_CONF_DESC(36, REG_GPIO_H_PD, BIT(2)), - PINCTRL_CONF_DESC(37, REG_GPIO_H_PD, BIT(3)), - PINCTRL_CONF_DESC(38, REG_GPIO_H_PD, BIT(4)), - PINCTRL_CONF_DESC(39, REG_GPIO_H_PD, BIT(5)), - PINCTRL_CONF_DESC(40, REG_GPIO_H_PD, BIT(6)), - PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, I2C_SCL_PD_MASK), - PINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_PD_MASK), - PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, AN7583_I2C1_SCL_PD_MASK), - PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, AN7583_I2C1_SDA_PD_MASK), - PINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, SPI_CLK_PD_MASK), - PINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_PD_MASK), - PINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK), - PINCTRL_CONF_DESC(48, REG_I2C_SDA_PD, SPI_MISO_PD_MASK), - PINCTRL_CONF_DESC(49, REG_I2C_SDA_PD, UART1_TXD_PD_MASK), - PINCTRL_CONF_DESC(50, REG_I2C_SDA_PD, UART1_RXD_PD_MASK), - PINCTRL_CONF_DESC(51, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK), - PINCTRL_CONF_DESC(52, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK), - PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, AN7583_MDC_0_PD_MASK), - PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, AN7583_MDIO_0_PD_MASK), -}; - -static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] =3D= { - PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK), - PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK), - PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK), - PINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SCL_E2_MASK), - PINCTRL_CONF_DESC(4, REG_I2C_SDA_E2, SPI_CS0_E2_MASK), - PINCTRL_CONF_DESC(5, REG_I2C_SDA_E2, SPI_CLK_E2_MASK), - PINCTRL_CONF_DESC(6, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK), - PINCTRL_CONF_DESC(7, REG_I2C_SDA_E2, SPI_MISO_E2_MASK), - PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(0)), - PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(1)), - PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(2)), - PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(3)), - PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(4)), - PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(5)), - PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(6)), - PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(7)), - PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(8)), - PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(9)), - PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(10)), - PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(11)), - PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(12)), - PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(13)), - PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(14)), - PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(15)), - PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(16)), - PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(17)), - PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(18)), - PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(19)), - PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(20)), - PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(21)), - PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(22)), - PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(23)), - PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(24)), - PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(25)), - PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(26)), - PINCTRL_CONF_DESC(40, REG_GPIO_L_E2, BIT(27)), - PINCTRL_CONF_DESC(41, REG_GPIO_L_E2, BIT(28)), - PINCTRL_CONF_DESC(42, REG_GPIO_L_E2, BIT(29)), - PINCTRL_CONF_DESC(43, REG_GPIO_L_E2, BIT(30)), - PINCTRL_CONF_DESC(44, REG_GPIO_L_E2, BIT(31)), - PINCTRL_CONF_DESC(45, REG_GPIO_H_E2, BIT(0)), - PINCTRL_CONF_DESC(46, REG_GPIO_H_E2, BIT(1)), - PINCTRL_CONF_DESC(47, REG_GPIO_H_E2, BIT(2)), - PINCTRL_CONF_DESC(48, REG_GPIO_H_E2, BIT(3)), - PINCTRL_CONF_DESC(49, REG_GPIO_H_E2, BIT(4)), - PINCTRL_CONF_DESC(50, REG_GPIO_H_E2, BIT(5)), - PINCTRL_CONF_DESC(51, REG_GPIO_H_E2, BIT(6)), - PINCTRL_CONF_DESC(52, REG_GPIO_H_E2, BIT(7)), - PINCTRL_CONF_DESC(53, REG_GPIO_H_E2, BIT(8)), - PINCTRL_CONF_DESC(54, REG_GPIO_H_E2, BIT(9)), - PINCTRL_CONF_DESC(55, REG_GPIO_H_E2, BIT(10)), - PINCTRL_CONF_DESC(56, REG_GPIO_H_E2, BIT(11)), - PINCTRL_CONF_DESC(57, REG_GPIO_H_E2, BIT(12)), - PINCTRL_CONF_DESC(58, REG_GPIO_H_E2, BIT(13)), - PINCTRL_CONF_DESC(59, REG_GPIO_H_E2, BIT(14)), - PINCTRL_CONF_DESC(61, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK), - PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK), - PINCTRL_CONF_DESC(63, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK), -}; - -static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] =3D= { - PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)), - PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)), - PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)), - PINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(3)), - PINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(4)), - PINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(5)), - PINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(6)), - PINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(7)), - PINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(8)), - PINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(9)), - PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(10)), - PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(11)), - PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(12)), - PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(13)), - PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(14)), - PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(15)), - PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(16)), - PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(17)), - PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(18)), - PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(19)), - PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(20)), - PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(21)), - PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(22)), - PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(23)), - PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(24)), - PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(25)), - PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(26)), - PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(27)), - PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(28)), - PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(29)), - PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(30)), - PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(31)), - PINCTRL_CONF_DESC(34, REG_GPIO_H_E2, BIT(0)), - PINCTRL_CONF_DESC(35, REG_GPIO_H_E2, BIT(1)), - PINCTRL_CONF_DESC(36, REG_GPIO_H_E2, BIT(2)), - PINCTRL_CONF_DESC(37, REG_GPIO_H_E2, BIT(3)), - PINCTRL_CONF_DESC(38, REG_GPIO_H_E2, BIT(4)), - PINCTRL_CONF_DESC(39, REG_GPIO_H_E2, BIT(5)), - PINCTRL_CONF_DESC(40, REG_GPIO_H_E2, BIT(6)), - PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, I2C_SCL_E2_MASK), - PINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_E2_MASK), - PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, AN7583_I2C1_SCL_E2_MASK), - PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, AN7583_I2C1_SDA_E2_MASK), - PINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, SPI_CLK_E2_MASK), - PINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_E2_MASK), - PINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK), - PINCTRL_CONF_DESC(48, REG_I2C_SDA_E2, SPI_MISO_E2_MASK), - PINCTRL_CONF_DESC(49, REG_I2C_SDA_E2, UART1_TXD_E2_MASK), - PINCTRL_CONF_DESC(50, REG_I2C_SDA_E2, UART1_RXD_E2_MASK), - PINCTRL_CONF_DESC(51, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK), - PINCTRL_CONF_DESC(52, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK), - PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, AN7583_MDC_0_E2_MASK), - PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, AN7583_MDIO_0_E2_MASK), -}; - -static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] =3D= { - PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK), - PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK), - PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK), - PINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SCL_E4_MASK), - PINCTRL_CONF_DESC(4, REG_I2C_SDA_E4, SPI_CS0_E4_MASK), - PINCTRL_CONF_DESC(5, REG_I2C_SDA_E4, SPI_CLK_E4_MASK), - PINCTRL_CONF_DESC(6, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK), - PINCTRL_CONF_DESC(7, REG_I2C_SDA_E4, SPI_MISO_E4_MASK), - PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(0)), - PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(1)), - PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(2)), - PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(3)), - PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(4)), - PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(5)), - PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(6)), - PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(7)), - PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(8)), - PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(9)), - PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(10)), - PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(11)), - PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(12)), - PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(13)), - PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(14)), - PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(15)), - PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(16)), - PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(17)), - PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(18)), - PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(19)), - PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(20)), - PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(21)), - PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(22)), - PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(23)), - PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(24)), - PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(25)), - PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(26)), - PINCTRL_CONF_DESC(40, REG_GPIO_L_E4, BIT(27)), - PINCTRL_CONF_DESC(41, REG_GPIO_L_E4, BIT(28)), - PINCTRL_CONF_DESC(42, REG_GPIO_L_E4, BIT(29)), - PINCTRL_CONF_DESC(43, REG_GPIO_L_E4, BIT(30)), - PINCTRL_CONF_DESC(44, REG_GPIO_L_E4, BIT(31)), - PINCTRL_CONF_DESC(45, REG_GPIO_H_E4, BIT(0)), - PINCTRL_CONF_DESC(46, REG_GPIO_H_E4, BIT(1)), - PINCTRL_CONF_DESC(47, REG_GPIO_H_E4, BIT(2)), - PINCTRL_CONF_DESC(48, REG_GPIO_H_E4, BIT(3)), - PINCTRL_CONF_DESC(49, REG_GPIO_H_E4, BIT(4)), - PINCTRL_CONF_DESC(50, REG_GPIO_H_E4, BIT(5)), - PINCTRL_CONF_DESC(51, REG_GPIO_H_E4, BIT(6)), - PINCTRL_CONF_DESC(52, REG_GPIO_H_E4, BIT(7)), - PINCTRL_CONF_DESC(53, REG_GPIO_H_E4, BIT(8)), - PINCTRL_CONF_DESC(54, REG_GPIO_H_E4, BIT(9)), - PINCTRL_CONF_DESC(55, REG_GPIO_H_E4, BIT(10)), - PINCTRL_CONF_DESC(56, REG_GPIO_H_E4, BIT(11)), - PINCTRL_CONF_DESC(57, REG_GPIO_H_E4, BIT(12)), - PINCTRL_CONF_DESC(58, REG_GPIO_H_E4, BIT(13)), - PINCTRL_CONF_DESC(59, REG_GPIO_H_E4, BIT(14)), - PINCTRL_CONF_DESC(61, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK), - PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK), - PINCTRL_CONF_DESC(63, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK), -}; - -static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] =3D= { - PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)), - PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)), - PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)), - PINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(3)), - PINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(4)), - PINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(5)), - PINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(6)), - PINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(7)), - PINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(8)), - PINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(9)), - PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(10)), - PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(11)), - PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(12)), - PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(13)), - PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(14)), - PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(15)), - PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(16)), - PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(17)), - PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(18)), - PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(19)), - PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(20)), - PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(21)), - PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(22)), - PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(23)), - PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(24)), - PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(25)), - PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(26)), - PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(27)), - PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(28)), - PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(29)), - PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(30)), - PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(31)), - PINCTRL_CONF_DESC(34, REG_GPIO_H_E4, BIT(0)), - PINCTRL_CONF_DESC(35, REG_GPIO_H_E4, BIT(1)), - PINCTRL_CONF_DESC(36, REG_GPIO_H_E4, BIT(2)), - PINCTRL_CONF_DESC(37, REG_GPIO_H_E4, BIT(3)), - PINCTRL_CONF_DESC(38, REG_GPIO_H_E4, BIT(4)), - PINCTRL_CONF_DESC(39, REG_GPIO_H_E4, BIT(5)), - PINCTRL_CONF_DESC(40, REG_GPIO_H_E4, BIT(6)), - PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, I2C_SCL_E4_MASK), - PINCTRL_CONF_DESC(42, REG_I2C_SDA_E4, I2C_SDA_E4_MASK), - PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, AN7583_I2C1_SCL_E4_MASK), - PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, AN7583_I2C1_SDA_E4_MASK), - PINCTRL_CONF_DESC(45, REG_I2C_SDA_E4, SPI_CLK_E4_MASK), - PINCTRL_CONF_DESC(46, REG_I2C_SDA_E4, SPI_CS0_E4_MASK), - PINCTRL_CONF_DESC(47, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK), - PINCTRL_CONF_DESC(48, REG_I2C_SDA_E4, SPI_MISO_E4_MASK), - PINCTRL_CONF_DESC(49, REG_I2C_SDA_E4, UART1_TXD_E4_MASK), - PINCTRL_CONF_DESC(50, REG_I2C_SDA_E4, UART1_RXD_E4_MASK), - PINCTRL_CONF_DESC(51, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK), - PINCTRL_CONF_DESC(52, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK), - PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, AN7583_MDC_0_E4_MASK), - PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, AN7583_MDIO_0_E4_MASK), -}; - -static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = =3D { - PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK), - PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK), - PINCTRL_CONF_DESC(63, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK), -}; - -static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[] = =3D { - PINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK), - PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK), -}; - static int airoha_convert_pin_to_reg_offset(struct pinctrl_dev *pctrl_dev, struct pinctrl_gpio_range *range, int pin) @@ -2478,7 +633,7 @@ static const struct pinctrl_ops airoha_pctlops =3D { .dt_free_map =3D pinconf_generic_dt_free_map, }; =20 -static int airoha_pinctrl_probe(struct platform_device *pdev) +int airoha_pinctrl_probe(struct platform_device *pdev) { const struct airoha_pinctrl_match_data *data; struct device *dev =3D &pdev->dev; @@ -2556,87 +711,10 @@ static int airoha_pinctrl_probe(struct platform_devi= ce *pdev) /* build gpio-chip */ return airoha_pinctrl_add_gpiochip(pinctrl, pdev); } - -static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = =3D { - .pins =3D en7581_pinctrl_pins, - .num_pins =3D ARRAY_SIZE(en7581_pinctrl_pins), - .grps =3D en7581_pinctrl_groups, - .num_grps =3D ARRAY_SIZE(en7581_pinctrl_groups), - .funcs =3D en7581_pinctrl_funcs, - .num_funcs =3D ARRAY_SIZE(en7581_pinctrl_funcs), - .confs_info =3D { - [AIROHA_PINCTRL_CONFS_PULLUP] =3D { - .confs =3D en7581_pinctrl_pullup_conf, - .num_confs =3D ARRAY_SIZE(en7581_pinctrl_pullup_conf), - }, - [AIROHA_PINCTRL_CONFS_PULLDOWN] =3D { - .confs =3D en7581_pinctrl_pulldown_conf, - .num_confs =3D ARRAY_SIZE(en7581_pinctrl_pulldown_conf), - }, - [AIROHA_PINCTRL_CONFS_DRIVE_E2] =3D { - .confs =3D en7581_pinctrl_drive_e2_conf, - .num_confs =3D ARRAY_SIZE(en7581_pinctrl_drive_e2_conf), - }, - [AIROHA_PINCTRL_CONFS_DRIVE_E4] =3D { - .confs =3D en7581_pinctrl_drive_e4_conf, - .num_confs =3D ARRAY_SIZE(en7581_pinctrl_drive_e4_conf), - }, - [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] =3D { - .confs =3D en7581_pinctrl_pcie_rst_od_conf, - .num_confs =3D ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf), - }, - }, -}; - -static const struct airoha_pinctrl_match_data an7583_pinctrl_match_data = =3D { - .pins =3D an7583_pinctrl_pins, - .num_pins =3D ARRAY_SIZE(an7583_pinctrl_pins), - .grps =3D an7583_pinctrl_groups, - .num_grps =3D ARRAY_SIZE(an7583_pinctrl_groups), - .funcs =3D an7583_pinctrl_funcs, - .num_funcs =3D ARRAY_SIZE(an7583_pinctrl_funcs), - .confs_info =3D { - [AIROHA_PINCTRL_CONFS_PULLUP] =3D { - .confs =3D an7583_pinctrl_pullup_conf, - .num_confs =3D ARRAY_SIZE(an7583_pinctrl_pullup_conf), - }, - [AIROHA_PINCTRL_CONFS_PULLDOWN] =3D { - .confs =3D an7583_pinctrl_pulldown_conf, - .num_confs =3D ARRAY_SIZE(an7583_pinctrl_pulldown_conf), - }, - [AIROHA_PINCTRL_CONFS_DRIVE_E2] =3D { - .confs =3D an7583_pinctrl_drive_e2_conf, - .num_confs =3D ARRAY_SIZE(an7583_pinctrl_drive_e2_conf), - }, - [AIROHA_PINCTRL_CONFS_DRIVE_E4] =3D { - .confs =3D an7583_pinctrl_drive_e4_conf, - .num_confs =3D ARRAY_SIZE(an7583_pinctrl_drive_e4_conf), - }, - [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] =3D { - .confs =3D an7583_pinctrl_pcie_rst_od_conf, - .num_confs =3D ARRAY_SIZE(an7583_pinctrl_pcie_rst_od_conf), - }, - }, -}; - -static const struct of_device_id airoha_pinctrl_of_match[] =3D { - { .compatible =3D "airoha,en7581-pinctrl", .data =3D &en7581_pinctrl_matc= h_data }, - { .compatible =3D "airoha,an7583-pinctrl", .data =3D &an7583_pinctrl_matc= h_data }, - { /* sentinel */ } -}; -MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match); - -static struct platform_driver airoha_pinctrl_driver =3D { - .probe =3D airoha_pinctrl_probe, - .driver =3D { - .name =3D "pinctrl-airoha", - .of_match_table =3D airoha_pinctrl_of_match, - }, -}; -module_platform_driver(airoha_pinctrl_driver); +EXPORT_SYMBOL_GPL(airoha_pinctrl_probe); =20 MODULE_LICENSE("GPL"); MODULE_AUTHOR("Lorenzo Bianconi "); MODULE_AUTHOR("Benjamin Larsson "); MODULE_AUTHOR("Markus Gothe "); -MODULE_DESCRIPTION("Pinctrl driver for Airoha SoC"); +MODULE_DESCRIPTION("Pinctrl common driver for Airoha SoC"); diff --git a/drivers/pinctrl/airoha/pinctrl-an7581.c b/drivers/pinctrl/airo= ha/pinctrl-an7581.c new file mode 100644 index 000000000000..22feb5e04388 --- /dev/null +++ b/drivers/pinctrl/airoha/pinctrl-an7581.c @@ -0,0 +1,1148 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Author: Lorenzo Bianconi + * Author: Benjamin Larsson + * Author: Markus Gothe + */ + +#include "airoha-common.h" + +static struct pinctrl_pin_desc en7581_pinctrl_pins[] =3D { + PINCTRL_PIN(0, "uart1_txd"), + PINCTRL_PIN(1, "uart1_rxd"), + PINCTRL_PIN(2, "i2c_scl"), + PINCTRL_PIN(3, "i2c_sda"), + PINCTRL_PIN(4, "spi_cs0"), + PINCTRL_PIN(5, "spi_clk"), + PINCTRL_PIN(6, "spi_mosi"), + PINCTRL_PIN(7, "spi_miso"), + PINCTRL_PIN(13, "gpio0"), + PINCTRL_PIN(14, "gpio1"), + PINCTRL_PIN(15, "gpio2"), + PINCTRL_PIN(16, "gpio3"), + PINCTRL_PIN(17, "gpio4"), + PINCTRL_PIN(18, "gpio5"), + PINCTRL_PIN(19, "gpio6"), + PINCTRL_PIN(20, "gpio7"), + PINCTRL_PIN(21, "gpio8"), + PINCTRL_PIN(22, "gpio9"), + PINCTRL_PIN(23, "gpio10"), + PINCTRL_PIN(24, "gpio11"), + PINCTRL_PIN(25, "gpio12"), + PINCTRL_PIN(26, "gpio13"), + PINCTRL_PIN(27, "gpio14"), + PINCTRL_PIN(28, "gpio15"), + PINCTRL_PIN(29, "gpio16"), + PINCTRL_PIN(30, "gpio17"), + PINCTRL_PIN(31, "gpio18"), + PINCTRL_PIN(32, "gpio19"), + PINCTRL_PIN(33, "gpio20"), + PINCTRL_PIN(34, "gpio21"), + PINCTRL_PIN(35, "gpio22"), + PINCTRL_PIN(36, "gpio23"), + PINCTRL_PIN(37, "gpio24"), + PINCTRL_PIN(38, "gpio25"), + PINCTRL_PIN(39, "gpio26"), + PINCTRL_PIN(40, "gpio27"), + PINCTRL_PIN(41, "gpio28"), + PINCTRL_PIN(42, "gpio29"), + PINCTRL_PIN(43, "gpio30"), + PINCTRL_PIN(44, "gpio31"), + PINCTRL_PIN(45, "gpio32"), + PINCTRL_PIN(46, "gpio33"), + PINCTRL_PIN(47, "gpio34"), + PINCTRL_PIN(48, "gpio35"), + PINCTRL_PIN(49, "gpio36"), + PINCTRL_PIN(50, "gpio37"), + PINCTRL_PIN(51, "gpio38"), + PINCTRL_PIN(52, "gpio39"), + PINCTRL_PIN(53, "gpio40"), + PINCTRL_PIN(54, "gpio41"), + PINCTRL_PIN(55, "gpio42"), + PINCTRL_PIN(56, "gpio43"), + PINCTRL_PIN(57, "gpio44"), + PINCTRL_PIN(58, "gpio45"), + PINCTRL_PIN(59, "gpio46"), + PINCTRL_PIN(61, "pcie_reset0"), + PINCTRL_PIN(62, "pcie_reset1"), + PINCTRL_PIN(63, "pcie_reset2"), +}; + +static const int en7581_pon_pins[] =3D { 49, 50, 51, 52, 53, 54 }; +static const int en7581_pon_tod_1pps_pins[] =3D { 46 }; +static const int en7581_gsw_tod_1pps_pins[] =3D { 46 }; +static const int en7581_sipo_pins[] =3D { 16, 17 }; +static const int en7581_sipo_rclk_pins[] =3D { 16, 17, 43 }; +static const int en7581_mdio_pins[] =3D { 14, 15 }; +static const int en7581_uart2_pins[] =3D { 48, 55 }; +static const int en7581_uart2_cts_rts_pins[] =3D { 46, 47 }; +static const int en7581_hsuart_pins[] =3D { 28, 29 }; +static const int en7581_hsuart_cts_rts_pins[] =3D { 26, 27 }; +static const int en7581_uart4_pins[] =3D { 38, 39 }; +static const int en7581_uart5_pins[] =3D { 18, 19 }; +static const int en7581_i2c0_pins[] =3D { 2, 3 }; +static const int en7581_i2c1_pins[] =3D { 14, 15 }; +static const int en7581_jtag_udi_pins[] =3D { 16, 17, 18, 19, 20 }; +static const int en7581_jtag_dfd_pins[] =3D { 16, 17, 18, 19, 20 }; +static const int en7581_i2s_pins[] =3D { 26, 27, 28, 29 }; +static const int en7581_pcm1_pins[] =3D { 22, 23, 24, 25 }; +static const int en7581_pcm2_pins[] =3D { 18, 19, 20, 21 }; +static const int en7581_spi_quad_pins[] =3D { 32, 33 }; +static const int en7581_spi_pins[] =3D { 4, 5, 6, 7 }; +static const int en7581_spi_cs1_pins[] =3D { 34 }; +static const int en7581_pcm_spi_pins[] =3D { 18, 19, 20, 21, 22, 23, 24, 2= 5 }; +static const int en7581_pcm_spi_int_pins[] =3D { 14 }; +static const int en7581_pcm_spi_rst_pins[] =3D { 15 }; +static const int en7581_pcm_spi_cs1_pins[] =3D { 43 }; +static const int en7581_pcm_spi_cs2_pins[] =3D { 40 }; +static const int en7581_pcm_spi_cs2_p128_pins[] =3D { 40 }; +static const int en7581_pcm_spi_cs2_p156_pins[] =3D { 40 }; +static const int en7581_pcm_spi_cs3_pins[] =3D { 41 }; +static const int en7581_pcm_spi_cs4_pins[] =3D { 42 }; +static const int en7581_emmc_pins[] =3D { 4, 5, 6, 30, 31, 32, 33, 34, 35,= 36, 37 }; +static const int en7581_pnand_pins[] =3D { 4, 5, 6, 7, 30, 31, 32, 33, 34,= 35, 36, 37, 38, 39, 40, 41, 42 }; +static const int en7581_gpio0_pins[] =3D { 13 }; +static const int en7581_gpio1_pins[] =3D { 14 }; +static const int en7581_gpio2_pins[] =3D { 15 }; +static const int en7581_gpio3_pins[] =3D { 16 }; +static const int en7581_gpio4_pins[] =3D { 17 }; +static const int en7581_gpio5_pins[] =3D { 18 }; +static const int en7581_gpio6_pins[] =3D { 19 }; +static const int en7581_gpio7_pins[] =3D { 20 }; +static const int en7581_gpio8_pins[] =3D { 21 }; +static const int en7581_gpio9_pins[] =3D { 22 }; +static const int en7581_gpio10_pins[] =3D { 23 }; +static const int en7581_gpio11_pins[] =3D { 24 }; +static const int en7581_gpio12_pins[] =3D { 25 }; +static const int en7581_gpio13_pins[] =3D { 26 }; +static const int en7581_gpio14_pins[] =3D { 27 }; +static const int en7581_gpio15_pins[] =3D { 28 }; +static const int en7581_gpio16_pins[] =3D { 29 }; +static const int en7581_gpio17_pins[] =3D { 30 }; +static const int en7581_gpio18_pins[] =3D { 31 }; +static const int en7581_gpio19_pins[] =3D { 32 }; +static const int en7581_gpio20_pins[] =3D { 33 }; +static const int en7581_gpio21_pins[] =3D { 34 }; +static const int en7581_gpio22_pins[] =3D { 35 }; +static const int en7581_gpio23_pins[] =3D { 36 }; +static const int en7581_gpio24_pins[] =3D { 37 }; +static const int en7581_gpio25_pins[] =3D { 38 }; +static const int en7581_gpio26_pins[] =3D { 39 }; +static const int en7581_gpio27_pins[] =3D { 40 }; +static const int en7581_gpio28_pins[] =3D { 41 }; +static const int en7581_gpio29_pins[] =3D { 42 }; +static const int en7581_gpio30_pins[] =3D { 43 }; +static const int en7581_gpio31_pins[] =3D { 44 }; +static const int en7581_gpio32_pins[] =3D { 45 }; +static const int en7581_gpio33_pins[] =3D { 46 }; +static const int en7581_gpio34_pins[] =3D { 47 }; +static const int en7581_gpio35_pins[] =3D { 48 }; +static const int en7581_gpio36_pins[] =3D { 49 }; +static const int en7581_gpio37_pins[] =3D { 50 }; +static const int en7581_gpio38_pins[] =3D { 51 }; +static const int en7581_gpio39_pins[] =3D { 52 }; +static const int en7581_gpio40_pins[] =3D { 53 }; +static const int en7581_gpio41_pins[] =3D { 54 }; +static const int en7581_gpio42_pins[] =3D { 55 }; +static const int en7581_gpio43_pins[] =3D { 56 }; +static const int en7581_gpio44_pins[] =3D { 57 }; +static const int en7581_gpio45_pins[] =3D { 58 }; +static const int en7581_gpio46_pins[] =3D { 59 }; +static const int en7581_pcie_reset0_pins[] =3D { 61 }; +static const int en7581_pcie_reset1_pins[] =3D { 62 }; +static const int en7581_pcie_reset2_pins[] =3D { 63 }; + +static const struct pingroup en7581_pinctrl_groups[] =3D { + PINCTRL_PIN_GROUP("pon", en7581_pon), + PINCTRL_PIN_GROUP("pon_tod_1pps", en7581_pon_tod_1pps), + PINCTRL_PIN_GROUP("gsw_tod_1pps", en7581_gsw_tod_1pps), + PINCTRL_PIN_GROUP("sipo", en7581_sipo), + PINCTRL_PIN_GROUP("sipo_rclk", en7581_sipo_rclk), + PINCTRL_PIN_GROUP("mdio", en7581_mdio), + PINCTRL_PIN_GROUP("uart2", en7581_uart2), + PINCTRL_PIN_GROUP("uart2_cts_rts", en7581_uart2_cts_rts), + PINCTRL_PIN_GROUP("hsuart", en7581_hsuart), + PINCTRL_PIN_GROUP("hsuart_cts_rts", en7581_hsuart_cts_rts), + PINCTRL_PIN_GROUP("uart4", en7581_uart4), + PINCTRL_PIN_GROUP("uart5", en7581_uart5), + PINCTRL_PIN_GROUP("i2c0", en7581_i2c0), + PINCTRL_PIN_GROUP("i2c1", en7581_i2c1), + PINCTRL_PIN_GROUP("jtag_udi", en7581_jtag_udi), + PINCTRL_PIN_GROUP("jtag_dfd", en7581_jtag_dfd), + PINCTRL_PIN_GROUP("i2s", en7581_i2s), + PINCTRL_PIN_GROUP("pcm1", en7581_pcm1), + PINCTRL_PIN_GROUP("pcm2", en7581_pcm2), + PINCTRL_PIN_GROUP("spi", en7581_spi), + PINCTRL_PIN_GROUP("spi_quad", en7581_spi_quad), + PINCTRL_PIN_GROUP("spi_cs1", en7581_spi_cs1), + PINCTRL_PIN_GROUP("pcm_spi", en7581_pcm_spi), + PINCTRL_PIN_GROUP("pcm_spi_int", en7581_pcm_spi_int), + PINCTRL_PIN_GROUP("pcm_spi_rst", en7581_pcm_spi_rst), + PINCTRL_PIN_GROUP("pcm_spi_cs1", en7581_pcm_spi_cs1), + PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7581_pcm_spi_cs2_p128), + PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7581_pcm_spi_cs2_p156), + PINCTRL_PIN_GROUP("pcm_spi_cs2", en7581_pcm_spi_cs2), + PINCTRL_PIN_GROUP("pcm_spi_cs3", en7581_pcm_spi_cs3), + PINCTRL_PIN_GROUP("pcm_spi_cs4", en7581_pcm_spi_cs4), + PINCTRL_PIN_GROUP("emmc", en7581_emmc), + PINCTRL_PIN_GROUP("pnand", en7581_pnand), + PINCTRL_PIN_GROUP("gpio0", en7581_gpio0), + PINCTRL_PIN_GROUP("gpio1", en7581_gpio1), + PINCTRL_PIN_GROUP("gpio2", en7581_gpio2), + PINCTRL_PIN_GROUP("gpio3", en7581_gpio3), + PINCTRL_PIN_GROUP("gpio4", en7581_gpio4), + PINCTRL_PIN_GROUP("gpio5", en7581_gpio5), + PINCTRL_PIN_GROUP("gpio6", en7581_gpio6), + PINCTRL_PIN_GROUP("gpio7", en7581_gpio7), + PINCTRL_PIN_GROUP("gpio8", en7581_gpio8), + PINCTRL_PIN_GROUP("gpio9", en7581_gpio9), + PINCTRL_PIN_GROUP("gpio10", en7581_gpio10), + PINCTRL_PIN_GROUP("gpio11", en7581_gpio11), + PINCTRL_PIN_GROUP("gpio12", en7581_gpio12), + PINCTRL_PIN_GROUP("gpio13", en7581_gpio13), + PINCTRL_PIN_GROUP("gpio14", en7581_gpio14), + PINCTRL_PIN_GROUP("gpio15", en7581_gpio15), + PINCTRL_PIN_GROUP("gpio16", en7581_gpio16), + PINCTRL_PIN_GROUP("gpio17", en7581_gpio17), + PINCTRL_PIN_GROUP("gpio18", en7581_gpio18), + PINCTRL_PIN_GROUP("gpio19", en7581_gpio19), + PINCTRL_PIN_GROUP("gpio20", en7581_gpio20), + PINCTRL_PIN_GROUP("gpio21", en7581_gpio21), + PINCTRL_PIN_GROUP("gpio22", en7581_gpio22), + PINCTRL_PIN_GROUP("gpio23", en7581_gpio23), + PINCTRL_PIN_GROUP("gpio24", en7581_gpio24), + PINCTRL_PIN_GROUP("gpio25", en7581_gpio25), + PINCTRL_PIN_GROUP("gpio26", en7581_gpio26), + PINCTRL_PIN_GROUP("gpio27", en7581_gpio27), + PINCTRL_PIN_GROUP("gpio28", en7581_gpio28), + PINCTRL_PIN_GROUP("gpio29", en7581_gpio29), + PINCTRL_PIN_GROUP("gpio30", en7581_gpio30), + PINCTRL_PIN_GROUP("gpio31", en7581_gpio31), + PINCTRL_PIN_GROUP("gpio32", en7581_gpio32), + PINCTRL_PIN_GROUP("gpio33", en7581_gpio33), + PINCTRL_PIN_GROUP("gpio34", en7581_gpio34), + PINCTRL_PIN_GROUP("gpio35", en7581_gpio35), + PINCTRL_PIN_GROUP("gpio36", en7581_gpio36), + PINCTRL_PIN_GROUP("gpio37", en7581_gpio37), + PINCTRL_PIN_GROUP("gpio38", en7581_gpio38), + PINCTRL_PIN_GROUP("gpio39", en7581_gpio39), + PINCTRL_PIN_GROUP("gpio40", en7581_gpio40), + PINCTRL_PIN_GROUP("gpio41", en7581_gpio41), + PINCTRL_PIN_GROUP("gpio42", en7581_gpio42), + PINCTRL_PIN_GROUP("gpio43", en7581_gpio43), + PINCTRL_PIN_GROUP("gpio44", en7581_gpio44), + PINCTRL_PIN_GROUP("gpio45", en7581_gpio45), + PINCTRL_PIN_GROUP("gpio46", en7581_gpio46), + PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0), + PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1), + PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2), +}; + +static const char *const pon_groups[] =3D { "pon" }; +static const char *const tod_1pps_groups[] =3D { "pon_tod_1pps", "gsw_tod_= 1pps" }; +static const char *const sipo_groups[] =3D { "sipo", "sipo_rclk" }; +static const char *const mdio_groups[] =3D { "mdio" }; +static const char *const uart_groups[] =3D { "uart2", "uart2_cts_rts", "hs= uart", + "hsuart_cts_rts", "uart4", + "uart5" }; +static const char *const i2c_groups[] =3D { "i2c1" }; +static const char *const jtag_groups[] =3D { "jtag_udi", "jtag_dfd" }; +static const char *const pcm_groups[] =3D { "pcm1", "pcm2" }; +static const char *const spi_groups[] =3D { "spi_quad", "spi_cs1" }; +static const char *const pcm_spi_groups[] =3D { "pcm_spi", "pcm_spi_int", + "pcm_spi_rst", "pcm_spi_cs1", + "pcm_spi_cs2_p156", + "pcm_spi_cs2_p128", + "pcm_spi_cs3", "pcm_spi_cs4" }; +static const char *const i2s_groups[] =3D { "i2s" }; +static const char *const emmc_groups[] =3D { "emmc" }; +static const char *const pnand_groups[] =3D { "pnand" }; +static const char *const pcie_reset_groups[] =3D { "pcie_reset0", "pcie_re= set1", + "pcie_reset2" }; +static const char *const pwm_groups[] =3D { "gpio0", "gpio1", + "gpio2", "gpio3", + "gpio4", "gpio5", + "gpio6", "gpio7", + "gpio8", "gpio9", + "gpio10", "gpio11", + "gpio12", "gpio13", + "gpio14", "gpio15", + "gpio16", "gpio17", + "gpio18", "gpio19", + "gpio20", "gpio21", + "gpio22", "gpio23", + "gpio24", "gpio25", + "gpio26", "gpio27", + "gpio28", "gpio29", + "gpio30", "gpio31", + "gpio36", "gpio37", + "gpio38", "gpio39", + "gpio40", "gpio41", + "gpio42", "gpio43", + "gpio44", "gpio45", + "gpio46" }; +static const char *const phy1_led0_groups[] =3D { "gpio33", "gpio34", + "gpio35", "gpio42" }; +static const char *const phy2_led0_groups[] =3D { "gpio33", "gpio34", + "gpio35", "gpio42" }; +static const char *const phy3_led0_groups[] =3D { "gpio33", "gpio34", + "gpio35", "gpio42" }; +static const char *const phy4_led0_groups[] =3D { "gpio33", "gpio34", + "gpio35", "gpio42" }; +static const char *const phy1_led1_groups[] =3D { "gpio43", "gpio44", + "gpio45", "gpio46" }; +static const char *const phy2_led1_groups[] =3D { "gpio43", "gpio44", + "gpio45", "gpio46" }; +static const char *const phy3_led1_groups[] =3D { "gpio43", "gpio44", + "gpio45", "gpio46" }; +static const char *const phy4_led1_groups[] =3D { "gpio43", "gpio44", + "gpio45", "gpio46" }; + +static const struct airoha_pinctrl_func_group pon_func_group[] =3D { + { + .name =3D "pon", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PON_MODE_MASK, + GPIO_PON_MODE_MASK + }, + .regmap_size =3D 1, + }, +}; + +static const struct airoha_pinctrl_func_group tod_1pps_func_group[] =3D { + { + .name =3D "pon_tod_1pps", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + PON_TOD_1PPS_MODE_MASK, + PON_TOD_1PPS_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "gsw_tod_1pps", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GSW_TOD_1PPS_MODE_MASK, + GSW_TOD_1PPS_MODE_MASK + }, + .regmap_size =3D 1, + }, +}; + +static const struct airoha_pinctrl_func_group sipo_func_group[] =3D { + { + .name =3D "sipo", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, + GPIO_SIPO_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "sipo_rclk", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK + }, + .regmap_size =3D 1, + }, +}; + +static const struct airoha_pinctrl_func_group mdio_func_group[] =3D { + { + .name =3D "mdio", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_MDC_IO_MASTER_MODE_MODE, + GPIO_MDC_IO_MASTER_MODE_MODE + }, + .regmap[1] =3D { + AIROHA_FUNC_MUX, + REG_FORCE_GPIO_EN, + FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2), + FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2) + }, + .regmap_size =3D 2, + }, +}; + +static const struct airoha_pinctrl_func_group uart_func_group[] =3D { + { + .name =3D "uart2", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_UART2_MODE_MASK, + GPIO_UART2_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "uart2_cts_rts", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK, + GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "hsuart", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, + GPIO_HSUART_MODE_MASK + }, + .regmap_size =3D 1, + }, + { + .name =3D "hsuart_cts_rts", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, + GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "uart4", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_UART4_MODE_MASK, + GPIO_UART4_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "uart5", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_UART5_MODE_MASK, + GPIO_UART5_MODE_MASK + }, + .regmap_size =3D 1, + }, +}; + +static const struct airoha_pinctrl_func_group i2c_func_group[] =3D { + { + .name =3D "i2c1", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_2ND_I2C_MODE_MASK, + GPIO_2ND_I2C_MODE_MASK + }, + .regmap_size =3D 1, + }, +}; + +static const struct airoha_pinctrl_func_group jtag_func_group[] =3D { + { + .name =3D "jtag_udi", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_NPU_UART_EN, + JTAG_UDI_EN_MASK, + JTAG_UDI_EN_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "jtag_dfd", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_NPU_UART_EN, + JTAG_DFD_EN_MASK, + JTAG_DFD_EN_MASK + }, + .regmap_size =3D 1, + }, +}; + +static const struct airoha_pinctrl_func_group pcm_func_group[] =3D { + { + .name =3D "pcm1", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM1_MODE_MASK, + GPIO_PCM1_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "pcm2", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM2_MODE_MASK, + GPIO_PCM2_MODE_MASK + }, + .regmap_size =3D 1, + }, +}; + +static const struct airoha_pinctrl_func_group spi_func_group[] =3D { + { + .name =3D "spi_quad", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_QUAD_MODE_MASK, + GPIO_SPI_QUAD_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "spi_cs1", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS1_MODE_MASK, + GPIO_SPI_CS1_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "spi_cs2", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS2_MODE_MASK, + GPIO_SPI_CS2_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "spi_cs3", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS3_MODE_MASK, + GPIO_SPI_CS3_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "spi_cs4", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS4_MODE_MASK, + GPIO_SPI_CS4_MODE_MASK + }, + .regmap_size =3D 1, + }, +}; + +static const struct airoha_pinctrl_func_group pcm_spi_func_group[] =3D { + { + .name =3D "pcm_spi", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_MODE_MASK, + GPIO_PCM_SPI_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "pcm_spi_int", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_INT_MODE_MASK, + GPIO_PCM_INT_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "pcm_spi_rst", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_RESET_MODE_MASK, + GPIO_PCM_RESET_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "pcm_spi_cs1", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS1_MODE_MASK, + GPIO_PCM_SPI_CS1_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "pcm_spi_cs2_p128", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS2_MODE_P128_MASK, + GPIO_PCM_SPI_CS2_MODE_P128_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "pcm_spi_cs2_p156", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS2_MODE_P156_MASK, + GPIO_PCM_SPI_CS2_MODE_P156_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "pcm_spi_cs3", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS3_MODE_MASK, + GPIO_PCM_SPI_CS3_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "pcm_spi_cs4", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS4_MODE_MASK, + GPIO_PCM_SPI_CS4_MODE_MASK + }, + .regmap_size =3D 1, + }, +}; + +static const struct airoha_pinctrl_func_group i2s_func_group[] =3D { + { + .name =3D "i2s", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_I2S_MODE_MASK, + GPIO_I2S_MODE_MASK + }, + .regmap_size =3D 1, + }, +}; + +static const struct airoha_pinctrl_func_group emmc_func_group[] =3D { + { + .name =3D "emmc", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_EMMC_MODE_MASK, + GPIO_EMMC_MODE_MASK + }, + .regmap_size =3D 1, + }, +}; + +static const struct airoha_pinctrl_func_group pnand_func_group[] =3D { + { + .name =3D "pnand", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PARALLEL_NAND_MODE_MASK, + GPIO_PARALLEL_NAND_MODE_MASK + }, + .regmap_size =3D 1, + }, +}; + +static const struct airoha_pinctrl_func_group pcie_reset_func_group[] =3D { + { + .name =3D "pcie_reset0", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PCIE_RESET0_MASK, + GPIO_PCIE_RESET0_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "pcie_reset1", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PCIE_RESET1_MASK, + GPIO_PCIE_RESET1_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "pcie_reset2", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PCIE_RESET2_MASK, + GPIO_PCIE_RESET2_MASK + }, + .regmap_size =3D 1, + }, +}; + +static const struct airoha_pinctrl_func_group pwm_func_group[] =3D { + AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG), +}; + +static const struct airoha_pinctrl_func_group phy1_led0_func_group[] =3D { + AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), +}; + +static const struct airoha_pinctrl_func_group phy2_led0_func_group[] =3D { + AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), +}; + +static const struct airoha_pinctrl_func_group phy3_led0_func_group[] =3D { + AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), +}; + +static const struct airoha_pinctrl_func_group phy4_led0_func_group[] =3D { + AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), +}; + +static const struct airoha_pinctrl_func_group phy1_led1_func_group[] =3D { + AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), +}; + +static const struct airoha_pinctrl_func_group phy2_led1_func_group[] =3D { + AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), +}; + +static const struct airoha_pinctrl_func_group phy3_led1_func_group[] =3D { + AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), +}; + +static const struct airoha_pinctrl_func_group phy4_led1_func_group[] =3D { + AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), +}; + +static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] =3D { + PINCTRL_FUNC_DESC("pon", pon), + PINCTRL_FUNC_DESC("tod_1pps", tod_1pps), + PINCTRL_FUNC_DESC("sipo", sipo), + PINCTRL_FUNC_DESC("mdio", mdio), + PINCTRL_FUNC_DESC("uart", uart), + PINCTRL_FUNC_DESC("i2c", i2c), + PINCTRL_FUNC_DESC("jtag", jtag), + PINCTRL_FUNC_DESC("pcm", pcm), + PINCTRL_FUNC_DESC("spi", spi), + PINCTRL_FUNC_DESC("pcm_spi", pcm_spi), + PINCTRL_FUNC_DESC("i2s", i2s), + PINCTRL_FUNC_DESC("emmc", emmc), + PINCTRL_FUNC_DESC("pnand", pnand), + PINCTRL_FUNC_DESC("pcie_reset", pcie_reset), + PINCTRL_FUNC_DESC("pwm", pwm), + PINCTRL_FUNC_DESC("phy1_led0", phy1_led0), + PINCTRL_FUNC_DESC("phy2_led0", phy2_led0), + PINCTRL_FUNC_DESC("phy3_led0", phy3_led0), + PINCTRL_FUNC_DESC("phy4_led0", phy4_led0), + PINCTRL_FUNC_DESC("phy1_led1", phy1_led1), + PINCTRL_FUNC_DESC("phy2_led1", phy2_led1), + PINCTRL_FUNC_DESC("phy3_led1", phy3_led1), + PINCTRL_FUNC_DESC("phy4_led1", phy4_led1), +}; + +static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] =3D { + PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK), + PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK), + PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK), + PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SCL_PU_MASK), + PINCTRL_CONF_DESC(4, REG_I2C_SDA_PU, SPI_CS0_PU_MASK), + PINCTRL_CONF_DESC(5, REG_I2C_SDA_PU, SPI_CLK_PU_MASK), + PINCTRL_CONF_DESC(6, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK), + PINCTRL_CONF_DESC(7, REG_I2C_SDA_PU, SPI_MISO_PU_MASK), + PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(0)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(1)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(2)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(3)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(4)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(5)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(6)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(7)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(8)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(9)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(10)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(11)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(12)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(13)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(14)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(15)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(16)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(17)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(18)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(19)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(20)), + PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(21)), + PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(22)), + PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(23)), + PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(24)), + PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(25)), + PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(26)), + PINCTRL_CONF_DESC(40, REG_GPIO_L_PU, BIT(27)), + PINCTRL_CONF_DESC(41, REG_GPIO_L_PU, BIT(28)), + PINCTRL_CONF_DESC(42, REG_GPIO_L_PU, BIT(29)), + PINCTRL_CONF_DESC(43, REG_GPIO_L_PU, BIT(30)), + PINCTRL_CONF_DESC(44, REG_GPIO_L_PU, BIT(31)), + PINCTRL_CONF_DESC(45, REG_GPIO_H_PU, BIT(0)), + PINCTRL_CONF_DESC(46, REG_GPIO_H_PU, BIT(1)), + PINCTRL_CONF_DESC(47, REG_GPIO_H_PU, BIT(2)), + PINCTRL_CONF_DESC(48, REG_GPIO_H_PU, BIT(3)), + PINCTRL_CONF_DESC(49, REG_GPIO_H_PU, BIT(4)), + PINCTRL_CONF_DESC(50, REG_GPIO_H_PU, BIT(5)), + PINCTRL_CONF_DESC(51, REG_GPIO_H_PU, BIT(6)), + PINCTRL_CONF_DESC(52, REG_GPIO_H_PU, BIT(7)), + PINCTRL_CONF_DESC(53, REG_GPIO_H_PU, BIT(8)), + PINCTRL_CONF_DESC(54, REG_GPIO_H_PU, BIT(9)), + PINCTRL_CONF_DESC(55, REG_GPIO_H_PU, BIT(10)), + PINCTRL_CONF_DESC(56, REG_GPIO_H_PU, BIT(11)), + PINCTRL_CONF_DESC(57, REG_GPIO_H_PU, BIT(12)), + PINCTRL_CONF_DESC(58, REG_GPIO_H_PU, BIT(13)), + PINCTRL_CONF_DESC(59, REG_GPIO_H_PU, BIT(14)), + PINCTRL_CONF_DESC(61, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK), + PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK), + PINCTRL_CONF_DESC(63, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK), +}; + +static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] =3D= { + PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK), + PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK), + PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK), + PINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SCL_PD_MASK), + PINCTRL_CONF_DESC(4, REG_I2C_SDA_PD, SPI_CS0_PD_MASK), + PINCTRL_CONF_DESC(5, REG_I2C_SDA_PD, SPI_CLK_PD_MASK), + PINCTRL_CONF_DESC(6, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK), + PINCTRL_CONF_DESC(7, REG_I2C_SDA_PD, SPI_MISO_PD_MASK), + PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(0)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(1)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(2)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(3)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(4)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(5)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(6)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(7)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(8)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(9)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(10)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(11)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(12)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(13)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(14)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(15)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(16)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(17)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(18)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(19)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(20)), + PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(21)), + PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(22)), + PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(23)), + PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(24)), + PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(25)), + PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(26)), + PINCTRL_CONF_DESC(40, REG_GPIO_L_PD, BIT(27)), + PINCTRL_CONF_DESC(41, REG_GPIO_L_PD, BIT(28)), + PINCTRL_CONF_DESC(42, REG_GPIO_L_PD, BIT(29)), + PINCTRL_CONF_DESC(43, REG_GPIO_L_PD, BIT(30)), + PINCTRL_CONF_DESC(44, REG_GPIO_L_PD, BIT(31)), + PINCTRL_CONF_DESC(45, REG_GPIO_H_PD, BIT(0)), + PINCTRL_CONF_DESC(46, REG_GPIO_H_PD, BIT(1)), + PINCTRL_CONF_DESC(47, REG_GPIO_H_PD, BIT(2)), + PINCTRL_CONF_DESC(48, REG_GPIO_H_PD, BIT(3)), + PINCTRL_CONF_DESC(49, REG_GPIO_H_PD, BIT(4)), + PINCTRL_CONF_DESC(50, REG_GPIO_H_PD, BIT(5)), + PINCTRL_CONF_DESC(51, REG_GPIO_H_PD, BIT(6)), + PINCTRL_CONF_DESC(52, REG_GPIO_H_PD, BIT(7)), + PINCTRL_CONF_DESC(53, REG_GPIO_H_PD, BIT(8)), + PINCTRL_CONF_DESC(54, REG_GPIO_H_PD, BIT(9)), + PINCTRL_CONF_DESC(55, REG_GPIO_H_PD, BIT(10)), + PINCTRL_CONF_DESC(56, REG_GPIO_H_PD, BIT(11)), + PINCTRL_CONF_DESC(57, REG_GPIO_H_PD, BIT(12)), + PINCTRL_CONF_DESC(58, REG_GPIO_H_PD, BIT(13)), + PINCTRL_CONF_DESC(59, REG_GPIO_H_PD, BIT(14)), + PINCTRL_CONF_DESC(61, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK), + PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK), + PINCTRL_CONF_DESC(63, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK), +}; + +static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] =3D= { + PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK), + PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK), + PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK), + PINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SCL_E2_MASK), + PINCTRL_CONF_DESC(4, REG_I2C_SDA_E2, SPI_CS0_E2_MASK), + PINCTRL_CONF_DESC(5, REG_I2C_SDA_E2, SPI_CLK_E2_MASK), + PINCTRL_CONF_DESC(6, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK), + PINCTRL_CONF_DESC(7, REG_I2C_SDA_E2, SPI_MISO_E2_MASK), + PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(0)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(1)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(2)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(3)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(4)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(5)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(6)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(7)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(8)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(9)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(10)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(11)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(12)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(13)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(14)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(15)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(16)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(17)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(18)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(19)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(20)), + PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(21)), + PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(22)), + PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(23)), + PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(24)), + PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(25)), + PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(26)), + PINCTRL_CONF_DESC(40, REG_GPIO_L_E2, BIT(27)), + PINCTRL_CONF_DESC(41, REG_GPIO_L_E2, BIT(28)), + PINCTRL_CONF_DESC(42, REG_GPIO_L_E2, BIT(29)), + PINCTRL_CONF_DESC(43, REG_GPIO_L_E2, BIT(30)), + PINCTRL_CONF_DESC(44, REG_GPIO_L_E2, BIT(31)), + PINCTRL_CONF_DESC(45, REG_GPIO_H_E2, BIT(0)), + PINCTRL_CONF_DESC(46, REG_GPIO_H_E2, BIT(1)), + PINCTRL_CONF_DESC(47, REG_GPIO_H_E2, BIT(2)), + PINCTRL_CONF_DESC(48, REG_GPIO_H_E2, BIT(3)), + PINCTRL_CONF_DESC(49, REG_GPIO_H_E2, BIT(4)), + PINCTRL_CONF_DESC(50, REG_GPIO_H_E2, BIT(5)), + PINCTRL_CONF_DESC(51, REG_GPIO_H_E2, BIT(6)), + PINCTRL_CONF_DESC(52, REG_GPIO_H_E2, BIT(7)), + PINCTRL_CONF_DESC(53, REG_GPIO_H_E2, BIT(8)), + PINCTRL_CONF_DESC(54, REG_GPIO_H_E2, BIT(9)), + PINCTRL_CONF_DESC(55, REG_GPIO_H_E2, BIT(10)), + PINCTRL_CONF_DESC(56, REG_GPIO_H_E2, BIT(11)), + PINCTRL_CONF_DESC(57, REG_GPIO_H_E2, BIT(12)), + PINCTRL_CONF_DESC(58, REG_GPIO_H_E2, BIT(13)), + PINCTRL_CONF_DESC(59, REG_GPIO_H_E2, BIT(14)), + PINCTRL_CONF_DESC(61, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK), + PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK), + PINCTRL_CONF_DESC(63, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK), +}; + +static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] =3D= { + PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK), + PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK), + PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK), + PINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SCL_E4_MASK), + PINCTRL_CONF_DESC(4, REG_I2C_SDA_E4, SPI_CS0_E4_MASK), + PINCTRL_CONF_DESC(5, REG_I2C_SDA_E4, SPI_CLK_E4_MASK), + PINCTRL_CONF_DESC(6, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK), + PINCTRL_CONF_DESC(7, REG_I2C_SDA_E4, SPI_MISO_E4_MASK), + PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(0)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(1)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(2)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(3)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(4)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(5)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(6)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(7)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(8)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(9)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(10)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(11)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(12)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(13)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(14)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(15)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(16)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(17)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(18)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(19)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(20)), + PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(21)), + PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(22)), + PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(23)), + PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(24)), + PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(25)), + PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(26)), + PINCTRL_CONF_DESC(40, REG_GPIO_L_E4, BIT(27)), + PINCTRL_CONF_DESC(41, REG_GPIO_L_E4, BIT(28)), + PINCTRL_CONF_DESC(42, REG_GPIO_L_E4, BIT(29)), + PINCTRL_CONF_DESC(43, REG_GPIO_L_E4, BIT(30)), + PINCTRL_CONF_DESC(44, REG_GPIO_L_E4, BIT(31)), + PINCTRL_CONF_DESC(45, REG_GPIO_H_E4, BIT(0)), + PINCTRL_CONF_DESC(46, REG_GPIO_H_E4, BIT(1)), + PINCTRL_CONF_DESC(47, REG_GPIO_H_E4, BIT(2)), + PINCTRL_CONF_DESC(48, REG_GPIO_H_E4, BIT(3)), + PINCTRL_CONF_DESC(49, REG_GPIO_H_E4, BIT(4)), + PINCTRL_CONF_DESC(50, REG_GPIO_H_E4, BIT(5)), + PINCTRL_CONF_DESC(51, REG_GPIO_H_E4, BIT(6)), + PINCTRL_CONF_DESC(52, REG_GPIO_H_E4, BIT(7)), + PINCTRL_CONF_DESC(53, REG_GPIO_H_E4, BIT(8)), + PINCTRL_CONF_DESC(54, REG_GPIO_H_E4, BIT(9)), + PINCTRL_CONF_DESC(55, REG_GPIO_H_E4, BIT(10)), + PINCTRL_CONF_DESC(56, REG_GPIO_H_E4, BIT(11)), + PINCTRL_CONF_DESC(57, REG_GPIO_H_E4, BIT(12)), + PINCTRL_CONF_DESC(58, REG_GPIO_H_E4, BIT(13)), + PINCTRL_CONF_DESC(59, REG_GPIO_H_E4, BIT(14)), + PINCTRL_CONF_DESC(61, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK), + PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK), + PINCTRL_CONF_DESC(63, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK), +}; + +static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = =3D { + PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK), + PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK), + PINCTRL_CONF_DESC(63, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK), +}; + +static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = =3D { + .pins =3D en7581_pinctrl_pins, + .num_pins =3D ARRAY_SIZE(en7581_pinctrl_pins), + .grps =3D en7581_pinctrl_groups, + .num_grps =3D ARRAY_SIZE(en7581_pinctrl_groups), + .funcs =3D en7581_pinctrl_funcs, + .num_funcs =3D ARRAY_SIZE(en7581_pinctrl_funcs), + .confs_info =3D { + [AIROHA_PINCTRL_CONFS_PULLUP] =3D { + .confs =3D en7581_pinctrl_pullup_conf, + .num_confs =3D ARRAY_SIZE(en7581_pinctrl_pullup_conf), + }, + [AIROHA_PINCTRL_CONFS_PULLDOWN] =3D { + .confs =3D en7581_pinctrl_pulldown_conf, + .num_confs =3D ARRAY_SIZE(en7581_pinctrl_pulldown_conf), + }, + [AIROHA_PINCTRL_CONFS_DRIVE_E2] =3D { + .confs =3D en7581_pinctrl_drive_e2_conf, + .num_confs =3D ARRAY_SIZE(en7581_pinctrl_drive_e2_conf), + }, + [AIROHA_PINCTRL_CONFS_DRIVE_E4] =3D { + .confs =3D en7581_pinctrl_drive_e4_conf, + .num_confs =3D ARRAY_SIZE(en7581_pinctrl_drive_e4_conf), + }, + [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] =3D { + .confs =3D en7581_pinctrl_pcie_rst_od_conf, + .num_confs =3D ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf), + }, + }, +}; + +static const struct of_device_id airoha_pinctrl_of_match[] =3D { + { .compatible =3D "airoha,en7581-pinctrl", .data =3D &en7581_pinctrl_matc= h_data }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match); + +static struct platform_driver airoha_pinctrl_driver =3D { + .probe =3D airoha_pinctrl_probe, + .driver =3D { + .name =3D "pinctrl-airoha-an7581", + .of_match_table =3D airoha_pinctrl_of_match, + }, +}; +module_platform_driver(airoha_pinctrl_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Lorenzo Bianconi "); +MODULE_AUTHOR("Benjamin Larsson "); +MODULE_AUTHOR("Markus Gothe "); +MODULE_DESCRIPTION("Pinctrl driver for Airoha AN7581 SoC"); diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airo= ha/pinctrl-an7583.c new file mode 100644 index 000000000000..5b5e766abd45 --- /dev/null +++ b/drivers/pinctrl/airoha/pinctrl-an7583.c @@ -0,0 +1,1078 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Author: Lorenzo Bianconi + * Author: Benjamin Larsson + * Author: Markus Gothe + */ + +#include "airoha-common.h" + +static struct pinctrl_pin_desc an7583_pinctrl_pins[] =3D { + PINCTRL_PIN(2, "gpio0"), + PINCTRL_PIN(3, "gpio1"), + PINCTRL_PIN(4, "gpio2"), + PINCTRL_PIN(5, "gpio3"), + PINCTRL_PIN(6, "gpio4"), + PINCTRL_PIN(7, "gpio5"), + PINCTRL_PIN(8, "gpio6"), + PINCTRL_PIN(9, "gpio7"), + PINCTRL_PIN(10, "gpio8"), + PINCTRL_PIN(11, "gpio9"), + PINCTRL_PIN(12, "gpio10"), + PINCTRL_PIN(13, "gpio11"), + PINCTRL_PIN(14, "gpio12"), + PINCTRL_PIN(15, "gpio13"), + PINCTRL_PIN(16, "gpio14"), + PINCTRL_PIN(17, "gpio15"), + PINCTRL_PIN(18, "gpio16"), + PINCTRL_PIN(19, "gpio17"), + PINCTRL_PIN(20, "gpio18"), + PINCTRL_PIN(21, "gpio19"), + PINCTRL_PIN(22, "gpio20"), + PINCTRL_PIN(23, "gpio21"), + PINCTRL_PIN(24, "gpio22"), + PINCTRL_PIN(25, "gpio23"), + PINCTRL_PIN(26, "gpio24"), + PINCTRL_PIN(27, "gpio25"), + PINCTRL_PIN(28, "gpio26"), + PINCTRL_PIN(29, "gpio27"), + PINCTRL_PIN(30, "gpio28"), + PINCTRL_PIN(31, "gpio29"), + PINCTRL_PIN(32, "gpio30"), + PINCTRL_PIN(33, "gpio31"), + PINCTRL_PIN(34, "gpio32"), + PINCTRL_PIN(35, "gpio33"), + PINCTRL_PIN(36, "gpio34"), + PINCTRL_PIN(37, "gpio35"), + PINCTRL_PIN(38, "gpio36"), + PINCTRL_PIN(39, "gpio37"), + PINCTRL_PIN(40, "gpio38"), + PINCTRL_PIN(41, "i2c0_scl"), + PINCTRL_PIN(42, "i2c0_sda"), + PINCTRL_PIN(43, "i2c1_scl"), + PINCTRL_PIN(44, "i2c1_sda"), + PINCTRL_PIN(45, "spi_clk"), + PINCTRL_PIN(46, "spi_cs"), + PINCTRL_PIN(47, "spi_mosi"), + PINCTRL_PIN(48, "spi_miso"), + PINCTRL_PIN(49, "uart_txd"), + PINCTRL_PIN(50, "uart_rxd"), + PINCTRL_PIN(51, "pcie_reset0"), + PINCTRL_PIN(52, "pcie_reset1"), + PINCTRL_PIN(53, "mdc_0"), + PINCTRL_PIN(54, "mdio_0"), +}; + +static const int an7583_pon_pins[] =3D { 15, 16, 17, 18, 19, 20 }; +static const int an7583_pon_tod_1pps_pins[] =3D { 32 }; +static const int an7583_gsw_tod_1pps_pins[] =3D { 32 }; +static const int an7583_sipo_pins[] =3D { 34, 35 }; +static const int an7583_sipo_rclk_pins[] =3D { 34, 35, 33 }; +static const int an7583_mdio_pins[] =3D { 43, 44 }; +static const int an7583_uart2_pins[] =3D { 34, 35 }; +static const int an7583_uart2_cts_rts_pins[] =3D { 32, 33 }; +static const int an7583_hsuart_pins[] =3D { 30, 31 }; +static const int an7583_hsuart_cts_rts_pins[] =3D { 28, 29 }; +static const int an7583_npu_uart_pins[] =3D { 7, 8 }; +static const int an7583_uart4_pins[] =3D { 7, 8 }; +static const int an7583_uart5_pins[] =3D { 23, 24 }; +static const int an7583_i2c0_pins[] =3D { 41, 42 }; +static const int an7583_i2c1_pins[] =3D { 43, 44 }; +static const int an7583_jtag_udi_pins[] =3D { 23, 24, 22, 25, 26 }; +static const int an7583_jtag_dfd_pins[] =3D { 23, 24, 22, 25, 26 }; +static const int an7583_pcm1_pins[] =3D { 10, 11, 12, 13, 14 }; +static const int an7583_pcm2_pins[] =3D { 28, 29, 30, 31, 24 }; +static const int an7583_spi_pins[] =3D { 28, 29, 30, 31 }; +static const int an7583_spi_quad_pins[] =3D { 25, 26 }; +static const int an7583_spi_cs1_pins[] =3D { 27 }; +static const int an7583_pcm_spi_pins[] =3D { 28, 29, 30, 31, 10, 11, 12, 1= 3 }; +static const int an7583_pcm_spi_rst_pins[] =3D { 14 }; +static const int an7583_pcm_spi_cs1_pins[] =3D { 24 }; +static const int an7583_emmc_pins[] =3D { 7, 8, 9, 22, 23, 24, 25, 26, 45,= 46, 47 }; +static const int an7583_pnand_pins[] =3D { 7, 8, 9, 22, 23, 24, 25, 26, 27= , 28, 29, 30, 31, 45, 46, 47, 48 }; +static const int an7583_gpio0_pins[] =3D { 2 }; +static const int an7583_gpio1_pins[] =3D { 3 }; +static const int an7583_gpio2_pins[] =3D { 4 }; +static const int an7583_gpio3_pins[] =3D { 5 }; +static const int an7583_gpio4_pins[] =3D { 6 }; +static const int an7583_gpio5_pins[] =3D { 7 }; +static const int an7583_gpio6_pins[] =3D { 8 }; +static const int an7583_gpio7_pins[] =3D { 9 }; +static const int an7583_gpio8_pins[] =3D { 10 }; +static const int an7583_gpio9_pins[] =3D { 11 }; +static const int an7583_gpio10_pins[] =3D { 12 }; +static const int an7583_gpio11_pins[] =3D { 13 }; +static const int an7583_gpio12_pins[] =3D { 14 }; +static const int an7583_gpio13_pins[] =3D { 15 }; +static const int an7583_gpio14_pins[] =3D { 16 }; +static const int an7583_gpio15_pins[] =3D { 17 }; +static const int an7583_gpio16_pins[] =3D { 18 }; +static const int an7583_gpio17_pins[] =3D { 19 }; +static const int an7583_gpio18_pins[] =3D { 20 }; +static const int an7583_gpio19_pins[] =3D { 21 }; +static const int an7583_gpio20_pins[] =3D { 22 }; +static const int an7583_gpio21_pins[] =3D { 23 }; +static const int an7583_gpio22_pins[] =3D { 24 }; +static const int an7583_gpio23_pins[] =3D { 25 }; +static const int an7583_gpio24_pins[] =3D { 26 }; +static const int an7583_gpio25_pins[] =3D { 27 }; +static const int an7583_gpio26_pins[] =3D { 28 }; +static const int an7583_gpio27_pins[] =3D { 29 }; +static const int an7583_gpio28_pins[] =3D { 30 }; +static const int an7583_gpio29_pins[] =3D { 31 }; +static const int an7583_gpio30_pins[] =3D { 32 }; +static const int an7583_gpio31_pins[] =3D { 33 }; +static const int an7583_gpio32_pins[] =3D { 34 }; +static const int an7583_gpio33_pins[] =3D { 35 }; +static const int an7583_gpio34_pins[] =3D { 36 }; +static const int an7583_gpio35_pins[] =3D { 37 }; +static const int an7583_gpio36_pins[] =3D { 38 }; +static const int an7583_gpio37_pins[] =3D { 39 }; +static const int an7583_gpio38_pins[] =3D { 40 }; +static const int an7583_gpio39_pins[] =3D { 41 }; +static const int an7583_gpio40_pins[] =3D { 42 }; +static const int an7583_gpio41_pins[] =3D { 43 }; +static const int an7583_gpio42_pins[] =3D { 44 }; +static const int an7583_gpio43_pins[] =3D { 45 }; +static const int an7583_gpio44_pins[] =3D { 46 }; +static const int an7583_gpio45_pins[] =3D { 47 }; +static const int an7583_gpio46_pins[] =3D { 48 }; +static const int an7583_gpio47_pins[] =3D { 49 }; +static const int an7583_gpio48_pins[] =3D { 50 }; +static const int an7583_pcie_reset0_pins[] =3D { 51 }; +static const int an7583_pcie_reset1_pins[] =3D { 52 }; + +static const struct pingroup an7583_pinctrl_groups[] =3D { + PINCTRL_PIN_GROUP("pon", an7583_pon), + PINCTRL_PIN_GROUP("pon_tod_1pps", an7583_pon_tod_1pps), + PINCTRL_PIN_GROUP("gsw_tod_1pps", an7583_gsw_tod_1pps), + PINCTRL_PIN_GROUP("sipo", an7583_sipo), + PINCTRL_PIN_GROUP("sipo_rclk", an7583_sipo_rclk), + PINCTRL_PIN_GROUP("mdio", an7583_mdio), + PINCTRL_PIN_GROUP("uart2", an7583_uart2), + PINCTRL_PIN_GROUP("uart2_cts_rts", an7583_uart2_cts_rts), + PINCTRL_PIN_GROUP("hsuart", an7583_hsuart), + PINCTRL_PIN_GROUP("hsuart_cts_rts", an7583_hsuart_cts_rts), + PINCTRL_PIN_GROUP("npu_uart", an7583_npu_uart), + PINCTRL_PIN_GROUP("uart4", an7583_uart4), + PINCTRL_PIN_GROUP("uart5", an7583_uart5), + PINCTRL_PIN_GROUP("i2c0", an7583_i2c0), + PINCTRL_PIN_GROUP("i2c1", an7583_i2c1), + PINCTRL_PIN_GROUP("jtag_udi", an7583_jtag_udi), + PINCTRL_PIN_GROUP("jtag_dfd", an7583_jtag_dfd), + PINCTRL_PIN_GROUP("pcm1", an7583_pcm1), + PINCTRL_PIN_GROUP("pcm2", an7583_pcm2), + PINCTRL_PIN_GROUP("spi", an7583_spi), + PINCTRL_PIN_GROUP("spi_quad", an7583_spi_quad), + PINCTRL_PIN_GROUP("spi_cs1", an7583_spi_cs1), + PINCTRL_PIN_GROUP("pcm_spi", an7583_pcm_spi), + PINCTRL_PIN_GROUP("pcm_spi_rst", an7583_pcm_spi_rst), + PINCTRL_PIN_GROUP("pcm_spi_cs1", an7583_pcm_spi_cs1), + PINCTRL_PIN_GROUP("emmc", an7583_emmc), + PINCTRL_PIN_GROUP("pnand", an7583_pnand), + PINCTRL_PIN_GROUP("gpio0", an7583_gpio0), + PINCTRL_PIN_GROUP("gpio1", an7583_gpio1), + PINCTRL_PIN_GROUP("gpio2", an7583_gpio2), + PINCTRL_PIN_GROUP("gpio3", an7583_gpio3), + PINCTRL_PIN_GROUP("gpio4", an7583_gpio4), + PINCTRL_PIN_GROUP("gpio5", an7583_gpio5), + PINCTRL_PIN_GROUP("gpio6", an7583_gpio6), + PINCTRL_PIN_GROUP("gpio7", an7583_gpio7), + PINCTRL_PIN_GROUP("gpio8", an7583_gpio8), + PINCTRL_PIN_GROUP("gpio9", an7583_gpio9), + PINCTRL_PIN_GROUP("gpio10", an7583_gpio10), + PINCTRL_PIN_GROUP("gpio11", an7583_gpio11), + PINCTRL_PIN_GROUP("gpio12", an7583_gpio12), + PINCTRL_PIN_GROUP("gpio13", an7583_gpio13), + PINCTRL_PIN_GROUP("gpio14", an7583_gpio14), + PINCTRL_PIN_GROUP("gpio15", an7583_gpio15), + PINCTRL_PIN_GROUP("gpio16", an7583_gpio16), + PINCTRL_PIN_GROUP("gpio17", an7583_gpio17), + PINCTRL_PIN_GROUP("gpio18", an7583_gpio18), + PINCTRL_PIN_GROUP("gpio19", an7583_gpio19), + PINCTRL_PIN_GROUP("gpio20", an7583_gpio20), + PINCTRL_PIN_GROUP("gpio21", an7583_gpio21), + PINCTRL_PIN_GROUP("gpio22", an7583_gpio22), + PINCTRL_PIN_GROUP("gpio23", an7583_gpio23), + PINCTRL_PIN_GROUP("gpio24", an7583_gpio24), + PINCTRL_PIN_GROUP("gpio25", an7583_gpio25), + PINCTRL_PIN_GROUP("gpio26", an7583_gpio26), + PINCTRL_PIN_GROUP("gpio27", an7583_gpio27), + PINCTRL_PIN_GROUP("gpio28", an7583_gpio28), + PINCTRL_PIN_GROUP("gpio29", an7583_gpio29), + PINCTRL_PIN_GROUP("gpio30", an7583_gpio30), + PINCTRL_PIN_GROUP("gpio31", an7583_gpio31), + PINCTRL_PIN_GROUP("gpio32", an7583_gpio32), + PINCTRL_PIN_GROUP("gpio33", an7583_gpio33), + PINCTRL_PIN_GROUP("gpio34", an7583_gpio34), + PINCTRL_PIN_GROUP("gpio35", an7583_gpio35), + PINCTRL_PIN_GROUP("gpio36", an7583_gpio36), + PINCTRL_PIN_GROUP("gpio37", an7583_gpio37), + PINCTRL_PIN_GROUP("gpio38", an7583_gpio38), + PINCTRL_PIN_GROUP("gpio39", an7583_gpio39), + PINCTRL_PIN_GROUP("gpio40", an7583_gpio40), + PINCTRL_PIN_GROUP("gpio41", an7583_gpio41), + PINCTRL_PIN_GROUP("gpio42", an7583_gpio42), + PINCTRL_PIN_GROUP("gpio43", an7583_gpio43), + PINCTRL_PIN_GROUP("gpio44", an7583_gpio44), + PINCTRL_PIN_GROUP("gpio45", an7583_gpio45), + PINCTRL_PIN_GROUP("gpio46", an7583_gpio46), + PINCTRL_PIN_GROUP("gpio47", an7583_gpio47), + PINCTRL_PIN_GROUP("gpio48", an7583_gpio48), + PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0), + PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1), +}; + +static const char *const pon_groups[] =3D { "pon" }; +static const char *const tod_1pps_groups[] =3D { "pon_tod_1pps", "gsw_tod_= 1pps" }; +static const char *const sipo_groups[] =3D { "sipo", "sipo_rclk" }; +static const char *const an7583_mdio_groups[] =3D { "mdio" }; +static const char *const uart_groups[] =3D { "uart2", "uart2_cts_rts", "hs= uart", + "hsuart_cts_rts", "uart4", + "uart5" }; +static const char *const i2c_groups[] =3D { "i2c1" }; +static const char *const jtag_groups[] =3D { "jtag_udi", "jtag_dfd" }; +static const char *const pcm_groups[] =3D { "pcm1", "pcm2" }; +static const char *const spi_groups[] =3D { "spi_quad", "spi_cs1" }; +static const char *const an7583_pcm_spi_groups[] =3D { "pcm_spi", + "pcm_spi_rst", "pcm_spi_cs1" }; +static const char *const emmc_groups[] =3D { "emmc" }; +static const char *const pnand_groups[] =3D { "pnand" }; +static const char *const an7583_pcie_reset_groups[] =3D { "pcie_reset0", "= pcie_reset1" }; +static const char *const an7583_pwm_groups[] =3D { "gpio0", "gpio1", + "gpio2", "gpio3", + "gpio4", "gpio5", + "gpio6", "gpio7", + "gpio8", "gpio9", + "gpio10", "gpio11", + "gpio12", "gpio13", + "gpio14", "gpio15", + "gpio16", "gpio17", + "gpio18", "gpio19", + "gpio20", "gpio21", + "gpio22", "gpio23", + "gpio24", "gpio25", + "gpio26", "gpio27", + "gpio28", "gpio29", + "gpio30", "gpio31", + "gpio36", "gpio37", + "gpio38", "gpio39", + "gpio40", "gpio41", + "gpio42", "gpio43", + "gpio44", "gpio45", + "gpio46", "gpio47", + "gpio48" }; +static const char *const an7583_phy1_led0_groups[] =3D { "gpio1", "gpio2", + "gpio3", "gpio4" }; +static const char *const an7583_phy2_led0_groups[] =3D { "gpio1", "gpio2", + "gpio3", "gpio4" }; +static const char *const an7583_phy3_led0_groups[] =3D { "gpio1", "gpio2", + "gpio3", "gpio4" }; +static const char *const an7583_phy4_led0_groups[] =3D { "gpio1", "gpio2", + "gpio3", "gpio4" }; +static const char *const an7583_phy1_led1_groups[] =3D { "gpio8", "gpio9", + "gpio10", "gpio11" }; +static const char *const an7583_phy2_led1_groups[] =3D { "gpio8", "gpio9", + "gpio10", "gpio11" }; +static const char *const an7583_phy3_led1_groups[] =3D { "gpio8", "gpio9", + "gpio10", "gpio11" }; +static const char *const an7583_phy4_led1_groups[] =3D { "gpio8", "gpio9", + "gpio10", "gpio11" }; + +static const struct airoha_pinctrl_func_group pon_func_group[] =3D { + { + .name =3D "pon", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PON_MODE_MASK, + GPIO_PON_MODE_MASK + }, + .regmap_size =3D 1, + }, +}; + +static const struct airoha_pinctrl_func_group tod_1pps_func_group[] =3D { + { + .name =3D "pon_tod_1pps", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + PON_TOD_1PPS_MODE_MASK, + PON_TOD_1PPS_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "gsw_tod_1pps", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GSW_TOD_1PPS_MODE_MASK, + GSW_TOD_1PPS_MODE_MASK + }, + .regmap_size =3D 1, + }, +}; + +static const struct airoha_pinctrl_func_group sipo_func_group[] =3D { + { + .name =3D "sipo", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, + GPIO_SIPO_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "sipo_rclk", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK + }, + .regmap_size =3D 1, + }, +}; + +static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] =3D= { + { + .name =3D "mdio", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_SGMII_MDIO_MODE_MASK, + GPIO_SGMII_MDIO_MODE_MASK + }, + .regmap[1] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_MDC_IO_MASTER_MODE_MODE, + GPIO_MDC_IO_MASTER_MODE_MODE + }, + .regmap_size =3D 2, + }, +}; + +static const struct airoha_pinctrl_func_group uart_func_group[] =3D { + { + .name =3D "uart2", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_UART2_MODE_MASK, + GPIO_UART2_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "uart2_cts_rts", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK, + GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "hsuart", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, + GPIO_HSUART_MODE_MASK + }, + .regmap_size =3D 1, + }, + { + .name =3D "hsuart_cts_rts", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, + GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "uart4", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_UART4_MODE_MASK, + GPIO_UART4_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "uart5", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_UART5_MODE_MASK, + GPIO_UART5_MODE_MASK + }, + .regmap_size =3D 1, + }, +}; + +static const struct airoha_pinctrl_func_group i2c_func_group[] =3D { + { + .name =3D "i2c1", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_2ND_I2C_MODE_MASK, + GPIO_2ND_I2C_MODE_MASK + }, + .regmap_size =3D 1, + }, +}; + +static const struct airoha_pinctrl_func_group jtag_func_group[] =3D { + { + .name =3D "jtag_udi", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_NPU_UART_EN, + JTAG_UDI_EN_MASK, + JTAG_UDI_EN_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "jtag_dfd", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_NPU_UART_EN, + JTAG_DFD_EN_MASK, + JTAG_DFD_EN_MASK + }, + .regmap_size =3D 1, + }, +}; + +static const struct airoha_pinctrl_func_group pcm_func_group[] =3D { + { + .name =3D "pcm1", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM1_MODE_MASK, + GPIO_PCM1_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "pcm2", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM2_MODE_MASK, + GPIO_PCM2_MODE_MASK + }, + .regmap_size =3D 1, + }, +}; + +static const struct airoha_pinctrl_func_group spi_func_group[] =3D { + { + .name =3D "spi_quad", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_QUAD_MODE_MASK, + GPIO_SPI_QUAD_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "spi_cs1", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS1_MODE_MASK, + GPIO_SPI_CS1_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "spi_cs2", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS2_MODE_MASK, + GPIO_SPI_CS2_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "spi_cs3", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS3_MODE_MASK, + GPIO_SPI_CS3_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "spi_cs4", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS4_MODE_MASK, + GPIO_SPI_CS4_MODE_MASK + }, + .regmap_size =3D 1, + }, +}; + +static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[] = =3D { + { + .name =3D "pcm_spi", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_MODE_MASK, + GPIO_PCM_SPI_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "pcm_spi_int", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_INT_MODE_MASK, + GPIO_PCM_INT_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "pcm_spi_rst", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_RESET_MODE_MASK, + GPIO_PCM_RESET_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "pcm_spi_cs1", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS1_MODE_MASK, + GPIO_PCM_SPI_CS1_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "pcm_spi_cs2", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + AN7583_GPIO_PCM_SPI_CS2_MODE_MASK, + AN7583_GPIO_PCM_SPI_CS2_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "pcm_spi_cs3", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS3_MODE_MASK, + GPIO_PCM_SPI_CS3_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "pcm_spi_cs4", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS4_MODE_MASK, + GPIO_PCM_SPI_CS4_MODE_MASK + }, + .regmap_size =3D 1, + }, +}; + +static const struct airoha_pinctrl_func_group emmc_func_group[] =3D { + { + .name =3D "emmc", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_EMMC_MODE_MASK, + GPIO_EMMC_MODE_MASK + }, + .regmap_size =3D 1, + }, +}; + +static const struct airoha_pinctrl_func_group pnand_func_group[] =3D { + { + .name =3D "pnand", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PARALLEL_NAND_MODE_MASK, + GPIO_PARALLEL_NAND_MODE_MASK + }, + .regmap_size =3D 1, + }, +}; + +static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group= [] =3D { + { + .name =3D "pcie_reset0", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PCIE_RESET0_MASK, + GPIO_PCIE_RESET0_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "pcie_reset1", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PCIE_RESET1_MASK, + GPIO_PCIE_RESET1_MASK + }, + .regmap_size =3D 1, + }, +}; + +static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] =3D { + AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio47", GPIO47_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio48", GPIO48_FLASH_MODE_CFG), +}; + +static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[= ] =3D { + AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), +}; + +static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[= ] =3D { + AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), +}; + +static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[= ] =3D { + AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), +}; + +static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[= ] =3D { + AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), +}; + +static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[= ] =3D { + AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), +}; + +static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[= ] =3D { + AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), +}; + +static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[= ] =3D { + AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), +}; + +static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[= ] =3D { + AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), +}; + +static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] =3D { + PINCTRL_FUNC_DESC("pon", pon), + PINCTRL_FUNC_DESC("tod_1pps", tod_1pps), + PINCTRL_FUNC_DESC("sipo", sipo), + PINCTRL_FUNC_DESC("mdio", an7583_mdio), + PINCTRL_FUNC_DESC("uart", uart), + PINCTRL_FUNC_DESC("i2c", i2c), + PINCTRL_FUNC_DESC("jtag", jtag), + PINCTRL_FUNC_DESC("pcm", pcm), + PINCTRL_FUNC_DESC("spi", spi), + PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi), + PINCTRL_FUNC_DESC("emmc", emmc), + PINCTRL_FUNC_DESC("pnand", pnand), + PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset), + PINCTRL_FUNC_DESC("pwm", an7583_pwm), + PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0), + PINCTRL_FUNC_DESC("phy2_led0", an7583_phy2_led0), + PINCTRL_FUNC_DESC("phy3_led0", an7583_phy3_led0), + PINCTRL_FUNC_DESC("phy4_led0", an7583_phy4_led0), + PINCTRL_FUNC_DESC("phy1_led1", an7583_phy1_led1), + PINCTRL_FUNC_DESC("phy2_led1", an7583_phy2_led1), + PINCTRL_FUNC_DESC("phy3_led1", an7583_phy3_led1), + PINCTRL_FUNC_DESC("phy4_led1", an7583_phy4_led1), +}; + +static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] =3D { + PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)), + PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)), + PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)), + PINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(3)), + PINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(4)), + PINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(5)), + PINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(6)), + PINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(7)), + PINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(8)), + PINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(9)), + PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(10)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(11)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(12)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(13)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(14)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(15)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(16)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(17)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(18)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(19)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(20)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(21)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(22)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(23)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(24)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(25)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(26)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(27)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(28)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(29)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(30)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(31)), + PINCTRL_CONF_DESC(34, REG_GPIO_H_PU, BIT(0)), + PINCTRL_CONF_DESC(35, REG_GPIO_H_PU, BIT(1)), + PINCTRL_CONF_DESC(36, REG_GPIO_H_PU, BIT(2)), + PINCTRL_CONF_DESC(37, REG_GPIO_H_PU, BIT(3)), + PINCTRL_CONF_DESC(38, REG_GPIO_H_PU, BIT(4)), + PINCTRL_CONF_DESC(39, REG_GPIO_H_PU, BIT(5)), + PINCTRL_CONF_DESC(40, REG_GPIO_H_PU, BIT(6)), + PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, I2C_SCL_PU_MASK), + PINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_PU_MASK), + PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, AN7583_I2C1_SCL_PU_MASK), + PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, AN7583_I2C1_SDA_PU_MASK), + PINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, SPI_CLK_PU_MASK), + PINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_PU_MASK), + PINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK), + PINCTRL_CONF_DESC(48, REG_I2C_SDA_PU, SPI_MISO_PU_MASK), + PINCTRL_CONF_DESC(49, REG_I2C_SDA_PU, UART1_TXD_PU_MASK), + PINCTRL_CONF_DESC(50, REG_I2C_SDA_PU, UART1_RXD_PU_MASK), + PINCTRL_CONF_DESC(51, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK), + PINCTRL_CONF_DESC(52, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK), + PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, AN7583_MDC_0_PU_MASK), + PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, AN7583_MDIO_0_PU_MASK), +}; + +static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] =3D= { + PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)), + PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)), + PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)), + PINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(3)), + PINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(4)), + PINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(5)), + PINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(6)), + PINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(7)), + PINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(8)), + PINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(9)), + PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(10)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(11)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(12)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(13)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(14)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(15)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(16)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(17)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(18)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(19)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(20)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(21)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(22)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(23)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(24)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(25)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(26)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(27)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(28)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(29)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(30)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(31)), + PINCTRL_CONF_DESC(34, REG_GPIO_H_PD, BIT(0)), + PINCTRL_CONF_DESC(35, REG_GPIO_H_PD, BIT(1)), + PINCTRL_CONF_DESC(36, REG_GPIO_H_PD, BIT(2)), + PINCTRL_CONF_DESC(37, REG_GPIO_H_PD, BIT(3)), + PINCTRL_CONF_DESC(38, REG_GPIO_H_PD, BIT(4)), + PINCTRL_CONF_DESC(39, REG_GPIO_H_PD, BIT(5)), + PINCTRL_CONF_DESC(40, REG_GPIO_H_PD, BIT(6)), + PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, I2C_SCL_PD_MASK), + PINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_PD_MASK), + PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, AN7583_I2C1_SCL_PD_MASK), + PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, AN7583_I2C1_SDA_PD_MASK), + PINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, SPI_CLK_PD_MASK), + PINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_PD_MASK), + PINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK), + PINCTRL_CONF_DESC(48, REG_I2C_SDA_PD, SPI_MISO_PD_MASK), + PINCTRL_CONF_DESC(49, REG_I2C_SDA_PD, UART1_TXD_PD_MASK), + PINCTRL_CONF_DESC(50, REG_I2C_SDA_PD, UART1_RXD_PD_MASK), + PINCTRL_CONF_DESC(51, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK), + PINCTRL_CONF_DESC(52, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK), + PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, AN7583_MDC_0_PD_MASK), + PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, AN7583_MDIO_0_PD_MASK), +}; + +static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] =3D= { + PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)), + PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)), + PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)), + PINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(3)), + PINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(4)), + PINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(5)), + PINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(6)), + PINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(7)), + PINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(8)), + PINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(9)), + PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(10)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(11)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(12)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(13)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(14)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(15)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(16)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(17)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(18)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(19)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(20)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(21)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(22)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(23)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(24)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(25)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(26)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(27)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(28)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(29)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(30)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(31)), + PINCTRL_CONF_DESC(34, REG_GPIO_H_E2, BIT(0)), + PINCTRL_CONF_DESC(35, REG_GPIO_H_E2, BIT(1)), + PINCTRL_CONF_DESC(36, REG_GPIO_H_E2, BIT(2)), + PINCTRL_CONF_DESC(37, REG_GPIO_H_E2, BIT(3)), + PINCTRL_CONF_DESC(38, REG_GPIO_H_E2, BIT(4)), + PINCTRL_CONF_DESC(39, REG_GPIO_H_E2, BIT(5)), + PINCTRL_CONF_DESC(40, REG_GPIO_H_E2, BIT(6)), + PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, I2C_SCL_E2_MASK), + PINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_E2_MASK), + PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, AN7583_I2C1_SCL_E2_MASK), + PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, AN7583_I2C1_SDA_E2_MASK), + PINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, SPI_CLK_E2_MASK), + PINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_E2_MASK), + PINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK), + PINCTRL_CONF_DESC(48, REG_I2C_SDA_E2, SPI_MISO_E2_MASK), + PINCTRL_CONF_DESC(49, REG_I2C_SDA_E2, UART1_TXD_E2_MASK), + PINCTRL_CONF_DESC(50, REG_I2C_SDA_E2, UART1_RXD_E2_MASK), + PINCTRL_CONF_DESC(51, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK), + PINCTRL_CONF_DESC(52, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK), + PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, AN7583_MDC_0_E2_MASK), + PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, AN7583_MDIO_0_E2_MASK), +}; + +static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] =3D= { + PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)), + PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)), + PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)), + PINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(3)), + PINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(4)), + PINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(5)), + PINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(6)), + PINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(7)), + PINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(8)), + PINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(9)), + PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(10)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(11)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(12)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(13)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(14)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(15)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(16)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(17)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(18)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(19)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(20)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(21)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(22)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(23)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(24)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(25)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(26)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(27)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(28)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(29)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(30)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(31)), + PINCTRL_CONF_DESC(34, REG_GPIO_H_E4, BIT(0)), + PINCTRL_CONF_DESC(35, REG_GPIO_H_E4, BIT(1)), + PINCTRL_CONF_DESC(36, REG_GPIO_H_E4, BIT(2)), + PINCTRL_CONF_DESC(37, REG_GPIO_H_E4, BIT(3)), + PINCTRL_CONF_DESC(38, REG_GPIO_H_E4, BIT(4)), + PINCTRL_CONF_DESC(39, REG_GPIO_H_E4, BIT(5)), + PINCTRL_CONF_DESC(40, REG_GPIO_H_E4, BIT(6)), + PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, I2C_SCL_E4_MASK), + PINCTRL_CONF_DESC(42, REG_I2C_SDA_E4, I2C_SDA_E4_MASK), + PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, AN7583_I2C1_SCL_E4_MASK), + PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, AN7583_I2C1_SDA_E4_MASK), + PINCTRL_CONF_DESC(45, REG_I2C_SDA_E4, SPI_CLK_E4_MASK), + PINCTRL_CONF_DESC(46, REG_I2C_SDA_E4, SPI_CS0_E4_MASK), + PINCTRL_CONF_DESC(47, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK), + PINCTRL_CONF_DESC(48, REG_I2C_SDA_E4, SPI_MISO_E4_MASK), + PINCTRL_CONF_DESC(49, REG_I2C_SDA_E4, UART1_TXD_E4_MASK), + PINCTRL_CONF_DESC(50, REG_I2C_SDA_E4, UART1_RXD_E4_MASK), + PINCTRL_CONF_DESC(51, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK), + PINCTRL_CONF_DESC(52, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK), + PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, AN7583_MDC_0_E4_MASK), + PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, AN7583_MDIO_0_E4_MASK), +}; + +static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[] = =3D { + PINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK), + PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK), +}; + +static const struct airoha_pinctrl_match_data an7583_pinctrl_match_data = =3D { + .pins =3D an7583_pinctrl_pins, + .num_pins =3D ARRAY_SIZE(an7583_pinctrl_pins), + .grps =3D an7583_pinctrl_groups, + .num_grps =3D ARRAY_SIZE(an7583_pinctrl_groups), + .funcs =3D an7583_pinctrl_funcs, + .num_funcs =3D ARRAY_SIZE(an7583_pinctrl_funcs), + .confs_info =3D { + [AIROHA_PINCTRL_CONFS_PULLUP] =3D { + .confs =3D an7583_pinctrl_pullup_conf, + .num_confs =3D ARRAY_SIZE(an7583_pinctrl_pullup_conf), + }, + [AIROHA_PINCTRL_CONFS_PULLDOWN] =3D { + .confs =3D an7583_pinctrl_pulldown_conf, + .num_confs =3D ARRAY_SIZE(an7583_pinctrl_pulldown_conf), + }, + [AIROHA_PINCTRL_CONFS_DRIVE_E2] =3D { + .confs =3D an7583_pinctrl_drive_e2_conf, + .num_confs =3D ARRAY_SIZE(an7583_pinctrl_drive_e2_conf), + }, + [AIROHA_PINCTRL_CONFS_DRIVE_E4] =3D { + .confs =3D an7583_pinctrl_drive_e4_conf, + .num_confs =3D ARRAY_SIZE(an7583_pinctrl_drive_e4_conf), + }, + [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] =3D { + .confs =3D an7583_pinctrl_pcie_rst_od_conf, + .num_confs =3D ARRAY_SIZE(an7583_pinctrl_pcie_rst_od_conf), + }, + }, +}; + +static const struct of_device_id airoha_pinctrl_of_match[] =3D { + { .compatible =3D "airoha,an7583-pinctrl", .data =3D &an7583_pinctrl_matc= h_data }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match); + +static struct platform_driver airoha_pinctrl_driver =3D { + .probe =3D airoha_pinctrl_probe, + .driver =3D { + .name =3D "pinctrl-airoha-an7583", + .of_match_table =3D airoha_pinctrl_of_match, + }, +}; +module_platform_driver(airoha_pinctrl_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Lorenzo Bianconi "); +MODULE_AUTHOR("Benjamin Larsson "); +MODULE_AUTHOR("Markus Gothe "); +MODULE_DESCRIPTION("Pinctrl driver for Airoha AN7583 SoC"); --=20 2.53.0 From nobody Mon Jun 8 05:29:11 2026 Received: from PA4PR04CU001.outbound.protection.outlook.com (mail-francecentralazon11023095.outbound.protection.outlook.com [40.107.162.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 605EE2773D8; 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charset="utf-8" We have only an7581 specific code in the pinctrl-an7581 kernel module, so 'en7581_' prefix is not necessary anymore. Remove it. Signed-off-by: Mikhail Kshevetskiy --- drivers/pinctrl/airoha/pinctrl-an7581.c | 384 ++++++++++++------------ 1 file changed, 192 insertions(+), 192 deletions(-) diff --git a/drivers/pinctrl/airoha/pinctrl-an7581.c b/drivers/pinctrl/airo= ha/pinctrl-an7581.c index 22feb5e04388..56c452e278f5 100644 --- a/drivers/pinctrl/airoha/pinctrl-an7581.c +++ b/drivers/pinctrl/airoha/pinctrl-an7581.c @@ -7,7 +7,7 @@ =20 #include "airoha-common.h" =20 -static struct pinctrl_pin_desc en7581_pinctrl_pins[] =3D { +static struct pinctrl_pin_desc pinctrl_pins[] =3D { PINCTRL_PIN(0, "uart1_txd"), PINCTRL_PIN(1, "uart1_rxd"), PINCTRL_PIN(2, "i2c_scl"), @@ -68,174 +68,174 @@ static struct pinctrl_pin_desc en7581_pinctrl_pins[] = =3D { PINCTRL_PIN(63, "pcie_reset2"), }; =20 -static const int en7581_pon_pins[] =3D { 49, 50, 51, 52, 53, 54 }; -static const int en7581_pon_tod_1pps_pins[] =3D { 46 }; -static const int en7581_gsw_tod_1pps_pins[] =3D { 46 }; -static const int en7581_sipo_pins[] =3D { 16, 17 }; -static const int en7581_sipo_rclk_pins[] =3D { 16, 17, 43 }; -static const int en7581_mdio_pins[] =3D { 14, 15 }; -static const int en7581_uart2_pins[] =3D { 48, 55 }; -static const int en7581_uart2_cts_rts_pins[] =3D { 46, 47 }; -static const int en7581_hsuart_pins[] =3D { 28, 29 }; -static const int en7581_hsuart_cts_rts_pins[] =3D { 26, 27 }; -static const int en7581_uart4_pins[] =3D { 38, 39 }; -static const int en7581_uart5_pins[] =3D { 18, 19 }; -static const int en7581_i2c0_pins[] =3D { 2, 3 }; -static const int en7581_i2c1_pins[] =3D { 14, 15 }; -static const int en7581_jtag_udi_pins[] =3D { 16, 17, 18, 19, 20 }; -static const int en7581_jtag_dfd_pins[] =3D { 16, 17, 18, 19, 20 }; -static const int en7581_i2s_pins[] =3D { 26, 27, 28, 29 }; -static const int en7581_pcm1_pins[] =3D { 22, 23, 24, 25 }; -static const int en7581_pcm2_pins[] =3D { 18, 19, 20, 21 }; -static const int en7581_spi_quad_pins[] =3D { 32, 33 }; -static const int en7581_spi_pins[] =3D { 4, 5, 6, 7 }; -static const int en7581_spi_cs1_pins[] =3D { 34 }; -static const int en7581_pcm_spi_pins[] =3D { 18, 19, 20, 21, 22, 23, 24, 2= 5 }; -static const int en7581_pcm_spi_int_pins[] =3D { 14 }; -static const int en7581_pcm_spi_rst_pins[] =3D { 15 }; -static const int en7581_pcm_spi_cs1_pins[] =3D { 43 }; -static const int en7581_pcm_spi_cs2_pins[] =3D { 40 }; -static const int en7581_pcm_spi_cs2_p128_pins[] =3D { 40 }; -static const int en7581_pcm_spi_cs2_p156_pins[] =3D { 40 }; -static const int en7581_pcm_spi_cs3_pins[] =3D { 41 }; -static const int en7581_pcm_spi_cs4_pins[] =3D { 42 }; -static const int en7581_emmc_pins[] =3D { 4, 5, 6, 30, 31, 32, 33, 34, 35,= 36, 37 }; -static const int en7581_pnand_pins[] =3D { 4, 5, 6, 7, 30, 31, 32, 33, 34,= 35, 36, 37, 38, 39, 40, 41, 42 }; -static const int en7581_gpio0_pins[] =3D { 13 }; -static const int en7581_gpio1_pins[] =3D { 14 }; -static const int en7581_gpio2_pins[] =3D { 15 }; -static const int en7581_gpio3_pins[] =3D { 16 }; -static const int en7581_gpio4_pins[] =3D { 17 }; -static const int en7581_gpio5_pins[] =3D { 18 }; -static const int en7581_gpio6_pins[] =3D { 19 }; -static const int en7581_gpio7_pins[] =3D { 20 }; -static const int en7581_gpio8_pins[] =3D { 21 }; -static const int en7581_gpio9_pins[] =3D { 22 }; -static const int en7581_gpio10_pins[] =3D { 23 }; -static const int en7581_gpio11_pins[] =3D { 24 }; -static const int en7581_gpio12_pins[] =3D { 25 }; -static const int en7581_gpio13_pins[] =3D { 26 }; -static const int en7581_gpio14_pins[] =3D { 27 }; -static const int en7581_gpio15_pins[] =3D { 28 }; -static const int en7581_gpio16_pins[] =3D { 29 }; -static const int en7581_gpio17_pins[] =3D { 30 }; -static const int en7581_gpio18_pins[] =3D { 31 }; -static const int en7581_gpio19_pins[] =3D { 32 }; -static const int en7581_gpio20_pins[] =3D { 33 }; -static const int en7581_gpio21_pins[] =3D { 34 }; -static const int en7581_gpio22_pins[] =3D { 35 }; -static const int en7581_gpio23_pins[] =3D { 36 }; -static const int en7581_gpio24_pins[] =3D { 37 }; -static const int en7581_gpio25_pins[] =3D { 38 }; -static const int en7581_gpio26_pins[] =3D { 39 }; -static const int en7581_gpio27_pins[] =3D { 40 }; -static const int en7581_gpio28_pins[] =3D { 41 }; -static const int en7581_gpio29_pins[] =3D { 42 }; -static const int en7581_gpio30_pins[] =3D { 43 }; -static const int en7581_gpio31_pins[] =3D { 44 }; -static const int en7581_gpio32_pins[] =3D { 45 }; -static const int en7581_gpio33_pins[] =3D { 46 }; -static const int en7581_gpio34_pins[] =3D { 47 }; -static const int en7581_gpio35_pins[] =3D { 48 }; -static const int en7581_gpio36_pins[] =3D { 49 }; -static const int en7581_gpio37_pins[] =3D { 50 }; -static const int en7581_gpio38_pins[] =3D { 51 }; -static const int en7581_gpio39_pins[] =3D { 52 }; -static const int en7581_gpio40_pins[] =3D { 53 }; -static const int en7581_gpio41_pins[] =3D { 54 }; -static const int en7581_gpio42_pins[] =3D { 55 }; -static const int en7581_gpio43_pins[] =3D { 56 }; -static const int en7581_gpio44_pins[] =3D { 57 }; -static const int en7581_gpio45_pins[] =3D { 58 }; -static const int en7581_gpio46_pins[] =3D { 59 }; -static const int en7581_pcie_reset0_pins[] =3D { 61 }; -static const int en7581_pcie_reset1_pins[] =3D { 62 }; -static const int en7581_pcie_reset2_pins[] =3D { 63 }; +static const int pon_pins[] =3D { 49, 50, 51, 52, 53, 54 }; +static const int pon_tod_1pps_pins[] =3D { 46 }; +static const int gsw_tod_1pps_pins[] =3D { 46 }; +static const int sipo_pins[] =3D { 16, 17 }; +static const int sipo_rclk_pins[] =3D { 16, 17, 43 }; +static const int mdio_pins[] =3D { 14, 15 }; +static const int uart2_pins[] =3D { 48, 55 }; +static const int uart2_cts_rts_pins[] =3D { 46, 47 }; +static const int hsuart_pins[] =3D { 28, 29 }; +static const int hsuart_cts_rts_pins[] =3D { 26, 27 }; +static const int uart4_pins[] =3D { 38, 39 }; +static const int uart5_pins[] =3D { 18, 19 }; +static const int i2c0_pins[] =3D { 2, 3 }; +static const int i2c1_pins[] =3D { 14, 15 }; +static const int jtag_udi_pins[] =3D { 16, 17, 18, 19, 20 }; +static const int jtag_dfd_pins[] =3D { 16, 17, 18, 19, 20 }; +static const int i2s_pins[] =3D { 26, 27, 28, 29 }; +static const int pcm1_pins[] =3D { 22, 23, 24, 25 }; +static const int pcm2_pins[] =3D { 18, 19, 20, 21 }; +static const int spi_quad_pins[] =3D { 32, 33 }; +static const int spi_pins[] =3D { 4, 5, 6, 7 }; +static const int spi_cs1_pins[] =3D { 34 }; +static const int pcm_spi_pins[] =3D { 18, 19, 20, 21, 22, 23, 24, 25 }; +static const int pcm_spi_int_pins[] =3D { 14 }; +static const int pcm_spi_rst_pins[] =3D { 15 }; +static const int pcm_spi_cs1_pins[] =3D { 43 }; +static const int pcm_spi_cs2_pins[] =3D { 40 }; +static const int pcm_spi_cs2_p128_pins[] =3D { 40 }; +static const int pcm_spi_cs2_p156_pins[] =3D { 40 }; +static const int pcm_spi_cs3_pins[] =3D { 41 }; +static const int pcm_spi_cs4_pins[] =3D { 42 }; +static const int emmc_pins[] =3D { 4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37= }; +static const int pnand_pins[] =3D { 4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36= , 37, 38, 39, 40, 41, 42 }; +static const int gpio0_pins[] =3D { 13 }; +static const int gpio1_pins[] =3D { 14 }; +static const int gpio2_pins[] =3D { 15 }; +static const int gpio3_pins[] =3D { 16 }; +static const int gpio4_pins[] =3D { 17 }; +static const int gpio5_pins[] =3D { 18 }; +static const int gpio6_pins[] =3D { 19 }; +static const int gpio7_pins[] =3D { 20 }; +static const int gpio8_pins[] =3D { 21 }; +static const int gpio9_pins[] =3D { 22 }; +static const int gpio10_pins[] =3D { 23 }; +static const int gpio11_pins[] =3D { 24 }; +static const int gpio12_pins[] =3D { 25 }; +static const int gpio13_pins[] =3D { 26 }; +static const int gpio14_pins[] =3D { 27 }; +static const int gpio15_pins[] =3D { 28 }; +static const int gpio16_pins[] =3D { 29 }; +static const int gpio17_pins[] =3D { 30 }; +static const int gpio18_pins[] =3D { 31 }; +static const int gpio19_pins[] =3D { 32 }; +static const int gpio20_pins[] =3D { 33 }; +static const int gpio21_pins[] =3D { 34 }; +static const int gpio22_pins[] =3D { 35 }; +static const int gpio23_pins[] =3D { 36 }; +static const int gpio24_pins[] =3D { 37 }; +static const int gpio25_pins[] =3D { 38 }; +static const int gpio26_pins[] =3D { 39 }; +static const int gpio27_pins[] =3D { 40 }; +static const int gpio28_pins[] =3D { 41 }; +static const int gpio29_pins[] =3D { 42 }; +static const int gpio30_pins[] =3D { 43 }; +static const int gpio31_pins[] =3D { 44 }; +static const int gpio32_pins[] =3D { 45 }; +static const int gpio33_pins[] =3D { 46 }; +static const int gpio34_pins[] =3D { 47 }; +static const int gpio35_pins[] =3D { 48 }; +static const int gpio36_pins[] =3D { 49 }; +static const int gpio37_pins[] =3D { 50 }; +static const int gpio38_pins[] =3D { 51 }; +static const int gpio39_pins[] =3D { 52 }; +static const int gpio40_pins[] =3D { 53 }; +static const int gpio41_pins[] =3D { 54 }; +static const int gpio42_pins[] =3D { 55 }; +static const int gpio43_pins[] =3D { 56 }; +static const int gpio44_pins[] =3D { 57 }; +static const int gpio45_pins[] =3D { 58 }; +static const int gpio46_pins[] =3D { 59 }; +static const int pcie_reset0_pins[] =3D { 61 }; +static const int pcie_reset1_pins[] =3D { 62 }; +static const int pcie_reset2_pins[] =3D { 63 }; =20 -static const struct pingroup en7581_pinctrl_groups[] =3D { - PINCTRL_PIN_GROUP("pon", en7581_pon), - PINCTRL_PIN_GROUP("pon_tod_1pps", en7581_pon_tod_1pps), - PINCTRL_PIN_GROUP("gsw_tod_1pps", en7581_gsw_tod_1pps), - PINCTRL_PIN_GROUP("sipo", en7581_sipo), - PINCTRL_PIN_GROUP("sipo_rclk", en7581_sipo_rclk), - PINCTRL_PIN_GROUP("mdio", en7581_mdio), - PINCTRL_PIN_GROUP("uart2", en7581_uart2), - PINCTRL_PIN_GROUP("uart2_cts_rts", en7581_uart2_cts_rts), - PINCTRL_PIN_GROUP("hsuart", en7581_hsuart), - PINCTRL_PIN_GROUP("hsuart_cts_rts", en7581_hsuart_cts_rts), - PINCTRL_PIN_GROUP("uart4", en7581_uart4), - PINCTRL_PIN_GROUP("uart5", en7581_uart5), - PINCTRL_PIN_GROUP("i2c0", en7581_i2c0), - PINCTRL_PIN_GROUP("i2c1", en7581_i2c1), - PINCTRL_PIN_GROUP("jtag_udi", en7581_jtag_udi), - PINCTRL_PIN_GROUP("jtag_dfd", en7581_jtag_dfd), - PINCTRL_PIN_GROUP("i2s", en7581_i2s), - PINCTRL_PIN_GROUP("pcm1", en7581_pcm1), - PINCTRL_PIN_GROUP("pcm2", en7581_pcm2), - PINCTRL_PIN_GROUP("spi", en7581_spi), - PINCTRL_PIN_GROUP("spi_quad", en7581_spi_quad), - PINCTRL_PIN_GROUP("spi_cs1", en7581_spi_cs1), - PINCTRL_PIN_GROUP("pcm_spi", en7581_pcm_spi), - PINCTRL_PIN_GROUP("pcm_spi_int", en7581_pcm_spi_int), - PINCTRL_PIN_GROUP("pcm_spi_rst", en7581_pcm_spi_rst), - PINCTRL_PIN_GROUP("pcm_spi_cs1", en7581_pcm_spi_cs1), - PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7581_pcm_spi_cs2_p128), - PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7581_pcm_spi_cs2_p156), - PINCTRL_PIN_GROUP("pcm_spi_cs2", en7581_pcm_spi_cs2), - PINCTRL_PIN_GROUP("pcm_spi_cs3", en7581_pcm_spi_cs3), - PINCTRL_PIN_GROUP("pcm_spi_cs4", en7581_pcm_spi_cs4), - PINCTRL_PIN_GROUP("emmc", en7581_emmc), - PINCTRL_PIN_GROUP("pnand", en7581_pnand), - PINCTRL_PIN_GROUP("gpio0", en7581_gpio0), - PINCTRL_PIN_GROUP("gpio1", en7581_gpio1), - PINCTRL_PIN_GROUP("gpio2", en7581_gpio2), - PINCTRL_PIN_GROUP("gpio3", en7581_gpio3), - PINCTRL_PIN_GROUP("gpio4", en7581_gpio4), - PINCTRL_PIN_GROUP("gpio5", en7581_gpio5), - PINCTRL_PIN_GROUP("gpio6", en7581_gpio6), - PINCTRL_PIN_GROUP("gpio7", en7581_gpio7), - PINCTRL_PIN_GROUP("gpio8", en7581_gpio8), - PINCTRL_PIN_GROUP("gpio9", en7581_gpio9), - PINCTRL_PIN_GROUP("gpio10", en7581_gpio10), - PINCTRL_PIN_GROUP("gpio11", en7581_gpio11), - PINCTRL_PIN_GROUP("gpio12", en7581_gpio12), - PINCTRL_PIN_GROUP("gpio13", en7581_gpio13), - PINCTRL_PIN_GROUP("gpio14", en7581_gpio14), - PINCTRL_PIN_GROUP("gpio15", en7581_gpio15), - PINCTRL_PIN_GROUP("gpio16", en7581_gpio16), - PINCTRL_PIN_GROUP("gpio17", en7581_gpio17), - PINCTRL_PIN_GROUP("gpio18", en7581_gpio18), - PINCTRL_PIN_GROUP("gpio19", en7581_gpio19), - PINCTRL_PIN_GROUP("gpio20", en7581_gpio20), - PINCTRL_PIN_GROUP("gpio21", en7581_gpio21), - PINCTRL_PIN_GROUP("gpio22", en7581_gpio22), - PINCTRL_PIN_GROUP("gpio23", en7581_gpio23), - PINCTRL_PIN_GROUP("gpio24", en7581_gpio24), - PINCTRL_PIN_GROUP("gpio25", en7581_gpio25), - PINCTRL_PIN_GROUP("gpio26", en7581_gpio26), - PINCTRL_PIN_GROUP("gpio27", en7581_gpio27), - PINCTRL_PIN_GROUP("gpio28", en7581_gpio28), - PINCTRL_PIN_GROUP("gpio29", en7581_gpio29), - PINCTRL_PIN_GROUP("gpio30", en7581_gpio30), - PINCTRL_PIN_GROUP("gpio31", en7581_gpio31), - PINCTRL_PIN_GROUP("gpio32", en7581_gpio32), - PINCTRL_PIN_GROUP("gpio33", en7581_gpio33), - PINCTRL_PIN_GROUP("gpio34", en7581_gpio34), - PINCTRL_PIN_GROUP("gpio35", en7581_gpio35), - PINCTRL_PIN_GROUP("gpio36", en7581_gpio36), - PINCTRL_PIN_GROUP("gpio37", en7581_gpio37), - PINCTRL_PIN_GROUP("gpio38", en7581_gpio38), - PINCTRL_PIN_GROUP("gpio39", en7581_gpio39), - PINCTRL_PIN_GROUP("gpio40", en7581_gpio40), - PINCTRL_PIN_GROUP("gpio41", en7581_gpio41), - PINCTRL_PIN_GROUP("gpio42", en7581_gpio42), - PINCTRL_PIN_GROUP("gpio43", en7581_gpio43), - PINCTRL_PIN_GROUP("gpio44", en7581_gpio44), - PINCTRL_PIN_GROUP("gpio45", en7581_gpio45), - PINCTRL_PIN_GROUP("gpio46", en7581_gpio46), - PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0), - PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1), - PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2), +static const struct pingroup pinctrl_groups[] =3D { + PINCTRL_PIN_GROUP("pon", pon), + PINCTRL_PIN_GROUP("pon_tod_1pps", pon_tod_1pps), + PINCTRL_PIN_GROUP("gsw_tod_1pps", gsw_tod_1pps), + PINCTRL_PIN_GROUP("sipo", sipo), + PINCTRL_PIN_GROUP("sipo_rclk", sipo_rclk), + PINCTRL_PIN_GROUP("mdio", mdio), + PINCTRL_PIN_GROUP("uart2", uart2), + PINCTRL_PIN_GROUP("uart2_cts_rts", uart2_cts_rts), + PINCTRL_PIN_GROUP("hsuart", hsuart), + PINCTRL_PIN_GROUP("hsuart_cts_rts", hsuart_cts_rts), + PINCTRL_PIN_GROUP("uart4", uart4), + PINCTRL_PIN_GROUP("uart5", uart5), + PINCTRL_PIN_GROUP("i2c0", i2c0), + PINCTRL_PIN_GROUP("i2c1", i2c1), + PINCTRL_PIN_GROUP("jtag_udi", jtag_udi), + PINCTRL_PIN_GROUP("jtag_dfd", jtag_dfd), + PINCTRL_PIN_GROUP("i2s", i2s), + PINCTRL_PIN_GROUP("pcm1", pcm1), + PINCTRL_PIN_GROUP("pcm2", pcm2), + PINCTRL_PIN_GROUP("spi", spi), + PINCTRL_PIN_GROUP("spi_quad", spi_quad), + PINCTRL_PIN_GROUP("spi_cs1", spi_cs1), + PINCTRL_PIN_GROUP("pcm_spi", pcm_spi), + PINCTRL_PIN_GROUP("pcm_spi_int", pcm_spi_int), + PINCTRL_PIN_GROUP("pcm_spi_rst", pcm_spi_rst), + PINCTRL_PIN_GROUP("pcm_spi_cs1", pcm_spi_cs1), + PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", pcm_spi_cs2_p128), + PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", pcm_spi_cs2_p156), + PINCTRL_PIN_GROUP("pcm_spi_cs2", pcm_spi_cs2), + PINCTRL_PIN_GROUP("pcm_spi_cs3", pcm_spi_cs3), + PINCTRL_PIN_GROUP("pcm_spi_cs4", pcm_spi_cs4), + PINCTRL_PIN_GROUP("emmc", emmc), + PINCTRL_PIN_GROUP("pnand", pnand), + PINCTRL_PIN_GROUP("gpio0", gpio0), + PINCTRL_PIN_GROUP("gpio1", gpio1), + PINCTRL_PIN_GROUP("gpio2", gpio2), + PINCTRL_PIN_GROUP("gpio3", gpio3), + PINCTRL_PIN_GROUP("gpio4", gpio4), + PINCTRL_PIN_GROUP("gpio5", gpio5), + PINCTRL_PIN_GROUP("gpio6", gpio6), + PINCTRL_PIN_GROUP("gpio7", gpio7), + PINCTRL_PIN_GROUP("gpio8", gpio8), + PINCTRL_PIN_GROUP("gpio9", gpio9), + PINCTRL_PIN_GROUP("gpio10", gpio10), + PINCTRL_PIN_GROUP("gpio11", gpio11), + PINCTRL_PIN_GROUP("gpio12", gpio12), + PINCTRL_PIN_GROUP("gpio13", gpio13), + PINCTRL_PIN_GROUP("gpio14", gpio14), + PINCTRL_PIN_GROUP("gpio15", gpio15), + PINCTRL_PIN_GROUP("gpio16", gpio16), + PINCTRL_PIN_GROUP("gpio17", gpio17), + PINCTRL_PIN_GROUP("gpio18", gpio18), + PINCTRL_PIN_GROUP("gpio19", gpio19), + PINCTRL_PIN_GROUP("gpio20", gpio20), + PINCTRL_PIN_GROUP("gpio21", gpio21), + PINCTRL_PIN_GROUP("gpio22", gpio22), + PINCTRL_PIN_GROUP("gpio23", gpio23), + PINCTRL_PIN_GROUP("gpio24", gpio24), + PINCTRL_PIN_GROUP("gpio25", gpio25), + PINCTRL_PIN_GROUP("gpio26", gpio26), + PINCTRL_PIN_GROUP("gpio27", gpio27), + PINCTRL_PIN_GROUP("gpio28", gpio28), + PINCTRL_PIN_GROUP("gpio29", gpio29), + PINCTRL_PIN_GROUP("gpio30", gpio30), + PINCTRL_PIN_GROUP("gpio31", gpio31), + PINCTRL_PIN_GROUP("gpio32", gpio32), + PINCTRL_PIN_GROUP("gpio33", gpio33), + PINCTRL_PIN_GROUP("gpio34", gpio34), + PINCTRL_PIN_GROUP("gpio35", gpio35), + PINCTRL_PIN_GROUP("gpio36", gpio36), + PINCTRL_PIN_GROUP("gpio37", gpio37), + PINCTRL_PIN_GROUP("gpio38", gpio38), + PINCTRL_PIN_GROUP("gpio39", gpio39), + PINCTRL_PIN_GROUP("gpio40", gpio40), + PINCTRL_PIN_GROUP("gpio41", gpio41), + PINCTRL_PIN_GROUP("gpio42", gpio42), + PINCTRL_PIN_GROUP("gpio43", gpio43), + PINCTRL_PIN_GROUP("gpio44", gpio44), + PINCTRL_PIN_GROUP("gpio45", gpio45), + PINCTRL_PIN_GROUP("gpio46", gpio46), + PINCTRL_PIN_GROUP("pcie_reset0", pcie_reset0), + PINCTRL_PIN_GROUP("pcie_reset1", pcie_reset1), + PINCTRL_PIN_GROUP("pcie_reset2", pcie_reset2), }; =20 static const char *const pon_groups[] =3D { "pon" }; @@ -819,7 +819,7 @@ static const struct airoha_pinctrl_func_group phy4_led1= _func_group[] =3D { LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), }; =20 -static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] =3D { +static const struct airoha_pinctrl_func pinctrl_funcs[] =3D { PINCTRL_FUNC_DESC("pon", pon), PINCTRL_FUNC_DESC("tod_1pps", tod_1pps), PINCTRL_FUNC_DESC("sipo", sipo), @@ -845,7 +845,7 @@ static const struct airoha_pinctrl_func en7581_pinctrl_= funcs[] =3D { PINCTRL_FUNC_DESC("phy4_led1", phy4_led1), }; =20 -static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] =3D { +static const struct airoha_pinctrl_conf pinctrl_pullup_conf[] =3D { PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK), PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK), PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK), @@ -906,7 +906,7 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_= pullup_conf[] =3D { PINCTRL_CONF_DESC(63, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK), }; =20 -static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] =3D= { +static const struct airoha_pinctrl_conf pinctrl_pulldown_conf[] =3D { PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK), PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK), PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK), @@ -967,7 +967,7 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_= pulldown_conf[] =3D { PINCTRL_CONF_DESC(63, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK), }; =20 -static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] =3D= { +static const struct airoha_pinctrl_conf pinctrl_drive_e2_conf[] =3D { PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK), PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK), PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK), @@ -1028,7 +1028,7 @@ static const struct airoha_pinctrl_conf en7581_pinctr= l_drive_e2_conf[] =3D { PINCTRL_CONF_DESC(63, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK), }; =20 -static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] =3D= { +static const struct airoha_pinctrl_conf pinctrl_drive_e4_conf[] =3D { PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK), PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK), PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK), @@ -1089,45 +1089,45 @@ static const struct airoha_pinctrl_conf en7581_pinc= trl_drive_e4_conf[] =3D { PINCTRL_CONF_DESC(63, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK), }; =20 -static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = =3D { +static const struct airoha_pinctrl_conf pinctrl_pcie_rst_od_conf[] =3D { PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK), PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK), PINCTRL_CONF_DESC(63, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK), }; =20 -static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = =3D { - .pins =3D en7581_pinctrl_pins, - .num_pins =3D ARRAY_SIZE(en7581_pinctrl_pins), - .grps =3D en7581_pinctrl_groups, - .num_grps =3D ARRAY_SIZE(en7581_pinctrl_groups), - .funcs =3D en7581_pinctrl_funcs, - .num_funcs =3D ARRAY_SIZE(en7581_pinctrl_funcs), +static const struct airoha_pinctrl_match_data pinctrl_match_data =3D { + .pins =3D pinctrl_pins, + .num_pins =3D ARRAY_SIZE(pinctrl_pins), + .grps =3D pinctrl_groups, + .num_grps =3D ARRAY_SIZE(pinctrl_groups), + .funcs =3D pinctrl_funcs, + .num_funcs =3D ARRAY_SIZE(pinctrl_funcs), .confs_info =3D { [AIROHA_PINCTRL_CONFS_PULLUP] =3D { - .confs =3D en7581_pinctrl_pullup_conf, - .num_confs =3D ARRAY_SIZE(en7581_pinctrl_pullup_conf), + .confs =3D pinctrl_pullup_conf, + .num_confs =3D ARRAY_SIZE(pinctrl_pullup_conf), }, [AIROHA_PINCTRL_CONFS_PULLDOWN] =3D { - .confs =3D en7581_pinctrl_pulldown_conf, - .num_confs =3D ARRAY_SIZE(en7581_pinctrl_pulldown_conf), + .confs =3D pinctrl_pulldown_conf, + .num_confs =3D ARRAY_SIZE(pinctrl_pulldown_conf), }, [AIROHA_PINCTRL_CONFS_DRIVE_E2] =3D { - .confs =3D en7581_pinctrl_drive_e2_conf, - .num_confs =3D ARRAY_SIZE(en7581_pinctrl_drive_e2_conf), + .confs =3D pinctrl_drive_e2_conf, + .num_confs =3D ARRAY_SIZE(pinctrl_drive_e2_conf), }, [AIROHA_PINCTRL_CONFS_DRIVE_E4] =3D { - .confs =3D en7581_pinctrl_drive_e4_conf, - .num_confs =3D ARRAY_SIZE(en7581_pinctrl_drive_e4_conf), + .confs =3D pinctrl_drive_e4_conf, + .num_confs =3D ARRAY_SIZE(pinctrl_drive_e4_conf), }, [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] =3D { - .confs =3D en7581_pinctrl_pcie_rst_od_conf, - .num_confs =3D ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf), + .confs =3D pinctrl_pcie_rst_od_conf, + .num_confs =3D ARRAY_SIZE(pinctrl_pcie_rst_od_conf), }, }, }; =20 static const struct of_device_id airoha_pinctrl_of_match[] =3D { - { .compatible =3D "airoha,en7581-pinctrl", .data =3D &en7581_pinctrl_matc= h_data }, + { .compatible =3D "airoha,en7581-pinctrl", .data =3D &pinctrl_match_data = }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match); --=20 2.53.0 From nobody Mon Jun 8 05:29:11 2026 Received: from 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Walleij , Sean Wang , Lorenzo Bianconi , Matthias Brugger , AngeloGioacchino Del Regno , Christian Marangi , Bartosz Golaszewski , Benjamin Larsson , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Matheus Sampaio Queiroga , Markus Gothe Cc: Mikhail Kshevetskiy Subject: [PATCH 16/18] pinctrl: airoha: an7583: remove an7583 prefix from variable names Date: Sun, 7 Jun 2026 03:16:52 +0300 Message-ID: <20260607001654.1439480-17-mikhail.kshevetskiy@iopsys.eu> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260607001654.1439480-1-mikhail.kshevetskiy@iopsys.eu> References: <20260607001654.1439480-1-mikhail.kshevetskiy@iopsys.eu> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: GV3PEPF0001DBFE.SWEP280.PROD.OUTLOOK.COM (2603:10a6:158:400::319) To DU2PR08MB10037.eurprd08.prod.outlook.com (2603:10a6:10:49a::20) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: 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X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 8d891be1-7bce-4216-9a99-bee9de02ba58 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: xN6tmjsfeBaRIMqX7VoIh4RqVLLEYLV+JxdDycy1SiiWEarX5u4GoHSbif9b1TaLHAt+jneH7PpBWgNoEqYLAwk6Fohg5xHpg5eW1EyGl4c= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MRWPR08MB11707 Content-Type: text/plain; charset="utf-8" We have only an7583 specific code in the pinctrl-an7583 kernel module, so 'an75831_' prefix is not necessary anymore. Remove it. Signed-off-by: Mikhail Kshevetskiy --- drivers/pinctrl/airoha/pinctrl-an7583.c | 482 ++++++++++++------------ 1 file changed, 241 insertions(+), 241 deletions(-) diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airo= ha/pinctrl-an7583.c index 5b5e766abd45..4675cdf7727d 100644 --- a/drivers/pinctrl/airoha/pinctrl-an7583.c +++ b/drivers/pinctrl/airoha/pinctrl-an7583.c @@ -7,7 +7,7 @@ =20 #include "airoha-common.h" =20 -static struct pinctrl_pin_desc an7583_pinctrl_pins[] =3D { +static struct pinctrl_pin_desc pinctrl_pins[] =3D { PINCTRL_PIN(2, "gpio0"), PINCTRL_PIN(3, "gpio1"), PINCTRL_PIN(4, "gpio2"), @@ -63,170 +63,170 @@ static struct pinctrl_pin_desc an7583_pinctrl_pins[] = =3D { PINCTRL_PIN(54, "mdio_0"), }; =20 -static const int an7583_pon_pins[] =3D { 15, 16, 17, 18, 19, 20 }; -static const int an7583_pon_tod_1pps_pins[] =3D { 32 }; -static const int an7583_gsw_tod_1pps_pins[] =3D { 32 }; -static const int an7583_sipo_pins[] =3D { 34, 35 }; -static const int an7583_sipo_rclk_pins[] =3D { 34, 35, 33 }; -static const int an7583_mdio_pins[] =3D { 43, 44 }; -static const int an7583_uart2_pins[] =3D { 34, 35 }; -static const int an7583_uart2_cts_rts_pins[] =3D { 32, 33 }; -static const int an7583_hsuart_pins[] =3D { 30, 31 }; -static const int an7583_hsuart_cts_rts_pins[] =3D { 28, 29 }; -static const int an7583_npu_uart_pins[] =3D { 7, 8 }; -static const int an7583_uart4_pins[] =3D { 7, 8 }; -static const int an7583_uart5_pins[] =3D { 23, 24 }; -static const int an7583_i2c0_pins[] =3D { 41, 42 }; -static const int an7583_i2c1_pins[] =3D { 43, 44 }; -static const int an7583_jtag_udi_pins[] =3D { 23, 24, 22, 25, 26 }; -static const int an7583_jtag_dfd_pins[] =3D { 23, 24, 22, 25, 26 }; -static const int an7583_pcm1_pins[] =3D { 10, 11, 12, 13, 14 }; -static const int an7583_pcm2_pins[] =3D { 28, 29, 30, 31, 24 }; -static const int an7583_spi_pins[] =3D { 28, 29, 30, 31 }; -static const int an7583_spi_quad_pins[] =3D { 25, 26 }; -static const int an7583_spi_cs1_pins[] =3D { 27 }; -static const int an7583_pcm_spi_pins[] =3D { 28, 29, 30, 31, 10, 11, 12, 1= 3 }; -static const int an7583_pcm_spi_rst_pins[] =3D { 14 }; -static const int an7583_pcm_spi_cs1_pins[] =3D { 24 }; -static const int an7583_emmc_pins[] =3D { 7, 8, 9, 22, 23, 24, 25, 26, 45,= 46, 47 }; -static const int an7583_pnand_pins[] =3D { 7, 8, 9, 22, 23, 24, 25, 26, 27= , 28, 29, 30, 31, 45, 46, 47, 48 }; -static const int an7583_gpio0_pins[] =3D { 2 }; -static const int an7583_gpio1_pins[] =3D { 3 }; -static const int an7583_gpio2_pins[] =3D { 4 }; -static const int an7583_gpio3_pins[] =3D { 5 }; -static const int an7583_gpio4_pins[] =3D { 6 }; -static const int an7583_gpio5_pins[] =3D { 7 }; -static const int an7583_gpio6_pins[] =3D { 8 }; -static const int an7583_gpio7_pins[] =3D { 9 }; -static const int an7583_gpio8_pins[] =3D { 10 }; -static const int an7583_gpio9_pins[] =3D { 11 }; -static const int an7583_gpio10_pins[] =3D { 12 }; -static const int an7583_gpio11_pins[] =3D { 13 }; -static const int an7583_gpio12_pins[] =3D { 14 }; -static const int an7583_gpio13_pins[] =3D { 15 }; -static const int an7583_gpio14_pins[] =3D { 16 }; -static const int an7583_gpio15_pins[] =3D { 17 }; -static const int an7583_gpio16_pins[] =3D { 18 }; -static const int an7583_gpio17_pins[] =3D { 19 }; -static const int an7583_gpio18_pins[] =3D { 20 }; -static const int an7583_gpio19_pins[] =3D { 21 }; -static const int an7583_gpio20_pins[] =3D { 22 }; -static const int an7583_gpio21_pins[] =3D { 23 }; -static const int an7583_gpio22_pins[] =3D { 24 }; -static const int an7583_gpio23_pins[] =3D { 25 }; -static const int an7583_gpio24_pins[] =3D { 26 }; -static const int an7583_gpio25_pins[] =3D { 27 }; -static const int an7583_gpio26_pins[] =3D { 28 }; -static const int an7583_gpio27_pins[] =3D { 29 }; -static const int an7583_gpio28_pins[] =3D { 30 }; -static const int an7583_gpio29_pins[] =3D { 31 }; -static const int an7583_gpio30_pins[] =3D { 32 }; -static const int an7583_gpio31_pins[] =3D { 33 }; -static const int an7583_gpio32_pins[] =3D { 34 }; -static const int an7583_gpio33_pins[] =3D { 35 }; -static const int an7583_gpio34_pins[] =3D { 36 }; -static const int an7583_gpio35_pins[] =3D { 37 }; -static const int an7583_gpio36_pins[] =3D { 38 }; -static const int an7583_gpio37_pins[] =3D { 39 }; -static const int an7583_gpio38_pins[] =3D { 40 }; -static const int an7583_gpio39_pins[] =3D { 41 }; -static const int an7583_gpio40_pins[] =3D { 42 }; -static const int an7583_gpio41_pins[] =3D { 43 }; -static const int an7583_gpio42_pins[] =3D { 44 }; -static const int an7583_gpio43_pins[] =3D { 45 }; -static const int an7583_gpio44_pins[] =3D { 46 }; -static const int an7583_gpio45_pins[] =3D { 47 }; -static const int an7583_gpio46_pins[] =3D { 48 }; -static const int an7583_gpio47_pins[] =3D { 49 }; -static const int an7583_gpio48_pins[] =3D { 50 }; -static const int an7583_pcie_reset0_pins[] =3D { 51 }; -static const int an7583_pcie_reset1_pins[] =3D { 52 }; +static const int pon_pins[] =3D { 15, 16, 17, 18, 19, 20 }; +static const int pon_tod_1pps_pins[] =3D { 32 }; +static const int gsw_tod_1pps_pins[] =3D { 32 }; +static const int sipo_pins[] =3D { 34, 35 }; +static const int sipo_rclk_pins[] =3D { 34, 35, 33 }; +static const int mdio_pins[] =3D { 43, 44 }; +static const int uart2_pins[] =3D { 34, 35 }; +static const int uart2_cts_rts_pins[] =3D { 32, 33 }; +static const int hsuart_pins[] =3D { 30, 31 }; +static const int hsuart_cts_rts_pins[] =3D { 28, 29 }; +static const int npu_uart_pins[] =3D { 7, 8 }; +static const int uart4_pins[] =3D { 7, 8 }; +static const int uart5_pins[] =3D { 23, 24 }; +static const int i2c0_pins[] =3D { 41, 42 }; +static const int i2c1_pins[] =3D { 43, 44 }; +static const int jtag_udi_pins[] =3D { 23, 24, 22, 25, 26 }; +static const int jtag_dfd_pins[] =3D { 23, 24, 22, 25, 26 }; +static const int pcm1_pins[] =3D { 10, 11, 12, 13, 14 }; +static const int pcm2_pins[] =3D { 28, 29, 30, 31, 24 }; +static const int spi_pins[] =3D { 28, 29, 30, 31 }; +static const int spi_quad_pins[] =3D { 25, 26 }; +static const int spi_cs1_pins[] =3D { 27 }; +static const int pcm_spi_pins[] =3D { 28, 29, 30, 31, 10, 11, 12, 13 }; +static const int pcm_spi_rst_pins[] =3D { 14 }; +static const int pcm_spi_cs1_pins[] =3D { 24 }; +static const int emmc_pins[] =3D { 7, 8, 9, 22, 23, 24, 25, 26, 45, 46, 47= }; +static const int pnand_pins[] =3D { 7, 8, 9, 22, 23, 24, 25, 26, 27, 28, 2= 9, 30, 31, 45, 46, 47, 48 }; +static const int gpio0_pins[] =3D { 2 }; +static const int gpio1_pins[] =3D { 3 }; +static const int gpio2_pins[] =3D { 4 }; +static const int gpio3_pins[] =3D { 5 }; +static const int gpio4_pins[] =3D { 6 }; +static const int gpio5_pins[] =3D { 7 }; +static const int gpio6_pins[] =3D { 8 }; +static const int gpio7_pins[] =3D { 9 }; +static const int gpio8_pins[] =3D { 10 }; +static const int gpio9_pins[] =3D { 11 }; +static const int gpio10_pins[] =3D { 12 }; +static const int gpio11_pins[] =3D { 13 }; +static const int gpio12_pins[] =3D { 14 }; +static const int gpio13_pins[] =3D { 15 }; +static const int gpio14_pins[] =3D { 16 }; +static const int gpio15_pins[] =3D { 17 }; +static const int gpio16_pins[] =3D { 18 }; +static const int gpio17_pins[] =3D { 19 }; +static const int gpio18_pins[] =3D { 20 }; +static const int gpio19_pins[] =3D { 21 }; +static const int gpio20_pins[] =3D { 22 }; +static const int gpio21_pins[] =3D { 23 }; +static const int gpio22_pins[] =3D { 24 }; +static const int gpio23_pins[] =3D { 25 }; +static const int gpio24_pins[] =3D { 26 }; +static const int gpio25_pins[] =3D { 27 }; +static const int gpio26_pins[] =3D { 28 }; +static const int gpio27_pins[] =3D { 29 }; +static const int gpio28_pins[] =3D { 30 }; +static const int gpio29_pins[] =3D { 31 }; +static const int gpio30_pins[] =3D { 32 }; +static const int gpio31_pins[] =3D { 33 }; +static const int gpio32_pins[] =3D { 34 }; +static const int gpio33_pins[] =3D { 35 }; +static const int gpio34_pins[] =3D { 36 }; +static const int gpio35_pins[] =3D { 37 }; +static const int gpio36_pins[] =3D { 38 }; +static const int gpio37_pins[] =3D { 39 }; +static const int gpio38_pins[] =3D { 40 }; +static const int gpio39_pins[] =3D { 41 }; +static const int gpio40_pins[] =3D { 42 }; +static const int gpio41_pins[] =3D { 43 }; +static const int gpio42_pins[] =3D { 44 }; +static const int gpio43_pins[] =3D { 45 }; +static const int gpio44_pins[] =3D { 46 }; +static const int gpio45_pins[] =3D { 47 }; +static const int gpio46_pins[] =3D { 48 }; +static const int gpio47_pins[] =3D { 49 }; +static const int gpio48_pins[] =3D { 50 }; +static const int pcie_reset0_pins[] =3D { 51 }; +static const int pcie_reset1_pins[] =3D { 52 }; =20 -static const struct pingroup an7583_pinctrl_groups[] =3D { - PINCTRL_PIN_GROUP("pon", an7583_pon), - PINCTRL_PIN_GROUP("pon_tod_1pps", an7583_pon_tod_1pps), - PINCTRL_PIN_GROUP("gsw_tod_1pps", an7583_gsw_tod_1pps), - PINCTRL_PIN_GROUP("sipo", an7583_sipo), - PINCTRL_PIN_GROUP("sipo_rclk", an7583_sipo_rclk), - PINCTRL_PIN_GROUP("mdio", an7583_mdio), - PINCTRL_PIN_GROUP("uart2", an7583_uart2), - PINCTRL_PIN_GROUP("uart2_cts_rts", an7583_uart2_cts_rts), - PINCTRL_PIN_GROUP("hsuart", an7583_hsuart), - PINCTRL_PIN_GROUP("hsuart_cts_rts", an7583_hsuart_cts_rts), - PINCTRL_PIN_GROUP("npu_uart", an7583_npu_uart), - PINCTRL_PIN_GROUP("uart4", an7583_uart4), - PINCTRL_PIN_GROUP("uart5", an7583_uart5), - PINCTRL_PIN_GROUP("i2c0", an7583_i2c0), - PINCTRL_PIN_GROUP("i2c1", an7583_i2c1), - PINCTRL_PIN_GROUP("jtag_udi", an7583_jtag_udi), - PINCTRL_PIN_GROUP("jtag_dfd", an7583_jtag_dfd), - PINCTRL_PIN_GROUP("pcm1", an7583_pcm1), - PINCTRL_PIN_GROUP("pcm2", an7583_pcm2), - PINCTRL_PIN_GROUP("spi", an7583_spi), - PINCTRL_PIN_GROUP("spi_quad", an7583_spi_quad), - PINCTRL_PIN_GROUP("spi_cs1", an7583_spi_cs1), - PINCTRL_PIN_GROUP("pcm_spi", an7583_pcm_spi), - PINCTRL_PIN_GROUP("pcm_spi_rst", an7583_pcm_spi_rst), - PINCTRL_PIN_GROUP("pcm_spi_cs1", an7583_pcm_spi_cs1), - PINCTRL_PIN_GROUP("emmc", an7583_emmc), - PINCTRL_PIN_GROUP("pnand", an7583_pnand), - PINCTRL_PIN_GROUP("gpio0", an7583_gpio0), - PINCTRL_PIN_GROUP("gpio1", an7583_gpio1), - PINCTRL_PIN_GROUP("gpio2", an7583_gpio2), - PINCTRL_PIN_GROUP("gpio3", an7583_gpio3), - PINCTRL_PIN_GROUP("gpio4", an7583_gpio4), - PINCTRL_PIN_GROUP("gpio5", an7583_gpio5), - PINCTRL_PIN_GROUP("gpio6", an7583_gpio6), - PINCTRL_PIN_GROUP("gpio7", an7583_gpio7), - PINCTRL_PIN_GROUP("gpio8", an7583_gpio8), - PINCTRL_PIN_GROUP("gpio9", an7583_gpio9), - PINCTRL_PIN_GROUP("gpio10", an7583_gpio10), - PINCTRL_PIN_GROUP("gpio11", an7583_gpio11), - PINCTRL_PIN_GROUP("gpio12", an7583_gpio12), - PINCTRL_PIN_GROUP("gpio13", an7583_gpio13), - PINCTRL_PIN_GROUP("gpio14", an7583_gpio14), - PINCTRL_PIN_GROUP("gpio15", an7583_gpio15), - PINCTRL_PIN_GROUP("gpio16", an7583_gpio16), - PINCTRL_PIN_GROUP("gpio17", an7583_gpio17), - PINCTRL_PIN_GROUP("gpio18", an7583_gpio18), - PINCTRL_PIN_GROUP("gpio19", an7583_gpio19), - PINCTRL_PIN_GROUP("gpio20", an7583_gpio20), - PINCTRL_PIN_GROUP("gpio21", an7583_gpio21), - PINCTRL_PIN_GROUP("gpio22", an7583_gpio22), - PINCTRL_PIN_GROUP("gpio23", an7583_gpio23), - PINCTRL_PIN_GROUP("gpio24", an7583_gpio24), - PINCTRL_PIN_GROUP("gpio25", an7583_gpio25), - PINCTRL_PIN_GROUP("gpio26", an7583_gpio26), - PINCTRL_PIN_GROUP("gpio27", an7583_gpio27), - PINCTRL_PIN_GROUP("gpio28", an7583_gpio28), - PINCTRL_PIN_GROUP("gpio29", an7583_gpio29), - PINCTRL_PIN_GROUP("gpio30", an7583_gpio30), - PINCTRL_PIN_GROUP("gpio31", an7583_gpio31), - PINCTRL_PIN_GROUP("gpio32", an7583_gpio32), - PINCTRL_PIN_GROUP("gpio33", an7583_gpio33), - PINCTRL_PIN_GROUP("gpio34", an7583_gpio34), - PINCTRL_PIN_GROUP("gpio35", an7583_gpio35), - PINCTRL_PIN_GROUP("gpio36", an7583_gpio36), - PINCTRL_PIN_GROUP("gpio37", an7583_gpio37), - PINCTRL_PIN_GROUP("gpio38", an7583_gpio38), - PINCTRL_PIN_GROUP("gpio39", an7583_gpio39), - PINCTRL_PIN_GROUP("gpio40", an7583_gpio40), - PINCTRL_PIN_GROUP("gpio41", an7583_gpio41), - PINCTRL_PIN_GROUP("gpio42", an7583_gpio42), - PINCTRL_PIN_GROUP("gpio43", an7583_gpio43), - PINCTRL_PIN_GROUP("gpio44", an7583_gpio44), - PINCTRL_PIN_GROUP("gpio45", an7583_gpio45), - PINCTRL_PIN_GROUP("gpio46", an7583_gpio46), - PINCTRL_PIN_GROUP("gpio47", an7583_gpio47), - PINCTRL_PIN_GROUP("gpio48", an7583_gpio48), - PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0), - PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1), +static const struct pingroup pinctrl_groups[] =3D { + PINCTRL_PIN_GROUP("pon", pon), + PINCTRL_PIN_GROUP("pon_tod_1pps", pon_tod_1pps), + PINCTRL_PIN_GROUP("gsw_tod_1pps", gsw_tod_1pps), + PINCTRL_PIN_GROUP("sipo", sipo), + PINCTRL_PIN_GROUP("sipo_rclk", sipo_rclk), + PINCTRL_PIN_GROUP("mdio", mdio), + PINCTRL_PIN_GROUP("uart2", uart2), + PINCTRL_PIN_GROUP("uart2_cts_rts", uart2_cts_rts), + PINCTRL_PIN_GROUP("hsuart", hsuart), + PINCTRL_PIN_GROUP("hsuart_cts_rts", hsuart_cts_rts), + PINCTRL_PIN_GROUP("npu_uart", npu_uart), + PINCTRL_PIN_GROUP("uart4", uart4), + PINCTRL_PIN_GROUP("uart5", uart5), + PINCTRL_PIN_GROUP("i2c0", i2c0), + PINCTRL_PIN_GROUP("i2c1", i2c1), + PINCTRL_PIN_GROUP("jtag_udi", jtag_udi), + PINCTRL_PIN_GROUP("jtag_dfd", jtag_dfd), + PINCTRL_PIN_GROUP("pcm1", pcm1), + PINCTRL_PIN_GROUP("pcm2", pcm2), + PINCTRL_PIN_GROUP("spi", spi), + PINCTRL_PIN_GROUP("spi_quad", spi_quad), + PINCTRL_PIN_GROUP("spi_cs1", spi_cs1), + PINCTRL_PIN_GROUP("pcm_spi", pcm_spi), + PINCTRL_PIN_GROUP("pcm_spi_rst", pcm_spi_rst), + PINCTRL_PIN_GROUP("pcm_spi_cs1", pcm_spi_cs1), + PINCTRL_PIN_GROUP("emmc", emmc), + PINCTRL_PIN_GROUP("pnand", pnand), + PINCTRL_PIN_GROUP("gpio0", gpio0), + PINCTRL_PIN_GROUP("gpio1", gpio1), + PINCTRL_PIN_GROUP("gpio2", gpio2), + PINCTRL_PIN_GROUP("gpio3", gpio3), + PINCTRL_PIN_GROUP("gpio4", gpio4), + PINCTRL_PIN_GROUP("gpio5", gpio5), + PINCTRL_PIN_GROUP("gpio6", gpio6), + PINCTRL_PIN_GROUP("gpio7", gpio7), + PINCTRL_PIN_GROUP("gpio8", gpio8), + PINCTRL_PIN_GROUP("gpio9", gpio9), + PINCTRL_PIN_GROUP("gpio10", gpio10), + PINCTRL_PIN_GROUP("gpio11", gpio11), + PINCTRL_PIN_GROUP("gpio12", gpio12), + PINCTRL_PIN_GROUP("gpio13", gpio13), + PINCTRL_PIN_GROUP("gpio14", gpio14), + PINCTRL_PIN_GROUP("gpio15", gpio15), + PINCTRL_PIN_GROUP("gpio16", gpio16), + PINCTRL_PIN_GROUP("gpio17", gpio17), + PINCTRL_PIN_GROUP("gpio18", gpio18), + PINCTRL_PIN_GROUP("gpio19", gpio19), + PINCTRL_PIN_GROUP("gpio20", gpio20), + PINCTRL_PIN_GROUP("gpio21", gpio21), + PINCTRL_PIN_GROUP("gpio22", gpio22), + PINCTRL_PIN_GROUP("gpio23", gpio23), + PINCTRL_PIN_GROUP("gpio24", gpio24), + PINCTRL_PIN_GROUP("gpio25", gpio25), + PINCTRL_PIN_GROUP("gpio26", gpio26), + PINCTRL_PIN_GROUP("gpio27", gpio27), + PINCTRL_PIN_GROUP("gpio28", gpio28), + PINCTRL_PIN_GROUP("gpio29", gpio29), + PINCTRL_PIN_GROUP("gpio30", gpio30), + PINCTRL_PIN_GROUP("gpio31", gpio31), + PINCTRL_PIN_GROUP("gpio32", gpio32), + PINCTRL_PIN_GROUP("gpio33", gpio33), + PINCTRL_PIN_GROUP("gpio34", gpio34), + PINCTRL_PIN_GROUP("gpio35", gpio35), + PINCTRL_PIN_GROUP("gpio36", gpio36), + PINCTRL_PIN_GROUP("gpio37", gpio37), + PINCTRL_PIN_GROUP("gpio38", gpio38), + PINCTRL_PIN_GROUP("gpio39", gpio39), + PINCTRL_PIN_GROUP("gpio40", gpio40), + PINCTRL_PIN_GROUP("gpio41", gpio41), + PINCTRL_PIN_GROUP("gpio42", gpio42), + PINCTRL_PIN_GROUP("gpio43", gpio43), + PINCTRL_PIN_GROUP("gpio44", gpio44), + PINCTRL_PIN_GROUP("gpio45", gpio45), + PINCTRL_PIN_GROUP("gpio46", gpio46), + PINCTRL_PIN_GROUP("gpio47", gpio47), + PINCTRL_PIN_GROUP("gpio48", gpio48), + PINCTRL_PIN_GROUP("pcie_reset0", pcie_reset0), + PINCTRL_PIN_GROUP("pcie_reset1", pcie_reset1), }; =20 static const char *const pon_groups[] =3D { "pon" }; static const char *const tod_1pps_groups[] =3D { "pon_tod_1pps", "gsw_tod_= 1pps" }; static const char *const sipo_groups[] =3D { "sipo", "sipo_rclk" }; -static const char *const an7583_mdio_groups[] =3D { "mdio" }; +static const char *const mdio_groups[] =3D { "mdio" }; static const char *const uart_groups[] =3D { "uart2", "uart2_cts_rts", "hs= uart", "hsuart_cts_rts", "uart4", "uart5" }; @@ -234,49 +234,49 @@ static const char *const i2c_groups[] =3D { "i2c1" }; static const char *const jtag_groups[] =3D { "jtag_udi", "jtag_dfd" }; static const char *const pcm_groups[] =3D { "pcm1", "pcm2" }; static const char *const spi_groups[] =3D { "spi_quad", "spi_cs1" }; -static const char *const an7583_pcm_spi_groups[] =3D { "pcm_spi", - "pcm_spi_rst", "pcm_spi_cs1" }; +static const char *const pcm_spi_groups[] =3D { "pcm_spi", + "pcm_spi_rst", "pcm_spi_cs1" }; static const char *const emmc_groups[] =3D { "emmc" }; static const char *const pnand_groups[] =3D { "pnand" }; -static const char *const an7583_pcie_reset_groups[] =3D { "pcie_reset0", "= pcie_reset1" }; -static const char *const an7583_pwm_groups[] =3D { "gpio0", "gpio1", - "gpio2", "gpio3", - "gpio4", "gpio5", - "gpio6", "gpio7", - "gpio8", "gpio9", - "gpio10", "gpio11", - "gpio12", "gpio13", - "gpio14", "gpio15", - "gpio16", "gpio17", - "gpio18", "gpio19", - "gpio20", "gpio21", - "gpio22", "gpio23", - "gpio24", "gpio25", - "gpio26", "gpio27", - "gpio28", "gpio29", - "gpio30", "gpio31", - "gpio36", "gpio37", - "gpio38", "gpio39", - "gpio40", "gpio41", - "gpio42", "gpio43", - "gpio44", "gpio45", - "gpio46", "gpio47", - "gpio48" }; -static const char *const an7583_phy1_led0_groups[] =3D { "gpio1", "gpio2", +static const char *const pcie_reset_groups[] =3D { "pcie_reset0", "pcie_re= set1" }; +static const char *const pwm_groups[] =3D { "gpio0", "gpio1", + "gpio2", "gpio3", + "gpio4", "gpio5", + "gpio6", "gpio7", + "gpio8", "gpio9", + "gpio10", "gpio11", + "gpio12", "gpio13", + "gpio14", "gpio15", + "gpio16", "gpio17", + "gpio18", "gpio19", + "gpio20", "gpio21", + "gpio22", "gpio23", + "gpio24", "gpio25", + "gpio26", "gpio27", + "gpio28", "gpio29", + "gpio30", "gpio31", + "gpio36", "gpio37", + "gpio38", "gpio39", + "gpio40", "gpio41", + "gpio42", "gpio43", + "gpio44", "gpio45", + "gpio46", "gpio47", + "gpio48" }; +static const char *const phy1_led0_groups[] =3D { "gpio1", "gpio2", "gpio3", "gpio4" }; -static const char *const an7583_phy2_led0_groups[] =3D { "gpio1", "gpio2", +static const char *const phy2_led0_groups[] =3D { "gpio1", "gpio2", "gpio3", "gpio4" }; -static const char *const an7583_phy3_led0_groups[] =3D { "gpio1", "gpio2", +static const char *const phy3_led0_groups[] =3D { "gpio1", "gpio2", "gpio3", "gpio4" }; -static const char *const an7583_phy4_led0_groups[] =3D { "gpio1", "gpio2", +static const char *const phy4_led0_groups[] =3D { "gpio1", "gpio2", "gpio3", "gpio4" }; -static const char *const an7583_phy1_led1_groups[] =3D { "gpio8", "gpio9", +static const char *const phy1_led1_groups[] =3D { "gpio8", "gpio9", "gpio10", "gpio11" }; -static const char *const an7583_phy2_led1_groups[] =3D { "gpio8", "gpio9", +static const char *const phy2_led1_groups[] =3D { "gpio8", "gpio9", "gpio10", "gpio11" }; -static const char *const an7583_phy3_led1_groups[] =3D { "gpio8", "gpio9", +static const char *const phy3_led1_groups[] =3D { "gpio8", "gpio9", "gpio10", "gpio11" }; -static const char *const an7583_phy4_led1_groups[] =3D { "gpio8", "gpio9", +static const char *const phy4_led1_groups[] =3D { "gpio8", "gpio9", "gpio10", "gpio11" }; =20 static const struct airoha_pinctrl_func_group pon_func_group[] =3D { @@ -336,7 +336,7 @@ static const struct airoha_pinctrl_func_group sipo_func= _group[] =3D { }, }; =20 -static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] =3D= { +static const struct airoha_pinctrl_func_group mdio_func_group[] =3D { { .name =3D "mdio", .regmap[0] =3D { @@ -520,7 +520,7 @@ static const struct airoha_pinctrl_func_group spi_func_= group[] =3D { }, }; =20 -static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[] = =3D { +static const struct airoha_pinctrl_func_group pcm_spi_func_group[] =3D { { .name =3D "pcm_spi", .regmap[0] =3D { @@ -613,7 +613,7 @@ static const struct airoha_pinctrl_func_group pnand_fun= c_group[] =3D { }, }; =20 -static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group= [] =3D { +static const struct airoha_pinctrl_func_group pcie_reset_func_group[] =3D { { .name =3D "pcie_reset0", .regmap[0] =3D { @@ -635,7 +635,7 @@ static const struct airoha_pinctrl_func_group an7583_pc= ie_reset_func_group[] =3D { }, }; =20 -static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] =3D { +static const struct airoha_pinctrl_func_group pwm_func_group[] =3D { AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG), AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG), AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG), @@ -683,7 +683,7 @@ static const struct airoha_pinctrl_func_group an7583_pw= m_func_group[] =3D { AIROHA_PINCTRL_PWM_EXT("gpio48", GPIO48_FLASH_MODE_CFG), }; =20 -static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[= ] =3D { +static const struct airoha_pinctrl_func_group phy1_led0_func_group[] =3D { AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, @@ -694,7 +694,7 @@ static const struct airoha_pinctrl_func_group an7583_ph= y1_led0_func_group[] =3D { LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), }; =20 -static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[= ] =3D { +static const struct airoha_pinctrl_func_group phy2_led0_func_group[] =3D { AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, @@ -705,7 +705,7 @@ static const struct airoha_pinctrl_func_group an7583_ph= y2_led0_func_group[] =3D { LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), }; =20 -static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[= ] =3D { +static const struct airoha_pinctrl_func_group phy3_led0_func_group[] =3D { AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, @@ -716,7 +716,7 @@ static const struct airoha_pinctrl_func_group an7583_ph= y3_led0_func_group[] =3D { LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), }; =20 -static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[= ] =3D { +static const struct airoha_pinctrl_func_group phy4_led0_func_group[] =3D { AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, @@ -727,7 +727,7 @@ static const struct airoha_pinctrl_func_group an7583_ph= y4_led0_func_group[] =3D { LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), }; =20 -static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[= ] =3D { +static const struct airoha_pinctrl_func_group phy1_led1_func_group[] =3D { AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, @@ -738,7 +738,7 @@ static const struct airoha_pinctrl_func_group an7583_ph= y1_led1_func_group[] =3D { LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), }; =20 -static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[= ] =3D { +static const struct airoha_pinctrl_func_group phy2_led1_func_group[] =3D { AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, @@ -749,7 +749,7 @@ static const struct airoha_pinctrl_func_group an7583_ph= y2_led1_func_group[] =3D { LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), }; =20 -static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[= ] =3D { +static const struct airoha_pinctrl_func_group phy3_led1_func_group[] =3D { AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, @@ -760,7 +760,7 @@ static const struct airoha_pinctrl_func_group an7583_ph= y3_led1_func_group[] =3D { LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), }; =20 -static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[= ] =3D { +static const struct airoha_pinctrl_func_group phy4_led1_func_group[] =3D { AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, @@ -771,32 +771,32 @@ static const struct airoha_pinctrl_func_group an7583_= phy4_led1_func_group[] =3D { LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), }; =20 -static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] =3D { +static const struct airoha_pinctrl_func pinctrl_funcs[] =3D { PINCTRL_FUNC_DESC("pon", pon), PINCTRL_FUNC_DESC("tod_1pps", tod_1pps), PINCTRL_FUNC_DESC("sipo", sipo), - PINCTRL_FUNC_DESC("mdio", an7583_mdio), + PINCTRL_FUNC_DESC("mdio", mdio), PINCTRL_FUNC_DESC("uart", uart), PINCTRL_FUNC_DESC("i2c", i2c), PINCTRL_FUNC_DESC("jtag", jtag), PINCTRL_FUNC_DESC("pcm", pcm), PINCTRL_FUNC_DESC("spi", spi), - PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi), + PINCTRL_FUNC_DESC("pcm_spi", pcm_spi), PINCTRL_FUNC_DESC("emmc", emmc), PINCTRL_FUNC_DESC("pnand", pnand), - PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset), - PINCTRL_FUNC_DESC("pwm", an7583_pwm), - PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0), - PINCTRL_FUNC_DESC("phy2_led0", an7583_phy2_led0), - PINCTRL_FUNC_DESC("phy3_led0", an7583_phy3_led0), - PINCTRL_FUNC_DESC("phy4_led0", an7583_phy4_led0), - PINCTRL_FUNC_DESC("phy1_led1", an7583_phy1_led1), - PINCTRL_FUNC_DESC("phy2_led1", an7583_phy2_led1), - PINCTRL_FUNC_DESC("phy3_led1", an7583_phy3_led1), - PINCTRL_FUNC_DESC("phy4_led1", an7583_phy4_led1), + PINCTRL_FUNC_DESC("pcie_reset", pcie_reset), + PINCTRL_FUNC_DESC("pwm", pwm), + PINCTRL_FUNC_DESC("phy1_led0", phy1_led0), + PINCTRL_FUNC_DESC("phy2_led0", phy2_led0), + PINCTRL_FUNC_DESC("phy3_led0", phy3_led0), + PINCTRL_FUNC_DESC("phy4_led0", phy4_led0), + PINCTRL_FUNC_DESC("phy1_led1", phy1_led1), + PINCTRL_FUNC_DESC("phy2_led1", phy2_led1), + PINCTRL_FUNC_DESC("phy3_led1", phy3_led1), + PINCTRL_FUNC_DESC("phy4_led1", phy4_led1), }; =20 -static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] =3D { +static const struct airoha_pinctrl_conf pinctrl_pullup_conf[] =3D { PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)), PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)), PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)), @@ -852,7 +852,7 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_= pullup_conf[] =3D { PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, AN7583_MDIO_0_PU_MASK), }; =20 -static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] =3D= { +static const struct airoha_pinctrl_conf pinctrl_pulldown_conf[] =3D { PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)), PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)), PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)), @@ -908,7 +908,7 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_= pulldown_conf[] =3D { PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, AN7583_MDIO_0_PD_MASK), }; =20 -static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] =3D= { +static const struct airoha_pinctrl_conf pinctrl_drive_e2_conf[] =3D { PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)), PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)), PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)), @@ -964,7 +964,7 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_= drive_e2_conf[] =3D { PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, AN7583_MDIO_0_E2_MASK), }; =20 -static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] =3D= { +static const struct airoha_pinctrl_conf pinctrl_drive_e4_conf[] =3D { PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)), PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)), PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)), @@ -1020,44 +1020,44 @@ static const struct airoha_pinctrl_conf an7583_pinc= trl_drive_e4_conf[] =3D { PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, AN7583_MDIO_0_E4_MASK), }; =20 -static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[] = =3D { +static const struct airoha_pinctrl_conf pinctrl_pcie_rst_od_conf[] =3D { PINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK), PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK), }; =20 -static const struct airoha_pinctrl_match_data an7583_pinctrl_match_data = =3D { - .pins =3D an7583_pinctrl_pins, - .num_pins =3D ARRAY_SIZE(an7583_pinctrl_pins), - .grps =3D an7583_pinctrl_groups, - .num_grps =3D ARRAY_SIZE(an7583_pinctrl_groups), - .funcs =3D an7583_pinctrl_funcs, - .num_funcs =3D ARRAY_SIZE(an7583_pinctrl_funcs), +static const struct airoha_pinctrl_match_data pinctrl_match_data =3D { + .pins =3D pinctrl_pins, + .num_pins =3D ARRAY_SIZE(pinctrl_pins), + .grps =3D pinctrl_groups, + .num_grps =3D ARRAY_SIZE(pinctrl_groups), + .funcs =3D pinctrl_funcs, + .num_funcs =3D ARRAY_SIZE(pinctrl_funcs), .confs_info =3D { [AIROHA_PINCTRL_CONFS_PULLUP] =3D { - .confs =3D an7583_pinctrl_pullup_conf, - .num_confs =3D ARRAY_SIZE(an7583_pinctrl_pullup_conf), + .confs =3D pinctrl_pullup_conf, + .num_confs =3D ARRAY_SIZE(pinctrl_pullup_conf), }, [AIROHA_PINCTRL_CONFS_PULLDOWN] =3D { - .confs =3D an7583_pinctrl_pulldown_conf, - .num_confs =3D ARRAY_SIZE(an7583_pinctrl_pulldown_conf), + .confs =3D pinctrl_pulldown_conf, + .num_confs =3D ARRAY_SIZE(pinctrl_pulldown_conf), }, [AIROHA_PINCTRL_CONFS_DRIVE_E2] =3D { - .confs =3D an7583_pinctrl_drive_e2_conf, - .num_confs =3D ARRAY_SIZE(an7583_pinctrl_drive_e2_conf), + .confs =3D pinctrl_drive_e2_conf, + .num_confs =3D ARRAY_SIZE(pinctrl_drive_e2_conf), }, [AIROHA_PINCTRL_CONFS_DRIVE_E4] =3D { - .confs =3D an7583_pinctrl_drive_e4_conf, - .num_confs =3D ARRAY_SIZE(an7583_pinctrl_drive_e4_conf), + .confs =3D pinctrl_drive_e4_conf, + .num_confs =3D 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X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 8d891be1-7bce-4216-9a99-bee9de02ba58 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 3SA24H2Bo9cTC44QZDrpAW6udl7Xjenq1u++8eXafR8RY4rTd5aJbSh5WW3v5yheIUZqNruDzohRiUTLScpHg0bPwRk1ubml+WBsqiSR2D0= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MRWPR08MB11707 Content-Type: text/plain; charset="utf-8" en7523 a bit differs from an7581/an7583. It has different register offsets and slightly different bitfield masks. Let's adapt common header and existing drivers for the future addition of en7523. Signed-off-by: Mikhail Kshevetskiy --- drivers/pinctrl/airoha/airoha-common.h | 42 ++++++-- drivers/pinctrl/airoha/pinctrl-an7581.c | 138 ++++++++++++------------ drivers/pinctrl/airoha/pinctrl-an7583.c | 132 +++++++++++------------ 3 files changed, 167 insertions(+), 145 deletions(-) diff --git a/drivers/pinctrl/airoha/airoha-common.h b/drivers/pinctrl/airoh= a/airoha-common.h index 611194725757..f10cc7d20d15 100644 --- a/drivers/pinctrl/airoha/airoha-common.h +++ b/drivers/pinctrl/airoha/airoha-common.h @@ -56,7 +56,8 @@ } =20 /* MUX */ -#define REG_GPIO_2ND_I2C_MODE 0x0214 +#define AN7581_REG_GPIO_2ND_I2C_MODE 0x0214 +#define EN7523_REG_GPIO_2ND_I2C_MODE 0x0210 #define GPIO_MDC_IO_MASTER_MODE_MODE BIT(14) #define GPIO_I2C_MASTER_MODE_MODE BIT(13) #define GPIO_I2S_MODE_MASK BIT(12) @@ -73,7 +74,8 @@ #define GSW_TOD_1PPS_MODE_MASK BIT(1) #define GPIO_2ND_I2C_MODE_MASK BIT(0) =20 -#define REG_GPIO_SPI_CS1_MODE 0x0218 +#define AN7581_REG_GPIO_SPI_CS1_MODE 0x0218 +#define EN7523_REG_GPIO_SPI_CS1_MODE 0x0214 #define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21) #define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20) #define GPIO_PCM_SPI_CS2_MODE_P156_MASK BIT(19) @@ -91,7 +93,8 @@ #define GPIO_SPI_CS2_MODE_MASK BIT(1) #define GPIO_SPI_CS1_MODE_MASK BIT(0) =20 -#define REG_GPIO_PON_MODE 0x021c +#define AN7581_REG_GPIO_PON_MODE 0x021c +#define EN7523_REG_GPIO_PON_MODE 0x0218 #define GPIO_PARALLEL_NAND_MODE_MASK BIT(14) #define GPIO_SGMII_MDIO_MODE_MASK BIT(13) #define GPIO_PCIE_RESET2_MASK BIT(12) @@ -108,11 +111,14 @@ #define GPIO_EMMC_MODE_MASK BIT(1) #define GPIO_PON_MODE_MASK BIT(0) =20 -#define REG_NPU_UART_EN 0x0224 +#define AN7581_REG_NPU_UART_EN 0x0224 +#define EN7523_REG_NPU_UART_EN 0x0220 #define JTAG_UDI_EN_MASK BIT(4) #define JTAG_DFD_EN_MASK BIT(3) +#define NPU_UART_EN_MASK BIT(2) =20 -#define REG_FORCE_GPIO_EN 0x0228 +#define AN7581_REG_FORCE_GPIO_EN 0x0228 +#define EN7523_REG_FORCE_GPIO_EN 0x0224 #define FORCE_GPIO_EN(n) BIT(n) =20 /* LED MAP */ @@ -142,6 +148,10 @@ #define SPI_MOSI_E2_MASK BIT(13) #define SPI_CLK_E2_MASK BIT(12) #define SPI_CS0_E2_MASK BIT(11) +#define EN7523_SPI_MISO_E2_MASK BIT(13) +#define EN7523_SPI_MOSI_E2_MASK BIT(12) +#define EN7523_SPI_CLK_E2_MASK BIT(11) +#define EN7523_SPI_CS0_E2_MASK BIT(10) #define PCIE2_RESET_E2_MASK BIT(10) #define PCIE1_RESET_E2_MASK BIT(9) #define PCIE0_RESET_E2_MASK BIT(8) @@ -159,6 +169,10 @@ #define SPI_MOSI_E4_MASK BIT(13) #define SPI_CLK_E4_MASK BIT(12) #define SPI_CS0_E4_MASK BIT(11) +#define EN7523_SPI_MISO_E4_MASK BIT(13) +#define EN7523_SPI_MOSI_E4_MASK BIT(12) +#define EN7523_SPI_CLK_E4_MASK BIT(11) +#define EN7523_SPI_CS0_E4_MASK BIT(10) #define PCIE2_RESET_E4_MASK BIT(10) #define PCIE1_RESET_E4_MASK BIT(9) #define PCIE0_RESET_E4_MASK BIT(8) @@ -181,6 +195,10 @@ #define SPI_MOSI_PU_MASK BIT(13) #define SPI_CLK_PU_MASK BIT(12) #define SPI_CS0_PU_MASK BIT(11) +#define EN7523_SPI_MISO_PU_MASK BIT(13) +#define EN7523_SPI_MOSI_PU_MASK BIT(12) +#define EN7523_SPI_CLK_PU_MASK BIT(11) +#define EN7523_SPI_CS0_PU_MASK BIT(10) #define PCIE2_RESET_PU_MASK BIT(10) #define PCIE1_RESET_PU_MASK BIT(9) #define PCIE0_RESET_PU_MASK BIT(8) @@ -198,6 +216,10 @@ #define SPI_MOSI_PD_MASK BIT(13) #define SPI_CLK_PD_MASK BIT(12) #define SPI_CS0_PD_MASK BIT(11) +#define EN7523_SPI_MISO_PD_MASK BIT(13) +#define EN7523_SPI_MOSI_PD_MASK BIT(12) +#define EN7523_SPI_CLK_PD_MASK BIT(11) +#define EN7523_SPI_CS0_PD_MASK BIT(10) #define PCIE2_RESET_PD_MASK BIT(10) #define PCIE1_RESET_PD_MASK BIT(9) #define PCIE0_RESET_PD_MASK BIT(8) @@ -322,12 +344,12 @@ .regmap_size =3D 1, \ } \ =20 -#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \ +#define AIROHA_PINCTRL_PHY_LED0(variant, gpio, mux_val, map_mask, map_val)= \ { \ .name =3D (gpio), \ .regmap[0] =3D { \ AIROHA_FUNC_MUX, \ - REG_GPIO_2ND_I2C_MODE, \ + variant##_REG_GPIO_2ND_I2C_MODE, \ (mux_val), \ (mux_val), \ }, \ @@ -340,12 +362,12 @@ .regmap_size =3D 2, \ } =20 -#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \ +#define AIROHA_PINCTRL_PHY_LED1(variant, gpio, mux_val, map_mask, map_val)= \ { \ .name =3D (gpio), \ .regmap[0] =3D { \ AIROHA_FUNC_MUX, \ - REG_GPIO_2ND_I2C_MODE, \ + variant##_REG_GPIO_2ND_I2C_MODE, \ (mux_val), \ (mux_val), \ }, \ @@ -449,7 +471,7 @@ enum airoha_pinctrl_confs_type { AIROHA_PINCTRL_CONFS_DRIVE_E4, AIROHA_PINCTRL_CONFS_PCIE_RST_OD, =20 - AIROHA_PINCTRL_CONFS_MAX, + AIROHA_PINCTRL_CONFS_MAX }; =20 struct airoha_pinctrl { diff --git a/drivers/pinctrl/airoha/pinctrl-an7581.c b/drivers/pinctrl/airo= ha/pinctrl-an7581.c index 56c452e278f5..838c7ae62e3f 100644 --- a/drivers/pinctrl/airoha/pinctrl-an7581.c +++ b/drivers/pinctrl/airoha/pinctrl-an7581.c @@ -303,7 +303,7 @@ static const struct airoha_pinctrl_func_group pon_func_= group[] =3D { .name =3D "pon", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, + AN7581_REG_GPIO_PON_MODE, GPIO_PON_MODE_MASK, GPIO_PON_MODE_MASK }, @@ -316,7 +316,7 @@ static const struct airoha_pinctrl_func_group tod_1pps_= func_group[] =3D { .name =3D "pon_tod_1pps", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, + AN7581_REG_GPIO_2ND_I2C_MODE, PON_TOD_1PPS_MODE_MASK, PON_TOD_1PPS_MODE_MASK }, @@ -325,7 +325,7 @@ static const struct airoha_pinctrl_func_group tod_1pps_= func_group[] =3D { .name =3D "gsw_tod_1pps", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, + AN7581_REG_GPIO_2ND_I2C_MODE, GSW_TOD_1PPS_MODE_MASK, GSW_TOD_1PPS_MODE_MASK }, @@ -338,7 +338,7 @@ static const struct airoha_pinctrl_func_group sipo_func= _group[] =3D { .name =3D "sipo", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, + AN7581_REG_GPIO_PON_MODE, GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, GPIO_SIPO_MODE_MASK }, @@ -347,7 +347,7 @@ static const struct airoha_pinctrl_func_group sipo_func= _group[] =3D { .name =3D "sipo_rclk", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, + AN7581_REG_GPIO_PON_MODE, GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK }, @@ -360,13 +360,13 @@ static const struct airoha_pinctrl_func_group mdio_fu= nc_group[] =3D { .name =3D "mdio", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, + AN7581_REG_GPIO_2ND_I2C_MODE, GPIO_MDC_IO_MASTER_MODE_MODE, GPIO_MDC_IO_MASTER_MODE_MODE }, .regmap[1] =3D { AIROHA_FUNC_MUX, - REG_FORCE_GPIO_EN, + AN7581_REG_FORCE_GPIO_EN, FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2), FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2) }, @@ -379,7 +379,7 @@ static const struct airoha_pinctrl_func_group uart_func= _group[] =3D { .name =3D "uart2", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, + AN7581_REG_GPIO_PON_MODE, GPIO_UART2_MODE_MASK, GPIO_UART2_MODE_MASK }, @@ -388,7 +388,7 @@ static const struct airoha_pinctrl_func_group uart_func= _group[] =3D { .name =3D "uart2_cts_rts", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, + AN7581_REG_GPIO_PON_MODE, GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK, GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK }, @@ -397,7 +397,7 @@ static const struct airoha_pinctrl_func_group uart_func= _group[] =3D { .name =3D "hsuart", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, + AN7581_REG_GPIO_PON_MODE, GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, GPIO_HSUART_MODE_MASK }, @@ -407,7 +407,7 @@ static const struct airoha_pinctrl_func_group uart_func= _group[] =3D { .name =3D "hsuart_cts_rts", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, + AN7581_REG_GPIO_PON_MODE, GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK }, @@ -416,7 +416,7 @@ static const struct airoha_pinctrl_func_group uart_func= _group[] =3D { .name =3D "uart4", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, + AN7581_REG_GPIO_PON_MODE, GPIO_UART4_MODE_MASK, GPIO_UART4_MODE_MASK }, @@ -425,7 +425,7 @@ static const struct airoha_pinctrl_func_group uart_func= _group[] =3D { .name =3D "uart5", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, + AN7581_REG_GPIO_PON_MODE, GPIO_UART5_MODE_MASK, GPIO_UART5_MODE_MASK }, @@ -438,7 +438,7 @@ static const struct airoha_pinctrl_func_group i2c_func_= group[] =3D { .name =3D "i2c1", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, + AN7581_REG_GPIO_2ND_I2C_MODE, GPIO_2ND_I2C_MODE_MASK, GPIO_2ND_I2C_MODE_MASK }, @@ -451,7 +451,7 @@ static const struct airoha_pinctrl_func_group jtag_func= _group[] =3D { .name =3D "jtag_udi", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_NPU_UART_EN, + AN7581_REG_NPU_UART_EN, JTAG_UDI_EN_MASK, JTAG_UDI_EN_MASK }, @@ -460,7 +460,7 @@ static const struct airoha_pinctrl_func_group jtag_func= _group[] =3D { .name =3D "jtag_dfd", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_NPU_UART_EN, + AN7581_REG_NPU_UART_EN, JTAG_DFD_EN_MASK, JTAG_DFD_EN_MASK }, @@ -473,7 +473,7 @@ static const struct airoha_pinctrl_func_group pcm_func_= group[] =3D { .name =3D "pcm1", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, + AN7581_REG_GPIO_SPI_CS1_MODE, GPIO_PCM1_MODE_MASK, GPIO_PCM1_MODE_MASK }, @@ -482,7 +482,7 @@ static const struct airoha_pinctrl_func_group pcm_func_= group[] =3D { .name =3D "pcm2", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, + AN7581_REG_GPIO_SPI_CS1_MODE, GPIO_PCM2_MODE_MASK, GPIO_PCM2_MODE_MASK }, @@ -495,7 +495,7 @@ static const struct airoha_pinctrl_func_group spi_func_= group[] =3D { .name =3D "spi_quad", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, + AN7581_REG_GPIO_SPI_CS1_MODE, GPIO_SPI_QUAD_MODE_MASK, GPIO_SPI_QUAD_MODE_MASK }, @@ -504,7 +504,7 @@ static const struct airoha_pinctrl_func_group spi_func_= group[] =3D { .name =3D "spi_cs1", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, + AN7581_REG_GPIO_SPI_CS1_MODE, GPIO_SPI_CS1_MODE_MASK, GPIO_SPI_CS1_MODE_MASK }, @@ -513,7 +513,7 @@ static const struct airoha_pinctrl_func_group spi_func_= group[] =3D { .name =3D "spi_cs2", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, + AN7581_REG_GPIO_SPI_CS1_MODE, GPIO_SPI_CS2_MODE_MASK, GPIO_SPI_CS2_MODE_MASK }, @@ -522,7 +522,7 @@ static const struct airoha_pinctrl_func_group spi_func_= group[] =3D { .name =3D "spi_cs3", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, + AN7581_REG_GPIO_SPI_CS1_MODE, GPIO_SPI_CS3_MODE_MASK, GPIO_SPI_CS3_MODE_MASK }, @@ -531,7 +531,7 @@ static const struct airoha_pinctrl_func_group spi_func_= group[] =3D { .name =3D "spi_cs4", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, + AN7581_REG_GPIO_SPI_CS1_MODE, GPIO_SPI_CS4_MODE_MASK, GPIO_SPI_CS4_MODE_MASK }, @@ -544,7 +544,7 @@ static const struct airoha_pinctrl_func_group pcm_spi_f= unc_group[] =3D { .name =3D "pcm_spi", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, + AN7581_REG_GPIO_SPI_CS1_MODE, GPIO_PCM_SPI_MODE_MASK, GPIO_PCM_SPI_MODE_MASK }, @@ -553,7 +553,7 @@ static const struct airoha_pinctrl_func_group pcm_spi_f= unc_group[] =3D { .name =3D "pcm_spi_int", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, + AN7581_REG_GPIO_SPI_CS1_MODE, GPIO_PCM_INT_MODE_MASK, GPIO_PCM_INT_MODE_MASK }, @@ -562,7 +562,7 @@ static const struct airoha_pinctrl_func_group pcm_spi_f= unc_group[] =3D { .name =3D "pcm_spi_rst", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, + AN7581_REG_GPIO_SPI_CS1_MODE, GPIO_PCM_RESET_MODE_MASK, GPIO_PCM_RESET_MODE_MASK }, @@ -571,7 +571,7 @@ static const struct airoha_pinctrl_func_group pcm_spi_f= unc_group[] =3D { .name =3D "pcm_spi_cs1", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, + AN7581_REG_GPIO_SPI_CS1_MODE, GPIO_PCM_SPI_CS1_MODE_MASK, GPIO_PCM_SPI_CS1_MODE_MASK }, @@ -580,7 +580,7 @@ static const struct airoha_pinctrl_func_group pcm_spi_f= unc_group[] =3D { .name =3D "pcm_spi_cs2_p128", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, + AN7581_REG_GPIO_SPI_CS1_MODE, GPIO_PCM_SPI_CS2_MODE_P128_MASK, GPIO_PCM_SPI_CS2_MODE_P128_MASK }, @@ -589,7 +589,7 @@ static const struct airoha_pinctrl_func_group pcm_spi_f= unc_group[] =3D { .name =3D "pcm_spi_cs2_p156", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, + AN7581_REG_GPIO_SPI_CS1_MODE, GPIO_PCM_SPI_CS2_MODE_P156_MASK, GPIO_PCM_SPI_CS2_MODE_P156_MASK }, @@ -598,7 +598,7 @@ static const struct airoha_pinctrl_func_group pcm_spi_f= unc_group[] =3D { .name =3D "pcm_spi_cs3", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, + AN7581_REG_GPIO_SPI_CS1_MODE, GPIO_PCM_SPI_CS3_MODE_MASK, GPIO_PCM_SPI_CS3_MODE_MASK }, @@ -607,7 +607,7 @@ static const struct airoha_pinctrl_func_group pcm_spi_f= unc_group[] =3D { .name =3D "pcm_spi_cs4", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, + AN7581_REG_GPIO_SPI_CS1_MODE, GPIO_PCM_SPI_CS4_MODE_MASK, GPIO_PCM_SPI_CS4_MODE_MASK }, @@ -620,7 +620,7 @@ static const struct airoha_pinctrl_func_group i2s_func_= group[] =3D { .name =3D "i2s", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, + AN7581_REG_GPIO_2ND_I2C_MODE, GPIO_I2S_MODE_MASK, GPIO_I2S_MODE_MASK }, @@ -633,7 +633,7 @@ static const struct airoha_pinctrl_func_group emmc_func= _group[] =3D { .name =3D "emmc", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, + AN7581_REG_GPIO_PON_MODE, GPIO_EMMC_MODE_MASK, GPIO_EMMC_MODE_MASK }, @@ -646,7 +646,7 @@ static const struct airoha_pinctrl_func_group pnand_fun= c_group[] =3D { .name =3D "pnand", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, + AN7581_REG_GPIO_PON_MODE, GPIO_PARALLEL_NAND_MODE_MASK, GPIO_PARALLEL_NAND_MODE_MASK }, @@ -659,7 +659,7 @@ static const struct airoha_pinctrl_func_group pcie_rese= t_func_group[] =3D { .name =3D "pcie_reset0", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, + AN7581_REG_GPIO_PON_MODE, GPIO_PCIE_RESET0_MASK, GPIO_PCIE_RESET0_MASK }, @@ -668,7 +668,7 @@ static const struct airoha_pinctrl_func_group pcie_rese= t_func_group[] =3D { .name =3D "pcie_reset1", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, + AN7581_REG_GPIO_PON_MODE, GPIO_PCIE_RESET1_MASK, GPIO_PCIE_RESET1_MASK }, @@ -677,7 +677,7 @@ static const struct airoha_pinctrl_func_group pcie_rese= t_func_group[] =3D { .name =3D "pcie_reset2", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, + AN7581_REG_GPIO_PON_MODE, GPIO_PCIE_RESET2_MASK, GPIO_PCIE_RESET2_MASK }, @@ -732,90 +732,90 @@ static const struct airoha_pinctrl_func_group pwm_fun= c_group[] =3D { }; =20 static const struct airoha_pinctrl_func_group phy1_led0_func_group[] =3D { - AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, + AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio33", GPIO_LAN0_LED0_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, + AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio34", GPIO_LAN1_LED0_MODE_MASK, LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, + AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio35", GPIO_LAN2_LED0_MODE_MASK, LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, + AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio42", GPIO_LAN3_LED0_MODE_MASK, LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), }; =20 static const struct airoha_pinctrl_func_group phy2_led0_func_group[] =3D { - AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, + AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio33", GPIO_LAN0_LED0_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, + AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio34", GPIO_LAN1_LED0_MODE_MASK, LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, + AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio35", GPIO_LAN2_LED0_MODE_MASK, LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, + AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio42", GPIO_LAN3_LED0_MODE_MASK, LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), }; =20 static const struct airoha_pinctrl_func_group phy3_led0_func_group[] =3D { - AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, + AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio33", GPIO_LAN0_LED0_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, + AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio34", GPIO_LAN1_LED0_MODE_MASK, LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, + AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio35", GPIO_LAN2_LED0_MODE_MASK, LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, + AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio42", GPIO_LAN3_LED0_MODE_MASK, LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), }; =20 static const struct airoha_pinctrl_func_group phy4_led0_func_group[] =3D { - AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, + AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio33", GPIO_LAN0_LED0_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, + AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio34", GPIO_LAN1_LED0_MODE_MASK, LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, + AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio35", GPIO_LAN2_LED0_MODE_MASK, LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, + AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio42", GPIO_LAN3_LED0_MODE_MASK, LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), }; =20 static const struct airoha_pinctrl_func_group phy1_led1_func_group[] =3D { - AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, + AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio43", GPIO_LAN0_LED1_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, + AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio44", GPIO_LAN1_LED1_MODE_MASK, LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, + AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio45", GPIO_LAN2_LED1_MODE_MASK, LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, + AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio46", GPIO_LAN3_LED1_MODE_MASK, LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), }; =20 static const struct airoha_pinctrl_func_group phy2_led1_func_group[] =3D { - AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, + AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio43", GPIO_LAN0_LED1_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, + AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio44", GPIO_LAN1_LED1_MODE_MASK, LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, + AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio45", GPIO_LAN2_LED1_MODE_MASK, LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, + AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio46", GPIO_LAN3_LED1_MODE_MASK, LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), }; =20 static const struct airoha_pinctrl_func_group phy3_led1_func_group[] =3D { - AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, + AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio43", GPIO_LAN0_LED1_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, + AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio44", GPIO_LAN1_LED1_MODE_MASK, LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, + AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio45", GPIO_LAN2_LED1_MODE_MASK, LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, + AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio46", GPIO_LAN3_LED1_MODE_MASK, LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), }; =20 static const struct airoha_pinctrl_func_group phy4_led1_func_group[] =3D { - AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, + AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio43", GPIO_LAN0_LED1_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, + AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio44", GPIO_LAN1_LED1_MODE_MASK, LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, + AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio45", GPIO_LAN2_LED1_MODE_MASK, LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, + AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio46", GPIO_LAN3_LED1_MODE_MASK, LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), }; =20 diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airo= ha/pinctrl-an7583.c index 4675cdf7727d..c47aca9f1077 100644 --- a/drivers/pinctrl/airoha/pinctrl-an7583.c +++ b/drivers/pinctrl/airoha/pinctrl-an7583.c @@ -284,7 +284,7 @@ static const struct airoha_pinctrl_func_group pon_func_= group[] =3D { .name =3D "pon", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, + AN7581_REG_GPIO_PON_MODE, GPIO_PON_MODE_MASK, GPIO_PON_MODE_MASK }, @@ -297,7 +297,7 @@ static const struct airoha_pinctrl_func_group tod_1pps_= func_group[] =3D { .name =3D "pon_tod_1pps", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, + AN7581_REG_GPIO_2ND_I2C_MODE, PON_TOD_1PPS_MODE_MASK, PON_TOD_1PPS_MODE_MASK }, @@ -306,7 +306,7 @@ static const struct airoha_pinctrl_func_group tod_1pps_= func_group[] =3D { .name =3D "gsw_tod_1pps", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, + AN7581_REG_GPIO_2ND_I2C_MODE, GSW_TOD_1PPS_MODE_MASK, GSW_TOD_1PPS_MODE_MASK }, @@ -319,7 +319,7 @@ static const struct airoha_pinctrl_func_group sipo_func= _group[] =3D { .name =3D "sipo", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, + AN7581_REG_GPIO_PON_MODE, GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, GPIO_SIPO_MODE_MASK }, @@ -328,7 +328,7 @@ static const struct airoha_pinctrl_func_group sipo_func= _group[] =3D { .name =3D "sipo_rclk", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, + AN7581_REG_GPIO_PON_MODE, GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK }, @@ -341,13 +341,13 @@ static const struct airoha_pinctrl_func_group mdio_fu= nc_group[] =3D { .name =3D "mdio", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, + AN7581_REG_GPIO_PON_MODE, GPIO_SGMII_MDIO_MODE_MASK, GPIO_SGMII_MDIO_MODE_MASK }, .regmap[1] =3D { AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, + AN7581_REG_GPIO_SPI_CS1_MODE, GPIO_MDC_IO_MASTER_MODE_MODE, GPIO_MDC_IO_MASTER_MODE_MODE }, @@ -360,7 +360,7 @@ static const struct airoha_pinctrl_func_group uart_func= _group[] =3D { .name =3D "uart2", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, + AN7581_REG_GPIO_PON_MODE, GPIO_UART2_MODE_MASK, GPIO_UART2_MODE_MASK }, @@ -369,7 +369,7 @@ static const struct airoha_pinctrl_func_group uart_func= _group[] =3D { .name =3D "uart2_cts_rts", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, + AN7581_REG_GPIO_PON_MODE, GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK, GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK }, @@ -378,7 +378,7 @@ static const struct airoha_pinctrl_func_group uart_func= _group[] =3D { .name =3D "hsuart", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, + AN7581_REG_GPIO_PON_MODE, GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, GPIO_HSUART_MODE_MASK }, @@ -388,7 +388,7 @@ static const struct airoha_pinctrl_func_group uart_func= _group[] =3D { .name =3D "hsuart_cts_rts", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, + AN7581_REG_GPIO_PON_MODE, GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK }, @@ -397,7 +397,7 @@ static const struct airoha_pinctrl_func_group uart_func= _group[] =3D { .name =3D "uart4", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, + AN7581_REG_GPIO_PON_MODE, GPIO_UART4_MODE_MASK, GPIO_UART4_MODE_MASK }, @@ -406,7 +406,7 @@ static const struct airoha_pinctrl_func_group uart_func= _group[] =3D { .name =3D "uart5", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, + AN7581_REG_GPIO_PON_MODE, GPIO_UART5_MODE_MASK, GPIO_UART5_MODE_MASK }, @@ -419,7 +419,7 @@ static const struct airoha_pinctrl_func_group i2c_func_= group[] =3D { .name =3D "i2c1", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, + AN7581_REG_GPIO_2ND_I2C_MODE, GPIO_2ND_I2C_MODE_MASK, GPIO_2ND_I2C_MODE_MASK }, @@ -432,7 +432,7 @@ static const struct airoha_pinctrl_func_group jtag_func= _group[] =3D { .name =3D "jtag_udi", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_NPU_UART_EN, + AN7581_REG_NPU_UART_EN, JTAG_UDI_EN_MASK, JTAG_UDI_EN_MASK }, @@ -441,7 +441,7 @@ static const struct airoha_pinctrl_func_group jtag_func= _group[] =3D { .name =3D "jtag_dfd", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_NPU_UART_EN, + AN7581_REG_NPU_UART_EN, JTAG_DFD_EN_MASK, JTAG_DFD_EN_MASK }, @@ -454,7 +454,7 @@ static const struct airoha_pinctrl_func_group pcm_func_= group[] =3D { .name =3D "pcm1", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, + AN7581_REG_GPIO_SPI_CS1_MODE, GPIO_PCM1_MODE_MASK, GPIO_PCM1_MODE_MASK }, @@ -463,7 +463,7 @@ static const struct airoha_pinctrl_func_group pcm_func_= group[] =3D { .name =3D "pcm2", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, + AN7581_REG_GPIO_SPI_CS1_MODE, GPIO_PCM2_MODE_MASK, GPIO_PCM2_MODE_MASK }, @@ -476,7 +476,7 @@ static const struct airoha_pinctrl_func_group spi_func_= group[] =3D { .name =3D "spi_quad", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, + AN7581_REG_GPIO_SPI_CS1_MODE, GPIO_SPI_QUAD_MODE_MASK, GPIO_SPI_QUAD_MODE_MASK }, @@ -485,7 +485,7 @@ static const struct airoha_pinctrl_func_group spi_func_= group[] =3D { .name =3D "spi_cs1", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, + AN7581_REG_GPIO_SPI_CS1_MODE, GPIO_SPI_CS1_MODE_MASK, GPIO_SPI_CS1_MODE_MASK }, @@ -494,7 +494,7 @@ static const struct airoha_pinctrl_func_group spi_func_= group[] =3D { .name =3D "spi_cs2", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, + AN7581_REG_GPIO_SPI_CS1_MODE, GPIO_SPI_CS2_MODE_MASK, GPIO_SPI_CS2_MODE_MASK }, @@ -503,7 +503,7 @@ static const struct airoha_pinctrl_func_group spi_func_= group[] =3D { .name =3D "spi_cs3", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, + AN7581_REG_GPIO_SPI_CS1_MODE, GPIO_SPI_CS3_MODE_MASK, GPIO_SPI_CS3_MODE_MASK }, @@ -512,7 +512,7 @@ static const struct airoha_pinctrl_func_group spi_func_= group[] =3D { .name =3D "spi_cs4", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, + AN7581_REG_GPIO_SPI_CS1_MODE, GPIO_SPI_CS4_MODE_MASK, GPIO_SPI_CS4_MODE_MASK }, @@ -525,7 +525,7 @@ static const struct airoha_pinctrl_func_group pcm_spi_f= unc_group[] =3D { .name =3D "pcm_spi", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, + AN7581_REG_GPIO_SPI_CS1_MODE, GPIO_PCM_SPI_MODE_MASK, GPIO_PCM_SPI_MODE_MASK }, @@ -534,7 +534,7 @@ static const struct airoha_pinctrl_func_group pcm_spi_f= unc_group[] =3D { .name =3D "pcm_spi_int", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, + AN7581_REG_GPIO_SPI_CS1_MODE, GPIO_PCM_INT_MODE_MASK, GPIO_PCM_INT_MODE_MASK }, @@ -543,7 +543,7 @@ static const struct airoha_pinctrl_func_group pcm_spi_f= unc_group[] =3D { .name =3D "pcm_spi_rst", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, + AN7581_REG_GPIO_SPI_CS1_MODE, GPIO_PCM_RESET_MODE_MASK, GPIO_PCM_RESET_MODE_MASK }, @@ -552,7 +552,7 @@ static const struct airoha_pinctrl_func_group pcm_spi_f= unc_group[] =3D { .name =3D "pcm_spi_cs1", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, + AN7581_REG_GPIO_SPI_CS1_MODE, GPIO_PCM_SPI_CS1_MODE_MASK, GPIO_PCM_SPI_CS1_MODE_MASK }, @@ -561,7 +561,7 @@ static const struct airoha_pinctrl_func_group pcm_spi_f= unc_group[] =3D { .name =3D "pcm_spi_cs2", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, + AN7581_REG_GPIO_SPI_CS1_MODE, AN7583_GPIO_PCM_SPI_CS2_MODE_MASK, AN7583_GPIO_PCM_SPI_CS2_MODE_MASK }, @@ -570,7 +570,7 @@ static const struct airoha_pinctrl_func_group pcm_spi_f= unc_group[] =3D { .name =3D "pcm_spi_cs3", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, + AN7581_REG_GPIO_SPI_CS1_MODE, GPIO_PCM_SPI_CS3_MODE_MASK, GPIO_PCM_SPI_CS3_MODE_MASK }, @@ -579,7 +579,7 @@ static const struct airoha_pinctrl_func_group pcm_spi_f= unc_group[] =3D { .name =3D "pcm_spi_cs4", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, + AN7581_REG_GPIO_SPI_CS1_MODE, GPIO_PCM_SPI_CS4_MODE_MASK, GPIO_PCM_SPI_CS4_MODE_MASK }, @@ -592,7 +592,7 @@ static const struct airoha_pinctrl_func_group emmc_func= _group[] =3D { .name =3D "emmc", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, + AN7581_REG_GPIO_PON_MODE, GPIO_EMMC_MODE_MASK, GPIO_EMMC_MODE_MASK }, @@ -605,7 +605,7 @@ static const struct airoha_pinctrl_func_group pnand_fun= c_group[] =3D { .name =3D "pnand", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, + AN7581_REG_GPIO_PON_MODE, GPIO_PARALLEL_NAND_MODE_MASK, GPIO_PARALLEL_NAND_MODE_MASK }, @@ -618,7 +618,7 @@ static const struct airoha_pinctrl_func_group pcie_rese= t_func_group[] =3D { .name =3D "pcie_reset0", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, + AN7581_REG_GPIO_PON_MODE, GPIO_PCIE_RESET0_MASK, GPIO_PCIE_RESET0_MASK }, @@ -627,7 +627,7 @@ static const struct airoha_pinctrl_func_group pcie_rese= t_func_group[] =3D { .name =3D "pcie_reset1", .regmap[0] =3D { AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, + AN7581_REG_GPIO_PON_MODE, GPIO_PCIE_RESET1_MASK, GPIO_PCIE_RESET1_MASK }, @@ -684,90 +684,90 @@ static const struct airoha_pinctrl_func_group pwm_fun= c_group[] =3D { }; =20 static const struct airoha_pinctrl_func_group phy1_led0_func_group[] =3D { - AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, + AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio1", GPIO_LAN0_LED0_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, + AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio2", GPIO_LAN1_LED0_MODE_MASK, LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, + AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio3", GPIO_LAN2_LED0_MODE_MASK, LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, + AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio4", GPIO_LAN3_LED0_MODE_MASK, LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), }; =20 static const struct airoha_pinctrl_func_group phy2_led0_func_group[] =3D { - AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, + AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio1", GPIO_LAN0_LED0_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, + AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio2", GPIO_LAN1_LED0_MODE_MASK, LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, + AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio3", GPIO_LAN2_LED0_MODE_MASK, LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, + AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio4", GPIO_LAN3_LED0_MODE_MASK, LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), }; =20 static const struct airoha_pinctrl_func_group phy3_led0_func_group[] =3D { - AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, + AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio1", GPIO_LAN0_LED0_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, + AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio2", GPIO_LAN1_LED0_MODE_MASK, LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, + AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio3", GPIO_LAN2_LED0_MODE_MASK, LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, + AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio4", GPIO_LAN3_LED0_MODE_MASK, LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), }; =20 static const struct airoha_pinctrl_func_group phy4_led0_func_group[] =3D { - AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, + AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio1", GPIO_LAN0_LED0_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, + AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio2", GPIO_LAN1_LED0_MODE_MASK, LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, + AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio3", GPIO_LAN2_LED0_MODE_MASK, LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, + AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio4", GPIO_LAN3_LED0_MODE_MASK, LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), }; =20 static const struct airoha_pinctrl_func_group phy1_led1_func_group[] =3D { - AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, + AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio8", GPIO_LAN0_LED1_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, + AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio9", GPIO_LAN1_LED1_MODE_MASK, LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, + AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio10", GPIO_LAN2_LED1_MODE_MASK, LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, + AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio11", GPIO_LAN3_LED1_MODE_MASK, LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), }; =20 static const struct airoha_pinctrl_func_group phy2_led1_func_group[] =3D { - AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, + AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio8", GPIO_LAN0_LED1_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, + AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio9", GPIO_LAN1_LED1_MODE_MASK, LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, + AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio10", GPIO_LAN2_LED1_MODE_MASK, LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, + AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio11", GPIO_LAN3_LED1_MODE_MASK, LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), }; =20 static const struct airoha_pinctrl_func_group phy3_led1_func_group[] =3D { - AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, + AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio8", GPIO_LAN0_LED1_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, + AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio9", GPIO_LAN1_LED1_MODE_MASK, LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, + AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio10", GPIO_LAN2_LED1_MODE_MASK, LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, + AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio11", GPIO_LAN3_LED1_MODE_MASK, LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), }; =20 static const struct airoha_pinctrl_func_group phy4_led1_func_group[] =3D { - AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, + AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio8", GPIO_LAN0_LED1_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, + AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio9", GPIO_LAN1_LED1_MODE_MASK, LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, + AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio10", GPIO_LAN2_LED1_MODE_MASK, LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, + AIROHA_PINCTRL_PHY_LED1(AN7581, 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X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 8d891be1-7bce-4216-9a99-bee9de02ba58 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 3sJ7iiGtuhTtqc9ypP/JFSLHlBVKAOTSu88JhssnALz7dS+vLWD0BcF1LbiQWv05DKKaOA2meHKAgWW5O8fadswMCdE+iXaj1M1xZRTH4So= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU2PR08MB10016 Content-Type: text/plain; charset="utf-8" This patch adds support of Airoha en7523 SoC pin controller. Signed-off-by: Mikhail Kshevetskiy --- drivers/pinctrl/airoha/Kconfig | 6 + drivers/pinctrl/airoha/Makefile | 1 + drivers/pinctrl/airoha/pinctrl-en7523.c | 850 ++++++++++++++++++++++++ 3 files changed, 857 insertions(+) create mode 100644 drivers/pinctrl/airoha/pinctrl-en7523.c diff --git a/drivers/pinctrl/airoha/Kconfig b/drivers/pinctrl/airoha/Kconfig index 08038a5b11c6..159b4496f64a 100644 --- a/drivers/pinctrl/airoha/Kconfig +++ b/drivers/pinctrl/airoha/Kconfig @@ -15,6 +15,7 @@ config PINCTRL_AIROHA select REGMAP_MMIO imply PINCTRL_AIROHA_AN7581 imply PINCTRL_AIROHA_AN7583 + imply PINCTRL_AIROHA_EN7523 help Say yes here to support pin controller and gpio driver on Airoha SoC. @@ -29,4 +30,9 @@ config PINCTRL_AIROHA_AN7583 depends on ARM64 || COMPILE_TEST depends on PINCTRL_AIROHA =20 +config PINCTRL_AIROHA_EN7523 + tristate "EN7523 pinctrl" + depends on ARM || COMPILE_TEST + depends on PINCTRL_AIROHA + endmenu diff --git a/drivers/pinctrl/airoha/Makefile b/drivers/pinctrl/airoha/Makef= ile index eac0f376b590..68ef023b7725 100644 --- a/drivers/pinctrl/airoha/Makefile +++ b/drivers/pinctrl/airoha/Makefile @@ -5,3 +5,4 @@ obj-$(CONFIG_PINCTRL_AIROHA) +=3D pinctrl-airoha.o =20 obj-$(CONFIG_PINCTRL_AIROHA_AN7581) +=3D pinctrl-an7581.o obj-$(CONFIG_PINCTRL_AIROHA_AN7583) +=3D pinctrl-an7583.o +obj-$(CONFIG_PINCTRL_AIROHA_EN7523) +=3D pinctrl-en7523.o diff --git a/drivers/pinctrl/airoha/pinctrl-en7523.c b/drivers/pinctrl/airo= ha/pinctrl-en7523.c new file mode 100644 index 000000000000..b77792c44dfc --- /dev/null +++ b/drivers/pinctrl/airoha/pinctrl-en7523.c @@ -0,0 +1,850 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Author: Lorenzo Bianconi + * Author: Benjamin Larsson + * Author: Markus Gothe + * Author: Matheus Sampaio Queiroga + * Author: Mikhail Kshevetskiy + */ +#include "airoha-common.h" + +static struct pinctrl_pin_desc pinctrl_pins[] =3D { + PINCTRL_PIN(2, "i2c_sda"), + PINCTRL_PIN(3, "i2c_scl"), + PINCTRL_PIN(4, "spi_cs0"), + PINCTRL_PIN(5, "spi_clk"), + PINCTRL_PIN(6, "spi_mosi"), + PINCTRL_PIN(7, "spi_miso"), + PINCTRL_PIN(8, "uart1_txd"), + PINCTRL_PIN(9, "uart1_rxd"), + PINCTRL_PIN(12, "gpio0"), + PINCTRL_PIN(13, "gpio1"), + PINCTRL_PIN(14, "gpio2"), + PINCTRL_PIN(15, "gpio3"), + PINCTRL_PIN(16, "gpio4"), + PINCTRL_PIN(17, "gpio5"), + PINCTRL_PIN(18, "gpio6"), + PINCTRL_PIN(19, "gpio7"), + PINCTRL_PIN(20, "gpio8"), + PINCTRL_PIN(21, "gpio9"), + PINCTRL_PIN(22, "gpio10"), + PINCTRL_PIN(23, "gpio11"), + PINCTRL_PIN(24, "gpio12"), + PINCTRL_PIN(25, "gpio13"), + PINCTRL_PIN(26, "gpio14"), + PINCTRL_PIN(27, "gpio15"), + PINCTRL_PIN(28, "gpio16"), + PINCTRL_PIN(29, "gpio17"), + PINCTRL_PIN(30, "gpio18"), + PINCTRL_PIN(31, "gpio19"), + PINCTRL_PIN(32, "gpio20"), + PINCTRL_PIN(33, "gpio21"), + PINCTRL_PIN(34, "gpio22"), + PINCTRL_PIN(35, "gpio23"), + PINCTRL_PIN(36, "gpio24"), + PINCTRL_PIN(37, "gpio25"), + PINCTRL_PIN(38, "gpio26"), + PINCTRL_PIN(39, "gpio27"), + PINCTRL_PIN(40, "pcie_reset0"), + PINCTRL_PIN(41, "pcie_reset1"), +}; + +static const int pon_pins[] =3D { 28, 29, 30, 31, 32, 33 }; +static const int pon_tod_1pps_pins[] =3D { 21 }; +static const int gsw_tod_1pps_pins[] =3D { 21 }; +static const int sipo_pins[] =3D { 13, 38 }; +static const int sipo_rclk_pins[] =3D { 13, 30, 38 }; +static const int mdio_pins[] =3D { 20, 21 }; +static const int uart2_pins[] =3D { 20, 21 }; +static const int npu_uart_pins[] =3D { 13, 38 }; +static const int i2c0_pins[] =3D { 2, 3 }; +static const int i2c1_pins[] =3D { 14, 15 }; +static const int jtag_udi_pins[] =3D { 34, 35, 36, 37, 38 }; +static const int jtag_dfd_pins[] =3D { 34, 35, 36, 37, 38 }; +static const int i2s_pins[] =3D { 16, 17, 18, 19 }; +static const int pcm1_pins[] =3D { 24, 25, 26, 27 }; +static const int pcm2_pins[] =3D { 16, 17, 18, 19 }; +static const int spi_pins[] =3D { 4, 5, 6, 7 }; +static const int spi_quad_pins[] =3D { 14, 15 }; +static const int spi_cs1_pins[] =3D { 21 }; +static const int pcm_spi_pins[] =3D { 16, 17, 18, 19, 24, 25, 26, 27 }; +static const int pcm_spi_int_pins[] =3D { 15 }; +static const int pcm_spi_rst_pins[] =3D { 14 }; +static const int pcm_spi_cs1_pins[] =3D { 22 }; +static const int pcm_spi_cs2_pins[] =3D { 39 }; +static const int pcm_spi_cs3_pins[] =3D { 20 }; +static const int pcm_spi_cs4_pins[] =3D { 23 }; +static const int gpio0_pins[] =3D { 12 }; +static const int gpio1_pins[] =3D { 13 }; +static const int gpio2_pins[] =3D { 14 }; +static const int gpio3_pins[] =3D { 15 }; +static const int gpio4_pins[] =3D { 16 }; +static const int gpio5_pins[] =3D { 17 }; +static const int gpio6_pins[] =3D { 18 }; +static const int gpio7_pins[] =3D { 19 }; +static const int gpio8_pins[] =3D { 20 }; +static const int gpio9_pins[] =3D { 21 }; +static const int gpio10_pins[] =3D { 22 }; +static const int gpio11_pins[] =3D { 23 }; +static const int gpio12_pins[] =3D { 24 }; +static const int gpio13_pins[] =3D { 25 }; +static const int gpio14_pins[] =3D { 26 }; +static const int gpio15_pins[] =3D { 27 }; +static const int gpio16_pins[] =3D { 28 }; +static const int gpio17_pins[] =3D { 29 }; +static const int gpio18_pins[] =3D { 30 }; +static const int gpio19_pins[] =3D { 31 }; +static const int gpio20_pins[] =3D { 32 }; +static const int gpio21_pins[] =3D { 33 }; +static const int gpio22_pins[] =3D { 34 }; +static const int gpio23_pins[] =3D { 35 }; +static const int gpio24_pins[] =3D { 36 }; +static const int gpio25_pins[] =3D { 37 }; +static const int gpio26_pins[] =3D { 38 }; +static const int gpio27_pins[] =3D { 39 }; +static const int pcie_reset0_pins[] =3D { 40 }; +static const int pcie_reset1_pins[] =3D { 41 }; + +static const struct pingroup pinctrl_groups[] =3D { + PINCTRL_PIN_GROUP("pon", pon), + PINCTRL_PIN_GROUP("pon_tod_1pps", pon_tod_1pps), + PINCTRL_PIN_GROUP("gsw_tod_1pps", gsw_tod_1pps), + PINCTRL_PIN_GROUP("sipo", sipo), + PINCTRL_PIN_GROUP("sipo_rclk", sipo_rclk), + PINCTRL_PIN_GROUP("mdio", mdio), + PINCTRL_PIN_GROUP("uart2", uart2), + PINCTRL_PIN_GROUP("npu_uart", npu_uart), + PINCTRL_PIN_GROUP("i2c0", i2c0), + PINCTRL_PIN_GROUP("i2c1", i2c1), + PINCTRL_PIN_GROUP("jtag_udi", jtag_udi), + PINCTRL_PIN_GROUP("jtag_dfd", jtag_dfd), + PINCTRL_PIN_GROUP("i2s", i2s), + PINCTRL_PIN_GROUP("pcm1", pcm1), + PINCTRL_PIN_GROUP("pcm2", pcm2), + PINCTRL_PIN_GROUP("spi", spi), + PINCTRL_PIN_GROUP("spi_quad", spi_quad), + PINCTRL_PIN_GROUP("spi_cs1", spi_cs1), + PINCTRL_PIN_GROUP("pcm_spi", pcm_spi), + PINCTRL_PIN_GROUP("pcm_spi_int", pcm_spi_int), + PINCTRL_PIN_GROUP("pcm_spi_rst", pcm_spi_rst), + PINCTRL_PIN_GROUP("pcm_spi_cs1", pcm_spi_cs1), + PINCTRL_PIN_GROUP("pcm_spi_cs2", pcm_spi_cs2), + PINCTRL_PIN_GROUP("pcm_spi_cs3", pcm_spi_cs3), + PINCTRL_PIN_GROUP("pcm_spi_cs4", pcm_spi_cs4), + PINCTRL_PIN_GROUP("gpio0", gpio0), + PINCTRL_PIN_GROUP("gpio1", gpio1), + PINCTRL_PIN_GROUP("gpio2", gpio2), + PINCTRL_PIN_GROUP("gpio3", gpio3), + PINCTRL_PIN_GROUP("gpio4", gpio4), + PINCTRL_PIN_GROUP("gpio5", gpio5), + PINCTRL_PIN_GROUP("gpio6", gpio6), + PINCTRL_PIN_GROUP("gpio7", gpio7), + PINCTRL_PIN_GROUP("gpio8", gpio8), + PINCTRL_PIN_GROUP("gpio9", gpio9), + PINCTRL_PIN_GROUP("gpio10", gpio10), + PINCTRL_PIN_GROUP("gpio11", gpio11), + PINCTRL_PIN_GROUP("gpio12", gpio12), + PINCTRL_PIN_GROUP("gpio13", gpio13), + PINCTRL_PIN_GROUP("gpio14", gpio14), + PINCTRL_PIN_GROUP("gpio15", gpio15), + PINCTRL_PIN_GROUP("gpio16", gpio16), + PINCTRL_PIN_GROUP("gpio17", gpio17), + PINCTRL_PIN_GROUP("gpio18", gpio18), + PINCTRL_PIN_GROUP("gpio19", gpio19), + PINCTRL_PIN_GROUP("gpio20", gpio20), + PINCTRL_PIN_GROUP("gpio21", gpio21), + PINCTRL_PIN_GROUP("gpio22", gpio22), + PINCTRL_PIN_GROUP("gpio23", gpio23), + PINCTRL_PIN_GROUP("gpio24", gpio24), + PINCTRL_PIN_GROUP("gpio25", gpio25), + PINCTRL_PIN_GROUP("gpio26", gpio26), + PINCTRL_PIN_GROUP("gpio27", gpio27), + PINCTRL_PIN_GROUP("pcie_reset0", pcie_reset0), + PINCTRL_PIN_GROUP("pcie_reset1", pcie_reset1), +}; + +static const char *const pon_groups[] =3D { "pon" }; +static const char *const tod_1pps_groups[] =3D { "pon_tod_1pps", "gsw_tod_= 1pps" }; +static const char *const sipo_groups[] =3D { "sipo", "sipo_rclk" }; +static const char *const mdio_groups[] =3D { "mdio" }; + +static const char *const uart_groups[] =3D { "uart2", "npu_uart" }; +static const char *const i2c_groups[] =3D { "i2c1" }; +static const char *const jtag_groups[] =3D { "jtag_udi", "jtag_dfd" }; +static const char *const pcm_groups[] =3D { "pcm1", "pcm2" }; +static const char *const spi_groups[] =3D { "spi_quad", "spi_cs1" }; +static const char *const pcm_spi_groups[] =3D { + "pcm_spi", "pcm_spi_int", "pcm_spi_rst", "pcm_spi_cs1", + "pcm_spi_cs2", "pcm_spi_cs3", "pcm_spi_cs4" +}; + +static const char *const i2s_groups[] =3D { "i2s" }; +static const char *const pcie_reset_groups[] =3D { + "pcie_reset0", "pcie_reset1" +}; + +static const char *const pwm_groups[] =3D { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", + "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", + "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", + "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27" +}; + +static const char *const phy1_led0_groups[] =3D { + "gpio22", "gpio23", "gpio24", "gpio25" +}; +static const char *const phy2_led0_groups[] =3D { + "gpio22", "gpio23", "gpio24", "gpio25" +}; +static const char *const phy3_led0_groups[] =3D { + "gpio22", "gpio23", "gpio24", "gpio25" +}; +static const char *const phy4_led0_groups[] =3D { + "gpio22", "gpio23", "gpio24", "gpio25" +}; +static const char *const phy1_led1_groups[] =3D { + "gpio7", "gpio6", "gpio5", "gpio4" +}; +static const char *const phy2_led1_groups[] =3D { + "gpio7", "gpio6", "gpio5", "gpio4" +}; +static const char *const phy3_led1_groups[] =3D { + "gpio7", "gpio6", "gpio5", "gpio4" +}; +static const char *const phy4_led1_groups[] =3D { + "gpio7", "gpio6", "gpio5", "gpio4" +}; + +static const struct airoha_pinctrl_func_group pon_func_group[] =3D { + { + .name =3D "pon", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + EN7523_REG_GPIO_PON_MODE, + GPIO_PON_MODE_MASK, + GPIO_PON_MODE_MASK + }, + .regmap_size =3D 1, + }, +}; + +static const struct airoha_pinctrl_func_group tod_1pps_func_group[] =3D { + { + .name =3D "pon_tod_1pps", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + EN7523_REG_GPIO_2ND_I2C_MODE, + PON_TOD_1PPS_MODE_MASK, + PON_TOD_1PPS_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "gsw_tod_1pps", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + EN7523_REG_GPIO_2ND_I2C_MODE, + GSW_TOD_1PPS_MODE_MASK, + GSW_TOD_1PPS_MODE_MASK + }, + .regmap_size =3D 1, + }, +}; + +static const struct airoha_pinctrl_func_group sipo_func_group[] =3D { + { + .name =3D "sipo", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + EN7523_REG_GPIO_PON_MODE, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, + GPIO_SIPO_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "sipo_rclk", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + EN7523_REG_GPIO_PON_MODE, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK + }, + .regmap_size =3D 1, + }, +}; + +static const struct airoha_pinctrl_func_group mdio_func_group[] =3D { + { + .name =3D "mdio", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + EN7523_REG_GPIO_PON_MODE, + GPIO_SGMII_MDIO_MODE_MASK, + GPIO_SGMII_MDIO_MODE_MASK + }, + .regmap_size =3D 1, + }, +}; + +static const struct airoha_pinctrl_func_group uart_func_group[] =3D { + { + .name =3D "uart2", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + EN7523_REG_GPIO_PON_MODE, + GPIO_UART2_MODE_MASK, + GPIO_UART2_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "npu_uart", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + EN7523_REG_NPU_UART_EN, + NPU_UART_EN_MASK, + NPU_UART_EN_MASK + }, + .regmap_size =3D 1, + } +}; + +static const struct airoha_pinctrl_func_group i2c_func_group[] =3D { + { + .name =3D "i2c1", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + EN7523_REG_GPIO_2ND_I2C_MODE, + GPIO_2ND_I2C_MODE_MASK, + GPIO_2ND_I2C_MODE_MASK + }, + .regmap_size =3D 1, + }, +}; + +static const struct airoha_pinctrl_func_group jtag_func_group[] =3D { + { + .name =3D "jtag_udi", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + EN7523_REG_NPU_UART_EN, + JTAG_UDI_EN_MASK, + JTAG_UDI_EN_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "jtag_dfd", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + EN7523_REG_NPU_UART_EN, + JTAG_DFD_EN_MASK, + JTAG_DFD_EN_MASK + }, + .regmap_size =3D 1, + }, +}; + +static const struct airoha_pinctrl_func_group pcm_func_group[] =3D { + { + .name =3D "pcm1", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + EN7523_REG_GPIO_SPI_CS1_MODE, + GPIO_PCM1_MODE_MASK, + GPIO_PCM1_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "pcm2", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + EN7523_REG_GPIO_SPI_CS1_MODE, + GPIO_PCM2_MODE_MASK, + GPIO_PCM2_MODE_MASK + }, + .regmap_size =3D 1, + }, +}; + +static const struct airoha_pinctrl_func_group spi_func_group[] =3D { + { + .name =3D "spi_quad", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + EN7523_REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_QUAD_MODE_MASK, + GPIO_SPI_QUAD_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "spi_cs1", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + EN7523_REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS1_MODE_MASK, + GPIO_SPI_CS1_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "spi_cs2", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + EN7523_REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS2_MODE_MASK, + GPIO_SPI_CS2_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "spi_cs3", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + EN7523_REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS3_MODE_MASK, + GPIO_SPI_CS3_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "spi_cs4", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + EN7523_REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS4_MODE_MASK, + GPIO_SPI_CS4_MODE_MASK + }, + .regmap_size =3D 1, + }, +}; + +static const struct airoha_pinctrl_func_group pcm_spi_func_group[] =3D { + { + .name =3D "pcm_spi", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + EN7523_REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_MODE_MASK, + GPIO_PCM_SPI_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "pcm_spi_int", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + EN7523_REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_INT_MODE_MASK, + GPIO_PCM_INT_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "pcm_spi_rst", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + EN7523_REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_RESET_MODE_MASK, + GPIO_PCM_RESET_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "pcm_spi_cs1", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + EN7523_REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS1_MODE_MASK, + GPIO_PCM_SPI_CS1_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "pcm_spi_cs2", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + EN7523_REG_GPIO_SPI_CS1_MODE, + AN7583_GPIO_PCM_SPI_CS2_MODE_MASK, + AN7583_GPIO_PCM_SPI_CS2_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "pcm_spi_cs3", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + EN7523_REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS3_MODE_MASK, + GPIO_PCM_SPI_CS3_MODE_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "pcm_spi_cs4", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + EN7523_REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS4_MODE_MASK, + GPIO_PCM_SPI_CS4_MODE_MASK + }, + .regmap_size =3D 1, + }, +}; + +static const struct airoha_pinctrl_func_group i2s_func_group[] =3D { + { + .name =3D "i2s", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + EN7523_REG_GPIO_2ND_I2C_MODE, + GPIO_I2S_MODE_MASK, + GPIO_I2S_MODE_MASK + }, + .regmap_size =3D 1, + }, +}; + +static const struct airoha_pinctrl_func_group pcie_reset_func_group[] =3D { + { + .name =3D "pcie_reset0", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + EN7523_REG_GPIO_PON_MODE, + GPIO_PCIE_RESET0_MASK, + GPIO_PCIE_RESET0_MASK + }, + .regmap_size =3D 1, + }, { + .name =3D "pcie_reset1", + .regmap[0] =3D { + AIROHA_FUNC_MUX, + EN7523_REG_GPIO_PON_MODE, + GPIO_PCIE_RESET1_MASK, + GPIO_PCIE_RESET1_MASK + }, + .regmap_size =3D 1, + }, +}; + +static const struct airoha_pinctrl_func_group pwm_func_group[] =3D { + AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG), +}; + +static const struct airoha_pinctrl_func_group phy1_led0_func_group[] =3D { + AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio22", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio23", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio24", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio25", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), +}; + +static const struct airoha_pinctrl_func_group phy2_led0_func_group[] =3D { + AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio22", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio23", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio24", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio25", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), +}; + +static const struct airoha_pinctrl_func_group phy3_led0_func_group[] =3D { + AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio22", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio23", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio24", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio25", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), +}; + +static const struct airoha_pinctrl_func_group phy4_led0_func_group[] =3D { + AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio22", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio23", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio24", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio25", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), +}; + +static const struct airoha_pinctrl_func_group phy1_led1_func_group[] =3D { + AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio7", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio6", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio5", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio4", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), +}; + +static const struct airoha_pinctrl_func_group phy2_led1_func_group[] =3D { + AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio7", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio6", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio5", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio4", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), +}; + +static const struct airoha_pinctrl_func_group phy3_led1_func_group[] =3D { + AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio7", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio6", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio5", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio4", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), +}; + +static const struct airoha_pinctrl_func_group phy4_led1_func_group[] =3D { + AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio7", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio6", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio5", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio4", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), +}; + +static const struct airoha_pinctrl_func pinctrl_funcs[] =3D { + PINCTRL_FUNC_DESC("pon", pon), + PINCTRL_FUNC_DESC("tod_1pps", tod_1pps), + PINCTRL_FUNC_DESC("sipo", sipo), + PINCTRL_FUNC_DESC("mdio", mdio), + PINCTRL_FUNC_DESC("uart", uart), + PINCTRL_FUNC_DESC("i2c", i2c), + PINCTRL_FUNC_DESC("jtag", jtag), + PINCTRL_FUNC_DESC("pcm", pcm), + PINCTRL_FUNC_DESC("spi", spi), + PINCTRL_FUNC_DESC("pcm_spi", pcm_spi), + PINCTRL_FUNC_DESC("i2s", i2s), + PINCTRL_FUNC_DESC("pcie_reset", pcie_reset), + PINCTRL_FUNC_DESC("pwm", pwm), + PINCTRL_FUNC_DESC("phy1_led0", phy1_led0), + PINCTRL_FUNC_DESC("phy2_led0", phy2_led0), + PINCTRL_FUNC_DESC("phy3_led0", phy3_led0), + PINCTRL_FUNC_DESC("phy4_led0", phy4_led0), + PINCTRL_FUNC_DESC("phy1_led1", phy1_led1), + PINCTRL_FUNC_DESC("phy2_led1", phy2_led1), + PINCTRL_FUNC_DESC("phy3_led1", phy3_led1), + PINCTRL_FUNC_DESC("phy4_led1", phy4_led1), +}; + +static const struct airoha_pinctrl_conf pinctrl_pullup_conf[] =3D { + PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(0)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(1)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(2)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(3)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(4)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(5)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(6)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(7)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(8)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(9)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(10)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(11)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(12)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(13)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(14)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(15)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(16)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(17)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(18)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(19)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(20)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(21)), + PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(22)), + PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(23)), + PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(24)), + PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(25)), + PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(26)), + PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(27)), + PINCTRL_CONF_DESC(40, REG_GPIO_L_PU, BIT(28)), + PINCTRL_CONF_DESC(41, REG_GPIO_L_PU, BIT(29)), +}; + +static const struct airoha_pinctrl_conf pinctrl_pulldown_conf[] =3D { + PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(0)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(1)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(2)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(3)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(4)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(5)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(6)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(7)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(8)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(9)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(10)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(11)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(12)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(13)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(14)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(15)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(16)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(17)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(18)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(19)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(20)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(21)), + PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(22)), + PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(23)), + PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(24)), + PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(25)), + PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(26)), + PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(27)), + PINCTRL_CONF_DESC(40, REG_GPIO_L_PD, BIT(28)), + PINCTRL_CONF_DESC(41, REG_GPIO_L_PD, BIT(29)), +}; + +static const struct airoha_pinctrl_conf pinctrl_drive_e2_conf[] =3D { + PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(0)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(1)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(2)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(3)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(4)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(5)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(6)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(7)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(8)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(9)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(10)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(11)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(12)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(13)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(14)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(15)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(16)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(17)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(18)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(19)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(20)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(21)), + PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(22)), + PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(23)), + PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(24)), + PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(25)), + PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(26)), + PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(27)), + PINCTRL_CONF_DESC(40, REG_GPIO_L_E2, BIT(28)), + PINCTRL_CONF_DESC(41, REG_GPIO_L_E2, BIT(29)), +}; + +static const struct airoha_pinctrl_conf pinctrl_drive_e4_conf[] =3D { + PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(0)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(1)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(2)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(3)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(4)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(5)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(6)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(7)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(8)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(9)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(10)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(11)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(12)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(13)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(14)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(15)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(16)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(17)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(18)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(19)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(20)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(21)), + PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(22)), + PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(23)), + PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(24)), + PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(25)), + PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(26)), + PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(27)), + PINCTRL_CONF_DESC(40, REG_GPIO_L_E4, BIT(28)), + PINCTRL_CONF_DESC(41, REG_GPIO_L_E4, BIT(29)), +}; + +static const struct airoha_pinctrl_conf pinctrl_pcie_rst_od_conf[] =3D { + PINCTRL_CONF_DESC(40, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK), + PINCTRL_CONF_DESC(41, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK), +}; + +static const struct airoha_pinctrl_match_data pinctrl_match_data =3D { + .pins =3D pinctrl_pins, + .num_pins =3D ARRAY_SIZE(pinctrl_pins), + .grps =3D pinctrl_groups, + .num_grps =3D ARRAY_SIZE(pinctrl_groups), + .funcs =3D pinctrl_funcs, + .num_funcs =3D ARRAY_SIZE(pinctrl_funcs), + .confs_info =3D { + [AIROHA_PINCTRL_CONFS_PULLUP] =3D { + .confs =3D pinctrl_pullup_conf, + .num_confs =3D ARRAY_SIZE(pinctrl_pullup_conf), + }, + [AIROHA_PINCTRL_CONFS_PULLDOWN] =3D { + .confs =3D pinctrl_pulldown_conf, + .num_confs =3D ARRAY_SIZE(pinctrl_pulldown_conf), + }, + [AIROHA_PINCTRL_CONFS_DRIVE_E2] =3D { + .confs =3D pinctrl_drive_e2_conf, + .num_confs =3D ARRAY_SIZE(pinctrl_drive_e2_conf), + }, + [AIROHA_PINCTRL_CONFS_DRIVE_E4] =3D { + .confs =3D pinctrl_drive_e4_conf, + .num_confs =3D ARRAY_SIZE(pinctrl_drive_e4_conf), + }, + [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] =3D { + .confs =3D pinctrl_pcie_rst_od_conf, + .num_confs =3D ARRAY_SIZE(pinctrl_pcie_rst_od_conf), + }, + }, +}; + +static const struct of_device_id airoha_pinctrl_of_match[] =3D { + { .compatible =3D "airoha,en7523-pinctrl", .data =3D &pinctrl_match_data = }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match); + +static struct platform_driver airoha_pinctrl_driver =3D { + .probe =3D airoha_pinctrl_probe, + .driver =3D { + .name =3D "pinctrl-airoha-en7523", + .of_match_table =3D airoha_pinctrl_of_match, + }, +}; +module_platform_driver(airoha_pinctrl_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Lorenzo Bianconi "); +MODULE_AUTHOR("Benjamin Larsson "); +MODULE_AUTHOR("Markus Gothe "); +MODULE_AUTHOR("Matheus Sampaio Queiroga "); +MODULE_AUTHOR("Mikhail Kshevetskiy "); +MODULE_DESCRIPTION("Pinctrl driver for Airoha EN7523 SoC"); --=20 2.53.0