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Fri, 05 Jun 2026 13:56:27 -0700 (PDT) From: Bhargav Joshi Date: Sat, 06 Jun 2026 02:26:10 +0530 Subject: [PATCH 1/3] dt-bindings: interrupt-controller: ti,irq-crossbar: Convert to DT schema Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260606-crossbar-v1-1-f67f7cb9ee50@gmail.com> References: <20260606-crossbar-v1-0-f67f7cb9ee50@gmail.com> In-Reply-To: <20260606-crossbar-v1-0-f67f7cb9ee50@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Gleixner , Sricharan R , Aaro Koskinen , Andreas Kemnade , Kevin Hilman , Roger Quadros , Tony Lindgren Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, goledhruva@gmail.com, m-chawdhry@ti.com, daniel.baluta@gmail.com, simona.toaca@nxp.com, j.bhargav.u@gmail.com X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780692975; l=6926; i=j.bhargav.u@gmail.com; h=from:subject:message-id; bh=65ILo2+sWblozJ+nGvK5FhHOAhxeUGueknxcV9j0Cbk=; b=eeKxLpPKNpHMBI/bRnCYUS9QnwrIEkc566aoS6b2pgrPEEuK6+w1uwcUOWHBScoUGFeqnX+7Y RL3F/y4U3DGARfRQx2lwcPT7fehnheK8+jIw7oO/kXL/Vkt+0T8D2sk X-Developer-Key: i=j.bhargav.u@gmail.com; a=ed25519; pk=IqNDwUZKECEA+n8wXctFLBbYL9NhFstZNbOznm/nX1k= Convert TI irq-crossbar binding from text format to DT schema. As part of conversion following changes are made: - Add '#interrupt-cells' as a required property which was missing in text binding - As irq-crossbar is interrupt-controller. Move binding from bindings/arm/omap to bindings/interrupt-controller - property ti,irqs-reserved is defined and used as a array but other binding ti,pruss-intc.yaml uses same property name as a unit8 bitmask which causes erros in dt_binding_check. Update ti,irqs-reserved property name to ti,crossbar-irqs-reserved to resolve duplicate naming. Signed-off-by: Bhargav Joshi --- .../devicetree/bindings/arm/omap/crossbar.txt | 55 ------------ .../interrupt-controller/ti,irq-crossbar.yaml | 98 ++++++++++++++++++= ++++ 2 files changed, 98 insertions(+), 55 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt b/Docu= mentation/devicetree/bindings/arm/omap/crossbar.txt deleted file mode 100644 index a43e4c7aba3d..000000000000 --- a/Documentation/devicetree/bindings/arm/omap/crossbar.txt +++ /dev/null @@ -1,55 +0,0 @@ -Some socs have a large number of interrupts requests to service -the needs of its many peripherals and subsystems. All of the -interrupt lines from the subsystems are not needed at the same -time, so they have to be muxed to the irq-controller appropriately. -In such places a interrupt controllers are preceded by an CROSSBAR -that provides flexibility in muxing the device requests to the controller -inputs. - -Required properties: -- compatible : Should be "ti,irq-crossbar" -- reg: Base address and the size of the crossbar registers. -- interrupt-controller: indicates that this block is an interrupt controll= er. -- ti,max-irqs: Total number of irqs available at the parent interrupt cont= roller. -- ti,max-crossbar-sources: Maximum number of crossbar sources that can be = routed. -- ti,reg-size: Size of a individual register in bytes. Every individual - register is assumed to be of same size. Valid sizes are 1, 2, 4. -- ti,irqs-reserved: List of the reserved irq lines that are not muxed using - crossbar. These interrupt lines are reserved in the soc, - so crossbar bar driver should not consider them as free - lines. - -Optional properties: -- ti,irqs-skip: This is similar to "ti,irqs-reserved", but these are for - SOC-specific hard-wiring of those irqs which unexpectedly bypasses the - crossbar. These irqs have a crossbar register, but still cannot be used. - -- ti,irqs-safe-map: integer which maps to a safe configuration to use - when the interrupt controller irq is unused (when not provided, default = is 0) - -Examples: - crossbar_mpu: crossbar@4a002a48 { - compatible =3D "ti,irq-crossbar"; - reg =3D <0x4a002a48 0x130>; - ti,max-irqs =3D <160>; - ti,max-crossbar-sources =3D <400>; - ti,reg-size =3D <2>; - ti,irqs-reserved =3D <0 1 2 3 5 6 131 132>; - ti,irqs-skip =3D <10 133 139 140>; - }; - -Consumer: -=3D=3D=3D=3D=3D=3D=3D=3D -See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt = and -Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml for -further details. - -An interrupt consumer on an SoC using crossbar will use: - interrupts =3D - -Example: - device_x@4a023000 { - /* Crossbar 8 used */ - interrupts =3D ; - ... - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,irq-= crossbar.yaml b/Documentation/devicetree/bindings/interrupt-controller/ti,i= rq-crossbar.yaml new file mode 100644 index 000000000000..b31e147c2672 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/ti,irq-crossba= r.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/ti,irq-crossbar.ya= ml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments IRQ Crossbar + +maintainers: + - Sricharan R + +description: + Some socs have a large number of interrupts requests to service the need= s of + its many peripherals and subsystems. All of the interrupt lines from the + subsystems are not needed at the same time, so they have to be muxed to = the + irq-controller appropriately. In such places a interrupt controllers are + preceded by an CROSSBAR that provides flexibility in muxing the device + requests to the controller inputs. + +properties: + compatible: + const: ti,irq-crossbar + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 3 + + ti,max-irqs: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Total number of irqs available at the parent interrupt controller. + minimum: 1 + + ti,max-crossbar-sources: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Maximum number of crossbar sources that can be routed. + minimum: 1 + + ti,reg-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Size of a individual register in bytes. Every individual + register is assumed to be of same size. + enum: [1, 2, 4] + + ti,crossbar-irqs-reserved: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + List of the reserved irq lines that are not muxed using crossbar. Th= ese + interrupt lines are reserved in the soc, so crossbar bar driver shou= ld not + consider them as free lines. + + ti,irqs-skip: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + Similar to "ti,crossbar-irqs-reserved", but these are for SOC-specif= ic hard-wiring + of those irqs which unexpectedly bypasses the crossbar. These irqs h= ave a + crossbar register, but still cannot be used. + + ti,irqs-safe-map: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + integer which maps to a safe configuration to use when the interrupt + controller irq is unused. + default: 0 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - ti,max-irqs + - ti,max-crossbar-sources + - ti,reg-size + - ti,crossbar-irqs-reserved + +additionalProperties: false + +examples: + - | + #include + + crossbar_mpu: crossbar@4a002a48 { + compatible =3D "ti,irq-crossbar"; + reg =3D <0x4a002a48 0x130>; + interrupt-controller; + #interrupt-cells =3D <3>; + ti,max-irqs =3D <160>; + ti,max-crossbar-sources =3D <400>; + ti,reg-size =3D <2>; + ti,crossbar-irqs-reserved =3D <0 1 2 3 5 6 131 132>; + ti,irqs-skip =3D <10 133 139 140>; + }; --=20 2.54.0 From nobody Mon Jun 8 06:36:47 2026 Received: from mail-pl1-f174.google.com (mail-pl1-f174.google.com [209.85.214.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 06FEF3CEBB6 for ; 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Fri, 05 Jun 2026 13:56:33 -0700 (PDT) Received: from [192.168.1.3] ([2401:4900:881c:baba:b3d5:d6d:608b:987f]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3712fcb2607sm2197036a91.0.2026.06.05.13.56.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Jun 2026 13:56:32 -0700 (PDT) From: Bhargav Joshi Date: Sat, 06 Jun 2026 02:26:11 +0530 Subject: [PATCH 2/3] irqchip: irq-crossbar: Handle renamed irqs-reserved property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260606-crossbar-v1-2-f67f7cb9ee50@gmail.com> References: <20260606-crossbar-v1-0-f67f7cb9ee50@gmail.com> In-Reply-To: <20260606-crossbar-v1-0-f67f7cb9ee50@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Gleixner , Sricharan R , Aaro Koskinen , Andreas Kemnade , Kevin Hilman , Roger Quadros , Tony Lindgren Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, goledhruva@gmail.com, m-chawdhry@ti.com, daniel.baluta@gmail.com, simona.toaca@nxp.com, j.bhargav.u@gmail.com X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780692975; l=2064; i=j.bhargav.u@gmail.com; h=from:subject:message-id; bh=D/NehaAy+y0UChkX+5Urd3CLYL6nH8BL3LRA38L6uJY=; b=N+uc/uaK6/z0ZtSi78zcV8A/8ppuMi7cAioXppdZfRkMlCsr6KA4moSD+0m+B6zHKd9XRVNZ7 rsZ7B1vuw7IA0xT+qQJZZRmswPObkNu/lBjXwe5GnRqfouQpWBfZd5g X-Developer-Key: i=j.bhargav.u@gmail.com; a=ed25519; pk=IqNDwUZKECEA+n8wXctFLBbYL9NhFstZNbOznm/nX1k= The DT binding for the TI IRQ Crossbar has been converted from text to YAML schema. As part of that conversion, 'ti,irqs-reserved' was renamed to 'ti,crossbar-irqs-reserved' to avoid a property name collision with ti,pruss-intc.yaml Update the driver to try the new property name first and fall back to the old name ensuring compatibility with older device trees. Signed-off-by: Bhargav Joshi --- drivers/irqchip/irq-crossbar.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c index cd1134101ace..64b042ce11a9 100644 --- a/drivers/irqchip/irq-crossbar.c +++ b/drivers/irqchip/irq-crossbar.c @@ -5,6 +5,7 @@ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com * Author: Sricharan R */ +#include "linux/of.h" #include #include #include @@ -197,6 +198,7 @@ static int __init crossbar_of_init(struct device_node *= node) u32 max =3D 0, entry, reg_size; int i, size, reserved =3D 0; const __be32 *irqsr; + const char *pname; int ret =3D -ENOMEM; =20 cb =3D kzalloc_obj(*cb); @@ -231,14 +233,21 @@ static int __init crossbar_of_init(struct device_node= *node) for (i =3D 0; i < max; i++) cb->irq_map[i] =3D IRQ_FREE; =20 - /* Get and mark reserved irqs */ - irqsr =3D of_get_property(node, "ti,irqs-reserved", &size); + /* + * Get and mark reserved irqs + * try new property name first, fall back to old name for compatibility + * on older device trees. + */ + pname =3D of_property_present(node, "ti,crossbar-irqs-reserved") ? + "ti,crossbar-irqs-reserved" : "ti,irqs-reserved"; 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Fri, 05 Jun 2026 13:56:39 -0700 (PDT) Received: from [192.168.1.3] ([2401:4900:881c:baba:b3d5:d6d:608b:987f]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3712fcb2607sm2197036a91.0.2026.06.05.13.56.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Jun 2026 13:56:38 -0700 (PDT) From: Bhargav Joshi Date: Sat, 06 Jun 2026 02:26:12 +0530 Subject: [PATCH 3/3] ARM: dts: omap: dra7: Use new property name ti,crossbar-irqs-reserved Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260606-crossbar-v1-3-f67f7cb9ee50@gmail.com> References: <20260606-crossbar-v1-0-f67f7cb9ee50@gmail.com> In-Reply-To: <20260606-crossbar-v1-0-f67f7cb9ee50@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Gleixner , Sricharan R , Aaro Koskinen , Andreas Kemnade , Kevin Hilman , Roger Quadros , Tony Lindgren Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, goledhruva@gmail.com, m-chawdhry@ti.com, daniel.baluta@gmail.com, simona.toaca@nxp.com, j.bhargav.u@gmail.com X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780692975; l=982; i=j.bhargav.u@gmail.com; h=from:subject:message-id; bh=TAlX/MBj9t38pJGd4AC8U0jUF1uArbeoK5p0c92YSSU=; b=xRBSV+NoD4DR5C5gkumtbkwnLNDvsIJyxmZUieht1Fedlt3KjTOz2Yo9d1RpZCU/aQ5yyTDZJ 49SBeen4Ej+DqESpaPWR2BrOOohvXKTqLZGWhXVYNSZe4+wpy849Q4u X-Developer-Key: i=j.bhargav.u@gmail.com; a=ed25519; pk=IqNDwUZKECEA+n8wXctFLBbYL9NhFstZNbOznm/nX1k= Property name for irq-crossbar 'ti,irqs-reserved' is updated to 'ti,crossbar-irqs-reserved' by new binding conversion. Update the crossbar node in dra7.dtsi to use the new property name. since driver accepts both new and old name this is non-functional change. Signed-off-by: Bhargav Joshi --- arch/arm/boot/dts/ti/omap/dra7.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/ti/omap/dra7.dtsi b/arch/arm/boot/dts/ti/oma= p/dra7.dtsi index 711ce4c31bb1..80bee3db3a53 100644 --- a/arch/arm/boot/dts/ti/omap/dra7.dtsi +++ b/arch/arm/boot/dts/ti/omap/dra7.dtsi @@ -866,7 +866,7 @@ crossbar_mpu: crossbar@4a002a48 { ti,max-irqs =3D <160>; ti,max-crossbar-sources =3D ; ti,reg-size =3D <2>; - ti,irqs-reserved =3D <0 1 2 3 5 6 131 132>; + ti,crossbar-irqs-reserved =3D <0 1 2 3 5 6 131 132>; ti,irqs-skip =3D <10 133 139 140>; ti,irqs-safe-map =3D <0>; }; --=20 2.54.0