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McKenney" , Ethan Nelson-Moore , , , , Subject: [PATCH net-next V3 1/7] devlink: Skip health recover notifications before register Date: Fri, 5 Jun 2026 21:10:24 +0300 Message-ID: <20260605181030.3486619-2-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260605181030.3486619-1-mbloch@nvidia.com> References: <20260605181030.3486619-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C380:EE_|SA3PR12MB9130:EE_ X-MS-Office365-Filtering-Correlation-Id: b475daea-a6d5-454f-d303-08dec32dd25b X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|1800799024|376014|7416014|6133799003|22082099003|18002099003|11063799006|56012099006; X-Microsoft-Antispam-Message-Info: 11NQFb3+/EFTLwKgPv5NfPFb8jR9YVuyokSUsyjxjrDy8pZRH/3GIKtI7HTybJF5JJu6vKNi+6i/BojUKJebs/QyeXZCV6es9HlYM5gE9Dtvxvebi4xhw51bjre0LE9kFgnCl46WauetnQGXvqOGpeI7vNYJqV9K97RU7yMCXxxvivjp+yQfW6aDpH6C4obDKXLA0er3kiQnawQwoUMs65PGaF2V3UKLGk+n0aCrx5bkFO//ESOYZAuDIQ+64MJgbbdNVsABF0fJXrUNimHdLLMTUtfvsX5V4wk2Lr4Ry5/U68VHA1orHKnL9KhliIUcfB0pv+MC7QGU1Yr9F7ykk7kvgerN7dFLN8SUEQ+iFhwLo3p6FIFbC8TJ3wnSdNachEWraPO+IbnHuSSeJBvNPJzyanEF8r5v4VJ0JyRBaU/EHoKohyRIFS5fSgQU5usjQl8n0sjQVSRwaYU0THXLUETZqoh8cDo14rTRrYce3APScW4acx354BJiD8yJXxBBP30FhgRBFoRqZZ5JGsMPjs4cOgUBt5lzOv/5xVP2r5xhcFsljNZoJ12tuXsZBpfKcE9yU0wEYwnIT2igDvV/SfXVEdT20vVoXUK28AlDZLPI4Iqvz9hiYRHq6f7RlDAmIw7Nf8mCiKBprQaRgdfbtPZ/i6efzMi4DvIt0T3Va4wbKcypr7ALqj/l0PLwnl8gGor9r8bjz7P3qFdpRvqCcdw0MqaUtDEOjnu2R/WXEhs= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700016)(1800799024)(376014)(7416014)(6133799003)(22082099003)(18002099003)(11063799006)(56012099006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: xxyDHrly4Y+6GGE9/TMXhBezBAO5tWzuXlrryP3iLbT7bi7BsdumPY5QM0objl1A6l77y04A+ZFeVk554Q7/BzgPi4bUyg3TEdVrnMislNbsde6PE8S933HThyY/qiKpmI6GizdzdYDOasjkD/+irMevV9DZVSaRBgnYIcffCSnVy2gu12CaC/OY+6YNks9KUuaf3WHLY18ArUflklfWn+nv/mEOaP+/JBIiNm8SAEGRv6W5CCXUqaokz/7StFRbchB/qGnWlAsZaVOxD11nalvfU96+JVFuHaOryx8JBftYjfFXZpnQqfvm7BUS4u/fU6XU4zxO5Al+n+uUXMUnVDrGcw9fN5krKk2tXTDYIxuMvo0YIJEkLJfxYQ+CB8a4Pogciji1V/JMgEROKJtTbYURN43JmQntgm6lmnUxMRzLoqWXWpWbataC6HbToiPh X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jun 2026 18:11:10.1192 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b475daea-a6d5-454f-d303-08dec32dd25b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C380.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB9130 Content-Type: text/plain; charset="utf-8" devlink health reports can be generated before the devlink instance is registered. This can happen during driver initialization when a driver creates health reporters early and its health polling detects an error before devlink_register() is reached. devlink health still records the report state and counters in that case, but userspace cannot observe the devlink instance yet and there is no registered handle to notify through. Skip the netlink notification while the devlink instance is not registered instead of asserting registration. This keeps later userspace queries useful after registration while avoiding a warning from early health reports. Signed-off-by: Mark Bloch --- net/devlink/health.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/net/devlink/health.c b/net/devlink/health.c index ea7a334e939b..376e79497771 100644 --- a/net/devlink/health.c +++ b/net/devlink/health.c @@ -513,9 +513,8 @@ static void devlink_recover_notify(struct devlink_healt= h_reporter *reporter, int err; =20 WARN_ON(cmd !=3D DEVLINK_CMD_HEALTH_REPORTER_RECOVER); - ASSERT_DEVLINK_REGISTERED(devlink); =20 - if (!devlink_nl_notify_need(devlink)) + if (!__devl_is_registered(devlink) || !devlink_nl_notify_need(devlink)) return; =20 msg =3D nlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL); --=20 2.34.1 From nobody Mon Jun 8 05:25:47 2026 Received: from SA9PR02CU001.outbound.protection.outlook.com (mail-southcentralusazon11013033.outbound.protection.outlook.com [40.93.196.33]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA639383C94; 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McKenney" , Ethan Nelson-Moore , , , , Subject: [PATCH net-next V3 2/7] netdevsim: Register devlink after device init Date: Fri, 5 Jun 2026 21:10:25 +0300 Message-ID: <20260605181030.3486619-3-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260605181030.3486619-1-mbloch@nvidia.com> References: <20260605181030.3486619-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C381:EE_|LV2PR12MB5798:EE_ X-MS-Office365-Filtering-Correlation-Id: 9ac8e2e1-5a19-4a0d-1375-08dec32dd526 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|36860700016|1800799024|56012099006|11063799006|18002099003|6133799003|22082099003; X-Microsoft-Antispam-Message-Info: ftWqh5jr5h+DAdGQd8P6qkG/VSJEuWDWYCpxEtzlidZmPJas3YcdnL1t/NS+I40JGQllK52k5e1q+hgtBf1XJYLQvlc3S8BU6xUTWH+KhiQGDmAjnZpIiDP4/eU3pH+adEFKgF7/uBct7BicYbGjWIlXM49C05rIcFZKpSjN4rLGlaytEeB7nIVZGop+JSOiYm/mkLi/Ms0uwUJrQGvIiAB79Hd3GoJtG0qJgHbq+U8q5ufepOYuBpYdKfG9jUacoI9wOsQHHnSrhiLAh5mqYI4+HKqY8MAxhm99HImQEw9G8jvsDi4O0fpZe/uZ6NOpUMMj1YTvJl3fUI8HlhZet2a7oPpXD0945XlzL5xGMHDwq0qhvOf7JYGzy2A4VdZEsBV0djcsX4sEStn5MiuWFUqS5cXHPtQD7o2vV77XbMHsHfhXO4FxC6wiyCVPIM8il1s2yp9wb9uQb58HehEWgusjmIhyVEklJFMPIgU4i6mZ5FLTJy1x6V/M/t/V0rJvZjmzMqj/fGdI2l3rNnbH6wW40CRpGnNyTQ4qUnKwQKq9Dz9j3OFVgI33WDNpclsc2oL/YFSnqWStydhOXe9yKrWg3WqtjUtXFVS1Ib9g49cVItVFhc4DA/2ZfqY6L9mCm01ze3EJCkVu1/3U58rDsX46UbNDdgi7Oedth0u8+UYmmMZB07iUpEBr5BWiTIb7WiBYA/vaVdZ7AeyMi6l08bfAzBe5mRtNwjw3nKFCscY= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(82310400026)(36860700016)(1800799024)(56012099006)(11063799006)(18002099003)(6133799003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Q+KVtXfIPYtnX2Qr59MtQNRZEnmqSWltaUWAZcATvLHeLChJwlxdeNywpVMemXBjomfJxx1onYEAD3bOaPijHZW4bN+0zclPJ7vQeZUaYzhxLQSM/Jk93DarcnseaUUK/f3jpKQysg/Cem0e4hUff9gVoCpqCDflOJfwqUBaUfieT+H5eDK2gLeNO2sTTFMT1K/fxEUMZ8eSxlJcmRsQAWsYEBjwppgxXn3v/nySuek9fh7tmgbF3Q40FjI0CozrC3MHYr1DUsv1iIK3LTxBR91ID84jW8zkmVkXU/TMeA5/chHBcgcVMd/V9JcQ/FnRoEqwkcxGFj4IbqoHLeGWSKBz3KNS++iqN94jjqDLwI2DQQnJGZMQHdSQ6unNlKLVKA2FxIzdAzkHXs3U0criZQM670L7KeijYMvbKz6WcmNuCmsKsljniG5csQbzcJQk X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jun 2026 18:11:14.9046 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9ac8e2e1-5a19-4a0d-1375-08dec32dd526 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C381.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5798 Content-Type: text/plain; charset="utf-8" devl_register() makes the devlink instance visible to userspace. A later patch also makes registration the point where devlink core may call eswitch_mode_set() to apply a boot-time default eswitch mode. Move netdevsim registration after all objects (resources, params, regions, traps, debugfs etc) are initialized, and after the initial eswitch mode is set to legacy. Move devl_unregister() to the beginning of nsim_drv_remove(), before those devlink objects are torn down. This keeps devlink register/unregister as the notification barrier and makes the later object teardown paths run after devlink is no longer registered, so they do not emit their own netlink DEL notifications. Signed-off-by: Mark Bloch --- drivers/net/netdevsim/dev.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/net/netdevsim/dev.c b/drivers/net/netdevsim/dev.c index aed9ad5f1b43..7cf4102b049e 100644 --- a/drivers/net/netdevsim/dev.c +++ b/drivers/net/netdevsim/dev.c @@ -1680,13 +1680,9 @@ int nsim_drv_probe(struct nsim_bus_dev *nsim_bus_dev) goto err_devlink_unlock; } =20 - err =3D devl_register(devlink); - if (err) - goto err_vfc_free; - err =3D nsim_dev_resources_register(devlink); if (err) - goto err_dl_unregister; + goto err_vfc_free; =20 err =3D devl_params_register(devlink, nsim_devlink_params, ARRAY_SIZE(nsim_devlink_params)); @@ -1733,9 +1729,14 @@ int nsim_drv_probe(struct nsim_bus_dev *nsim_bus_dev) goto err_hwstats_exit; =20 nsim_dev->esw_mode =3D DEVLINK_ESWITCH_MODE_LEGACY; + err =3D devl_register(devlink); + if (err) + goto err_port_del_all; devl_unlock(devlink); return 0; =20 +err_port_del_all: + nsim_dev_port_del_all(nsim_dev); err_hwstats_exit: nsim_dev_hwstats_exit(nsim_dev); err_psample_exit: @@ -1757,8 +1758,6 @@ int nsim_drv_probe(struct nsim_bus_dev *nsim_bus_dev) ARRAY_SIZE(nsim_devlink_params)); err_resource_unregister: devl_resources_unregister(devlink); -err_dl_unregister: - devl_unregister(devlink); err_vfc_free: kfree(nsim_dev->vfconfigs); err_devlink_unlock: @@ -1797,6 +1796,7 @@ void nsim_drv_remove(struct nsim_bus_dev *nsim_bus_de= v) struct devlink *devlink =3D priv_to_devlink(nsim_dev); =20 devl_lock(devlink); + devl_unregister(devlink); nsim_dev_reload_destroy(nsim_dev); =20 nsim_bpf_dev_exit(nsim_dev); @@ -1804,7 +1804,6 @@ void nsim_drv_remove(struct nsim_bus_dev *nsim_bus_de= v) devl_params_unregister(devlink, nsim_devlink_params, ARRAY_SIZE(nsim_devlink_params)); devl_resources_unregister(devlink); - devl_unregister(devlink); kfree(nsim_dev->vfconfigs); kfree(nsim_dev->fa_cookie); mutex_destroy(&nsim_dev->progs_list_lock); --=20 2.34.1 From nobody Mon Jun 8 05:25:47 2026 Received: from SJ2PR03CU001.outbound.protection.outlook.com (mail-westusazon11012040.outbound.protection.outlook.com [52.101.43.40]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C48F3383C94; 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McKenney" , Ethan Nelson-Moore , , , , , Shay Drori , Moshe Shemesh Subject: [PATCH net-next V3 3/7] net/mlx5: Clear FW reset-in-progress bit before reload Date: Fri, 5 Jun 2026 21:10:26 +0300 Message-ID: <20260605181030.3486619-4-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260605181030.3486619-1-mbloch@nvidia.com> References: <20260605181030.3486619-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C380:EE_|SN7PR12MB7225:EE_ X-MS-Office365-Filtering-Correlation-Id: 184666b3-1b1c-480b-82c8-08dec32ddca0 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|1800799024|36860700016|22082099003|18002099003|11063799006|56012099006; X-Microsoft-Antispam-Message-Info: dgw641jGrcVG083PM9yUjyg/+JhEFdyXZQJSUpdxWznGZVHBpVGAoNF9OQ65hVpu1Po6kIuC8ttRCWYJNa3dTTkm8smfYTzHtYwgMnqHBXgkk4Xo2i3hr35VJqF3NqWprUnNACHDkEXMS1XCLvt7ycxBKZePyLUOd6vNv8enOrftBkPfX87mAj+JS2nrhd97Dmn+wKnPWgyfhLlgSOKlYSK8AvXkAqxKcBifXENWWeV4mSvdO+vHT+d7jXto4UBSw4XPsU/d/QkFlHBn8tbC/UnUTTmZcyfjNGlD0pRTPZDl+zBncpndz7OCtiuk9xPRj7jiSFoLC9UYXcvzGwfw7AcbnWmYAMwRt+L9ybJqfstBysMCUyiVrkfPkqh596aDUozauo3nYql8sGrp3plOei50iIxhxX20V7R2zrz9PT4NRDfGvY2WfpIaumoCHPpByLmGX7Ga7uXeFct9/HhqvFaQFDQGTya5Z5HEyhbbbEFpzEX4b3OZlSYyS7vbi4ErRalm48If6o/twBsDUHjxbX91pKJUkj/sUfoJfxjX/UUagqItb+fyhk4UFcYNTe2+GNGeQLouu1rZFGGvTXeP7ShZPENGhklV0H4mF0K9Wi+nHjFTtp3nHvW2ZOVgwusyv1+OjLMoClqzWxQZ+5B70izh+PvarlCudVZ/eYIUcgbjbUCKXwpPGfPKJRw+UK4yYZh+CDPuPQL3voYblxktr/I93syrH7C4GkXLFKYUIkc= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(82310400026)(1800799024)(36860700016)(22082099003)(18002099003)(11063799006)(56012099006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: +hBe/BMcAnm50+4GrXpMSocY5vjH6y7Yy/Cc2QGeso/kuIq6qy0MSo2F2AGxXnArWI2tqw7TfwgaY0Ep6Pk6vTSzVgPFCjtrmJYW1yuDtfrCoslRXzgcZYp8EQXeYPP1g4axAnCC8loplleLjbJlmVNzqNEQTqeCKE7kBenJAadMTWe5cpF20wpUcYLvdcLWfRNmPe5peKyxP/mgwu+29pL23tA0J7i6J03UhlYZbAJ0z9Qy7ZScGF1YRUqpDuIOceRicX2OYIR3hYNuWo1XjQdYUmCfRgX7Ez8foDw2F7WpJyusN2NZLwtealyYga2zoemrcDTNJ21Dnbos141Cfup+Piq86SP0qQDYExu6peC3rj3qW+tsczLHjwkvxrNMw6J334RjRY1Pph2Q4Rp3yB/cuaqAMs6Z6+/WDPlKOARyUj9sLdzNMqbVZ+6P4T96 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jun 2026 18:11:27.3644 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 184666b3-1b1c-480b-82c8-08dec32ddca0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C380.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7225 Content-Type: text/plain; charset="utf-8" mlx5 sets MLX5_FW_RESET_FLAGS_RESET_IN_PROGRESS when acknowledging a sync reset request. This bit blocks devlink reload and other devlink operations while the firmware reset is running, but it was kept set until after the driver reload finished. Clear the reset-in-progress bit once the reset unload flow is done and PCI access is back, before reloading the device. For a reset initiated through devlink, clear it before completing the reload waiter. For a reset reported through an asynchronous firmware event, keep the unload flow outside devl_lock, then take devl_lock before clearing the bit and reloading through the devl-locked load helper. Reviewed-by: Shay Drori Reviewed-by: Moshe Shemesh Signed-off-by: Mark Bloch --- .../ethernet/mellanox/mlx5/core/fw_reset.c | 28 +++++++++++-------- 1 file changed, 17 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c b/drivers/n= et/ethernet/mellanox/mlx5/core/fw_reset.c index 07440c58713a..7283e5b49eed 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c @@ -238,24 +238,30 @@ static void mlx5_fw_reset_complete_reload(struct mlx5= _core_dev *dev) { struct mlx5_fw_reset *fw_reset =3D dev->priv.fw_reset; struct devlink *devlink =3D priv_to_devlink(dev); + int err; =20 /* if this is the driver that initiated the fw reset, devlink completed t= he reload */ if (test_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags)) { + clear_bit(MLX5_FW_RESET_FLAGS_RESET_IN_PROGRESS, + &fw_reset->reset_flags); complete(&fw_reset->done); - } else { - mlx5_sync_reset_unload_flow(dev, false); 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McKenney" , Ethan Nelson-Moore , , , , , Shay Drori Subject: [PATCH net-next V3 4/7] net/mlx5: Register devlink after device init Date: Fri, 5 Jun 2026 21:10:27 +0300 Message-ID: <20260605181030.3486619-5-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260605181030.3486619-1-mbloch@nvidia.com> References: <20260605181030.3486619-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C381:EE_|CH1PR12MB9695:EE_ X-MS-Office365-Filtering-Correlation-Id: 6045a40d-02cb-49f2-a72b-08dec32de69a X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|7416014|376014|1800799024|6133799003|11063799006|56012099006|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: o4fbhzA25QUgCEHwdSy00KASEx6Tc4eTN3NTy8oMo712HINxIxGu18s6Gor+2aljzj0cPl64tF8PAv42IlSH6ZzohaVtD+0UbAA2N+rgtYNfhxbx6BwpQ88C3ziuceQpeSj8IWKERiQlL53OxdQFiFDXw1oeYeSvnC9Rt7yr8BTW1D8+1USsEDR6udPkWFc9uZtACrdXbWCPvz6MrnG5WSEjGpnmq8xOwCTMfPDL+itAkE7tSauOsXGECBvTDx00synvBYbjacnCmAAg++ge1/aEDFTEbUHOv695SSZemV8Tt62tipkzDguDlRQYoLAKfhHY8PdQSVud+f31SNXdehUcPdup15Y7PjPyV/TLkUdIN9jGI/TpiNdJB4yJhma6peQU+pxNbS6xwjaCZdGGuz2oCAydnrrEQeZMvDzMXpW5KMpLfh+N2q1nEhHXrSEQY+5pQLh/0fNyy/cdzdj+qlkUitqHSaP4CA7UwofrtfMxqML41IG2I8k5t73RWB2j6sYzK+L6PaGdMZIf4Mnc/qNJK2VYMDukOo/EYwYfwwnk26Xh13ADRoPHizNR0xSjErcXkURcVRgtcw+OWU7wIN9baKWR3oSjBp/9aIiw3+EKL694BuxZwZ8ubyGaYv6q8RnE0dzlNRnZJfXW1mhiGWk9BEfbMIiAZRH+MLrRFQbGqlRmAU4+5gsx12OlCklDBy8Oc5EYVSVzKDyuBZPJh2rXcIsmubO7inpPpbMlNOY= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(82310400026)(7416014)(376014)(1800799024)(6133799003)(11063799006)(56012099006)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: KaNePOcfClsobsO9LEVq79Zh3g2EZDM6LDc0KaiqLeO0ikGn78jQYGRmcN/t415WULiELP4ox27O+ieCF7u9IUzkFtL/QD++fSwQjacjNoFCbkm2H3Nm36D1bkkwMfWsSant6hFXeQ0CGc1bV7ClOiJkFnYCTuEgEEO/UGajXf3EoH99LEwn1opt2kEURQWnffHM3UECP/e3gUcqicJagbfhwKwaWZLK4wIYNgWuHgTvZtyIiCflhBZgahJo0yH/kV/PPt7tjss67PmQ0xUnx11dbkkea2O/uMQqGbH2roMjgVrnYLfafhtdgPWeGpPrYskZmk/tON4QdzHrlQM80oJrZFFBKLvWafbsszWA7oGnWFRqnauh1rLcGJ0/rsyLPHh6EGxQ0qdHeNDP9t+svtjbOyBKTRMqEqKGYJOrzjxxTjaEQYbOypUzEFSs/tpK X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jun 2026 18:11:44.1890 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6045a40d-02cb-49f2-a72b-08dec32de69a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C381.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH1PR12MB9695 Content-Type: text/plain; charset="utf-8" devl_register() makes the devlink instance visible to userspace. A later patch also makes registration the point where devlink core may call eswitch_mode_set() to apply a boot-time default eswitch mode. Move mlx5 devlink registration after mlx5 device initialization completes, including the lightweight init path, so registration-time devlink operations see initialized driver state. Move devl_unregister() before the matching teardown paths, so unregister notifications are emitted from devl_unregister() before mlx5 removes the devlink objects. Add a devl-locked uninit helper so failed nested devlink setup can unwind the initialized device before the instance is registered. Reviewed-by: Shay Drori Signed-off-by: Mark Bloch --- .../net/ethernet/mellanox/mlx5/core/main.c | 34 ++++++++++++++----- 1 file changed, 25 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/e= thernet/mellanox/mlx5/core/main.c index fd285aeb9630..4e3cb6ec8630 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c @@ -1454,31 +1454,40 @@ int mlx5_init_one_devl_locked(struct mlx5_core_dev = *dev) return err; } =20 +static void mlx5_uninit_one_devl_locked(struct mlx5_core_dev *dev); + int mlx5_init_one(struct mlx5_core_dev *dev) { struct devlink *devlink =3D priv_to_devlink(dev); int err; =20 devl_lock(devlink); + err =3D mlx5_init_one_devl_locked(dev); + if (err) + goto unlock; + if (dev->shd) { err =3D devl_nested_devlink_set(dev->shd, devlink); if (err) - goto unlock; + goto err_uninit; } + devl_register(devlink); - err =3D mlx5_init_one_devl_locked(dev); - if (err) - devl_unregister(devlink); + devl_unlock(devlink); + return 0; + +err_uninit: + mlx5_uninit_one_devl_locked(dev); unlock: devl_unlock(devlink); return err; } =20 -void mlx5_uninit_one(struct mlx5_core_dev *dev) +static void mlx5_uninit_one_devl_locked(struct mlx5_core_dev *dev) { struct devlink *devlink =3D priv_to_devlink(dev); =20 - devl_lock(devlink); + devl_assert_locked(devlink); mutex_lock(&dev->intf_state_mutex); =20 mlx5_hwmon_dev_unregister(dev); @@ -1501,7 +1510,15 @@ void mlx5_uninit_one(struct mlx5_core_dev *dev) mlx5_function_teardown(dev, true); out: mutex_unlock(&dev->intf_state_mutex); +} + +void mlx5_uninit_one(struct mlx5_core_dev *dev) +{ + struct devlink *devlink =3D priv_to_devlink(dev); + + devl_lock(devlink); devl_unregister(devlink); + mlx5_uninit_one_devl_locked(dev); devl_unlock(devlink); } =20 @@ -1636,7 +1653,6 @@ int mlx5_init_one_light(struct mlx5_core_dev *dev) int err; =20 devl_lock(devlink); - devl_register(devlink); dev->state =3D MLX5_DEVICE_STATE_UP; err =3D mlx5_function_enable(dev, true, mlx5_tout_ms(dev, FW_PRE_INIT_TIM= EOUT)); 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McKenney" , Ethan Nelson-Moore , , , , Subject: [PATCH net-next V3 5/7] octeontx2-af: Register devlink after SR-IOV init Date: Fri, 5 Jun 2026 21:10:28 +0300 Message-ID: <20260605181030.3486619-6-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260605181030.3486619-1-mbloch@nvidia.com> References: <20260605181030.3486619-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MW1PEPF0001615C:EE_|LV8PR12MB9230:EE_ X-MS-Office365-Filtering-Correlation-Id: 991af997-5fbe-437e-652b-08dec32de9e1 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|1800799024|36860700016|22082099003|18002099003|11063799006|56012099006; X-Microsoft-Antispam-Message-Info: WOD9XKmi1mIAlyrt3OuZnW2VlCIwrv/zsxf907axEY0+yJOeCNRA+PeIXhfi7ECKgExMHmqfqtkK0NGqwAMqUElbhClxoo7OlvAIGtbcArjs0xc7Bqiw2BSXlf4wzNhR3hQow4q5eS2X+nJcyjN62yWQDo9cShuKq0NmxTq23ud1m6EhYXT5CnO8FbIrA0vFVmZ+HYlKL8J4bEWFGKUgptmxvGiXr8u2imq6E7FDLeDo9LCoToE9VsDkslLo7uqMXGnWhpuMIrxA6cN6UHdr94ofzGdu4lL5MNETKBUUPzxQ9L0NrjxIpn9ojnSzh/CQr+NiajRb2A47r/hSg/gi+gDnwmiQl0BrnMYpJMZF7jASx3Or4ZaL4cTuktR17DaUYDd63TNvZBXq7MxM5rkZs6TyRkwbRDutUCxL5T3AlfoI3NgwvDtC0dfJbqnCGk7CkjQAoGz+t6I4i2GanQAHOEFwafQuiCEXcSyE4HPzVkQoX90z+N4wgx872HlyL1L0sKAUWJRraQ+hrNK3gRrWzCaNIY+nyQG3s81qsKW+rO7VZU0MOFdiex3w8Eudv0MEKWBkKV4kzC6bN+D5R46nkxy2O9Sr/gutFz+pzxmtw1xuJzpFdSxNeHuHetwJPww+1LW5pSaw0zoe5q5WI3q41ysQf/BtwUJmK+2B2IcD9Ad/Jw+UREsVWvBFRb+P8NuNUTvkhUqXFNE5DeWAKKYZqjtVuNQ4Vcwf+T5/YstHPdU= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(82310400026)(1800799024)(36860700016)(22082099003)(18002099003)(11063799006)(56012099006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 5xC8XNgVSNoZmHewh6fhVtU6C42NyHorVq/57G0dBJ1m42T43NmoEyLdjOTnh+Za6FabFe+qm/lLNWP3fa+o4qlFPZKovMGPd3443EJDL8w8Zv7xRhSPD3D3ybj5r6+ee2PZIzqJeSprVDmYQdSneLywSS+UNp8IV/sum5xukNEmh1hJqBa4RaaQrWP3Ri2Ry4/JyBMAK/RwyIDkzjFeQ43edErrkNTOsLDfXUOR636jXD3Bqdh9b1CJMQOsVyzvIz7j8Tp1hzdTrdID21LhG9dWm5vfaaAJuYKWs8ws+Ah9xUkiV5IO+cOalj/Z7oMyh7U6O2N8YxfiVOuF6dLKq+l4AVftwYqMfPyd/GTnVGaIclfn/RF2w2FfLLleu7rNV6EvjhRO6lO/z4Hx2/rY40TLg+35NsHGbikHTbT0h3HJRYJLY3vwbmGuQmFBX9oH X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jun 2026 18:11:49.7348 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 991af997-5fbe-437e-652b-08dec32de9e1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MW1PEPF0001615C.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9230 Content-Type: text/plain; charset="utf-8" A later patch makes devlink registration the point where devlink core may call eswitch_mode_set() to apply a boot-time default eswitch mode. Move octeontx2 AF devlink registration after SR-IOV is enabled and the representor switch lock is initialized, so the AF eswitch mode set path sees the state it depends on. If devlink registration fails after SR-IOV setup, unregister interrupts before disabling SR-IOV. This keeps the AF-VF mailbox IRQ handlers synchronized before the AF-VF mailbox workqueue is destroyed. Signed-off-by: Mark Bloch --- .../net/ethernet/marvell/octeontx2/af/rvu.c | 24 ++++++++++--------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c b/drivers/net/= ethernet/marvell/octeontx2/af/rvu.c index 3cf131508ecf..c2b52eb4ffab 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c @@ -3545,6 +3545,7 @@ static void rvu_update_module_params(struct rvu *rvu) static int rvu_probe(struct pci_dev *pdev, const struct pci_device_id *id) { struct device *dev =3D &pdev->dev; + bool sriov_done =3D false; struct rvu *rvu; int err; =20 @@ -3634,26 +3635,27 @@ static int rvu_probe(struct pci_dev *pdev, const st= ruct pci_device_id *id) goto err_flr; } =20 - err =3D rvu_register_dl(rvu); - if (err) { - dev_err(dev, "%s: Failed to register devlink\n", __func__); - goto err_irq; - } - rvu_setup_rvum_blk_revid(rvu); =20 /* Enable AF's VFs (if any) */ err =3D rvu_enable_sriov(rvu); if (err) { dev_err(dev, "%s: Failed to enable sriov\n", __func__); - goto err_dl; + goto err_irq; + } + sriov_done =3D true; + + mutex_init(&rvu->rswitch.switch_lock); + + err =3D rvu_register_dl(rvu); + if (err) { + dev_err(dev, "%s: Failed to register devlink\n", __func__); + goto err_irq; } =20 /* Initialize debugfs */ rvu_dbg_init(rvu); =20 - mutex_init(&rvu->rswitch.switch_lock); - if (rvu->fwdata) ptp_start(rvu, rvu->fwdata->sclk, rvu->fwdata->ptp_ext_clk_rate, rvu->fwdata->ptp_ext_tstamp); @@ -3662,10 +3664,10 @@ static int rvu_probe(struct pci_dev *pdev, const st= ruct pci_device_id *id) rvu_alloc_cint_qint_mem(rvu, &rvu->pf[RVU_AFPF], BLKADDR_NIX0, (rvu->hw->block[BLKADDR_NIX0].lf.max)); return 0; -err_dl: - rvu_unregister_dl(rvu); err_irq: rvu_unregister_interrupts(rvu); + if (sriov_done) + rvu_disable_sriov(rvu); err_flr: rvu_flr_wq_destroy(rvu); err_mbox: --=20 2.34.1 From nobody Mon Jun 8 05:25:47 2026 Received: from PH0PR06CU001.outbound.protection.outlook.com (mail-westus3azon11011022.outbound.protection.outlook.com [40.107.208.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C3DE395AC3; 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McKenney" , Ethan Nelson-Moore , , , , Subject: [PATCH net-next V3 6/7] octeontx2-pf: Register devlink after SR-IOV state init Date: Fri, 5 Jun 2026 21:10:29 +0300 Message-ID: <20260605181030.3486619-7-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260605181030.3486619-1-mbloch@nvidia.com> References: <20260605181030.3486619-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MW1PEPF0001615C:EE_|CH3PR12MB8728:EE_ X-MS-Office365-Filtering-Correlation-Id: cf9b0e84-95b3-49cf-8ae7-08dec32ded09 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|36860700016|1800799024|6133799003|22082099003|18002099003|11063799006|56012099006; X-Microsoft-Antispam-Message-Info: q8zvO9SI6n3Om9/cp0araI6oP8VlAOpF5ggGJv8RNhypjd7iFWUDtvOlhEgbhKvkiHtIFu5JdgXCzLIAGofoaLWmEjkUHuGzbS6VTbCPd1ssxlF6rrS3aJwuqNrdzg+OG+SeLTtCF7i4vbj84IVEfAT6L5IJ9MjS3eq/6lxdTK3Qxp367ZzGrGjbh0DWgDQUjJxa0V3ECoGi5PSJ9iHGuoj1SR3coPlSDepTb0jVAGL8p0+CuKLuayUjHN9SPGHcPldXqO2HN7omTgmeTU3NiaDW2dGX7daTaR7jr+8vKArppvIM509wLZZVKM4LCBrYgMq8NIWHymwniM1+/7tm+/rXc69RbrO7B4ZJyTuBUZh7QrtXxee0jvfjH3p+U2b81IaAn2mNwuLNggNtw2z9UxYE+DK3ZttgN+x8wqXQgbVMmw50VeXjsx7KD/Bm0TCQ7EjdNjmwa+MtiOQZot/1yRteFh6Dvj5mtMrSkkl2a18KjdiGOER3sB/3Yf/swhAnO/YfT0yGOLMhuAhivy+DVx80kyDCKfFwvP50Gpw56SkHL5YKKU5BLGnDNoTCbQPWbrQq8uK3KxToeBqoenKtyz7Fy7gMoiI1x1FQ77S3w0TXJTVBjWk3/DUOuAGTVUaNJD1ziMg9TD+pZ8kdhbJ6lLwG2NjVWynmBPPorz1h4ioDQi5omjo/I2Gs205iuH/8zZyoMo0kH3p0i8V5O7TFC4hRxrollCBx9UK715BKjks= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(82310400026)(36860700016)(1800799024)(6133799003)(22082099003)(18002099003)(11063799006)(56012099006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: q6NtkYjUp4/2LQFa9HvK5tSy5x2WcZ2BqUJT4P5ze5UUY2vtEHTNG+CctvrMxwjmpqHw8LmLHt1efYqsuhlZZKNpVJGi+WTvPHy5sCKQHUz/NJemZBTXm9m/RRQNgPPe/TTK1+cGfOa8BbTm8HnUgNcBJLRwqFPU3eHRJvoPIg9XsevpHyNu0m3G317PIwFhycAHhzXsl2tPuz8tSr/KxPOr8khGV7qUqO0VQzZys+qIxOCcVYNP/rtbBP/ubKroeit6dyamcD+G5CjIEb5F4B8TpLBXvy339O5Xv3HQkLC95kIS7ylbKn677SJY1nhB4ERmKeNBmdZiZV8X7IevTp2mf4pZ8n7Y9zORrTxoqWXcH04YZyq+81TlPZowxRlpbNBIuyyCBRhMn8YVfc6ke8jZTBnl7zHoP7FHsjbEWw+lLROTW7UmuCD/nQlQHOql X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jun 2026 18:11:55.0312 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cf9b0e84-95b3-49cf-8ae7-08dec32ded09 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MW1PEPF0001615C.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8728 Content-Type: text/plain; charset="utf-8" A later patch makes devlink registration the point where devlink core may call eswitch_mode_set() to apply a boot-time default eswitch mode. Move octeontx2 PF devlink registration after PF SR-IOV configuration state is initialized, so representor creation has the state it needs. Add a separate unwind label so failures after devlink registration unregister devlink before cleaning up SR-IOV state. Signed-off-by: Mark Bloch --- .../ethernet/marvell/octeontx2/nic/otx2_pf.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c b/drivers= /net/ethernet/marvell/octeontx2/nic/otx2_pf.c index f9fbf0c17648..47d2c6a24636 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c @@ -3278,14 +3278,14 @@ static int otx2_probe(struct pci_dev *pdev, const s= truct pci_device_id *id) if (err) goto err_mcam_flow_del; =20 - err =3D otx2_register_dl(pf); - if (err) - goto err_mcam_flow_del; - /* Initialize SR-IOV resources */ err =3D otx2_sriov_vfcfg_init(pf); if (err) - goto err_pf_sriov_init; + goto err_shutdown_tc; + + err =3D otx2_register_dl(pf); + if (err) + goto err_sriov_cleannup; =20 /* Enable link notifications */ otx2_cgx_config_linkevents(pf, true); @@ -3293,7 +3293,7 @@ static int otx2_probe(struct pci_dev *pdev, const str= uct pci_device_id *id) pf->af_xdp_zc_qidx =3D bitmap_zalloc(qcount, GFP_KERNEL); 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McKenney" , Ethan Nelson-Moore , , , , Subject: [PATCH net-next V3 7/7] devlink: Add eswitch mode boot defaults Date: Fri, 5 Jun 2026 21:10:30 +0300 Message-ID: <20260605181030.3486619-8-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260605181030.3486619-1-mbloch@nvidia.com> References: <20260605181030.3486619-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C381:EE_|DS0PR12MB9421:EE_ X-MS-Office365-Filtering-Correlation-Id: 60d1fc0b-5b6a-45e4-b6c2-08dec32df089 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|376014|82310400026|7416014|1800799024|22082099003|18002099003|6133799003|3023799007|11063799006|56012099006; X-Microsoft-Antispam-Message-Info: H9PVqLzEVRJaWI0ulDtiJwKyseXFbheuY/WmXqkrmyfoQh17uZ0W/zDqNYbudknYpVsDZxEvuM3dUpDf4Pvez5SSg4eq/adhM1ZvrQhRSGg34Xir6n756Oc+zX4Jsp3JF283Zl5zJL2evg6vztEE5U8KGS16h7pDjVfUtUEhKiUc64odVjaAd/GzRQruV0nURFCod/GwsMDQUTfxQxwgzmhGQD3F+ruUQDjQcYmemz9k3gZZrvcf/az6qFmQgaGTffuYsm1pZUNvWSPW9w5gNTOXvkJ958dFH8q8s6HRZ/BGEO5mc/1xwROZ7+0Abu5bD1ovUO6pRL38O4/UhLvZGTqBga4EExPlCo3S2pGlHDsoYR4Zdva+182TZOTzSfButqo0taF8x053tXNlpBnHoG6VP/phr6E4kKcL4A2OgyUVGBIsCD4M/qtyv2dIMmvROVbSSUAmep1tWWRbbs0Ok5eDt+FD+9ieaXlnHiugMSe5/3fhmRr0julubyLtstSvwdC5vgkQmuDmUE2a3Klq5hnIHyTzQFjl97fougR46rK9UUGK2XZv+Z+PFuWdMdXSkR928SS9dLdbvER69xl2Zr0cAmxOGfz8OyMR9wvkc0UM0d8KeIvcCTw9QlUhbyPiMVQSX3nNOWpsG1CzVwTeyQFax6En/t0K96DYJ/PcY88HheRrxrwycFWtqN5LynBxl09dFSFO+DEWROvEZyf4WcaGNOQszfY3n0C0W/P1Ny0= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(376014)(82310400026)(7416014)(1800799024)(22082099003)(18002099003)(6133799003)(3023799007)(11063799006)(56012099006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: B11b0Ef/bg6YSj0iB23a08JnHI2oqnuvgjkRMmGFlyKh8AbbB0SGthW9l93cODe2Y3eSdsztHhga1doS9FT+Xv16h10t0yeMwG/jDQXb49zUfQ3xf4JkYaFK1zfBwwhk+lkQtiEy1Z1mMzeA6WlRuVHzheMiYhnQlpO5hZ28n8N29hdZHk9Bq8+fH+DHXJ5hcdrbHqgljV/dBm15lK3+ITfjKjoGUM7ad0i13kDq+aU66uL5HCYlusgxYQ02HLe1QN/8ggXNL+LWaPDN/fAibWujKCzBQM3zGkw9jVtuV36rUOc8rJWIlqNm2XjCiimKcn1HdXWxSM3TpXC94Ls4uzycijv+JIOtZQSbMOJ6xwIdMGWBLuFsk6xevXN2l9YFXsLNxLDSsMpXmV6cwQFP8Q93MjO9IRXfS5Ya8TArGzrOqQVYKeFDDhSgXOORHBpF X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jun 2026 18:12:00.8603 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 60d1fc0b-5b6a-45e4-b6c2-08dec32df089 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C381.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB9421 Content-Type: text/plain; charset="utf-8" Add devlink_eswitch_mode=3D command line support for setting a default eswitch mode during device initialization. The supported syntax selects either all devlink handles or one explicit comma-separated handle list: devlink_eswitch_mode=3D*=3D devlink_eswitch_mode=3D[,...]=3D where is one of legacy, switchdev or switchdev_inactive. All selected handles receive the same mode. Assigning different modes to different handle lists in the same parameter value is not supported. The default is applied through the existing eswitch_mode_set() devlink operation, matching the userspace devlink eswitch mode command. devlink core applies it when a matching devlink instance is registered and after a successful devlink reload that performed DRIVER_REINIT, so rebuilt device state returns to the requested boot default. Document the devlink_eswitch_mode=3D syntax and duplicate handle handling. Signed-off-by: Mark Bloch --- .../admin-guide/kernel-parameters.txt | 25 ++ .../networking/devlink/devlink-defaults.rst | 78 +++++ Documentation/networking/devlink/index.rst | 1 + net/devlink/core.c | 271 ++++++++++++++++++ net/devlink/dev.c | 3 + net/devlink/devl_internal.h | 1 + 6 files changed, 379 insertions(+) create mode 100644 Documentation/networking/devlink/devlink-defaults.rst diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index b3fdbbe3b3cc..b4fcc7f81166 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -1246,6 +1246,31 @@ Kernel parameters dell_smm_hwmon.fan_max=3D [HW] Maximum configurable fan speed. =20 + devlink_eswitch_mode=3D + [NET] + Format: + =3D + + : + * | [,...] + + : + / + + Configure default devlink eswitch mode for matching + devlink instances during device initialization. + + : + legacy | switchdev | switchdev_inactive + + Examples: + devlink_eswitch_mode=3D*=3Dswitchdev + devlink_eswitch_mode=3Dpci/0000:08:00.0=3Dswitchdev + devlink_eswitch_mode=3Dpci/0000:08:00.0,pci/0000:09:00.1=3Dswitchdev_in= active + + See Documentation/networking/devlink/devlink-defaults.rst + for the full syntax. + dfltcc=3D [HW,S390] Format: { on | off | def_only | inf_only | always } on: s390 zlib hardware support for compression on diff --git a/Documentation/networking/devlink/devlink-defaults.rst b/Docume= ntation/networking/devlink/devlink-defaults.rst new file mode 100644 index 000000000000..380c9e99210e --- /dev/null +++ b/Documentation/networking/devlink/devlink-defaults.rst @@ -0,0 +1,78 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D +Devlink Eswitch Mode Defaults +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D + +Devlink eswitch mode defaults allow the eswitch mode to be provided on the +kernel command line and applied to matching devlink instances during device +initialization. + +The devlink device is selected by its devlink handle. For PCI devices this= is +the same handle shown by ``devlink dev show``, for example +``pci/0000:08:00.0``. + +Kernel command line syntax +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D + +Defaults are specified with the ``devlink_eswitch_mode=3D`` kernel command= line +parameter. + +The general syntax is:: + + devlink_eswitch_mode=3D=3D + +```` is either ``*`` or one or more devlink handles:: + + * | /[,/...] + +``*`` applies the mode to every devlink instance. All handles in the same +selector receive the same eswitch mode. + +```` is one of ``legacy``, ``switchdev`` or ``switchdev_inactive``. + +Syntax rules +------------ + +The following syntax rules apply: + +* Specify the default in one ``devlink_eswitch_mode=3D`` parameter. Repeat= ed + ``devlink_eswitch_mode=3D`` parameters are not accumulated. +* The ``devlink_eswitch_mode=3D`` value is limited by the kernel command l= ine + size. +* Whitespace is not allowed within the parameter value. +* ```` must be either ``*`` or a handle list. ``*`` cannot be + combined with explicit handles. +* ```` and ```` must not be empty. +* ```` may contain ``:``. This allows PCI names such as + ``0000:08:00.0``. +* Handles must not contain whitespace, ``*``, ``=3D`` or more than one ``/= ``. +* A comma separates handles. +* Comma-separated default assignments are not supported. +* Duplicate handles are rejected and the devlink eswitch mode default is + ignored. + +The eswitch mode default corresponds to the userspace command:: + + devlink dev eswitch set mode + + +Examples +=3D=3D=3D=3D=3D=3D=3D=3D + +Set all devlink instances to switchdev mode:: + + devlink_eswitch_mode=3D*=3Dswitchdev + +Set one PCI devlink instance to switchdev mode:: + + devlink_eswitch_mode=3Dpci/0000:08:00.0=3Dswitchdev + +Set two PCI devlink instances to switchdev inactive mode:: + + devlink_eswitch_mode=3Dpci/0000:08:00.0,pci/0000:09:00.1=3Dswitchdev_ina= ctive + +The following is invalid because comma-separated default assignments are n= ot +supported:: + + devlink_eswitch_mode=3Dpci/0000:08:00.0=3Dswitchdev,pci/0000:09:00.0=3Ds= witchdev_inactive diff --git a/Documentation/networking/devlink/index.rst b/Documentation/net= working/devlink/index.rst index f7ba7dcf477d..0d27a7008b14 100644 --- a/Documentation/networking/devlink/index.rst +++ b/Documentation/networking/devlink/index.rst @@ -56,6 +56,7 @@ general. :maxdepth: 1 =20 devlink-dpipe + devlink-defaults devlink-eswitch-attr devlink-flash devlink-health diff --git a/net/devlink/core.c b/net/devlink/core.c index fe9f6a0a67d5..2111bffb628f 100644 --- a/net/devlink/core.c +++ b/net/devlink/core.c @@ -4,6 +4,10 @@ * Copyright (c) 2016 Jiri Pirko */ =20 +#include +#include +#include +#include #include #define CREATE_TRACE_POINTS #include @@ -16,6 +20,230 @@ EXPORT_TRACEPOINT_SYMBOL_GPL(devlink_trap_report); =20 DEFINE_XARRAY_FLAGS(devlinks, XA_FLAGS_ALLOC); =20 +static char *devlink_default_esw_mode_param; +static bool devlink_default_esw_mode_match_all; +static enum devlink_eswitch_mode devlink_default_esw_mode; +static LIST_HEAD(devlink_default_esw_mode_nodes); + +struct devlink_default_esw_mode_node { + struct list_head list; + char *bus_name; + char *dev_name; +}; + +static int __init +devlink_default_esw_mode_to_value(const char *str, + enum devlink_eswitch_mode *mode) +{ + if (!strcmp(str, "legacy")) { + *mode =3D DEVLINK_ESWITCH_MODE_LEGACY; + return 0; + } + if (!strcmp(str, "switchdev")) { + *mode =3D DEVLINK_ESWITCH_MODE_SWITCHDEV; + return 0; + } + if (!strcmp(str, "switchdev_inactive")) { + *mode =3D DEVLINK_ESWITCH_MODE_SWITCHDEV_INACTIVE; + return 0; + } + + return -EINVAL; +} + +static int __init +devlink_default_esw_mode_handle_parse(char *handle, char **bus_name, + char **dev_name) +{ + char *slash; + char *p; + + if (!*handle) + return -EINVAL; + + for (p =3D handle; *p; p++) { + if (*p =3D=3D '*' || *p =3D=3D '=3D') + return -EINVAL; + } + + slash =3D strchr(handle, '/'); + if (!slash || slash =3D=3D handle || !slash[1]) + return -EINVAL; + if (strchr(slash + 1, '/')) + return -EINVAL; + + *slash =3D '\0'; + + *bus_name =3D handle; + *dev_name =3D slash + 1; + return 0; +} + +static struct devlink_default_esw_mode_node * +devlink_default_esw_mode_node_find(const char *bus_name, const char *dev_n= ame) +{ + struct devlink_default_esw_mode_node *node; + + list_for_each_entry(node, &devlink_default_esw_mode_nodes, list) { + if (!strcmp(node->bus_name, bus_name) && + !strcmp(node->dev_name, dev_name)) + return node; + } + + return NULL; +} + +static int __init +devlink_default_esw_mode_node_add(const char *bus_name, const char *dev_na= me) +{ + struct devlink_default_esw_mode_node *node; + + if (devlink_default_esw_mode_node_find(bus_name, dev_name)) + return -EEXIST; + + node =3D kzalloc_obj(*node); + if (!node) + return -ENOMEM; + + INIT_LIST_HEAD(&node->list); + node->bus_name =3D kstrdup(bus_name, GFP_KERNEL); + node->dev_name =3D kstrdup(dev_name, GFP_KERNEL); + if (!node->bus_name || !node->dev_name) { + kfree(node->bus_name); + kfree(node->dev_name); + kfree(node); + return -ENOMEM; + } + + list_add_tail(&node->list, &devlink_default_esw_mode_nodes); + return 0; +} + +static int __init devlink_default_esw_mode_handles_parse(char *handles) +{ + char *handle; + int err; + + if (!strcmp(handles, "*")) { + devlink_default_esw_mode_match_all =3D true; + return 0; + } + + while ((handle =3D strsep(&handles, ",")) !=3D NULL) { + char *bus_name; + char *dev_name; + + err =3D devlink_default_esw_mode_handle_parse(handle, &bus_name, + &dev_name); + if (err) + return err; + + err =3D devlink_default_esw_mode_node_add(bus_name, dev_name); + if (err) + return err; + } + + return 0; +} + +static void __init +devlink_default_esw_mode_node_free(struct devlink_default_esw_mode_node *n= ode) +{ + kfree(node->bus_name); + kfree(node->dev_name); + kfree(node); +} + +static void __init devlink_default_esw_mode_nodes_clear(void) +{ + struct devlink_default_esw_mode_node *node; + struct devlink_default_esw_mode_node *node_tmp; + + list_for_each_entry_safe(node, node_tmp, + &devlink_default_esw_mode_nodes, list) { + list_del(&node->list); + devlink_default_esw_mode_node_free(node); + } + + devlink_default_esw_mode_match_all =3D false; +} + +static int __init devlink_default_esw_mode_parse(char *str) +{ + char *handles; + char *separator; + char *mode; + enum devlink_eswitch_mode esw_mode; + int err; + + if (!*str) + return -EINVAL; + + separator =3D strrchr(str, '=3D'); + if (!separator || separator =3D=3D str || !separator[1]) + return -EINVAL; + + *separator =3D '\0'; + handles =3D str; + mode =3D separator + 1; + + err =3D devlink_default_esw_mode_to_value(mode, &esw_mode); + if (err) + return err; + + err =3D devlink_default_esw_mode_handles_parse(handles); + if (err) + devlink_default_esw_mode_nodes_clear(); + else + devlink_default_esw_mode =3D esw_mode; + + return err; +} + +static bool devlink_default_esw_mode_match(struct devlink *devlink) +{ + const char *bus_name =3D devlink_bus_name(devlink); + const char *dev_name =3D devlink_dev_name(devlink); + struct devlink_default_esw_mode_node *node; + + if (devlink_default_esw_mode_match_all) + return true; + + node =3D devlink_default_esw_mode_node_find(bus_name, dev_name); + return !!node; +} + +void devlink_apply_default_esw_mode(struct devlink *devlink) +{ + const struct devlink_ops *ops =3D devlink->ops; + int err; + + devl_assert_locked(devlink); + + if (!devlink_default_esw_mode_match(devlink)) + return; + + if (!ops->eswitch_mode_set) { + if (!devlink_default_esw_mode_match_all) + devl_warn(devlink, + "devlink_eswitch_mode=3D selected this device but eswitch mode setti= ng is not supported\n"); + return; + } + + err =3D ops->eswitch_mode_set(devlink, devlink_default_esw_mode, NULL); + if (err) + devl_warn(devlink, + "Couldn't apply default eswitch mode, err %d\n", + err); +} + +static int __init devlink_default_esw_mode_setup(char *str) +{ + devlink_default_esw_mode_param =3D str; + return 1; +} +__setup("devlink_eswitch_mode=3D", devlink_default_esw_mode_setup); + static struct devlink *devlinks_xa_get(unsigned long index) { struct devlink *devlink; @@ -382,6 +610,20 @@ struct devlink *devlinks_xa_lookup_get(struct net *net= , unsigned long index) /** * devl_register - Register devlink instance * @devlink: devlink + * + * Make @devlink visible to userspace. Drivers must call this only after t= he + * instance is fully initialized and its devlink operations can be called. + * + * If a matching devlink_eswitch_mode=3D default was provided on the kernel + * command line, devlink core applies it before devl_register() returns. + * Drivers implementing eswitch_mode_set() must therefore be ready to perf= orm + * the same work as a userspace eswitch mode set request from this point, + * including creation of representors and other eswitch state. + * + * Context: Caller must hold the devlink instance lock. Use devlink_regist= er() + * when the lock is not already held. + * + * Return: 0 on success. */ int devl_register(struct devlink *devlink) { @@ -391,6 +633,7 @@ int devl_register(struct devlink *devlink) xa_set_mark(&devlinks, devlink->index, DEVLINK_REGISTERED); devlink_notify_register(devlink); devlink_rel_nested_in_notify(devlink); + devlink_apply_default_esw_mode(devlink); =20 return 0; } @@ -580,6 +823,31 @@ static int __init devlink_init(void) { int err; =20 + if (devlink_default_esw_mode_param) { + char *def; + + def =3D kstrdup(devlink_default_esw_mode_param, GFP_KERNEL); + if (!def) { + devlink_default_esw_mode_param =3D NULL; + pr_warn("devlink: devlink_eswitch_mode parameter ignored, failed to all= ocate memory\n"); + } else { + err =3D devlink_default_esw_mode_parse(def); + kfree(def); + if (err =3D=3D -EEXIST) { + devlink_default_esw_mode_param =3D NULL; + pr_warn("devlink: duplicate eswitch mode handles ignored\n"); + } else if (err =3D=3D -EINVAL) { + devlink_default_esw_mode_param =3D NULL; + pr_warn("devlink: invalid devlink_eswitch_mode parameter ignored\n"); + } else if (err =3D=3D -ENOMEM) { + devlink_default_esw_mode_param =3D NULL; + pr_warn("devlink: devlink_eswitch_mode parameter ignored, failed to al= locate memory\n"); + } else if (err) { + goto out; + } + } + } + err =3D register_pernet_subsys(&devlink_pernet_ops); if (err) goto out; @@ -595,7 +863,10 @@ static int __init devlink_init(void) out_unreg_pernet_subsys: unregister_pernet_subsys(&devlink_pernet_ops); out: + if (err) + devlink_default_esw_mode_nodes_clear(); WARN_ON(err); + return err; } =20 diff --git a/net/devlink/dev.c b/net/devlink/dev.c index 57b2b8f03543..0b4a831465e8 100644 --- a/net/devlink/dev.c +++ b/net/devlink/dev.c @@ -478,6 +478,9 @@ int devlink_reload(struct devlink *devlink, struct net = *dest_net, return err; =20 WARN_ON(!(*actions_performed & BIT(action))); + if (*actions_performed & BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT)) + devlink_apply_default_esw_mode(devlink); + /* Catch driver on updating the remote action within devlink reload */ WARN_ON(memcmp(remote_reload_stats, devlink->stats.remote_reload_stats, sizeof(remote_reload_stats))); diff --git a/net/devlink/devl_internal.h b/net/devlink/devl_internal.h index e4e48ee2da5a..12557b65248d 100644 --- a/net/devlink/devl_internal.h +++ b/net/devlink/devl_internal.h @@ -71,6 +71,7 @@ extern struct genl_family devlink_nl_family; struct devlink *__devlink_alloc(const struct devlink_ops *ops, size_t priv= _size, struct net *net, struct device *dev, const struct device_driver *dev_driver); +void devlink_apply_default_esw_mode(struct devlink *devlink); =20 #define devl_warn(devlink, format, args...) \ do { \ --=20 2.34.1