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De Francesco" , Shiju Jose , Smita Koralahalli , Li Ming , Tony Luck , , , , Subject: [PATCH] cxl: Fix CXL_HEADERLOG_SIZE to match RAS Capability size Date: Fri, 5 Jun 2026 13:06:10 -0500 Message-ID: <20260605180610.2249458-1-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF00017093:EE_|DM6PR12MB4482:EE_ X-MS-Office365-Filtering-Correlation-Id: 1f0562ef-cd41-458e-2422-08dec32d24ba X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|1800799024|36860700016|82310400026|376014|921020|6133799003|3023799007|18002099003|11063799006|56012099006; X-Microsoft-Antispam-Message-Info: ZZDv0e7vlqqulTMpopWHywUMHfAyPUX5ouZ6cvvAiJNEqUCPZQ8WpLUy4znEIfFA8y+gBe1DRdq0seOd6eG9/APKLOVYDU4574NoPZxaQVSlMlIJzXNOcmQlkvv4ugltdLt60RIG5U6IR0DDmpureMA0jlxphVRA89hYhaS7pe9m4FVvfPNF7NnOSv33xoh/9iTCqSpv6DCm/YoFgJDbKfcTSharypwO9fT6C5y1elPpvvl49T/MEilQUoQjHi4W95iSaSg2Yz/vKWDppZRqx9OYCZhq7NcDwXSwwL7pUzSoR+may0dpLUubjL7oImDC6G/eMI/zi1pl5UMYVSRVXwawL9Qxu0iOEV+kVGb81z+za3oCnuis4KSJid4ijSwaLZEJRtCXC936DzQCOxNZZrI7yFKcR04aBhT1Keo1sxVeHfZAGCqSB203VqH6VQWjrnzdCL2qin6aNG+pRul297tXzrOCTsPYuKy2Lg2LkKXsSKJBRXJayCQggbBI/Je5WLyNnnlgtlguhcLpN1k4uNFtGRvfmHWeNQsnQaqjUOfjoVX67mnYi5ZrVbyRaqK+O697FvXtqjHqssCuknn94XsEWep2fdpdiVxv6lhghNGDOA+kscFCHypiSftjyCAwVUMMaahHbz2kYtppa5R0mhBPHopZ5z4iYGxHnlry9q2ObHZJtrm+D2JLMpaTea5I9EVKHzECgJBCPpy9WLy1OlF6O/sN+aYuqUumCNhpFWCB4JfeIw/PZxqQCcqxh3BY3/v0oLKxArwgXt2erzsFww== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(7416014)(1800799024)(36860700016)(82310400026)(376014)(921020)(6133799003)(3023799007)(18002099003)(11063799006)(56012099006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ieVxY7by9n2qlGm+wWtSSEo5kHM3Z+lWsbpplL8VG9Som2RrA+bkDYeYWRHWwY5PrFdvF25icaqlyuaahreh5ckkpm+EI8+DVwguD6SmOsV+ZRGoTx9jV0qXfKvAH1Jv6wpPmhCIoaiFM6f/1cmIFxoxCwVJKqOBxSvlUQvErKjg7f1IU9yWsai6hxs8fOKaY+cSmV3fsgihkcmVntySiLzgByCEAiA6VK7U0p0QR0+JXa/UeOPDuqPs91yk7GQPCdL8eow7hE4DLgRH7wupZMGQAPOlRe4x80PmrqswP3taU7qvHyF4SpXMAiNdCL2zSGit0bjOofyIvAd8Gi6zx61dimnTHIVIQQBBTwbVD7WIZ957Kft36vLK+n42BzVhKTDcrSrCRA/aLRjZMmarMX8M970PwEFjfVUyqJh1q1CMs8WThO98WdQz3K8Vyy/C X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jun 2026 18:06:18.9468 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1f0562ef-cd41-458e-2422-08dec32d24ba X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017093.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4482 Content-Type: text/plain; charset="utf-8" The CXL r4.0 8.2.4.17.7 RAS Capability Structure has total length 0x58 bytes (CXL_RAS_CAPABILITY_LENGTH); the Header Log occupies the trailing 64 bytes at offset 0x18. CXL_HEADERLOG_SIZE was defined as SZ_512, eight times the actual on-device size. header_log_copy() reads CXL_HEADERLOG_SIZE_U32 (128) dwords from the RAS capability iomap, overrunning the 88-byte mapping by 448 bytes. The cxl_aer_uncorrectable_error trace event memcpy()s CXL_HEADERLOG_SIZE (512) bytes from its source. For the CPER caller the source is struct cxl_ras_capability_regs::header_log[16] (64 bytes) embedded in a stack-local cxl_cper_prot_err_work_data, so the memcpy reads 448 bytes of kernel stack into the trace event ring buffer where userspace can read it via tracefs. Set CXL_HEADERLOG_SIZE to 64 and derive CXL_HEADERLOG_SIZE_U32 from it, bringing all iomap readers into agreement on 16 dwords. Userspace tools such as rasdaemon have grown a dependency on the buggy 512-byte (128 u32) header_log layout in the cxl_aer_uncorrectable_error trace event. Add CXL_HEADERLOG_TRACE_SIZE_U32 =3D 128 and use it for the trace event __array and its memcpy to preserve that ABI. Both callers now pass a zero-filled u32[CXL_HEADERLOG_TRACE_SIZE_U32] staging buffer with only the first CXL_HEADERLOG_SIZE_U32 (16) entries populated from hardware; the remaining 112 u32s are zero-padded, keeping the 512-byte trace ring buffer layout intact. Fixes: 36f257e3b0ba ("acpi/ghes, cxl/pci: Process CXL CPER Protocol Errors") Fixes: 2905cb5236cb ("cxl/pci: Add (hopeful) error handling support") Cc: stable@vger.kernel.org Reported-by: Sashiko Signed-off-by: Terry Bowman Reviewed-by: Ben Cheatham Reviewed-by: Dave Jiang --- drivers/cxl/core/ras.c | 27 ++++++++++++++++++++------- drivers/cxl/core/trace.h | 24 ++++++++++++++++-------- drivers/cxl/cxl.h | 14 ++++++++++++-- 3 files changed, 48 insertions(+), 17 deletions(-) diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 006c6ffc2f56..99fb00949c2f 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -8,6 +8,10 @@ #include #include "trace.h" =20 +/* Check that UCE header definition is maintained to keep ABI intact */ +static_assert(CXL_HEADERLOG_TRACE_SIZE_U32 =3D=3D 128, + "rasdaemon ABI requires exactly 128 u32s"); + static void cxl_cper_trace_corr_port_prot_err(struct pci_dev *pdev, struct cxl_ras_capability_regs ras_cap) { @@ -19,6 +23,7 @@ static void cxl_cper_trace_corr_port_prot_err(struct pci_= dev *pdev, static void cxl_cper_trace_uncorr_port_prot_err(struct pci_dev *pdev, struct cxl_ras_capability_regs ras_cap) { + u32 hl[CXL_HEADERLOG_TRACE_SIZE_U32] =3D {}; u32 status =3D ras_cap.uncor_status & ~ras_cap.uncor_mask; u32 fe; =20 @@ -28,8 +33,8 @@ static void cxl_cper_trace_uncorr_port_prot_err(struct pc= i_dev *pdev, else fe =3D status; =20 - trace_cxl_port_aer_uncorrectable_error(&pdev->dev, status, fe, - ras_cap.header_log); + memcpy(hl, ras_cap.header_log, CXL_HEADERLOG_SIZE); + trace_cxl_port_aer_uncorrectable_error(&pdev->dev, status, fe, hl); } =20 static void cxl_cper_trace_corr_prot_err(struct cxl_memdev *cxlmd, @@ -44,6 +49,7 @@ static void cxl_cper_trace_uncorr_prot_err(struct cxl_memdev *cxlmd, struct cxl_ras_capability_regs ras_cap) { + u32 hl[CXL_HEADERLOG_TRACE_SIZE_U32] =3D {}; u32 status =3D ras_cap.uncor_status & ~ras_cap.uncor_mask; u32 fe; =20 @@ -53,8 +59,15 @@ cxl_cper_trace_uncorr_prot_err(struct cxl_memdev *cxlmd, else fe =3D status; =20 - trace_cxl_aer_uncorrectable_error(cxlmd, status, fe, - ras_cap.header_log); + /* + * ras_cap.header_log[] holds CXL_HEADERLOG_SIZE_U32 (16) hardware + * dwords. Copy them into the front of a zero-filled + * CXL_HEADERLOG_TRACE_SIZE_U32 (128) u32 staging buffer so the trace + * event memcpy sees a full 512-byte source and the userspace ABI + * (rasdaemon) is preserved. + */ + memcpy(hl, ras_cap.header_log, CXL_HEADERLOG_SIZE); + trace_cxl_aer_uncorrectable_error(cxlmd, status, fe, hl); } =20 static int match_memdev_by_parent(struct device *dev, const void *uport) @@ -204,12 +217,12 @@ static void header_log_copy(void __iomem *ras_base, u= 32 *log) { void __iomem *addr; u32 *log_addr; - int i, log_u32_size =3D CXL_HEADERLOG_SIZE / sizeof(u32); + int i; =20 addr =3D ras_base + CXL_RAS_HEADER_LOG_OFFSET; log_addr =3D log; =20 - for (i =3D 0; i < log_u32_size; i++) { + for (i =3D 0; i < CXL_HEADERLOG_SIZE_U32; i++) { *log_addr =3D readl(addr); log_addr++; addr +=3D sizeof(u32); @@ -222,7 +235,7 @@ static void header_log_copy(void __iomem *ras_base, u32= *log) */ bool cxl_handle_ras(struct device *dev, void __iomem *ras_base) { - u32 hl[CXL_HEADERLOG_SIZE_U32]; + u32 hl[CXL_HEADERLOG_TRACE_SIZE_U32] =3D {}; void __iomem *addr; u32 status; u32 fe; diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h index a972e4ef1936..d37876096dd7 100644 --- a/drivers/cxl/core/trace.h +++ b/drivers/cxl/core/trace.h @@ -56,7 +56,7 @@ TRACE_EVENT(cxl_port_aer_uncorrectable_error, __string(host, dev_name(dev->parent)) __field(u32, status) __field(u32, first_error) - __array(u32, header_log, CXL_HEADERLOG_SIZE_U32) + __array(u32, header_log, CXL_HEADERLOG_TRACE_SIZE_U32) ), TP_fast_assign( __assign_str(device); @@ -64,10 +64,14 @@ TRACE_EVENT(cxl_port_aer_uncorrectable_error, __entry->status =3D status; __entry->first_error =3D fe; /* - * Embed the 512B headerlog data for user app retrieval and - * parsing, but no need to print this in the trace buffer. + * Embed headerlog data for user app retrieval and parsing, + * but no need to print in the trace buffer. Only + * CXL_HEADERLOG_SIZE_U32 (16) dwords are hardware data; + * the remaining entries preserve the 512-byte ABI layout + * rasdaemon depends on and are zero-filled by the caller. */ - memcpy(__entry->header_log, hl, CXL_HEADERLOG_SIZE); + memcpy(__entry->header_log, hl, + CXL_HEADERLOG_TRACE_SIZE_U32 * sizeof(u32)); ), TP_printk("device=3D%s host=3D%s status: '%s' first_error: '%s'", __get_str(device), __get_str(host), @@ -85,7 +89,7 @@ TRACE_EVENT(cxl_aer_uncorrectable_error, __field(u64, serial) __field(u32, status) __field(u32, first_error) - __array(u32, header_log, CXL_HEADERLOG_SIZE_U32) + __array(u32, header_log, CXL_HEADERLOG_TRACE_SIZE_U32) ), TP_fast_assign( __assign_str(memdev); @@ -94,10 +98,14 @@ TRACE_EVENT(cxl_aer_uncorrectable_error, __entry->status =3D status; __entry->first_error =3D fe; /* - * Embed the 512B headerlog data for user app retrieval and - * parsing, but no need to print this in the trace buffer. + * Embed headerlog data for user app retrieval and parsing, + * but no need to print in the trace buffer. Only + * CXL_HEADERLOG_SIZE_U32 (16) dwords are hardware data; + * the remaining entries preserve the 512-byte ABI layout + * rasdaemon depends on and are zero-filled by the caller. */ - memcpy(__entry->header_log, hl, CXL_HEADERLOG_SIZE); + memcpy(__entry->header_log, hl, + CXL_HEADERLOG_TRACE_SIZE_U32 * sizeof(u32)); ), TP_printk("memdev=3D%s host=3D%s serial=3D%lld: status: '%s' first_error:= '%s'", __get_str(memdev), __get_str(host), __entry->serial, diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 9b947286eb9b..906fb480dad5 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -148,8 +148,18 @@ static inline int ways_to_eiw(unsigned int ways, u8 *e= iw) #define CXL_RAS_CAP_CONTROL_FE_MASK GENMASK(5, 0) #define CXL_RAS_HEADER_LOG_OFFSET 0x18 #define CXL_RAS_CAPABILITY_LENGTH 0x58 -#define CXL_HEADERLOG_SIZE SZ_512 -#define CXL_HEADERLOG_SIZE_U32 SZ_512 / sizeof(u32) +#define CXL_HEADERLOG_SIZE 64 +#define CXL_HEADERLOG_SIZE_U32 (CXL_HEADERLOG_SIZE / sizeof(u32)) + +/* + * The RAS UCE trace event header array was originally sized at SZ_512/siz= eof(u32) + * =3D 128 u32s due to a bug. Userspace tools (rasdaemon) have grown a dep= endency + * on that 512-byte layout. Keep the trace array at 128 u32s to preserve t= he + * ABI; only CXL_HEADERLOG_SIZE_U32 (16) dwords are valid hardware data, t= he + * remainder are zero-filled. + */ +#define CXL_HEADERLOG_TRACE_SIZE SZ_512 +#define CXL_HEADERLOG_TRACE_SIZE_U32 (CXL_HEADERLOG_TRACE_SIZE / sizeof(u3= 2)) =20 /* CXL 2.0 8.2.8.1 Device Capabilities Array Register */ #define CXLDEV_CAP_ARRAY_OFFSET 0x0 --=20 2.34.1