From nobody Mon Jun 8 05:26:07 2026 Received: from smtp-out2.suse.de (smtp-out2.suse.de [195.135.223.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F4AB3B52F5 for ; Fri, 5 Jun 2026 14:43:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.135.223.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780670616; cv=none; b=W8z1bEj4qKUpLsg6ZoLHL4u/rhw8+KGjpfJmU05zWkP2pRnyAVsjww8AOz9Qnb+5Q7k25Tkuj3SFuifEmeDf5bqLDBwNxjJxHPm0GsPUlE4bveRF5s/7zdB+ftNh6dQoPeLS8SauWT/fSjvzk/i7pcp1XTI/qpcC8PQr3Rdlxlo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780670616; c=relaxed/simple; bh=dJanACVNtJGpR2aTB+msFj3gLjqXQHmBUjBngJ5GrY0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=J16Fj6i7bJu5WTNYkmVpTz0cCmYrYBk9sopoz1MmIPTZVaVldNxY+94WpM40BjZ9N3raZLaqdBFykbd18kCZUDLanK4p3hM52US6NfVIc7JMxH3rdRr/332aWrStAFYBw24IW0qlyuyryzhjZFiYK2aVHezwyh4IacAUbSg/psc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b=epQUrVEF; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b=epQUrVEF; arc=none smtp.client-ip=195.135.223.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b="epQUrVEF"; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b="epQUrVEF" Received: from imap1.dmz-prg2.suse.org (unknown [10.150.64.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id C93F175992; Fri, 5 Jun 2026 14:43:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1780670603; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=J+5cq3+j4X/akDtIcMoCvLSbbIDblYGhZGXw0uvKbw0=; b=epQUrVEFXnUTKjaQYhvNXgYmnQD9xCM37U4AOrs5ekOdNGyMEpaqmbj2wUm+BiYxsHFfep UqFoM7wwjUcwrmP7Jr+mAkQl5iWKTdqRMje39pFLqC8RyVjBVS6ffF35GMTZD2NCJ30S5S aHtYN4VbbsLxdgC2jyabBdh1qbncELU= Authentication-Results: smtp-out2.suse.de; none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1780670603; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=J+5cq3+j4X/akDtIcMoCvLSbbIDblYGhZGXw0uvKbw0=; b=epQUrVEFXnUTKjaQYhvNXgYmnQD9xCM37U4AOrs5ekOdNGyMEpaqmbj2wUm+BiYxsHFfep UqFoM7wwjUcwrmP7Jr+mAkQl5iWKTdqRMje39pFLqC8RyVjBVS6ffF35GMTZD2NCJ30S5S aHtYN4VbbsLxdgC2jyabBdh1qbncELU= Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id 86EBF779A8; Fri, 5 Jun 2026 14:43:23 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id pau/H4vgImrmWwAAD6G6ig (envelope-from ); Fri, 05 Jun 2026 14:43:23 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Cc: Juergen Gross , Huang Rui , Mario Limonciello , Perry Yuan , K Prateek Nayak , "Rafael J. Wysocki" , Viresh Kumar Subject: [PATCH v2 01/10] x86/msr: Switch rdmsrl_on_cpu() users to rdmsrq_on_cpu() Date: Fri, 5 Jun 2026 16:43:05 +0200 Message-ID: <20260605144314.3031049-2-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260605144314.3031049-1-jgross@suse.com> References: <20260605144314.3031049-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam-Flag: NO X-Spamd-Result: default: False [-6.80 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[99.99%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; RCVD_COUNT_TWO(0.00)[2]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; FROM_HAS_DN(0.00)[]; MIME_TRACE(0.00)[0:+]; TO_MATCH_ENVRCPT_ALL(0.00)[]; FUZZY_RATELIMITED(0.00)[rspamd.com]; DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:helo,suse.com:email,suse.com:mid]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; FROM_EQ_ENVFROM(0.00)[]; TO_DN_SOME(0.00)[]; RCPT_COUNT_SEVEN(0.00)[9]; RCVD_TLS_ALL(0.00)[] X-Spam-Level: X-Spam-Score: -6.80 Content-Type: text/plain; charset="utf-8" rdmsrl_on_cpu() is a deprecated synonym for rdmsrq_on_cpu(). Switch its only user to rdmsrq_on_cpu(). Signed-off-by: Juergen Gross Reviewed-by: Dave Hansen --- V2: - carved out from other patch (Ingo Molnar) --- drivers/cpufreq/amd-pstate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 62b5d995281d..7847cf363ce8 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -476,7 +476,7 @@ static int msr_init_perf(struct amd_cpudata *cpudata) if (ret) return ret; =20 - ret =3D rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &cppc_req); + ret =3D rdmsrq_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &cppc_req); if (ret) return ret; =20 --=20 2.54.0 From nobody Mon Jun 8 05:26:07 2026 Received: from smtp-out1.suse.de (smtp-out1.suse.de [195.135.223.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 293AD3CC33C for ; Fri, 5 Jun 2026 14:43:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.135.223.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780670617; cv=none; b=VlpJmvsfEMtvN4RBAnz4TGDuhKBTgVCCT/rba2xSGPoFy1ICxNGpFZ5iPQZOZ1NsbX3a5hiKoZbNV7zlP4KlMqx6zUpcrq2aOqmEM23dLcYE7XDrY0hD7jReCy56x0sRQSUZXVHVik40bbFFZF5vijFp4oWGxTGzos0eXCDl6Do= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780670617; c=relaxed/simple; bh=pFBjqyCxiYBedqPM+ABvmFQ4fgktAKY/Hz3hXt8EJOY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=e+a4muc1IcjEqdZT5vlxydnXW7msyJH8nkPvqRYlxIfhFXJum0aOLk3Dzb4tkz0xYuxRoPrGIzh8OzLQ0LZre5mBUpK8sfZouV/az0h9DreDfHQf5CWuBqLY4gDymoByLCIIjK/MU6KlnxUH2X2oYUrEqbuBrFjajlNHWZf3qGk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b=XgexYzvo; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b=XgexYzvo; arc=none smtp.client-ip=195.135.223.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b="XgexYzvo"; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b="XgexYzvo" Received: from imap1.dmz-prg2.suse.org (unknown [10.150.64.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id 5DC316A868; Fri, 5 Jun 2026 14:43:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1780670609; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=PwWpZLnOsgQlN4uxI7yPcbJ1NY6p3hgv+jVC/E5PGIs=; b=XgexYzvoVIf7KX4A9+1Oz7NEe+7XVtjCX9Z13+wrHGcXUHoaYkiamuxe9zey26ZtFIZ6fk XA4ky2lxDC/TaBH7XmjsdRJyDslhfNhR7V8/6vwQj+HnVx+YVsgJWcyKbrC6Lu3ggv6Os+ YlzwgZ6KdtVgka4QdadHawS9PY5zRfo= Authentication-Results: smtp-out1.suse.de; none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1780670609; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=PwWpZLnOsgQlN4uxI7yPcbJ1NY6p3hgv+jVC/E5PGIs=; b=XgexYzvoVIf7KX4A9+1Oz7NEe+7XVtjCX9Z13+wrHGcXUHoaYkiamuxe9zey26ZtFIZ6fk XA4ky2lxDC/TaBH7XmjsdRJyDslhfNhR7V8/6vwQj+HnVx+YVsgJWcyKbrC6Lu3ggv6Os+ YlzwgZ6KdtVgka4QdadHawS9PY5zRfo= Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id 201EF779A8; Fri, 5 Jun 2026 14:43:29 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id kuvGBpHgImr+WwAAD6G6ig (envelope-from ); Fri, 05 Jun 2026 14:43:29 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" Subject: [PATCH v2 02/10] x86/msr: Remove rdmsrl_on_cpu() Date: Fri, 5 Jun 2026 16:43:06 +0200 Message-ID: <20260605144314.3031049-3-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260605144314.3031049-1-jgross@suse.com> References: <20260605144314.3031049-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam-Flag: NO X-Spam-Score: -6.80 X-Spamd-Result: default: False [-6.80 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; MIME_TRACE(0.00)[0:+]; FUZZY_RATELIMITED(0.00)[rspamd.com]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; TO_DN_SOME(0.00)[]; RCPT_COUNT_SEVEN(0.00)[8]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; FROM_EQ_ENVFROM(0.00)[]; FROM_HAS_DN(0.00)[]; R_RATELIMIT(0.00)[to_ip_from(RLfdszjqhz8kzzb9uwpzdm8png)]; DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:helo,suse.com:email,suse.com:mid]; RCVD_COUNT_TWO(0.00)[2]; TO_MATCH_ENVRCPT_ALL(0.00)[]; RCVD_TLS_ALL(0.00)[] X-Spam-Level: Content-Type: text/plain; charset="utf-8" With no user left, rdmsrl_on_cpu() can be deleted. Signed-off-by: Juergen Gross Reviewed-by: Dave Hansen --- V2: - carved out from other patch (Ingo Molnar) --- arch/x86/include/asm/msr.h | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 9c2ea29e12a9..fddadbc625be 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -329,7 +329,6 @@ static inline int wrmsr_safe_regs_on_cpu(unsigned int c= pu, u32 regs[8]) /* Compatibility wrappers: */ #define rdmsrl(msr, val) rdmsrq(msr, val) #define wrmsrl(msr, val) wrmsrq(msr, val) -#define rdmsrl_on_cpu(cpu, msr, q) rdmsrq_on_cpu(cpu, msr, q) =20 #endif /* __ASSEMBLER__ */ #endif /* _ASM_X86_MSR_H */ --=20 2.54.0 From nobody Mon Jun 8 05:26:07 2026 Received: from smtp-out2.suse.de (smtp-out2.suse.de [195.135.223.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 199923A2550 for ; Fri, 5 Jun 2026 14:43:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.135.223.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780670627; cv=none; b=QnAtu9vZdz14/S1DANttrgAjFCGd2QQ/3f6q0nYTrx4hHb+43QvAz9ymkA0Ewb7za8NaBEUcztQgQiZyzL/qTzDboItFNncDk+8QDjnRg9ldi9JKBLPJJh7WTRIpIF6ep09KBkmkGQeG8VtZLumfYZlTHq50SVnwyoG9kmJg5LY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780670627; c=relaxed/simple; bh=rt7fzzRl7yRTHyidGuY3CpBGL5GcZwN+449BW9cygB4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BF1YT9CI0sGT5xUjVlqj5CMfKoZuiQwbjJjROUSK7bVvl04ZRNrx7u/WR5rGQHdx8+Qo2sjeYh66X93gsTILWnag2765gRsJTU4TcGQYl0EqkZDIClt6JOYRn88RAE0AjcRDuxglGEBeSZVOon0Z5w2v9DwooyLttekBwrv64W4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; arc=none smtp.client-ip=195.135.223.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Received: from imap1.dmz-prg2.suse.org (imap1.dmz-prg2.suse.org [IPv6:2a07:de40:b281:104:10:150:64:97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id 1AFBC75994; Fri, 5 Jun 2026 14:43:35 +0000 (UTC) Authentication-Results: smtp-out2.suse.de; none Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id A95BE779A8; Fri, 5 Jun 2026 14:43:34 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id euslKJbgImoHXAAAD6G6ig (envelope-from ); Fri, 05 Jun 2026 14:43:34 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org, linux-edac@vger.kernel.org, linux-pm@vger.kernel.org, linux-hwmon@vger.kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Tony Luck , "Rafael J. Wysocki" , Viresh Kumar , Guenter Roeck , Daniel Lezcano , Zhang Rui , Lukasz Luba Subject: [PATCH v2 03/10] x86/msr: Switch rdmsr_on_cpu() users to rdmsrq_on_cpu() Date: Fri, 5 Jun 2026 16:43:07 +0200 Message-ID: <20260605144314.3031049-4-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260605144314.3031049-1-jgross@suse.com> References: <20260605144314.3031049-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Spam-Flag: NO X-Spam-Score: -4.00 X-Spam-Level: X-Rspamd-Server: rspamd2.dmz-prg2.suse.org X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[] X-Rspamd-Queue-Id: 1AFBC75994 X-Rspamd-Action: no action Content-Type: text/plain; charset="utf-8" In order to prepare retiring rdmsr_on_cpu() switch rdmsr_on_cpu() users to rdmsrq_on_cpu(). Signed-off-by: Juergen Gross Reviewed-by: Dave Hansen --- V2: - instead of changing rdmsr_on_cpu(), use rdmsrq_on_cpu() (Ingo Molnar) --- arch/x86/include/asm/msr.h | 2 +- arch/x86/kernel/cpu/mce/amd.c | 6 ++-- arch/x86/kernel/cpu/mce/inject.c | 8 ++--- drivers/cpufreq/amd_freq_sensitivity.c | 6 ++-- drivers/cpufreq/p4-clockmod.c | 32 ++++++++++---------- drivers/cpufreq/speedstep-centrino.c | 27 +++++++++-------- drivers/hwmon/coretemp.c | 12 ++++---- drivers/thermal/intel/x86_pkg_temp_thermal.c | 25 ++++++++------- 8 files changed, 58 insertions(+), 60 deletions(-) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index fddadbc625be..d5985d6fdaf9 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -292,7 +292,7 @@ static inline int wrmsrq_on_cpu(unsigned int cpu, u32 m= sr_no, u64 q) static inline void rdmsr_on_cpus(const struct cpumask *m, u32 msr_no, struct msr __percpu *msrs) { - rdmsr_on_cpu(0, msr_no, raw_cpu_ptr(&msrs->l), raw_cpu_ptr(&msrs->h)); + rdmsrq_on_cpu(0, msr_no, raw_cpu_ptr(&msrs->q)); } static inline void wrmsr_on_cpus(const struct cpumask *m, u32 msr_no, struct msr __percpu *msrs) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 6605a0224659..1305d9a2ee32 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -969,13 +969,13 @@ store_threshold_limit(struct threshold_block *b, cons= t char *buf, size_t size) =20 static ssize_t show_error_count(struct threshold_block *b, char *buf) { - u32 lo, hi; + struct msr val; =20 /* CPU might be offline by now */ - if (rdmsr_on_cpu(b->cpu, b->address, &lo, &hi)) + if (rdmsrq_on_cpu(b->cpu, b->address, &val.q)) return -ENODEV; =20 - return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) - + return sprintf(buf, "%u\n", ((val.h & THRESHOLD_MAX) - (THRESHOLD_MAX - b->threshold_limit))); } =20 diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inj= ect.c index d02c4f556cd0..bee9c35762b8 100644 --- a/arch/x86/kernel/cpu/mce/inject.c +++ b/arch/x86/kernel/cpu/mce/inject.c @@ -316,18 +316,18 @@ static struct notifier_block inject_nb =3D { */ static int toggle_hw_mce_inject(unsigned int cpu, bool enable) { - u32 l, h; + struct msr val; int err; =20 - err =3D rdmsr_on_cpu(cpu, MSR_K7_HWCR, &l, &h); + err =3D rdmsrq_on_cpu(cpu, MSR_K7_HWCR, &val.q); if (err) { pr_err("%s: error reading HWCR\n", __func__); return err; } =20 - enable ? (l |=3D BIT(18)) : (l &=3D ~BIT(18)); + enable ? (val.l |=3D BIT(18)) : (val.l &=3D ~BIT(18)); =20 - err =3D wrmsr_on_cpu(cpu, MSR_K7_HWCR, l, h); + err =3D wrmsr_on_cpu(cpu, MSR_K7_HWCR, val.l, val.h); if (err) pr_err("%s: error writing HWCR\n", __func__); =20 diff --git a/drivers/cpufreq/amd_freq_sensitivity.c b/drivers/cpufreq/amd_f= req_sensitivity.c index 13fed4b9e02b..739d54dc9f2b 100644 --- a/drivers/cpufreq/amd_freq_sensitivity.c +++ b/drivers/cpufreq/amd_freq_sensitivity.c @@ -51,10 +51,8 @@ static unsigned int amd_powersave_bias_target(struct cpu= freq_policy *policy, if (!policy->freq_table) return freq_next; =20 - rdmsr_on_cpu(policy->cpu, MSR_AMD64_FREQ_SENSITIVITY_ACTUAL, - &actual.l, &actual.h); - rdmsr_on_cpu(policy->cpu, MSR_AMD64_FREQ_SENSITIVITY_REFERENCE, - &reference.l, &reference.h); + rdmsrq_on_cpu(policy->cpu, MSR_AMD64_FREQ_SENSITIVITY_ACTUAL, &actual.q); + rdmsrq_on_cpu(policy->cpu, MSR_AMD64_FREQ_SENSITIVITY_REFERENCE, &referen= ce.q); actual.h &=3D 0x00ffffff; reference.h &=3D 0x00ffffff; =20 diff --git a/drivers/cpufreq/p4-clockmod.c b/drivers/cpufreq/p4-clockmod.c index 69c19233fcd4..d96e8b665f39 100644 --- a/drivers/cpufreq/p4-clockmod.c +++ b/drivers/cpufreq/p4-clockmod.c @@ -51,24 +51,24 @@ static unsigned int cpufreq_p4_get(unsigned int cpu); =20 static int cpufreq_p4_setdc(unsigned int cpu, unsigned int newstate) { - u32 l, h; + struct msr val; =20 if ((newstate > DC_DISABLE) || (newstate =3D=3D DC_RESV)) return -EINVAL; =20 - rdmsr_on_cpu(cpu, MSR_IA32_THERM_STATUS, &l, &h); + rdmsrq_on_cpu(cpu, MSR_IA32_THERM_STATUS, &val.q); =20 - if (l & 0x01) + if (val.l & 0x01) pr_debug("CPU#%d currently thermal throttled\n", cpu); =20 if (has_N44_O17_errata[cpu] && (newstate =3D=3D DC_25PT || newstate =3D=3D DC_DFLT)) newstate =3D DC_38PT; =20 - rdmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, &l, &h); + rdmsrq_on_cpu(cpu, MSR_IA32_THERM_CONTROL, &val.q); if (newstate =3D=3D DC_DISABLE) { pr_debug("CPU#%d disabling modulation\n", cpu); - wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, l & ~(1<<4), h); + wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, val.l & ~(1<<4), val.h); } else { pr_debug("CPU#%d setting duty cycle to %d%%\n", cpu, ((125 * newstate) / 10)); @@ -77,9 +77,9 @@ static int cpufreq_p4_setdc(unsigned int cpu, unsigned in= t newstate) * bits 3-1 : duty cycle * bit 0 : reserved */ - l =3D (l & ~14); - l =3D l | (1<<4) | ((newstate & 0x7)<<1); - wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, l, h); + val.l =3D (val.l & ~14); + val.l =3D val.l | (1<<4) | ((newstate & 0x7)<<1); + wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, val.l, val.h); } =20 return 0; @@ -205,18 +205,18 @@ static int cpufreq_p4_cpu_init(struct cpufreq_policy = *policy) =20 static unsigned int cpufreq_p4_get(unsigned int cpu) { - u32 l, h; + struct msr val; =20 - rdmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, &l, &h); + rdmsrq_on_cpu(cpu, MSR_IA32_THERM_CONTROL, &val.q); =20 - if (l & 0x10) { - l =3D l >> 1; - l &=3D 0x7; + if (val.l & 0x10) { + val.l =3D val.l >> 1; + val.l &=3D 0x7; } else - l =3D DC_DISABLE; + val.l =3D DC_DISABLE; =20 - if (l !=3D DC_DISABLE) - return stock_freq * l / 8; + if (val.l !=3D DC_DISABLE) + return stock_freq * val.l / 8; =20 return stock_freq; } diff --git a/drivers/cpufreq/speedstep-centrino.c b/drivers/cpufreq/speedst= ep-centrino.c index 3e6e85a92212..cefee19d1100 100644 --- a/drivers/cpufreq/speedstep-centrino.c +++ b/drivers/cpufreq/speedstep-centrino.c @@ -322,11 +322,11 @@ static unsigned extract_clock(unsigned msr, unsigned = int cpu, int failsafe) /* Return the current CPU frequency in kHz */ static unsigned int get_cur_freq(unsigned int cpu) { - unsigned l, h; + struct msr val; unsigned clock_freq; =20 - rdmsr_on_cpu(cpu, MSR_IA32_PERF_STATUS, &l, &h); - clock_freq =3D extract_clock(l, cpu, 0); + rdmsrq_on_cpu(cpu, MSR_IA32_PERF_STATUS, &val.q); + clock_freq =3D extract_clock(val.l, cpu, 0); =20 if (unlikely(clock_freq =3D=3D 0)) { /* @@ -335,8 +335,8 @@ static unsigned int get_cur_freq(unsigned int cpu) * P-state transition (like TM2). Get the last freq set=20 * in PERF_CTL. */ - rdmsr_on_cpu(cpu, MSR_IA32_PERF_CTL, &l, &h); - clock_freq =3D extract_clock(l, cpu, 1); + rdmsrq_on_cpu(cpu, MSR_IA32_PERF_CTL, &val.q); + clock_freq =3D extract_clock(val.l, cpu, 1); } return clock_freq; } @@ -417,7 +417,8 @@ static void centrino_cpu_exit(struct cpufreq_policy *po= licy) */ static int centrino_target(struct cpufreq_policy *policy, unsigned int ind= ex) { - unsigned int msr, oldmsr =3D 0, h =3D 0, cpu =3D policy->cpu; + unsigned int msr, cpu =3D policy->cpu; + struct msr oldmsr =3D { .q =3D 0 }; int retval =3D 0; unsigned int j, first_cpu; struct cpufreq_frequency_table *op_points; @@ -459,22 +460,22 @@ static int centrino_target(struct cpufreq_policy *pol= icy, unsigned int index) msr =3D op_points->driver_data; =20 if (first_cpu) { - rdmsr_on_cpu(good_cpu, MSR_IA32_PERF_CTL, &oldmsr, &h); - if (msr =3D=3D (oldmsr & 0xffff)) { + rdmsrq_on_cpu(good_cpu, MSR_IA32_PERF_CTL, &oldmsr.q); + if (msr =3D=3D (oldmsr.l & 0xffff)) { pr_debug("no change needed - msr was and needs " - "to be %x\n", oldmsr); + "to be %x\n", oldmsr.l); retval =3D 0; goto out; } =20 first_cpu =3D 0; /* all but 16 LSB are reserved, treat them with care */ - oldmsr &=3D ~0xffff; + oldmsr.l &=3D ~0xffff; msr &=3D 0xffff; - oldmsr |=3D msr; + oldmsr.l |=3D msr; } =20 - wrmsr_on_cpu(good_cpu, MSR_IA32_PERF_CTL, oldmsr, h); + wrmsr_on_cpu(good_cpu, MSR_IA32_PERF_CTL, oldmsr.l, oldmsr.h); if (policy->shared_type =3D=3D CPUFREQ_SHARED_TYPE_ANY) break; =20 @@ -490,7 +491,7 @@ static int centrino_target(struct cpufreq_policy *polic= y, unsigned int index) */ =20 for_each_cpu(j, covered_cpus) - wrmsr_on_cpu(j, MSR_IA32_PERF_CTL, oldmsr, h); + wrmsr_on_cpu(j, MSR_IA32_PERF_CTL, oldmsr.l, oldmsr.h); } retval =3D 0; =20 diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c index 6a0d94711ead..1259c78c95c6 100644 --- a/drivers/hwmon/coretemp.c +++ b/drivers/hwmon/coretemp.c @@ -356,15 +356,15 @@ static ssize_t show_label(struct device *dev, static ssize_t show_crit_alarm(struct device *dev, struct device_attribute *devattr, char *buf) { - u32 eax, edx; + struct msr val; struct temp_data *tdata =3D container_of(devattr, struct temp_data, sd_attrs[ATTR_CRIT_ALARM]); =20 mutex_lock(&tdata->update_lock); - rdmsr_on_cpu(tdata->cpu, tdata->status_reg, &eax, &edx); + rdmsrq_on_cpu(tdata->cpu, tdata->status_reg, &val.q); mutex_unlock(&tdata->update_lock); =20 - return sprintf(buf, "%d\n", (eax >> 5) & 1); + return sprintf(buf, "%d\n", (val.l >> 5) & 1); } =20 static ssize_t show_tjmax(struct device *dev, @@ -398,7 +398,7 @@ static ssize_t show_ttarget(struct device *dev, static ssize_t show_temp(struct device *dev, struct device_attribute *devattr, char *buf) { - u32 eax, edx; + struct msr val; struct temp_data *tdata =3D container_of(devattr, struct temp_data, sd_at= trs[ATTR_TEMP]); int tjmax; =20 @@ -407,14 +407,14 @@ static ssize_t show_temp(struct device *dev, tjmax =3D get_tjmax(tdata, dev); /* Check whether the time interval has elapsed */ if (time_after(jiffies, tdata->last_updated + HZ)) { - rdmsr_on_cpu(tdata->cpu, tdata->status_reg, &eax, &edx); + rdmsrq_on_cpu(tdata->cpu, tdata->status_reg, &val.q); /* * Ignore the valid bit. In all observed cases the register * value is either low or zero if the valid bit is 0. * Return it instead of reporting an error which doesn't * really help at all. */ - tdata->temp =3D tjmax - ((eax >> 16) & 0xff) * 1000; + tdata->temp =3D tjmax - ((val.l >> 16) & 0xff) * 1000; tdata->last_updated =3D jiffies; } =20 diff --git a/drivers/thermal/intel/x86_pkg_temp_thermal.c b/drivers/thermal= /intel/x86_pkg_temp_thermal.c index 540109761f0a..2e7de8cf756d 100644 --- a/drivers/thermal/intel/x86_pkg_temp_thermal.c +++ b/drivers/thermal/intel/x86_pkg_temp_thermal.c @@ -125,8 +125,9 @@ sys_set_trip_temp(struct thermal_zone_device *tzd, { struct zone_device *zonedev =3D thermal_zone_device_priv(tzd); unsigned int trip_index =3D THERMAL_TRIP_PRIV_TO_INT(trip->priv); - u32 l, h, mask, shift, intr; + u32 mask, shift, intr; int tj_max, val, ret; + struct msr v; =20 if (temp =3D=3D THERMAL_TEMP_INVALID) temp =3D 0; @@ -141,8 +142,7 @@ sys_set_trip_temp(struct thermal_zone_device *tzd, if (trip_index >=3D MAX_NUMBER_OF_TRIPS || val < 0 || val > 0x7f) return -EINVAL; =20 - ret =3D rdmsr_on_cpu(zonedev->cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, - &l, &h); + ret =3D rdmsrq_on_cpu(zonedev->cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &v.= q); if (ret < 0) return ret; =20 @@ -155,20 +155,19 @@ sys_set_trip_temp(struct thermal_zone_device *tzd, shift =3D THERM_SHIFT_THRESHOLD0; intr =3D THERM_INT_THRESHOLD0_ENABLE; } - l &=3D ~mask; + v.l &=3D ~mask; /* * When users space sets a trip temperature =3D=3D 0, which is indication * that, it is no longer interested in receiving notifications. */ if (!temp) { - l &=3D ~intr; + v.l &=3D ~intr; } else { - l |=3D val << shift; - l |=3D intr; + v.l |=3D val << shift; + v.l |=3D intr; } =20 - return wrmsr_on_cpu(zonedev->cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, - l, h); + return wrmsr_on_cpu(zonedev->cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, v.l, = v.h); } =20 /* Thermal zone callback registry */ @@ -277,7 +276,8 @@ static int pkg_temp_thermal_trips_init(int cpu, int tj_= max, struct thermal_trip *trips, int num_trips) { unsigned long thres_reg_value; - u32 mask, shift, eax, edx; + u32 mask, shift; + struct msr val; int ret, i; =20 for (i =3D 0; i < num_trips; i++) { @@ -290,12 +290,11 @@ static int pkg_temp_thermal_trips_init(int cpu, int t= j_max, shift =3D THERM_SHIFT_THRESHOLD0; } =20 - ret =3D rdmsr_on_cpu(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, - &eax, &edx); + ret =3D rdmsrq_on_cpu(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &val.q); if (ret < 0) return ret; =20 - thres_reg_value =3D (eax & mask) >> shift; + thres_reg_value =3D (val.l & mask) >> shift; =20 trips[i].temperature =3D thres_reg_value ? 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Peter Anvin" Subject: [PATCH v2 04/10] x86/msr: Remove rdmsr_on_cpu() Date: Fri, 5 Jun 2026 16:43:08 +0200 Message-ID: <20260605144314.3031049-5-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260605144314.3031049-1-jgross@suse.com> References: <20260605144314.3031049-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Queue-Id: 96F206A868 X-Spam-Flag: NO X-Spam-Score: -4.00 X-Spam-Level: X-Rspamd-Action: no action X-Rspamd-Server: rspamd1.dmz-prg2.suse.org X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[] Content-Type: text/plain; charset="utf-8" With no user left, rdmsr_on_cpu() can be deleted. Signed-off-by: Juergen Gross Reviewed-by: Dave Hansen --- V2: - delete rdmsr_on_cpu() instead of rdmsrq_on_cpu() (Ingo Molnar) --- arch/x86/include/asm/msr.h | 6 ------ arch/x86/lib/msr-smp.c | 16 ---------------- 2 files changed, 22 deletions(-) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index d5985d6fdaf9..22f914f7affe 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -256,7 +256,6 @@ int msr_set_bit(u32 msr, u8 bit); int msr_clear_bit(u32 msr, u8 bit); =20 #ifdef CONFIG_SMP -int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); int rdmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); int wrmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 q); @@ -269,11 +268,6 @@ int wrmsrq_safe_on_cpu(unsigned int cpu, u32 msr_no, u= 64 q); int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); #else /* CONFIG_SMP */ -static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *= h) -{ - rdmsr(msr_no, *l, *h); - return 0; -} static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) { wrmsr(msr_no, l, h); diff --git a/arch/x86/lib/msr-smp.c b/arch/x86/lib/msr-smp.c index b8f63419e6ae..65658e8877e6 100644 --- a/arch/x86/lib/msr-smp.c +++ b/arch/x86/lib/msr-smp.c @@ -31,22 +31,6 @@ static void __wrmsr_on_cpu(void *info) wrmsr(rv->msr_no, reg->l, reg->h); } =20 -int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) -{ - int err; - struct msr_info rv; - - memset(&rv, 0, sizeof(rv)); - - rv.msr_no =3D msr_no; - err =3D smp_call_function_single(cpu, __rdmsr_on_cpu, &rv, 1); - *l =3D rv.reg.l; - *h =3D rv.reg.h; - - return err; -} -EXPORT_SYMBOL(rdmsr_on_cpu); - int rdmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) { int err; --=20 2.54.0 From nobody Mon Jun 8 05:26:07 2026 Received: from smtp-out2.suse.de (smtp-out2.suse.de [195.135.223.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3F103DC4DF for ; Fri, 5 Jun 2026 14:43:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.135.223.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780670635; cv=none; b=jfGQ1jFhmHWiUTc7caOb/Kwv1YX6x06Li6HmmuY2KeQiNtcmn8kZLEfkPj0VN6xo8JJT0m3l4O3CwrfOQ/hQpQ2iOlBn083lUYDFS2dZWcRuZw+Fy0rjW5CQ95hmjVyHpFBqPN6yi0gVEpnsQvdnUwyG4QLArhSeh2ZjLNom0i8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780670635; c=relaxed/simple; bh=d4vIem6l7fTXp/vMbKUi1yG/Tanij/jCUntbBgos64Y=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZMwM1NBG47Ducby35vEVRAUhwOzhOgbJHpxJRCE89lNh7kHY0yqNuC2rOm2ASEmJP48Ke/pfgRGouqfdleg4zQhS7LvJ33BcRhFso7ltoSPjH5Hb2/yWhoC8a6kJgUAcPRS288i9+RqwK+iXbuwImxsCWWLdao7NqQgu6zGVI44= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; arc=none smtp.client-ip=195.135.223.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Received: from imap1.dmz-prg2.suse.org (imap1.dmz-prg2.suse.org [IPv6:2a07:de40:b281:104:10:150:64:97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id 7476275992; Fri, 5 Jun 2026 14:43:46 +0000 (UTC) Authentication-Results: smtp-out2.suse.de; none Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id E26E8779A8; Fri, 5 Jun 2026 14:43:45 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id eFg7NqHgImqXXAAAD6G6ig (envelope-from ); Fri, 05 Jun 2026 14:43:45 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org, linux-perf-users@vger.kernel.org, linux-edac@vger.kernel.org, linux-pm@vger.kernel.org Cc: Juergen Gross , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Thomas Gleixner , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Tony Luck , "Rafael J. Wysocki" , Viresh Kumar , Daniel Lezcano , Zhang Rui , Lukasz Luba Subject: [PATCH v2 05/10] x86/msr: Switch wrmsr_on_cpu() users to wrmsrq_on_cpu() Date: Fri, 5 Jun 2026 16:43:09 +0200 Message-ID: <20260605144314.3031049-6-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260605144314.3031049-1-jgross@suse.com> References: <20260605144314.3031049-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Spam-Flag: NO X-Spam-Score: -4.00 X-Spam-Level: X-Rspamd-Server: rspamd2.dmz-prg2.suse.org X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[] X-Rspamd-Queue-Id: 7476275992 X-Rspamd-Action: no action Content-Type: text/plain; charset="utf-8" In order to prepare retiring wrmsr_on_cpu() switch wrmsr_on_cpu() users to wrmsrq_on_cpu(). Signed-off-by: Juergen Gross Reviewed-by: Dave Hansen --- V2: - instead of changing wrmsr_on_cpu(), use wrmsrq_on_cpu() (Ingo Molnar) --- arch/x86/events/intel/ds.c | 11 ++++------- arch/x86/include/asm/msr.h | 2 +- arch/x86/kernel/cpu/mce/inject.c | 2 +- drivers/cpufreq/p4-clockmod.c | 4 ++-- drivers/cpufreq/speedstep-centrino.c | 4 ++-- drivers/thermal/intel/x86_pkg_temp_thermal.c | 2 +- 6 files changed, 11 insertions(+), 14 deletions(-) diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index 7f0d515c07c5..5b9c01383f49 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -780,9 +780,7 @@ void init_debug_store_on_cpu(int cpu) if (!ds) return; =20 - wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, - (u32)((u64)(unsigned long)ds), - (u32)((u64)(unsigned long)ds >> 32)); + wrmsrq_on_cpu(cpu, MSR_IA32_DS_AREA, (u64)(unsigned long)ds); } =20 void fini_debug_store_on_cpu(int cpu) @@ -790,7 +788,7 @@ void fini_debug_store_on_cpu(int cpu) if (!per_cpu(cpu_hw_events, cpu).ds) return; =20 - wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0); + wrmsrq_on_cpu(cpu, MSR_IA32_DS_AREA, 0); } =20 static DEFINE_PER_CPU(void *, insn_buffer); @@ -1095,8 +1093,7 @@ void init_arch_pebs_on_cpu(int cpu) * contiguous physical buffer (__alloc_pages_node() with order) */ arch_pebs_base =3D virt_to_phys(cpuc->pebs_vaddr) | PEBS_BUFFER_SHIFT; - wrmsr_on_cpu(cpu, MSR_IA32_PEBS_BASE, (u32)arch_pebs_base, - (u32)(arch_pebs_base >> 32)); + wrmsrq_on_cpu(cpu, MSR_IA32_PEBS_BASE, arch_pebs_base); x86_pmu.pebs_active =3D 1; } =20 @@ -1105,7 +1102,7 @@ inline void fini_arch_pebs_on_cpu(int cpu) if (!x86_pmu.arch_pebs) return; =20 - wrmsr_on_cpu(cpu, MSR_IA32_PEBS_BASE, 0, 0); + wrmsrq_on_cpu(cpu, MSR_IA32_PEBS_BASE, 0); } =20 /* diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 22f914f7affe..6e0d7a6335ff 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -291,7 +291,7 @@ static inline void rdmsr_on_cpus(const struct cpumask *= m, u32 msr_no, static inline void wrmsr_on_cpus(const struct cpumask *m, u32 msr_no, struct msr __percpu *msrs) { - wrmsr_on_cpu(0, msr_no, raw_cpu_read(msrs->l), raw_cpu_read(msrs->h)); + wrmsrq_on_cpu(0, msr_no, raw_cpu_read(msrs->q)); } static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inj= ect.c index bee9c35762b8..6d30e7720f31 100644 --- a/arch/x86/kernel/cpu/mce/inject.c +++ b/arch/x86/kernel/cpu/mce/inject.c @@ -327,7 +327,7 @@ static int toggle_hw_mce_inject(unsigned int cpu, bool = enable) =20 enable ? (val.l |=3D BIT(18)) : (val.l &=3D ~BIT(18)); =20 - err =3D wrmsr_on_cpu(cpu, MSR_K7_HWCR, val.l, val.h); + err =3D wrmsrq_on_cpu(cpu, MSR_K7_HWCR, val.q); if (err) pr_err("%s: error writing HWCR\n", __func__); =20 diff --git a/drivers/cpufreq/p4-clockmod.c b/drivers/cpufreq/p4-clockmod.c index d96e8b665f39..c1690aa48193 100644 --- a/drivers/cpufreq/p4-clockmod.c +++ b/drivers/cpufreq/p4-clockmod.c @@ -68,7 +68,7 @@ static int cpufreq_p4_setdc(unsigned int cpu, unsigned in= t newstate) rdmsrq_on_cpu(cpu, MSR_IA32_THERM_CONTROL, &val.q); if (newstate =3D=3D DC_DISABLE) { pr_debug("CPU#%d disabling modulation\n", cpu); - wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, val.l & ~(1<<4), val.h); + wrmsrq_on_cpu(cpu, MSR_IA32_THERM_CONTROL, val.q & ~(1ULL << 4)); } else { pr_debug("CPU#%d setting duty cycle to %d%%\n", cpu, ((125 * newstate) / 10)); @@ -79,7 +79,7 @@ static int cpufreq_p4_setdc(unsigned int cpu, unsigned in= t newstate) */ val.l =3D (val.l & ~14); val.l =3D val.l | (1<<4) | ((newstate & 0x7)<<1); - wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, val.l, val.h); + wrmsrq_on_cpu(cpu, MSR_IA32_THERM_CONTROL, val.q); } =20 return 0; diff --git a/drivers/cpufreq/speedstep-centrino.c b/drivers/cpufreq/speedst= ep-centrino.c index cefee19d1100..9237ed8f2b1f 100644 --- a/drivers/cpufreq/speedstep-centrino.c +++ b/drivers/cpufreq/speedstep-centrino.c @@ -475,7 +475,7 @@ static int centrino_target(struct cpufreq_policy *polic= y, unsigned int index) oldmsr.l |=3D msr; } =20 - wrmsr_on_cpu(good_cpu, MSR_IA32_PERF_CTL, oldmsr.l, oldmsr.h); + wrmsrq_on_cpu(good_cpu, MSR_IA32_PERF_CTL, oldmsr.q); if (policy->shared_type =3D=3D CPUFREQ_SHARED_TYPE_ANY) break; =20 @@ -491,7 +491,7 @@ static int centrino_target(struct cpufreq_policy *polic= y, unsigned int index) */ =20 for_each_cpu(j, covered_cpus) - wrmsr_on_cpu(j, MSR_IA32_PERF_CTL, oldmsr.l, oldmsr.h); + wrmsrq_on_cpu(j, MSR_IA32_PERF_CTL, oldmsr.q); } retval =3D 0; =20 diff --git a/drivers/thermal/intel/x86_pkg_temp_thermal.c b/drivers/thermal= /intel/x86_pkg_temp_thermal.c index 2e7de8cf756d..144603c356a0 100644 --- a/drivers/thermal/intel/x86_pkg_temp_thermal.c +++ b/drivers/thermal/intel/x86_pkg_temp_thermal.c @@ -167,7 +167,7 @@ sys_set_trip_temp(struct thermal_zone_device *tzd, v.l |=3D intr; } =20 - return wrmsr_on_cpu(zonedev->cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, v.l, = v.h); + return wrmsrq_on_cpu(zonedev->cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, v.q); } =20 /* Thermal zone callback registry */ --=20 2.54.0 From nobody Mon Jun 8 05:26:07 2026 Received: from smtp-out1.suse.de (smtp-out1.suse.de [195.135.223.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CDDEC2222AA for ; Fri, 5 Jun 2026 14:43:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.135.223.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780670637; cv=none; b=Lp/mLSkg7MGkNlUuiG5CA+G0gps0Sl45NR+FADIyj23jFzDf6yTAqhoBp8Jyu0/XbBrDaeu2EmyzRnD2WqVsjlOmO/bfL5ndb0B4Realah/xWgADF1P1mDE31a/RZkOqKgN6K49JZjaAYyn188Fy0zkGJniO31wUSvOKjhE2oj4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780670637; c=relaxed/simple; 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Fri, 5 Jun 2026 14:43:52 +0000 (UTC) Authentication-Results: smtp-out1.suse.de; none Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id C53D7779A8; Fri, 5 Jun 2026 14:43:51 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id qfYUL6fgImqaXAAAD6G6ig (envelope-from ); Fri, 05 Jun 2026 14:43:51 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" Subject: [PATCH v2 06/10] x86/msr: Remove wrmsr_on_cpu() Date: Fri, 5 Jun 2026 16:43:10 +0200 Message-ID: <20260605144314.3031049-7-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260605144314.3031049-1-jgross@suse.com> References: <20260605144314.3031049-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Spam-Flag: NO X-Spam-Score: -4.00 X-Spam-Level: X-Rspamd-Server: rspamd2.dmz-prg2.suse.org X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[] X-Rspamd-Queue-Id: 04EE26B1D5 X-Rspamd-Action: no action Content-Type: text/plain; charset="utf-8" With no user left, wrmsr_on_cpu() can be deleted. Signed-off-by: Juergen Gross Reviewed-by: Dave Hansen --- V2: - delete wrmsr_on_cpu() instead of wrmsrq_on_cpu() (Ingo Molnar) --- arch/x86/include/asm/msr.h | 6 ------ arch/x86/lib/msr-smp.c | 16 ---------------- 2 files changed, 22 deletions(-) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 6e0d7a6335ff..0205643c1ece 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -256,7 +256,6 @@ int msr_set_bit(u32 msr, u8 bit); int msr_clear_bit(u32 msr, u8 bit); =20 #ifdef CONFIG_SMP -int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); int rdmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); int wrmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 q); void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr __pe= rcpu *msrs); @@ -268,11 +267,6 @@ int wrmsrq_safe_on_cpu(unsigned int cpu, u32 msr_no, u= 64 q); int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); #else /* CONFIG_SMP */ -static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) -{ - wrmsr(msr_no, l, h); - return 0; -} static inline int rdmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) { rdmsrq(msr_no, *q); diff --git a/arch/x86/lib/msr-smp.c b/arch/x86/lib/msr-smp.c index 65658e8877e6..a434c80408a0 100644 --- a/arch/x86/lib/msr-smp.c +++ b/arch/x86/lib/msr-smp.c @@ -46,22 +46,6 @@ int rdmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) } EXPORT_SYMBOL(rdmsrq_on_cpu); =20 -int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) -{ - int err; - struct msr_info rv; - - memset(&rv, 0, sizeof(rv)); - - rv.msr_no =3D msr_no; - rv.reg.l =3D l; - rv.reg.h =3D h; - err =3D smp_call_function_single(cpu, __wrmsr_on_cpu, &rv, 1); - - return err; -} -EXPORT_SYMBOL(wrmsr_on_cpu); - int wrmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 q) { int err; --=20 2.54.0 From nobody Mon Jun 8 05:26:07 2026 Received: from smtp-out2.suse.de (smtp-out2.suse.de [195.135.223.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6A413EC2F4 for ; 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Fri, 5 Jun 2026 14:43:57 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id 7XUzF63gImqiXAAAD6G6ig (envelope-from ); Fri, 05 Jun 2026 14:43:57 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org, linux-hwmon@vger.kernel.org, linux-pm@vger.kernel.org Cc: Juergen Gross , "H. Peter Anvin" , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , Guenter Roeck , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba Subject: [PATCH v2 07/10] x86/msr: Switch rdmsr_safe_on_cpu() users to rdmsrq_safe_on_cpu() Date: Fri, 5 Jun 2026 16:43:11 +0200 Message-ID: <20260605144314.3031049-8-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260605144314.3031049-1-jgross@suse.com> References: <20260605144314.3031049-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam-Flag: NO X-Spamd-Result: default: False [-6.80 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; FUZZY_RATELIMITED(0.00)[rspamd.com]; ARC_NA(0.00)[]; MIME_TRACE(0.00)[0:+]; RCPT_COUNT_TWELVE(0.00)[15]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; TO_MATCH_ENVRCPT_ALL(0.00)[]; FROM_HAS_DN(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; R_RATELIMIT(0.00)[to_ip_from(RLfdszjqhz8kzzb9uwpzdm8png)]; TO_DN_SOME(0.00)[]; RCVD_TLS_ALL(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.com:email,suse.com:mid,imap1.dmz-prg2.suse.org:helo,intel.com:url] X-Spam-Level: X-Spam-Score: -6.80 Content-Type: text/plain; charset="utf-8" In order to prepare retiring rdmsr_safe_on_cpu() switch rdmsr_safe_on_cpu() users to rdmsrq_safe_on_cpu(). Signed-off-by: Juergen Gross Reviewed-by: Dave Hansen --- V2: - instead of changing rdmsr_safe_on_cpu(), use rdmsrq_safe_on_cpu() (Ingo Molnar) --- arch/x86/kernel/msr.c | 4 +-- arch/x86/lib/msr-smp.c | 17 +++++++++--- drivers/hwmon/coretemp.c | 32 +++++++++++------------ drivers/hwmon/via-cputemp.c | 16 ++++++------ drivers/thermal/intel/intel_tcc.c | 43 ++++++++++++++++--------------- 5 files changed, 62 insertions(+), 50 deletions(-) diff --git a/arch/x86/kernel/msr.c b/arch/x86/kernel/msr.c index 4469c784eaa0..60334317f30b 100644 --- a/arch/x86/kernel/msr.c +++ b/arch/x86/kernel/msr.c @@ -53,7 +53,7 @@ static ssize_t msr_read(struct file *file, char __user *b= uf, size_t count, loff_t *ppos) { u32 __user *tmp =3D (u32 __user *) buf; - u32 data[2]; + u64 data; u32 reg =3D *ppos; int cpu =3D iminor(file_inode(file)); int err =3D 0; @@ -63,7 +63,7 @@ static ssize_t msr_read(struct file *file, char __user *b= uf, return -EINVAL; /* Invalid chunk size */ =20 for (; count; count -=3D 8) { - err =3D rdmsr_safe_on_cpu(cpu, reg, &data[0], &data[1]); + err =3D rdmsrq_safe_on_cpu(cpu, reg, &data); if (err) break; if (copy_to_user(tmp, &data, 8)) { diff --git a/arch/x86/lib/msr-smp.c b/arch/x86/lib/msr-smp.c index a434c80408a0..f3c75b681603 100644 --- a/arch/x86/lib/msr-smp.c +++ b/arch/x86/lib/msr-smp.c @@ -190,11 +190,22 @@ EXPORT_SYMBOL(wrmsrq_safe_on_cpu); =20 int rdmsrq_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) { - u32 low, high; + struct msr_info_completion rv; + call_single_data_t csd; int err; =20 - err =3D rdmsr_safe_on_cpu(cpu, msr_no, &low, &high); - *q =3D (u64)high << 32 | low; + INIT_CSD(&csd, __rdmsr_safe_on_cpu, &rv); + + memset(&rv, 0, sizeof(rv)); + init_completion(&rv.done); + rv.msr.msr_no =3D msr_no; + + err =3D smp_call_function_single_async(cpu, &csd); + if (!err) { + wait_for_completion(&rv.done); + err =3D rv.msr.err; + } + *q =3D rv.msr.reg.q; =20 return err; } diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c index 1259c78c95c6..70711a7cca12 100644 --- a/drivers/hwmon/coretemp.c +++ b/drivers/hwmon/coretemp.c @@ -169,7 +169,7 @@ static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id, = struct device *dev) int tjmax_ee =3D 85000; int usemsr_ee =3D 1; int err; - u32 eax, edx; + u64 val; int i; u16 devfn =3D PCI_DEVFN(0, 0); struct pci_dev *host_bridge =3D pci_get_domain_bus_and_slot(0, 0, devfn); @@ -220,14 +220,14 @@ static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id= , struct device *dev) * http://softwarecommunity.intel.com/Wiki/Mobility/720.htm * For Core2 cores, check MSR 0x17, bit 28 1 =3D Mobile CPU */ - err =3D rdmsr_safe_on_cpu(id, 0x17, &eax, &edx); + err =3D rdmsrq_safe_on_cpu(id, 0x17, &val); if (err) { dev_warn(dev, "Unable to access MSR 0x17, assuming desktop" " CPU\n"); usemsr_ee =3D 0; } else if (c->x86_vfm < INTEL_CORE2_PENRYN && - !(eax & 0x10000000)) { + !(val & 0x10000000)) { /* * Trust bit 28 up to Penryn, I could not find any * documentation on that; if you happen to know @@ -235,8 +235,8 @@ static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id, = struct device *dev) */ usemsr_ee =3D 0; } else { - /* Platform ID bits 52:50 (EDX starts at bit 32) */ - platform_id =3D (edx >> 18) & 0x7; + /* Platform ID bits 52:50 */ + platform_id =3D (val >> 50) & 0x7; =20 /* * Mobile Penryn CPU seems to be platform ID 7 or 5 @@ -255,12 +255,12 @@ static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id= , struct device *dev) } =20 if (usemsr_ee) { - err =3D rdmsr_safe_on_cpu(id, 0xee, &eax, &edx); + err =3D rdmsrq_safe_on_cpu(id, 0xee, &val); if (err) { dev_warn(dev, "Unable to access MSR 0xEE, for Tjmax, left" " at default\n"); - } else if (eax & 0x40000000) { + } else if (val & 0x40000000) { tjmax =3D tjmax_ee; } } else if (tjmax =3D=3D 100000) { @@ -278,7 +278,7 @@ static int get_tjmax(struct temp_data *tdata, struct de= vice *dev) { struct cpuinfo_x86 *c =3D &cpu_data(tdata->cpu); int err; - u32 eax, edx; + u64 msrval; u32 val; =20 /* use static tjmax once it is set */ @@ -289,11 +289,11 @@ static int get_tjmax(struct temp_data *tdata, struct = device *dev) * A new feature of current Intel(R) processors, the * IA32_TEMPERATURE_TARGET contains the TjMax value */ - err =3D rdmsr_safe_on_cpu(tdata->cpu, MSR_IA32_TEMPERATURE_TARGET, &eax, = &edx); + err =3D rdmsrq_safe_on_cpu(tdata->cpu, MSR_IA32_TEMPERATURE_TARGET, &msrv= al); if (err) { dev_warn_once(dev, "Unable to read TjMax from CPU %u\n", tdata->cpu); } else { - val =3D (eax >> 16) & 0xff; + val =3D (msrval >> 16) & 0xff; if (val) return val * 1000; } @@ -314,7 +314,7 @@ static int get_tjmax(struct temp_data *tdata, struct de= vice *dev) =20 static int get_ttarget(struct temp_data *tdata, struct device *dev) { - u32 eax, edx; + u64 val; int tjmax, ttarget_offset, ret; =20 /* @@ -324,14 +324,14 @@ static int get_ttarget(struct temp_data *tdata, struc= t device *dev) if (tdata->tjmax) return -ENODEV; =20 - ret =3D rdmsr_safe_on_cpu(tdata->cpu, MSR_IA32_TEMPERATURE_TARGET, &eax, = &edx); + ret =3D rdmsrq_safe_on_cpu(tdata->cpu, MSR_IA32_TEMPERATURE_TARGET, &val); if (ret) return ret; =20 - tjmax =3D (eax >> 16) & 0xff; + tjmax =3D (val >> 16) & 0xff; =20 /* Read the still undocumented bits 8:15 of IA32_TEMPERATURE_TARGET. */ - ttarget_offset =3D (eax >> 8) & 0xff; + ttarget_offset =3D (val >> 8) & 0xff; =20 return (tjmax - ttarget_offset) * 1000; } @@ -560,7 +560,7 @@ static int create_core_data(struct platform_device *pde= v, unsigned int cpu, struct temp_data *tdata; struct platform_data *pdata =3D platform_get_drvdata(pdev); struct cpuinfo_x86 *c =3D &cpu_data(cpu); - u32 eax, edx; + u64 val; int err; =20 if (!housekeeping_cpu(cpu, HK_TYPE_MISC)) @@ -571,7 +571,7 @@ static int create_core_data(struct platform_device *pde= v, unsigned int cpu, return -ENOMEM; =20 /* Test if we can access the status register */ - err =3D rdmsr_safe_on_cpu(cpu, tdata->status_reg, &eax, &edx); + err =3D rdmsrq_safe_on_cpu(cpu, tdata->status_reg, &val); if (err) goto err; =20 diff --git a/drivers/hwmon/via-cputemp.c b/drivers/hwmon/via-cputemp.c index a5c03ed59c1f..ec421201049d 100644 --- a/drivers/hwmon/via-cputemp.c +++ b/drivers/hwmon/via-cputemp.c @@ -65,28 +65,28 @@ static ssize_t temp_show(struct device *dev, struct dev= ice_attribute *devattr, char *buf) { struct via_cputemp_data *data =3D dev_get_drvdata(dev); - u32 eax, edx; + u64 val; int err; =20 - err =3D rdmsr_safe_on_cpu(data->id, data->msr_temp, &eax, &edx); + err =3D rdmsrq_safe_on_cpu(data->id, data->msr_temp, &val); if (err) return -EAGAIN; =20 - return sprintf(buf, "%lu\n", ((unsigned long)eax & 0xffffff) * 1000); + return sprintf(buf, "%lu\n", ((unsigned long)val & 0xffffff) * 1000); } =20 static ssize_t cpu0_vid_show(struct device *dev, struct device_attribute *devattr, char *buf) { struct via_cputemp_data *data =3D dev_get_drvdata(dev); - u32 eax, edx; + u64 val; int err; =20 - err =3D rdmsr_safe_on_cpu(data->id, data->msr_vid, &eax, &edx); + err =3D rdmsrq_safe_on_cpu(data->id, data->msr_vid, &val); if (err) return -EAGAIN; =20 - return sprintf(buf, "%d\n", vid_from_reg(~edx & 0x7f, data->vrm)); + return sprintf(buf, "%d\n", vid_from_reg(~(val >> 32) & 0x7f, data->vrm)); } =20 static SENSOR_DEVICE_ATTR_RO(temp1_input, temp, SHOW_TEMP); @@ -112,7 +112,7 @@ static int via_cputemp_probe(struct platform_device *pd= ev) struct via_cputemp_data *data; struct cpuinfo_x86 *c =3D &cpu_data(pdev->id); int err; - u32 eax, edx; + u64 val; =20 data =3D devm_kzalloc(&pdev->dev, sizeof(struct via_cputemp_data), GFP_KERNEL); @@ -143,7 +143,7 @@ static int via_cputemp_probe(struct platform_device *pd= ev) } =20 /* test if we can access the TEMPERATURE MSR */ - err =3D rdmsr_safe_on_cpu(data->id, data->msr_temp, &eax, &edx); + err =3D rdmsrq_safe_on_cpu(data->id, data->msr_temp, &val); if (err) { dev_err(&pdev->dev, "Unable to access TEMPERATURE MSR, giving up\n"); diff --git a/drivers/thermal/intel/intel_tcc.c b/drivers/thermal/intel/inte= l_tcc.c index ab61fb122937..c6772a5e073a 100644 --- a/drivers/thermal/intel/intel_tcc.c +++ b/drivers/thermal/intel/intel_tcc.c @@ -181,17 +181,17 @@ static u32 get_temp_mask(bool pkg) */ int intel_tcc_get_tjmax(int cpu) { - u32 low, high; + struct msr msrval; int val, err; =20 if (cpu < 0) - err =3D rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &low, &high); + err =3D rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &msrval.l, &msrval.h); else - err =3D rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &low, &high); + err =3D rdmsrq_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &msrval.q); if (err) return err; =20 - val =3D (low >> 16) & 0xff; + val =3D (msrval.l >> 16) & 0xff; =20 return val ? val : -ENODATA; } @@ -208,17 +208,17 @@ EXPORT_SYMBOL_NS_GPL(intel_tcc_get_tjmax, "INTEL_TCC"= ); */ int intel_tcc_get_offset(int cpu) { - u32 low, high; + struct msr val; int err; =20 if (cpu < 0) - err =3D rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &low, &high); + err =3D rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &val.l, &val.h); else - err =3D rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &low, &high); + err =3D rdmsrq_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &val.q); if (err) return err; =20 - return (low >> 24) & intel_tcc_temp_masks.tcc_offset; + return (val.l >> 24) & intel_tcc_temp_masks.tcc_offset; } EXPORT_SYMBOL_NS_GPL(intel_tcc_get_offset, "INTEL_TCC"); =20 @@ -235,7 +235,7 @@ EXPORT_SYMBOL_NS_GPL(intel_tcc_get_offset, "INTEL_TCC"); =20 int intel_tcc_set_offset(int cpu, int offset) { - u32 low, high; + struct msr val; int err; =20 if (!intel_tcc_temp_masks.tcc_offset) @@ -245,23 +245,23 @@ int intel_tcc_set_offset(int cpu, int offset) return -EINVAL; =20 if (cpu < 0) - err =3D rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &low, &high); + err =3D rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &val.l, &val.h); else - err =3D rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &low, &high); + err =3D rdmsrq_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &val.q); if (err) return err; =20 /* MSR Locked */ - if (low & BIT(31)) + if (val.l & BIT(31)) return -EPERM; =20 - low &=3D ~(intel_tcc_temp_masks.tcc_offset << 24); - low |=3D offset << 24; + val.l &=3D ~(intel_tcc_temp_masks.tcc_offset << 24); + val.l |=3D offset << 24; =20 if (cpu < 0) - return wrmsr_safe(MSR_IA32_TEMPERATURE_TARGET, low, high); + return wrmsr_safe(MSR_IA32_TEMPERATURE_TARGET, val.l, val.h); else - return wrmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, low, high); + return wrmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, val.l, val.h); } EXPORT_SYMBOL_NS_GPL(intel_tcc_set_offset, "INTEL_TCC"); =20 @@ -279,7 +279,8 @@ EXPORT_SYMBOL_NS_GPL(intel_tcc_set_offset, "INTEL_TCC"); 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Peter Anvin" Subject: [PATCH v2 08/10] x86/msr: Remove rdmsr_safe_on_cpu() Date: Fri, 5 Jun 2026 16:43:12 +0200 Message-ID: <20260605144314.3031049-9-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260605144314.3031049-1-jgross@suse.com> References: <20260605144314.3031049-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam-Flag: NO X-Spam-Score: -6.80 X-Spamd-Result: default: False [-6.80 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; MIME_TRACE(0.00)[0:+]; FUZZY_RATELIMITED(0.00)[rspamd.com]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; TO_DN_SOME(0.00)[]; RCPT_COUNT_SEVEN(0.00)[8]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; FROM_EQ_ENVFROM(0.00)[]; FROM_HAS_DN(0.00)[]; R_RATELIMIT(0.00)[to_ip_from(RLfdszjqhz8kzzb9uwpzdm8png)]; DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:helo,suse.com:email,suse.com:mid]; RCVD_COUNT_TWO(0.00)[2]; TO_MATCH_ENVRCPT_ALL(0.00)[]; RCVD_TLS_ALL(0.00)[] X-Spam-Level: Content-Type: text/plain; charset="utf-8" With no user left, rdmsr_safe_on_cpu() can be deleted. Signed-off-by: Juergen Gross Reviewed-by: Dave Hansen --- V2: - delete rdmsr_safe_on_cpu() instead of rdmsrq_safe_on_cpu() (Ingo Molnar) --- arch/x86/include/asm/msr.h | 6 ------ arch/x86/lib/msr-smp.c | 24 ------------------------ 2 files changed, 30 deletions(-) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 0205643c1ece..b0bf1a761a40 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -260,7 +260,6 @@ int rdmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); int wrmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 q); void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr __pe= rcpu *msrs); void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr __pe= rcpu *msrs); -int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); int rdmsrq_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); int wrmsrq_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q); @@ -287,11 +286,6 @@ static inline void wrmsr_on_cpus(const struct cpumask = *m, u32 msr_no, { wrmsrq_on_cpu(0, msr_no, raw_cpu_read(msrs->q)); } -static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, - u32 *l, u32 *h) -{ - return rdmsr_safe(msr_no, l, h); -} static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u= 32 h) { return wrmsr_safe(msr_no, l, h); diff --git a/arch/x86/lib/msr-smp.c b/arch/x86/lib/msr-smp.c index f3c75b681603..f58e0bab0be0 100644 --- a/arch/x86/lib/msr-smp.c +++ b/arch/x86/lib/msr-smp.c @@ -132,30 +132,6 @@ static void __wrmsr_safe_on_cpu(void *info) rv->err =3D wrmsr_safe(rv->msr_no, rv->reg.l, rv->reg.h); } =20 -int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) -{ - struct msr_info_completion rv; - call_single_data_t csd; - int err; - - INIT_CSD(&csd, __rdmsr_safe_on_cpu, &rv); - - memset(&rv, 0, sizeof(rv)); - init_completion(&rv.done); - rv.msr.msr_no =3D msr_no; - - err =3D smp_call_function_single_async(cpu, &csd); - if (!err) { - wait_for_completion(&rv.done); - err =3D rv.msr.err; - } - *l =3D rv.msr.reg.l; - *h =3D rv.msr.reg.h; - - return err; -} -EXPORT_SYMBOL(rdmsr_safe_on_cpu); - int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) { int err; --=20 2.54.0 From nobody Mon Jun 8 05:26:07 2026 Received: from smtp-out1.suse.de (smtp-out1.suse.de [195.135.223.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3F8E3F23B3 for ; Fri, 5 Jun 2026 14:44:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.135.223.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780670657; cv=none; b=pFqsPCmi+1PoO+XUnCNGRL0RAl29BUHc0scQC3CuWdqQ0Roq1cvTswrf4Q4v4Uqnd29uVTn8Ktvrc+x8YEKYZ9ZzcyXh4PgUWMuFCmHs09YyNJ3G1HPecHxa0EMAPDdLzs8Nx9lXCT0+jFt6mR/f/Nwj4ktomZ4j3TVXIH4YKb8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780670657; c=relaxed/simple; bh=zoSxGzUQzMWz79F1rbRGs8AzOD+cnP/TCIMQzgBNKrM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=pC9OkIyLxw2Cgg5U8/XTdShtwAiDxEzVsctJfFvRAepFVa9rKDY9YwT6/gHM7YFDb8dK0y3crLJZYwnN/M63Bv/v3fSuUoifF9SQGf6ZkC7l+dBxfoJq0nktsY5d9KSgNgNjJHknjHfgVlLgiQbQ6kWypqMjsXcfsxNcX/7KX7A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; arc=none smtp.client-ip=195.135.223.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Received: from imap1.dmz-prg2.suse.org (imap1.dmz-prg2.suse.org [IPv6:2a07:de40:b281:104:10:150:64:97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id 03C346A868; Fri, 5 Jun 2026 14:44:09 +0000 (UTC) Authentication-Results: smtp-out1.suse.de; none Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id A89D0779A8; Fri, 5 Jun 2026 14:44:08 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id zGAPKLjgImqvXAAAD6G6ig (envelope-from ); Fri, 05 Jun 2026 14:44:08 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org, linux-pm@vger.kernel.org Cc: Juergen Gross , "H. Peter Anvin" , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba Subject: [PATCH v2 09/10] x86/msr: Switch wrmsr_safe_on_cpu() users to wrmsrq_safe_on_cpu() Date: Fri, 5 Jun 2026 16:43:13 +0200 Message-ID: <20260605144314.3031049-10-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260605144314.3031049-1-jgross@suse.com> References: <20260605144314.3031049-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Queue-Id: 03C346A868 X-Spam-Flag: NO X-Spam-Score: -4.00 X-Spam-Level: X-Rspamd-Action: no action X-Rspamd-Server: rspamd1.dmz-prg2.suse.org X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[] Content-Type: text/plain; charset="utf-8" In order to prepare retiring wrmsr_safe_on_cpu() switch wrmsr_safe_on_cpu() users to wrmsrq_safe_on_cpu(). Signed-off-by: Juergen Gross Reviewed-by: Dave Hansen --- V2: - instead of changing wrmsr_safe_on_cpu(), use wrmsrq_safe_on_cpu() (Ingo Molnar) --- arch/x86/kernel/msr.c | 4 ++-- drivers/thermal/intel/intel_tcc.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/msr.c b/arch/x86/kernel/msr.c index 60334317f30b..34bdb752f892 100644 --- a/arch/x86/kernel/msr.c +++ b/arch/x86/kernel/msr.c @@ -109,7 +109,7 @@ static ssize_t msr_write(struct file *file, const char = __user *buf, size_t count, loff_t *ppos) { const u32 __user *tmp =3D (const u32 __user *)buf; - u32 data[2]; + u64 data; u32 reg =3D *ppos; int cpu =3D iminor(file_inode(file)); int err =3D 0; @@ -134,7 +134,7 @@ static ssize_t msr_write(struct file *file, const char = __user *buf, =20 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); =20 - err =3D wrmsr_safe_on_cpu(cpu, reg, data[0], data[1]); + err =3D wrmsrq_safe_on_cpu(cpu, reg, data); if (err) break; =20 diff --git a/drivers/thermal/intel/intel_tcc.c b/drivers/thermal/intel/inte= l_tcc.c index c6772a5e073a..59f70bb5ffa5 100644 --- a/drivers/thermal/intel/intel_tcc.c +++ b/drivers/thermal/intel/intel_tcc.c @@ -261,7 +261,7 @@ int intel_tcc_set_offset(int cpu, int offset) if (cpu < 0) return wrmsr_safe(MSR_IA32_TEMPERATURE_TARGET, val.l, val.h); else - return wrmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, val.l, val.h); + return wrmsrq_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, val.q); } EXPORT_SYMBOL_NS_GPL(intel_tcc_set_offset, "INTEL_TCC"); =20 --=20 2.54.0 From nobody Mon Jun 8 05:26:07 2026 Received: from smtp-out1.suse.de (smtp-out1.suse.de [195.135.223.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1136E3F4846 for ; Fri, 5 Jun 2026 14:44:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.135.223.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780670670; cv=none; b=Xa+JVqGxuQgDPiSYThrFKAFSYCGSipJ7WuuXjvZ3HZK915P3L/kkHt5fj5BboJj5Fbo7LCPd1XsIFKHAtltGkcGDUjq/0BjHPBsGi5GC90hW7MICZojLjAYK5pcZqTC02LIBfwZ/r88BDN3kPkOU7u7frXnE/dTZvC8giorQy3g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780670670; c=relaxed/simple; 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Fri, 5 Jun 2026 14:44:14 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id I287Er7gImq0XAAAD6G6ig (envelope-from ); Fri, 05 Jun 2026 14:44:14 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" Subject: [PATCH v2 10/10] x86/msr: Remove wrmsr_safe_on_cpu() Date: Fri, 5 Jun 2026 16:43:14 +0200 Message-ID: <20260605144314.3031049-11-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260605144314.3031049-1-jgross@suse.com> References: <20260605144314.3031049-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam-Flag: NO X-Spamd-Result: default: False [-6.80 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; MIME_TRACE(0.00)[0:+]; FUZZY_RATELIMITED(0.00)[rspamd.com]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; TO_DN_SOME(0.00)[]; RCPT_COUNT_SEVEN(0.00)[8]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; FROM_EQ_ENVFROM(0.00)[]; FROM_HAS_DN(0.00)[]; R_RATELIMIT(0.00)[to_ip_from(RLfdszjqhz8kzzb9uwpzdm8png)]; DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:helo,suse.com:email,suse.com:mid]; RCVD_COUNT_TWO(0.00)[2]; TO_MATCH_ENVRCPT_ALL(0.00)[]; RCVD_TLS_ALL(0.00)[] X-Spam-Level: X-Spam-Score: -6.80 Content-Type: text/plain; charset="utf-8" With no user left, wrmsr_safe_on_cpu() can be deleted. Signed-off-by: Juergen Gross Reviewed-by: Dave Hansen --- V2: - delete wrmsr_safe_on_cpu() instead of wrmsrq_safe_on_cpu() (Ingo Molnar) --- arch/x86/include/asm/msr.h | 5 ----- arch/x86/lib/msr-smp.c | 16 ---------------- 2 files changed, 21 deletions(-) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index b0bf1a761a40..77dc7473d560 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -260,7 +260,6 @@ int rdmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); int wrmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 q); void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr __pe= rcpu *msrs); void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr __pe= rcpu *msrs); -int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); int rdmsrq_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); int wrmsrq_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q); int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); @@ -286,10 +285,6 @@ static inline void wrmsr_on_cpus(const struct cpumask = *m, u32 msr_no, { wrmsrq_on_cpu(0, msr_no, raw_cpu_read(msrs->q)); } -static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u= 32 h) -{ - return wrmsr_safe(msr_no, l, h); -} static inline int rdmsrq_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) { return rdmsrq_safe(msr_no, q); diff --git a/arch/x86/lib/msr-smp.c b/arch/x86/lib/msr-smp.c index f58e0bab0be0..0c6627773c80 100644 --- a/arch/x86/lib/msr-smp.c +++ b/arch/x86/lib/msr-smp.c @@ -132,22 +132,6 @@ static void __wrmsr_safe_on_cpu(void *info) rv->err =3D wrmsr_safe(rv->msr_no, rv->reg.l, rv->reg.h); } =20 -int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) -{ - int err; - struct msr_info rv; - - memset(&rv, 0, sizeof(rv)); - - rv.msr_no =3D msr_no; - rv.reg.l =3D l; - rv.reg.h =3D h; - err =3D smp_call_function_single(cpu, __wrmsr_safe_on_cpu, &rv, 1); - - return err ? err : rv.err; -} -EXPORT_SYMBOL(wrmsr_safe_on_cpu); - int wrmsrq_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q) { int err; --=20 2.54.0