From nobody Mon Jun 8 06:39:45 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC6654183BE; Fri, 5 Jun 2026 10:39:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780655973; cv=none; b=Bu1+1Ckw0+1K4Q90TjSv8WtGcQ3hMo7W/tgbphb16IGeFOryg1UzT1q/vIm7WuEHv5uSv47TiOwj8zzQ+uocEAayZrkQoyYyUd1QWEvmxzlZgmCII38IzzUs5KuHCUvYBzsDAUI8L3i6GmANbGEhjsCk4OsarJ7NoI+Yq6Zhls8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780655973; c=relaxed/simple; bh=FZyM4aI9IrXDDh/pxjTDWFt3k7Ku6S6cDnnXUo/Wo8I=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=gZNE4GCEykhEiVWPkAbuw1LCky30j+27avAYco4qHHFPlmvMUp0sqDPFwxad6a5e2hFT4sw1shpEcaWDwCYqnUtXGqVQdsNpzXHeFAZT1COErm/lFlRazGZcvCaKEEvHxsTrDjNHydSnSjamvorRkhtO8j3ZYHlcb3bvSMIg7is= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realsil.com.cn; spf=pass smtp.mailfrom=realsil.com.cn; dkim=pass (2048-bit key) header.d=realsil.com.cn header.i=@realsil.com.cn header.b=R8IWegpw; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realsil.com.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realsil.com.cn Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=realsil.com.cn header.i=@realsil.com.cn header.b="R8IWegpw" X-SpamFilter-By: ArmorX SpamTrap 5.80 with qID 655Ad8eE51324199, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=realsil.com.cn; s=dkim; t=1780655949; bh=kWcscj3TyaEVM4WJqLJLBNigkRUiU9RLRSvpWg1yyIE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=R8IWegpwMcUWb9ckGkxWq2YDmaz4P7TFQ2N9hgt8xGxIwZF0kk45CeMfjHGvgf8QI CteduwanFtn4yF3k3NreEqY5EGW7OFnIoyAP1DA6LwiB5gcfb1SCtTAjiEbyD3X/6q /7Pq5YvbXRiJwPeC/khniAIk5ZvAglYVt6oPt4AdII3mMZrKF4LH225jhgwniE0SZ/ wsklucUr0Yb5pd+056cTWbdfuJdA/AoVda/CaaUDNzFUKgbbH9HNtwt3Y7r2/iPU7s ddSjN3v/pK/6OCGSgWojSzWM3ELs7uAHEyI5hGw1k4u8lGDSlQTHSWMWsqqRLAwSSh 0WzO33TmKXk9Q== Received: from RS-EX-MBS4.realsil.com.cn ([172.29.17.104]) by rtits2.realtek.com.tw (8.15.2/3.28/5.94) with ESMTPS id 655Ad8eE51324199 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 5 Jun 2026 18:39:08 +0800 Received: from RS-EX-MBS1.realsil.com.cn (172.29.17.101) by RS-EX-MBS4.realsil.com.cn (172.29.17.104) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Fri, 5 Jun 2026 18:39:08 +0800 Received: from 172.29.37.154 (172.29.37.152) by RS-EX-MBS1.realsil.com.cn (172.29.17.101) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Fri, 5 Jun 2026 18:39:08 +0800 From: javen To: , , , , , , , CC: , , Javen Xu Subject: [PATCH net-next v1 1/6] r8169: add current_speed in private struct Date: Fri, 5 Jun 2026 18:39:00 +0800 Message-ID: <20260605103906.1445-2-javen_xu@realsil.com.cn> X-Mailer: git-send-email 2.50.1.windows.1 In-Reply-To: <20260605103906.1445-1-javen_xu@realsil.com.cn> References: <20260605103906.1445-1-javen_xu@realsil.com.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Javen Xu This patch adds current_speed in private strcut in order to decouple from phydev in the following patch supporting for phylink. Signed-off-by: Javen Xu --- drivers/net/ethernet/realtek/r8169_main.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethern= et/realtek/r8169_main.c index ec4fc21fa21f..fdc8c84dd112 100644 --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c @@ -750,6 +750,7 @@ struct rtl8169_private { u32 irq_mask; int irq; struct clk *clk; + int current_speed; =20 struct { DECLARE_BITMAP(flags, RTL_FLAG_MAX); @@ -1673,16 +1674,14 @@ static void rtl8169_irq_mask_and_ack(struct rtl8169= _private *tp) rtl_pci_commit(tp); } =20 -static void rtl_link_chg_patch(struct rtl8169_private *tp) +static void rtl_link_chg_patch(struct rtl8169_private *tp, int speed) { - struct phy_device *phydev =3D tp->phydev; - if (tp->mac_version =3D=3D RTL_GIGA_MAC_VER_34 || tp->mac_version =3D=3D RTL_GIGA_MAC_VER_38) { - if (phydev->speed =3D=3D SPEED_1000) { + if (speed =3D=3D SPEED_1000) { rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); - } else if (phydev->speed =3D=3D SPEED_100) { + } else if (speed =3D=3D SPEED_100) { rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); } else { @@ -1692,7 +1691,7 @@ static void rtl_link_chg_patch(struct rtl8169_private= *tp) rtl_reset_packet_filter(tp); } else if (tp->mac_version =3D=3D RTL_GIGA_MAC_VER_35 || tp->mac_version =3D=3D RTL_GIGA_MAC_VER_36) { - if (phydev->speed =3D=3D SPEED_1000) { + if (speed =3D=3D SPEED_1000) { rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); } else { @@ -1700,7 +1699,7 @@ static void rtl_link_chg_patch(struct rtl8169_private= *tp) rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); } } else if (tp->mac_version =3D=3D RTL_GIGA_MAC_VER_37) { - if (phydev->speed =3D=3D SPEED_10) { + if (speed =3D=3D SPEED_10) { rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); } else { @@ -2074,11 +2073,11 @@ rtl_coalesce_info(struct rtl8169_private *tp) ci =3D rtl_coalesce_info_8168_8136; =20 /* if speed is unknown assume highest one */ - if (tp->phydev->speed =3D=3D SPEED_UNKNOWN) + if (tp->current_speed =3D=3D SPEED_UNKNOWN) return ci; =20 for (; ci->speed; ci++) { - if (tp->phydev->speed =3D=3D ci->speed) + if (tp->current_speed =3D=3D ci->speed) return ci; } =20 @@ -2236,7 +2235,7 @@ static void rtl_set_eee_txidle_timer(struct rtl8169_p= rivate *tp) =20 static unsigned int r8169_get_tx_lpi_timer_us(struct rtl8169_private *tp) { - unsigned int speed =3D tp->phydev->speed; + unsigned int speed =3D tp->current_speed; unsigned int timer =3D tp->tx_lpi_timer; =20 if (!timer || speed =3D=3D SPEED_UNKNOWN) @@ -4968,8 +4967,9 @@ static void r8169_phylink_handler(struct net_device *= ndev) struct rtl8169_private *tp =3D netdev_priv(ndev); struct device *d =3D tp_to_dev(tp); =20 + tp->current_speed =3D tp->phydev->speed; if (netif_carrier_ok(ndev)) { - rtl_link_chg_patch(tp); + rtl_link_chg_patch(tp, tp->current_speed); rtl_enable_tx_lpi(tp, tp->phydev->enable_tx_lpi); pm_request_resume(d); } else { @@ -5667,6 +5667,7 @@ static int rtl_init_one(struct pci_dev *pdev, const s= truct pci_device_id *ent) ext_xid_str, xid); tp->mac_version =3D chip->mac_version; tp->fw_name =3D chip->fw_name; + tp->current_speed =3D SPEED_UNKNOWN; =20 /* Disable ASPM L1 as that cause random device stop working * problems as well as full system hangs for some PCIe devices users. --=20 2.43.0 From nobody Mon Jun 8 06:39:45 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC7674183CC; Fri, 5 Jun 2026 10:39:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780655972; cv=none; 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Fri, 5 Jun 2026 18:39:09 +0800 Received: from RS-EX-MBS1.realsil.com.cn (172.29.17.101) by RS-EX-MBS4.realsil.com.cn (172.29.17.104) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Fri, 5 Jun 2026 18:39:09 +0800 Received: from 172.29.37.154 (172.29.37.152) by RS-EX-MBS1.realsil.com.cn (172.29.17.101) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Fri, 5 Jun 2026 18:39:09 +0800 From: javen To: , , , , , , , CC: , , Javen Xu Subject: [PATCH net-next v1 2/6] r8169: add support for phylink Date: Fri, 5 Jun 2026 18:39:01 +0800 Message-ID: <20260605103906.1445-3-javen_xu@realsil.com.cn> X-Mailer: git-send-email 2.50.1.windows.1 In-Reply-To: <20260605103906.1445-1-javen_xu@realsil.com.cn> References: <20260605103906.1445-1-javen_xu@realsil.com.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Javen Xu Transfer old framework to phylink. Phylink can support fiber mode card which can not get link status or link speed from standard phy registers. Signed-off-by: Javen Xu --- drivers/net/ethernet/realtek/Kconfig | 1 + drivers/net/ethernet/realtek/r8169_main.c | 170 ++++++++++++++++------ 2 files changed, 123 insertions(+), 48 deletions(-) diff --git a/drivers/net/ethernet/realtek/Kconfig b/drivers/net/ethernet/re= altek/Kconfig index 9b0f4f9631db..49ac72734225 100644 --- a/drivers/net/ethernet/realtek/Kconfig +++ b/drivers/net/ethernet/realtek/Kconfig @@ -88,6 +88,7 @@ config R8169 select CRC32 select PHYLIB select REALTEK_PHY + select PHYLINK help Say Y here if you have a Realtek Ethernet adapter belonging to the following families: diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethern= et/realtek/r8169_main.c index fdc8c84dd112..97bcd36efdbb 100644 --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -775,6 +776,8 @@ struct rtl8169_private { struct r8169_led_classdev *leds; =20 u32 ocp_base; + struct phylink *phylink; + struct phylink_config phylink_config; }; =20 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); @@ -2554,9 +2557,6 @@ static void rtl8169_init_phy(struct rtl8169_private *= tp) if (tp->sfp_mode) rtl_sfp_init(tp); =20 - /* We may have called phy_speed_down before */ - phy_speed_up(tp->phydev); - genphy_soft_reset(tp->phydev); } =20 @@ -2658,13 +2658,10 @@ static void rtl_jumbo_config(struct rtl8169_private= *tp) pcie_set_readrq(tp->pci_dev, readrq); =20 /* Chip doesn't support pause in jumbo mode */ - if (jumbo) { - linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, - tp->phydev->advertising); - linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, - tp->phydev->advertising); - phy_start_aneg(tp->phydev); - } + if (jumbo) + tp->phylink_config.mac_capabilities &=3D ~(MAC_SYM_PAUSE | MAC_ASYM_PAUS= E); + else + tp->phylink_config.mac_capabilities |=3D (MAC_SYM_PAUSE | MAC_ASYM_PAUSE= ); } =20 DECLARE_RTL_COND(rtl_chipcmd_cond) @@ -2779,7 +2776,7 @@ static void rtl_prepare_power_down(struct rtl8169_pri= vate *tp) rtl_ephy_write(tp, 0x19, 0xff64); =20 if (device_may_wakeup(tp_to_dev(tp))) { - phy_speed_down(tp->phydev, false); + phylink_speed_down(tp->phylink, false); rtl_wol_enable_rx(tp); } } @@ -4139,11 +4136,17 @@ static int rtl8169_change_mtu(struct net_device *de= v, int new_mtu) { struct rtl8169_private *tp =3D netdev_priv(dev); =20 + if (netif_running(dev)) + phylink_stop(tp->phylink); + WRITE_ONCE(dev->mtu, new_mtu); netdev_update_features(dev); rtl_jumbo_config(tp); rtl_set_eee_txidle_timer(tp); =20 + if (netif_running(dev)) + phylink_start(tp->phylink); + return 0; } =20 @@ -4962,41 +4965,15 @@ static void rtl_enable_tx_lpi(struct rtl8169_privat= e *tp, bool enable) } } =20 -static void r8169_phylink_handler(struct net_device *ndev) -{ - struct rtl8169_private *tp =3D netdev_priv(ndev); - struct device *d =3D tp_to_dev(tp); - - tp->current_speed =3D tp->phydev->speed; - if (netif_carrier_ok(ndev)) { - rtl_link_chg_patch(tp, tp->current_speed); - rtl_enable_tx_lpi(tp, tp->phydev->enable_tx_lpi); - pm_request_resume(d); - } else { - pm_runtime_idle(d); - } - - phy_print_status(tp->phydev); -} - static int r8169_phy_connect(struct rtl8169_private *tp) { - struct phy_device *phydev =3D tp->phydev; - phy_interface_t phy_mode; int ret; =20 - phy_mode =3D tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : - PHY_INTERFACE_MODE_MII; - - ret =3D phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, - phy_mode); - if (ret) + ret =3D phylink_connect_phy(tp->phylink, tp->phydev); + if (ret) { + netdev_err(tp->dev, "failed to connect phy\n"); return ret; - - if (!tp->supports_gmii) - phy_set_max_speed(phydev, SPEED_100); - - phy_attached_info(phydev); + } =20 return 0; } @@ -5007,7 +4984,7 @@ static void rtl8169_down(struct rtl8169_private *tp) /* Clear all task flags */ bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); =20 - phy_stop(tp->phydev); + phylink_stop(tp->phylink); =20 /* Reset SerDes PHY to bring down fiber link */ if (tp->sfp_mode) @@ -5035,11 +5012,14 @@ static void rtl8169_up(struct rtl8169_private *tp) phy_init_hw(tp->phydev); phy_resume(tp->phydev); rtl8169_init_phy(tp); + + /* We may have called phy_speed_down before */ + phylink_speed_up(tp->phylink); napi_enable(&tp->napi); enable_work(&tp->wk.work); rtl_reset_work(tp); =20 - phy_start(tp->phydev); + phylink_start(tp->phylink); } =20 static int rtl8169_close(struct net_device *dev) @@ -5055,7 +5035,7 @@ static int rtl8169_close(struct net_device *dev) =20 free_irq(tp->irq, tp); =20 - phy_disconnect(tp->phydev); + phylink_disconnect_phy(tp->phylink); =20 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, tp->RxPhyAddr); @@ -5288,6 +5268,8 @@ static void rtl_remove_one(struct pci_dev *pdev) r8169_remove_leds(tp->leds); =20 unregister_netdev(tp->dev); + if (tp->phylink) + phylink_destroy(tp->phylink); =20 if (tp->dash_type !=3D RTL_DASH_NONE) rtl8168_driver_stop(tp); @@ -5474,10 +5456,8 @@ static int r8169_mdio_register(struct rtl8169_privat= e *tp) return -EUNATCH; } =20 - tp->phydev->mac_managed_pm =3D true; if (rtl_supports_eee(tp)) phy_support_eee(tp->phydev); - phy_support_asym_pause(tp->phydev); =20 /* mimic behavior of r8125/r8126 vendor drivers */ if (tp->mac_version =3D=3D RTL_GIGA_MAC_VER_61) @@ -5599,6 +5579,92 @@ static bool rtl_aspm_is_safe(struct rtl8169_private = *tp) return false; } =20 +static void rtl_mac_link_down(struct phylink_config *config, unsigned int = mode, + phy_interface_t interface) +{ + struct rtl8169_private *tp =3D container_of(config, struct rtl8169_privat= e, phylink_config); + + tp->current_speed =3D SPEED_UNKNOWN; + pm_runtime_idle(tp_to_dev(tp)); +} + +static void rtl_mac_link_up(struct phylink_config *config, struct phy_devi= ce *phydev, + unsigned int mode, phy_interface_t interface, + int speed, int duplex, bool tx_pause, bool rx_pause) +{ + struct rtl8169_private *tp =3D container_of(config, struct rtl8169_privat= e, phylink_config); + + struct device *d =3D tp_to_dev(tp); + + tp->current_speed =3D speed; + rtl_link_chg_patch(tp, speed); + + if (phydev) + rtl_enable_tx_lpi(tp, phydev->enable_tx_lpi); + + pm_request_resume(d); +} + +static struct phylink_pcs *rtl_mac_select_pcs(struct phylink_config *confi= g, + phy_interface_t interface) +{ + return NULL; +} + +static void rtl_mac_config(struct phylink_config *config, unsigned int mod= e, + const struct phylink_link_state *state) +{ +} + +static const struct phylink_mac_ops rtl_phylink_mac_ops =3D { + .mac_select_pcs =3D rtl_mac_select_pcs, + .mac_config =3D rtl_mac_config, + .mac_link_down =3D rtl_mac_link_down, + .mac_link_up =3D rtl_mac_link_up, +}; + +static int rtl_init_phylink(struct rtl8169_private *tp) +{ + struct phylink *pl; + phy_interface_t phy_mode; + + tp->phylink_config.dev =3D &tp->dev->dev; + tp->phylink_config.type =3D PHYLINK_NETDEV; + tp->phylink_config.mac_managed_pm =3D true; + + tp->phylink_config.mac_capabilities =3D MAC_ASYM_PAUSE | MAC_SYM_PAUSE; + + if (tp->sfp_mode) { + phy_mode =3D PHY_INTERFACE_MODE_INTERNAL; + tp->phylink_config.mac_capabilities |=3D MAC_10000FD; + } else { + tp->phylink_config.mac_capabilities |=3D MAC_10 | MAC_100; + phy_mode =3D PHY_INTERFACE_MODE_INTERNAL; + + if (tp->mac_version =3D=3D RTL_GIGA_MAC_VER_80) + tp->phylink_config.mac_capabilities |=3D MAC_1000FD | MAC_2500FD | + MAC_5000FD | MAC_10000FD; + else if (tp->mac_version =3D=3D RTL_GIGA_MAC_VER_70) + tp->phylink_config.mac_capabilities |=3D MAC_1000FD | + MAC_2500FD | MAC_5000FD; + else if (tp->mac_version >=3D RTL_GIGA_MAC_VER_61) + tp->phylink_config.mac_capabilities |=3D MAC_1000FD | MAC_2500FD; + else + if (tp->supports_gmii) + tp->phylink_config.mac_capabilities |=3D MAC_1000FD; + } + + __set_bit(phy_mode, tp->phylink_config.supported_interfaces); + pl =3D phylink_create(&tp->phylink_config, tp_to_dev(tp)->fwnode, + phy_mode, &rtl_phylink_mac_ops); + if (IS_ERR(pl)) + return PTR_ERR(pl); + + tp->phylink =3D pl; + + return 0; +} + static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *= ent) { const struct rtl_chip_info *chip; @@ -5789,13 +5855,21 @@ static int rtl_init_one(struct pci_dev *pdev, const= struct pci_device_id *ent) =20 pci_set_drvdata(pdev, tp); =20 - rc =3D r8169_mdio_register(tp); + rc =3D rtl_init_phylink(tp); if (rc) return rc; =20 + rc =3D r8169_mdio_register(tp); + if (rc) { + phylink_destroy(tp->phylink); + return rc; + } + rc =3D register_netdev(dev); - if (rc) + if (rc) { + phylink_destroy(tp->phylink); return rc; + } =20 if (IS_ENABLED(CONFIG_R8169_LEDS)) { if (rtl_is_8125(tp)) --=20 2.43.0 From nobody Mon Jun 8 06:39:45 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1DC994183DC; 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Fri, 5 Jun 2026 18:39:09 +0800 Received: from RS-EX-MBS1.realsil.com.cn (172.29.17.101) by RS-EX-MBS4.realsil.com.cn (172.29.17.104) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Fri, 5 Jun 2026 18:39:09 +0800 Received: from 172.29.37.154 (172.29.37.152) by RS-EX-MBS1.realsil.com.cn (172.29.17.101) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Fri, 5 Jun 2026 18:39:09 +0800 From: javen To: , , , , , , , CC: , , Javen Xu Subject: [PATCH net-next v1 3/6] r8169: decoupling tp->phydev Date: Fri, 5 Jun 2026 18:39:02 +0800 Message-ID: <20260605103906.1445-4-javen_xu@realsil.com.cn> X-Mailer: git-send-email 2.50.1.windows.1 In-Reply-To: <20260605103906.1445-1-javen_xu@realsil.com.cn> References: <20260605103906.1445-1-javen_xu@realsil.com.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Javen Xu Some functions in ethtool are bound to tp->phydev. But in phylink, we should replace it with functions which are bound to to->phylink. Signed-off-by: Javen Xu --- drivers/net/ethernet/realtek/r8169_main.c | 36 ++++++++++++++--------- 1 file changed, 22 insertions(+), 14 deletions(-) diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethern= et/realtek/r8169_main.c index 97bcd36efdbb..c46117e3a643 100644 --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c @@ -2256,7 +2256,7 @@ static int rtl8169_get_eee(struct net_device *dev, st= ruct ethtool_keee *data) if (!rtl_supports_eee(tp)) return -EOPNOTSUPP; =20 - ret =3D phy_ethtool_get_eee(tp->phydev, data); + ret =3D phylink_ethtool_get_eee(tp->phylink, data); if (ret) return ret; =20 @@ -2272,7 +2272,7 @@ static int rtl8169_set_eee(struct net_device *dev, st= ruct ethtool_keee *data) if (!rtl_supports_eee(tp)) return -EOPNOTSUPP; =20 - return phy_ethtool_set_eee(tp->phydev, data); + return phylink_ethtool_set_eee(tp->phylink, data); } =20 static void rtl8169_get_ringparam(struct net_device *dev, @@ -2303,13 +2303,8 @@ static void rtl8169_get_pauseparam(struct net_device= *dev, struct ethtool_pauseparam *data) { struct rtl8169_private *tp =3D netdev_priv(dev); - bool tx_pause, rx_pause; =20 - phy_get_pause(tp->phydev, &tx_pause, &rx_pause); - - data->autoneg =3D tp->phydev->autoneg; - data->tx_pause =3D tx_pause ? 1 : 0; - data->rx_pause =3D rx_pause ? 1 : 0; + phylink_ethtool_get_pauseparam(tp->phylink, data); } =20 static int rtl8169_set_pauseparam(struct net_device *dev, @@ -2320,9 +2315,7 @@ static int rtl8169_set_pauseparam(struct net_device *= dev, if (dev->mtu > ETH_DATA_LEN) return -EOPNOTSUPP; =20 - phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause); - - return 0; + return phylink_ethtool_set_pauseparam(tp->phylink, data); } =20 static void rtl8169_get_eth_mac_stats(struct net_device *dev, @@ -2388,6 +2381,14 @@ static void rtl8169_get_eth_ctrl_stats(struct net_de= vice *dev, le32_to_cpu(tp->counters->rx_unknown_opcode); } =20 +static int rtl8169_get_link_ksettings(struct net_device *ndev, + struct ethtool_link_ksettings *cmd) +{ + struct rtl8169_private *tp =3D netdev_priv(ndev); + + return phylink_ethtool_ksettings_get(tp->phylink, cmd); +} + static int rtl8169_set_link_ksettings(struct net_device *ndev, const struct ethtool_link_ksettings *cmd) { @@ -2397,7 +2398,7 @@ static int rtl8169_set_link_ksettings(struct net_devi= ce *ndev, int speed =3D cmd->base.speed; =20 if (!tp->sfp_mode) - return phy_ethtool_ksettings_set(phydev, cmd); + return phylink_ethtool_ksettings_set(tp->phylink, cmd); =20 if (cmd->base.autoneg !=3D AUTONEG_DISABLE) return -EINVAL; @@ -2418,6 +2419,13 @@ static int rtl8169_set_link_ksettings(struct net_dev= ice *ndev, return 0; } =20 +static int rtl8169_nway_reset(struct net_device *dev) +{ + struct rtl8169_private *tp =3D netdev_priv(dev); + + return phylink_ethtool_nway_reset(tp->phylink); +} + static const struct ethtool_ops rtl8169_ethtool_ops =3D { .supported_coalesce_params =3D ETHTOOL_COALESCE_USECS | ETHTOOL_COALESCE_MAX_FRAMES, @@ -2433,10 +2441,10 @@ static const struct ethtool_ops rtl8169_ethtool_ops= =3D { .get_sset_count =3D rtl8169_get_sset_count, .get_ethtool_stats =3D rtl8169_get_ethtool_stats, .get_ts_info =3D ethtool_op_get_ts_info, - .nway_reset =3D phy_ethtool_nway_reset, + .nway_reset =3D rtl8169_nway_reset, .get_eee =3D rtl8169_get_eee, .set_eee =3D rtl8169_set_eee, - .get_link_ksettings =3D phy_ethtool_get_link_ksettings, + .get_link_ksettings =3D rtl8169_get_link_ksettings, .set_link_ksettings =3D rtl8169_set_link_ksettings, .get_ringparam =3D rtl8169_get_ringparam, .get_pause_stats =3D rtl8169_get_pause_stats, --=20 2.43.0 From nobody Mon Jun 8 06:39:45 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 341F64183CD; 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Fri, 5 Jun 2026 18:39:09 +0800 Received: from RS-EX-MBS1.realsil.com.cn (172.29.17.101) by RS-EX-MBS4.realsil.com.cn (172.29.17.104) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Fri, 5 Jun 2026 18:39:09 +0800 Received: from 172.29.37.154 (172.29.37.152) by RS-EX-MBS1.realsil.com.cn (172.29.17.101) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Fri, 5 Jun 2026 18:39:09 +0800 From: javen To: , , , , , , , CC: , , Javen Xu Subject: [PATCH net-next v1 4/6] r8169: add support for RTL8116af Date: Fri, 5 Jun 2026 18:39:03 +0800 Message-ID: <20260605103906.1445-5-javen_xu@realsil.com.cn> X-Mailer: git-send-email 2.50.1.windows.1 In-Reply-To: <20260605103906.1445-1-javen_xu@realsil.com.cn> References: <20260605103906.1445-1-javen_xu@realsil.com.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Javen Xu RTL8116af is sfp mode. Phylink uses pcs to get the link status and speed from its serdes reg, instead of standard phy reg. Also, RTL8116af doesn't have internal phy, so we add some checks to ensure that tp->phydev is not empty when we need it. Signed-off-by: Javen Xu --- drivers/net/ethernet/realtek/r8169_main.c | 172 ++++++++++++++++++---- 1 file changed, 140 insertions(+), 32 deletions(-) diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethern= et/realtek/r8169_main.c index c46117e3a643..7b79305635fc 100644 --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c @@ -97,6 +97,12 @@ #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) #define JUMBO_16K (SZ_16K - VLAN_ETH_HLEN - ETH_FCS_LEN) =20 +#define OCP_SDS_ADDR_REG 0xEB10 +#define OCP_SDS_CMD_REG 0xEB0E +#define OCP_SDS_DATA_REG 0xEB14 +#define SDS_CMD_READ 0x0001 +#define RTL_SDS_C22_BASE 0x40 + static const struct rtl_chip_info { u32 mask; u32 val; @@ -729,6 +735,12 @@ enum rtl_dash_type { RTL_DASH_25_BP, }; =20 +enum rtl_sfp_mode { + RTL_SFP_NONE, + RTL_SFP_8168_AF, + RTL_SFP_8127_ATF, +}; + struct rtl8169_private { void __iomem *mmio_addr; /* memory map physical address */ struct pci_dev *pci_dev; @@ -737,6 +749,7 @@ struct rtl8169_private { struct napi_struct napi; enum mac_version mac_version; enum rtl_dash_type dash_type; + enum rtl_sfp_mode sfp_mode; u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ u32 dirty_tx; @@ -764,7 +777,6 @@ struct rtl8169_private { unsigned supports_gmii:1; unsigned aspm_manageable:1; unsigned dash_enabled:1; - bool sfp_mode:1; dma_addr_t counters_phys_addr; struct rtl8169_counters *counters; struct rtl8169_tc_offsets tc_offset; @@ -778,6 +790,7 @@ struct rtl8169_private { u32 ocp_base; struct phylink *phylink; struct phylink_config phylink_config; + struct phylink_pcs pcs; }; =20 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); @@ -1133,7 +1146,7 @@ static int r8168_phy_ocp_read(struct rtl8169_private = *tp, u32 reg) return 0; =20 /* Return dummy MII_PHYSID2 in SFP mode to match SFP PHY driver */ - if (tp->sfp_mode && reg =3D=3D (OCP_STD_PHY_BASE + 2 * MII_PHYSID2)) + if (tp->sfp_mode =3D=3D RTL_SFP_8127_ATF && reg =3D=3D (OCP_STD_PHY_BASE = + 2 * MII_PHYSID2)) return PHY_ID_RTL_DUMMY_SFP & 0xffff; =20 RTL_W32(tp, GPHY_OCP, reg << 15); @@ -1287,6 +1300,13 @@ static void mac_mcu_write(struct rtl8169_private *tp= , int reg, int value) r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); } =20 +static bool rtl_is_8116af(struct rtl8169_private *tp) +{ + return tp->mac_version =3D=3D RTL_GIGA_MAC_VER_52 && + (r8168_mac_ocp_read(tp, 0xdc00) & 0x0078) =3D=3D 0x0030 && + (r8168_mac_ocp_read(tp, 0xd006) & 0x00ff) =3D=3D 0x0000; +} + static int mac_mcu_read(struct rtl8169_private *tp, int reg) { return r8168_mac_ocp_read(tp, tp->ocp_base + reg); @@ -1582,6 +1602,20 @@ static bool rtl_dash_is_enabled(struct rtl8169_priva= te *tp) } } =20 +static enum rtl_sfp_mode rtl_get_sfp_mode(struct rtl8169_private *tp) +{ + if (rtl_is_8125(tp)) { + u16 data =3D r8168_mac_ocp_read(tp, 0xd006); + + if ((data & 0xff) =3D=3D 0x07) + return RTL_SFP_8127_ATF; + } else if (rtl_is_8116af(tp)) { + return RTL_SFP_8168_AF; + } + + return RTL_SFP_NONE; +} + static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp) { switch (tp->mac_version) { @@ -2397,7 +2431,7 @@ static int rtl8169_set_link_ksettings(struct net_devi= ce *ndev, int duplex =3D cmd->base.duplex; int speed =3D cmd->base.speed; =20 - if (!tp->sfp_mode) + if (tp->sfp_mode !=3D RTL_SFP_8127_ATF) return phylink_ethtool_ksettings_set(tp->phylink, cmd); =20 if (cmd->base.autoneg !=3D AUTONEG_DISABLE) @@ -2509,9 +2543,10 @@ void r8169_apply_firmware(struct rtl8169_private *tp) tp->ocp_base =3D OCP_STD_PHY_BASE; =20 /* PHY soft reset may still be in progress */ - phy_read_poll_timeout(tp->phydev, MII_BMCR, val, - !(val & BMCR_RESET), - 50000, 600000, true); + if (tp->phydev) + phy_read_poll_timeout(tp->phydev, MII_BMCR, val, + !(val & BMCR_RESET), + 50000, 600000, true); } } =20 @@ -2562,7 +2597,7 @@ static void rtl8169_init_phy(struct rtl8169_private *= tp) tp->pci_dev->subsystem_device =3D=3D 0xe000) phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); =20 - if (tp->sfp_mode) + if (tp->sfp_mode =3D=3D RTL_SFP_8127_ATF) rtl_sfp_init(tp); =20 genphy_soft_reset(tp->phydev); @@ -3697,12 +3732,14 @@ static void rtl_hw_start_8117(struct rtl8169_privat= e *tp) =20 rtl_pcie_state_l2l3_disable(tp); =20 - rg_saw_cnt =3D phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; - if (rg_saw_cnt > 0) { - u16 sw_cnt_1ms_ini; + if (tp->phydev) { + rg_saw_cnt =3D phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; + if (rg_saw_cnt > 0) { + u16 sw_cnt_1ms_ini; =20 - sw_cnt_1ms_ini =3D (16000000 / rg_saw_cnt) & 0x0fff; - r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); + sw_cnt_1ms_ini =3D (16000000 / rg_saw_cnt) & 0x0fff; + r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); + } } =20 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0000); @@ -4879,7 +4916,7 @@ static irqreturn_t rtl8169_interrupt(int irq, void *d= ev_instance) goto out; } =20 - if (status & LinkChg) + if (status & LinkChg && tp->phydev) phy_mac_interrupt(tp->phydev); =20 rtl_irq_disable(tp); @@ -4995,7 +5032,7 @@ static void rtl8169_down(struct rtl8169_private *tp) phylink_stop(tp->phylink); =20 /* Reset SerDes PHY to bring down fiber link */ - if (tp->sfp_mode) + if (tp->sfp_mode =3D=3D RTL_SFP_8127_ATF) rtl_sfp_reset(tp); =20 rtl8169_update_counters(tp); @@ -5017,9 +5054,11 @@ static void rtl8169_up(struct rtl8169_private *tp) rtl8168_driver_start(tp); =20 pci_set_master(tp->pci_dev); - phy_init_hw(tp->phydev); - phy_resume(tp->phydev); - rtl8169_init_phy(tp); + if (tp->phydev) { + phy_init_hw(tp->phydev); + phy_resume(tp->phydev); + rtl8169_init_phy(tp); + } =20 /* We may have called phy_speed_down before */ phylink_speed_up(tp->phylink); @@ -5100,9 +5139,11 @@ static int rtl_open(struct net_device *dev) if (retval < 0) goto err_release_fw_2; =20 - retval =3D r8169_phy_connect(tp); - if (retval) - goto err_free_irq; + if (tp->phydev) { + retval =3D r8169_phy_connect(tp); + if (retval) + goto err_free_irq; + } =20 rtl8169_up(tp); rtl8169_init_counter_offsets(tp); @@ -5616,6 +5657,10 @@ static void rtl_mac_link_up(struct phylink_config *c= onfig, struct phy_device *ph static struct phylink_pcs *rtl_mac_select_pcs(struct phylink_config *confi= g, phy_interface_t interface) { + struct rtl8169_private *tp =3D container_of(config, struct rtl8169_privat= e, phylink_config); + + if (interface =3D=3D PHY_INTERFACE_MODE_1000BASEX || interface =3D=3D PHY= _INTERFACE_MODE_SGMII) + return &tp->pcs; return NULL; } =20 @@ -5624,6 +5669,55 @@ static void rtl_mac_config(struct phylink_config *co= nfig, unsigned int mode, { } =20 +static u16 rtl8116af_sds_read(struct rtl8169_private *tp, u16 sds_reg) +{ + r8168_mac_ocp_write(tp, OCP_SDS_ADDR_REG, sds_reg); + r8168_mac_ocp_write(tp, OCP_SDS_CMD_REG, SDS_CMD_READ); + return r8168_mac_ocp_read(tp, OCP_SDS_DATA_REG); +} + +static void rtl8169_pcs_get_state(struct phylink_pcs *pcs, + unsigned int neg_mode, + struct phylink_link_state *state) +{ + struct rtl8169_private *tp =3D container_of(pcs, struct rtl8169_private, = pcs); + u16 bmsr, lpa; + + bmsr =3D rtl8116af_sds_read(tp, RTL_SDS_C22_BASE + MII_BMSR); + lpa =3D rtl8116af_sds_read(tp, RTL_SDS_C22_BASE + MII_LPA); + + state->link =3D !!(bmsr & BMSR_LSTATUS); + state->an_complete =3D !!(bmsr & BMSR_ANEGCOMPLETE); + if (state->link) { + state->speed =3D SPEED_1000; + state->duplex =3D DUPLEX_FULL; + } else { + state->speed =3D SPEED_UNKNOWN; + state->duplex =3D DUPLEX_UNKNOWN; + } + + if (lpa & LPA_1000XPAUSE) + state->pause |=3D MLO_PAUSE_RX | MLO_PAUSE_TX; +} + +static int rtl8169_pcs_config(struct phylink_pcs *pcs, unsigned int mode, + phy_interface_t interface, + const unsigned long *advertising, + bool permit_pause_to_mac) +{ + return 0; +} + +static int rtl8169_pcs_validate(struct phylink_pcs *pcs, unsigned long *su= pported, + const struct phylink_link_state *state) +{ + return 0; +} + +static void rtl8169_pcs_an_restart(struct phylink_pcs *pcs) +{ +} + static const struct phylink_mac_ops rtl_phylink_mac_ops =3D { .mac_select_pcs =3D rtl_mac_select_pcs, .mac_config =3D rtl_mac_config, @@ -5631,6 +5725,13 @@ static const struct phylink_mac_ops rtl_phylink_mac_= ops =3D { .mac_link_up =3D rtl_mac_link_up, }; =20 +static const struct phylink_pcs_ops r8169_pcs_ops =3D { + .pcs_validate =3D rtl8169_pcs_validate, + .pcs_get_state =3D rtl8169_pcs_get_state, + .pcs_config =3D rtl8169_pcs_config, + .pcs_an_restart =3D rtl8169_pcs_an_restart, +}; + static int rtl_init_phylink(struct rtl8169_private *tp) { struct phylink *pl; @@ -5642,10 +5743,19 @@ static int rtl_init_phylink(struct rtl8169_private = *tp) =20 tp->phylink_config.mac_capabilities =3D MAC_ASYM_PAUSE | MAC_SYM_PAUSE; =20 - if (tp->sfp_mode) { + switch (tp->sfp_mode) { + case RTL_SFP_8168_AF: + tp->pcs.ops =3D &r8169_pcs_ops; + tp->pcs.poll =3D true; + tp->phylink_config.default_an_inband =3D true; + phy_mode =3D PHY_INTERFACE_MODE_1000BASEX; + tp->phylink_config.mac_capabilities |=3D MAC_1000FD; + break; + case RTL_SFP_8127_ATF: phy_mode =3D PHY_INTERFACE_MODE_INTERNAL; tp->phylink_config.mac_capabilities |=3D MAC_10000FD; - } else { + break; + default: tp->phylink_config.mac_capabilities |=3D MAC_10 | MAC_100; phy_mode =3D PHY_INTERFACE_MODE_INTERNAL; =20 @@ -5660,6 +5770,7 @@ static int rtl_init_phylink(struct rtl8169_private *t= p) else if (tp->supports_gmii) tp->phylink_config.mac_capabilities |=3D MAC_1000FD; + break; } =20 __set_bit(phy_mode, tp->phylink_config.supported_interfaces); @@ -5754,12 +5865,7 @@ static int rtl_init_one(struct pci_dev *pdev, const = struct pci_device_id *ent) } tp->aspm_manageable =3D !rc; =20 - if (rtl_is_8125(tp)) { - u16 data =3D r8168_mac_ocp_read(tp, 0xd006); - - if ((data & 0xff) =3D=3D 0x07) - tp->sfp_mode =3D true; - } + tp->sfp_mode =3D rtl_get_sfp_mode(tp); =20 tp->dash_type =3D rtl_get_dash_type(tp); tp->dash_enabled =3D rtl_dash_is_enabled(tp); @@ -5867,10 +5973,12 @@ static int rtl_init_one(struct pci_dev *pdev, const= struct pci_device_id *ent) if (rc) return rc; =20 - rc =3D r8169_mdio_register(tp); - if (rc) { - phylink_destroy(tp->phylink); - return rc; + if (tp->sfp_mode !=3D RTL_SFP_8168_AF) { + rc =3D r8169_mdio_register(tp); + if (rc) { + phylink_destroy(tp->phylink); + return rc; + } } =20 rc =3D register_netdev(dev); --=20 2.43.0 From nobody Mon Jun 8 06:39:45 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D97A43F4125; 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Fri, 5 Jun 2026 18:39:09 +0800 Received: from RS-EX-MBS1.realsil.com.cn (172.29.17.101) by RS-EX-MBS4.realsil.com.cn (172.29.17.104) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Fri, 5 Jun 2026 18:39:09 +0800 Received: from 172.29.37.154 (172.29.37.152) by RS-EX-MBS1.realsil.com.cn (172.29.17.101) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Fri, 5 Jun 2026 18:39:09 +0800 From: javen To: , , , , , , , CC: , , Javen Xu Subject: [PATCH net-next v1 5/6] r8169: add ltr support for RTL8116af Date: Fri, 5 Jun 2026 18:39:04 +0800 Message-ID: <20260605103906.1445-6-javen_xu@realsil.com.cn> X-Mailer: git-send-email 2.50.1.windows.1 In-Reply-To: <20260605103906.1445-1-javen_xu@realsil.com.cn> References: <20260605103906.1445-1-javen_xu@realsil.com.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Javen Xu This patch adds ltr support for RTL8116af, enables RTL8116af enter l1.2 state. This makes sense for the system to enter c10 state. Signed-off-by: Javen Xu --- drivers/net/ethernet/realtek/r8169_main.c | 31 +++++++++++++++++++---- 1 file changed, 26 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethern= et/realtek/r8169_main.c index 7b79305635fc..b9c071b7b081 100644 --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c @@ -341,11 +341,13 @@ enum rtl_registers { ALDPS_LTR =3D 0xe0a2, LTR_OBFF_LOCK =3D 0xe032, LTR_SNOOP =3D 0xe034, + SEND_LTR_MSG =3D 0xe038, =20 #define ALDPS_LTR_EN BIT(0) #define LTR_OBFF_LOCK_EN BIT(0) #define LINK_SPEED_CHANGE_EN BIT(14) #define LTR_SNOOP_EN GENMASK(15, 14) +#define LTR_MSG_EN BIT(0) }; =20 enum rtl8168_8101_registers { @@ -3137,8 +3139,22 @@ static void rtl_enable_ltr(struct rtl8169_private *t= p) r8168_mac_ocp_write(tp, 0xcdf2, 0x9003); r8168_mac_ocp_modify(tp, LTR_OBFF_LOCK, 0x0000, LINK_SPEED_CHANGE_EN); break; - case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: case RTL_GIGA_MAC_VER_52: + r8168_mac_ocp_write(tp, 0xcdd0, 0x9003); + r8168_mac_ocp_modify(tp, LTR_SNOOP, 0x0000, LTR_SNOOP_EN); + r8168_mac_ocp_write(tp, 0xe02c, 0x1880); + r8168_mac_ocp_write(tp, 0xe02e, 0x4880); + r8168_mac_ocp_modify(tp, ALDPS_LTR, 0x0000, ALDPS_LTR_EN); + r8168_mac_ocp_write(tp, 0xcdd8, 0x9003); + r8168_mac_ocp_write(tp, 0xcdda, 0x9003); + r8168_mac_ocp_write(tp, 0xcddc, 0x9003); + r8168_mac_ocp_write(tp, 0xcdd2, 0x883c); + r8168_mac_ocp_write(tp, 0xcdd4, 0x8c12); + r8168_mac_ocp_write(tp, 0xcdd6, 0x9003); + r8168_mac_ocp_write(tp, 0xe0a6, 0x9003); + r8168_mac_ocp_write(tp, 0xe0a8, 0x9003); + break; + case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: r8168_mac_ocp_modify(tp, ALDPS_LTR, 0x0000, ALDPS_LTR_EN); RTL_W8(tp, COMBO_LTR_EXTEND, RTL_R8(tp, COMBO_LTR_EXTEND) | COMBO_LTR_EX= TEND_EN); fallthrough; @@ -3158,6 +3174,7 @@ static void rtl_enable_ltr(struct rtl8169_private *tp) } /* chip can trigger LTR */ r8168_mac_ocp_modify(tp, LTR_OBFF_LOCK, 0x0003, LTR_OBFF_LOCK_EN); + r8168_mac_ocp_modify(tp, SEND_LTR_MSG, 0x0000, LTR_MSG_EN); } =20 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool ena= ble) @@ -3191,6 +3208,7 @@ static void rtl_hw_aspm_clkreq_enable(struct rtl8169_= private *tp, bool enable) rtl_enable_ltr(tp); switch (tp->mac_version) { case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: + case RTL_GIGA_MAC_VER_52: case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: /* reset ephy tx/rx disable timer */ r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); @@ -3203,6 +3221,7 @@ static void rtl_hw_aspm_clkreq_enable(struct rtl8169_= private *tp, bool enable) } else { switch (tp->mac_version) { case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: + case RTL_GIGA_MAC_VER_52: case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); break; @@ -3716,7 +3735,9 @@ static void rtl_hw_start_8117(struct rtl8169_private = *tp) =20 rtl_eri_set_bits(tp, 0xd4, 0x0010); =20 - rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); + rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4000); + + r8168_mac_ocp_write(tp, 0xe098, 0xc302); =20 rtl_disable_rxdvgate(tp); =20 @@ -3743,9 +3764,9 @@ static void rtl_hw_start_8117(struct rtl8169_private = *tp) } =20 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0000); - r8168_mac_ocp_write(tp, 0xea80, 0x0003); - r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); - r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); + r8168_mac_ocp_write(tp, 0xea80, 0x0000); + r8168_mac_ocp_modify(tp, 0xe052, 0x0009, 0x0000); + r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x045f); =20 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); r8168_mac_ocp_write(tp, 0xe63e, 0x0000); --=20 2.43.0 From nobody Mon Jun 8 06:39:45 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC59A4183BD; Fri, 5 Jun 2026 10:39:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780655972; cv=none; b=TgawmzAr19IoI1LsIFihSk+vtDyb0tzyLeRj3TEeZlvoWglSQtuN20fGHrnzmenc1xBEWxK4ThYtD9PjLPm1obVSYIr6Y+B3KUIALSL6VVpaDxlzQ+jl8RzXTpgcb5NUHku4fSbIS3YeKh3eUegOhpd8jDgbqXNMJtj0Z8VCrh4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780655972; c=relaxed/simple; bh=WjqAZC/zgduqlquW8Ili7A6Cs3pw1Ugiq/xVJ6JZF9Q=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=QGENKME06cqmRiMFVRCcwn/1MPNVWVEyuJzbUCxDbJwynfBECs1tatA9pA4KqW2BjhtwTHZ5oBn/8CRj+1SzlL7ebgBSF6XM5uTPUnIg2Z7WUbM7I/5+NHJ/3aHCVxNA7OSywOz4HW2aEVDEfU5+Xj9iuxz8mIQe5RYqHVyX2E8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realsil.com.cn; spf=pass smtp.mailfrom=realsil.com.cn; dkim=pass (2048-bit key) header.d=realsil.com.cn header.i=@realsil.com.cn header.b=s2iQgylC; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realsil.com.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realsil.com.cn Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=realsil.com.cn header.i=@realsil.com.cn header.b="s2iQgylC" X-SpamFilter-By: ArmorX SpamTrap 5.80 with qID 655AdAeC51324199, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=realsil.com.cn; s=dkim; t=1780655950; bh=TRBZvvhNyKK02pPaeAhnsVR8oAEG+rewdu9dbu4Nuio=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=s2iQgylCjDZxDbzFBomS05do19A42Ujfm62ES4EN1hDsV61n9/ooElC5KTUFA5GD7 nuxcm5E5TNYxNne3ScuYVDkzFxjeK1B7XrjZx3qUOvHCmt7D5D4n3VMFQP70hN7x2D jVGrY/9BQNWooFm8Nw2VB9dkOAtmgbSOyQAK1i2jkutF2mU/re+ZM16zYw8QHgw6y/ Xm/WwGh7N5d+1aKgdqBhjdT5pDQmJ4rdgjZwlU3VTrDOHnAKCZOGOVFKW/Kp8erX1y BYAuzmtqUGXANGCf2F4odmOby39COMHH5SCRweeANsvw4qlLgUj4DfJ08JGBuqvYGr A7w1bE3VSri8g== Received: from RS-EX-MBS4.realsil.com.cn ([172.29.17.104]) by rtits2.realtek.com.tw (8.15.2/3.28/5.94) with ESMTPS id 655AdAeC51324199 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 5 Jun 2026 18:39:10 +0800 Received: from RS-EX-MBS1.realsil.com.cn (172.29.17.101) by RS-EX-MBS4.realsil.com.cn (172.29.17.104) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Fri, 5 Jun 2026 18:39:10 +0800 Received: from 172.29.37.154 (172.29.37.152) by RS-EX-MBS1.realsil.com.cn (172.29.17.101) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Fri, 5 Jun 2026 18:39:10 +0800 From: javen To: , , , , , , , CC: , , Javen Xu Subject: [PATCH net-next v1 6/6] r8169: fix RTL8116af can not enter s0idle and c10 Date: Fri, 5 Jun 2026 18:39:05 +0800 Message-ID: <20260605103906.1445-7-javen_xu@realsil.com.cn> X-Mailer: git-send-email 2.50.1.windows.1 In-Reply-To: <20260605103906.1445-1-javen_xu@realsil.com.cn> References: <20260605103906.1445-1-javen_xu@realsil.com.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Javen Xu RTL8116AF is a multi-function device. Functions 2 to 7 are hidden from the PCI core and return an all-ones response when their vendor ID is read, so they are not enumerated as normal PCI functions. However, these hidden functions can still affect platform power management. If they are left in D0 or keep ASPM disabled, the platform may fail to enter the low-power s0ix state and the CPU package may fail to enter Package C10. Put functions 2 to 7 into D3hot and enable ASPM on their PCIe link control register. Since these functions are hidden, access their configuration space through pci_bus_read_config_dword() / pci_bus_write_config_dword() using the same slot and the target function numbers. Ignore functions that return a PCI error response when reading their configuration space. Signed-off-by: Javen Xu --- drivers/net/ethernet/realtek/r8169_main.c | 31 +++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethern= et/realtek/r8169_main.c index b9c071b7b081..9c0a76f70d31 100644 --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c @@ -348,6 +348,9 @@ enum rtl_registers { #define LINK_SPEED_CHANGE_EN BIT(14) #define LTR_SNOOP_EN GENMASK(15, 14) #define LTR_MSG_EN BIT(0) +#define RTL8116AF_FUNC_PM_CSR 0x80 +#define RTL8116AF_FUNC_EXP_LNKCTL 0x44 +#define RTL_PM_D3HOT GENMASK(1, 0) }; =20 enum rtl8168_8101_registers { @@ -3715,6 +3718,33 @@ static void rtl_hw_start_8168ep_3(struct rtl8169_pri= vate *tp) r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); } =20 +static void rtl_disable_hidden_function(struct pci_dev *pdev) +{ + unsigned int slot =3D PCI_SLOT(pdev->devfn); + struct pci_bus *bus =3D pdev->bus; + unsigned int devfn; + int func; + int ret; + u32 val; + + for (func =3D 2; func < 8; func++) { + devfn =3D PCI_DEVFN(slot, func); + + ret =3D pci_bus_read_config_dword(bus, devfn, RTL8116AF_FUNC_PM_CSR, &va= l); + if (!ret && !PCI_POSSIBLE_ERROR(val)) { + val &=3D ~(PCI_PM_CTRL_STATE_MASK | PCI_PM_CTRL_PME_ENABLE); + val |=3D (RTL_PM_D3HOT | PCI_PM_CTRL_PME_ENABLE); + pci_bus_write_config_dword(bus, devfn, RTL8116AF_FUNC_PM_CSR, val); + } + + ret =3D pci_bus_read_config_dword(bus, devfn, RTL8116AF_FUNC_EXP_LNKCTL,= &val); + if (!ret && !PCI_POSSIBLE_ERROR(val)) { + val |=3D PCI_EXP_LNKCTL_ASPMC; + pci_bus_write_config_dword(bus, devfn, RTL8116AF_FUNC_EXP_LNKCTL, val); + } + } +} + static void rtl_hw_start_8117(struct rtl8169_private *tp) { static const struct ephy_info e_info_8117[] =3D { @@ -3773,6 +3803,7 @@ static void rtl_hw_start_8117(struct rtl8169_private = *tp) r8168_mac_ocp_write(tp, 0xc094, 0x0000); r8168_mac_ocp_write(tp, 0xc09e, 0x0000); =20 + rtl_disable_hidden_function(tp->pci_dev); /* firmware is for MAC only */ r8169_apply_firmware(tp); } --=20 2.43.0