From nobody Mon Jun 8 07:22:55 2026 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F6113B71C2; Fri, 5 Jun 2026 09:35:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780652143; cv=none; b=GRBi38oD57Oad5YWaYFHYWTtSDaivTZ+W6idUS68vSABTNDCLpORxMlQXAGqEKYOqj2oM8Q0KsEqACrvMHArBYTwOw26SmiECLZGcAWZ5Ci4GYRbi9JCgnTmTNYOJcomDUgsjU3XiVGiLCdw21zAtoeMQik4zDE+FKKZz0WoRKo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780652143; c=relaxed/simple; bh=uUr2WX0hfhqFblDSBBPdFGtDvl61n05tGhgtx80/7Yg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=XKlZvyNztRbkYK6LWMXPPCeT4JOct2I1rIT3SLryqt2KiagjVzsbb3hVm7lnvF+GHkAMWbm3KhXqc390yymJcrSS3XOXYNbx2cD/FmHrevMX/LW6pGOhbonTxcWoI71A37Ig//Gq8H+EIfUXyYeecRiEm8hZzo1E+7ZJwC49TJ4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=e/C67GuI; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="e/C67GuI" X-UUID: e78ec9f060c111f1b1788b6acf885367-20260605 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=/dslgzlo3e3q4Fp9CcQ8kHNOhLW06kFWzrlqwahyqjg=; b=e/C67GuIIBsuhtHyBRwL1cUOjGokQV2yFDzJ6p/4H1Dg48FL9cOD8tVE59fiseEniTvMKlrvQHvHsCWh+SvogjatflD1eu6CjAPqY4BncPT483M/4cgwjEvGMBFhmr8TcDIuL3Y2CllpxsUZIUf9c+J/rxepD+EzPpANhRLkc2w=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.15,REQID:27bc5fc0-2e3e-409a-9b46-e237767fffd5,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:e276073,CLOUDID:95aa8503-5b7c-4de7-bc39-cc187eea3c57,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|865|888|898,TC:-5,Cont ent:0|15|50,EDM:-3,IP:nil,URL:0,File:130,RT:0,Bulk:nil,QS:nil,BEC:-1,COL:0 ,OSI:0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: e78ec9f060c111f1b1788b6acf885367-20260605 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1236832425; Fri, 05 Jun 2026 17:35:35 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Fri, 5 Jun 2026 17:35:33 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Fri, 5 Jun 2026 17:35:33 +0800 From: Irui Wang To: Hans Verkuil , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Krzysztof Kozlowski , , , Tiffany Lin , kyrie wu CC: Yunfei Dong , Maoguang Meng , Longfei Wang , Irui Wang , , , , , , , "Rob Herring (Arm)" Subject: [PATCH v7 1/6] media: dt-bindings: mediatek,vcodec-encoder: Add MT8196 Date: Fri, 5 Jun 2026 17:35:13 +0800 Message-ID: <20260605093519.13695-2-irui.wang@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20260605093519.13695-1-irui.wang@mediatek.com> References: <20260605093519.13695-1-irui.wang@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" Add support for MT8196 video encoder which uses VCP (Video Co-Processor) for firmware management. Unlike previous platforms that use SCP/VPU, MT8196 requires VCP to load and execute the video encoding firmware, with the encoder communicating through VCP to perform encoding operations. Add the "mediatek,mt8196-vcodec-enc" compatible string and introduce the "mediatek,vcp" property to reference the VCP device, which is required for MT8196 encoder operation. Signed-off-by: Irui Wang Reviewed-by: Rob Herring (Arm) Reviewed-by: Nicolas Dufresne --- .../media/mediatek,vcodec-encoder.yaml | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-encode= r.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.ya= ml index ebc615584f92..72698456374a 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml @@ -24,6 +24,7 @@ properties: - mediatek,mt8188-vcodec-enc - mediatek,mt8192-vcodec-enc - mediatek,mt8195-vcodec-enc + - mediatek,mt8196-vcodec-enc - items: - const: mediatek,mt8186-vcodec-enc - const: mediatek,mt8183-vcodec-enc @@ -58,6 +59,13 @@ properties: description: Describes point to scp. =20 + mediatek,vcp: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Reference to the VCP (Video Co-Processor) device that loads and exec= utes + the video encoding firmware. The encoder communicates with the firmw= are + through VCP to perform encoding operations. + power-domains: maxItems: 1 =20 @@ -76,6 +84,20 @@ required: - iommus =20 allOf: + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8196-vcodec-enc + + then: + required: + - mediatek,vcp + else: + properties: + mediatek,vcp: false + - if: properties: compatible: --=20 2.45.2 From nobody Mon Jun 8 07:22:55 2026 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7793C3B71D0; Fri, 5 Jun 2026 09:35:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780652145; cv=none; b=lwV2QjtejFQOpmEo/T4bujBmvgb2LU+a9CW756Z2hfrnEvqsXymOVXv9afmD1OzeLLI1dQXNudm0GedGtolt5j9KPzf4o+tAr35ebVpQe0hltRDl1IJW/x4JE+y1LF92y6BqJ0us4Kcl1VrcMJNVZj3HfceUrcthuQR96t5Gnr8= ARC-Message-Signature: i=1; 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charset="utf-8" Add new platform data members to support different encoder ICs: - venc_model_num: encoder model number - fw_type: firmware type (VPU, SCP, or VCP) - fw_init: firmware-specific initialization callback - ipi_id: IPI ID for encoder communication This centralizes all static platform configuration in the platform data structure, eliminating the need for runtime device tree parsing and the per-device fw_init callback pointer. Each platform's pdata now directly specifies its firmware initialization function. Changes: 1. Add venc_model_num to pdata and remove mtk_vcodec_enc_get_chip_name() 2. Add fw_type to pdata for each platform (VPU or SCP) 3. Add ipi_id field declaration to pdata 4. Remove device tree parsing for fw_type Signed-off-by: Irui Wang --- .../mediatek/vcodec/common/mtk_vcodec_fw.c | 3 +- .../mediatek/vcodec/encoder/mtk_vcodec_enc.c | 22 +--------- .../vcodec/encoder/mtk_vcodec_enc_drv.c | 40 +++++++++++-------- .../vcodec/encoder/mtk_vcodec_enc_drv.h | 10 ++++- 4 files changed, 36 insertions(+), 39 deletions(-) diff --git a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.c = b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.c index a2e6a01272b2..9df64200d933 100644 --- a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.c +++ b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.c @@ -23,8 +23,9 @@ struct mtk_vcodec_fw *mtk_vcodec_fw_select(void *priv, en= um mtk_vcodec_fw_type t { if (fw_use =3D=3D ENCODER) { struct mtk_vcodec_enc_dev *enc_dev =3D priv; + const struct mtk_vcodec_enc_pdata *pdata =3D enc_dev->venc_pdata; =20 - return enc_dev->fw_init(priv, fw_use); + return pdata->fw_init(priv, fw_use); } =20 if (fw_use =3D=3D DECODER) { diff --git a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.= c b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.c index 48cb5dded70a..fcf0e4f90429 100644 --- a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.c +++ b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.c @@ -198,33 +198,15 @@ static int vidioc_enum_fmt_vid_out(struct file *file,= void *priv, pdata->num_output_formats); } =20 -static int mtk_vcodec_enc_get_chip_name(struct mtk_vcodec_enc_ctx *ctx) -{ - struct device *dev =3D &ctx->dev->plat_dev->dev; - - if (of_device_is_compatible(dev->of_node, "mediatek,mt8173-vcodec-enc")) - return 8173; - else if (of_device_is_compatible(dev->of_node, "mediatek,mt8183-vcodec-en= c")) - return 8183; - else if (of_device_is_compatible(dev->of_node, "mediatek,mt8192-vcodec-en= c")) - return 8192; - else if (of_device_is_compatible(dev->of_node, "mediatek,mt8195-vcodec-en= c")) - return 8195; - else if (of_device_is_compatible(dev->of_node, "mediatek,mt8188-vcodec-en= c")) - return 8188; - else - return 8173; -} - static int vidioc_venc_querycap(struct file *file, void *priv, struct v4l2_capability *cap) { struct mtk_vcodec_enc_ctx *ctx =3D file_to_enc_ctx(file); + const struct mtk_vcodec_enc_pdata *pdata =3D ctx->dev->venc_pdata; struct device *dev =3D &ctx->dev->plat_dev->dev; - int platform_name =3D mtk_vcodec_enc_get_chip_name(ctx); =20 strscpy(cap->driver, dev->driver->name, sizeof(cap->driver)); - snprintf(cap->card, sizeof(cap->card), "MT%d video encoder", platform_nam= e); + snprintf(cap->card, sizeof(cap->card), "MT%d video encoder", pdata->venc_= model_num); =20 return 0; } diff --git a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_= drv.c b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c index dc54d445d98d..5f1feb3b07a6 100644 --- a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c +++ b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c @@ -245,8 +245,6 @@ static int mtk_vcodec_probe(struct platform_device *pde= v) { struct mtk_vcodec_enc_dev *dev; struct video_device *vfd_enc; - phandle rproc_phandle; - enum mtk_vcodec_fw_type fw_type; int ret; =20 dev =3D devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); @@ -256,25 +254,17 @@ static int mtk_vcodec_probe(struct platform_device *p= dev) INIT_LIST_HEAD(&dev->ctx_list); dev->plat_dev =3D pdev; =20 - if (!of_property_read_u32(pdev->dev.of_node, "mediatek,vpu", - &rproc_phandle)) { - fw_type =3D VPU; - dev->fw_init =3D mtk_vcodec_fw_vpu_init; - } else if (!of_property_read_u32(pdev->dev.of_node, "mediatek,scp", - &rproc_phandle)) { - fw_type =3D SCP; - dev->fw_init =3D mtk_vcodec_fw_scp_init; - } else { - dev_err(&pdev->dev, "[MTK VCODEC] Could not get venc IPI device"); + dev->venc_pdata =3D of_device_get_match_data(&pdev->dev); + if (!dev->venc_pdata) { + dev_err(&pdev->dev, "Failed to get match data"); return -ENODEV; } - dma_set_max_seg_size(&pdev->dev, UINT_MAX); - - dev->fw_handler =3D mtk_vcodec_fw_select(dev, fw_type, ENCODER); + dev->fw_handler =3D mtk_vcodec_fw_select(dev, dev->venc_pdata->fw_type, E= NCODER); if (IS_ERR(dev->fw_handler)) return PTR_ERR(dev->fw_handler); =20 - dev->venc_pdata =3D of_device_get_match_data(&pdev->dev); + dma_set_max_seg_size(&pdev->dev, UINT_MAX); + ret =3D mtk_vcodec_init_enc_clk(dev); if (ret < 0) { dev_err(&pdev->dev, "[MTK VCODEC] Failed to get mtk vcodec clock source!= "); @@ -389,6 +379,7 @@ static int mtk_vcodec_probe(struct platform_device *pde= v) } =20 static const struct mtk_vcodec_enc_pdata mt8173_avc_pdata =3D { + .venc_model_num =3D 8173, .capture_formats =3D mtk_video_formats_capture_h264, .num_capture_formats =3D ARRAY_SIZE(mtk_video_formats_capture_h264), .output_formats =3D mtk_video_formats_output, @@ -396,9 +387,12 @@ static const struct mtk_vcodec_enc_pdata mt8173_avc_pd= ata =3D { .min_bitrate =3D 64, .max_bitrate =3D 60000000, .core_id =3D VENC_SYS, + .fw_type =3D VPU, + .fw_init =3D mtk_vcodec_fw_vpu_init, }; =20 static const struct mtk_vcodec_enc_pdata mt8173_vp8_pdata =3D { + .venc_model_num =3D 8173, .capture_formats =3D mtk_video_formats_capture_vp8, .num_capture_formats =3D ARRAY_SIZE(mtk_video_formats_capture_vp8), .output_formats =3D mtk_video_formats_output, @@ -406,9 +400,12 @@ static const struct mtk_vcodec_enc_pdata mt8173_vp8_pd= ata =3D { .min_bitrate =3D 64, .max_bitrate =3D 9000000, .core_id =3D VENC_LT_SYS, + .fw_type =3D VPU, + .fw_init =3D mtk_vcodec_fw_vpu_init, }; =20 static const struct mtk_vcodec_enc_pdata mt8183_pdata =3D { + .venc_model_num =3D 8183, .uses_ext =3D true, .capture_formats =3D mtk_video_formats_capture_h264, .num_capture_formats =3D ARRAY_SIZE(mtk_video_formats_capture_h264), @@ -417,9 +414,12 @@ static const struct mtk_vcodec_enc_pdata mt8183_pdata = =3D { .min_bitrate =3D 64, .max_bitrate =3D 40000000, .core_id =3D VENC_SYS, + .fw_type =3D SCP, + .fw_init =3D mtk_vcodec_fw_scp_init, }; =20 static const struct mtk_vcodec_enc_pdata mt8188_pdata =3D { + .venc_model_num =3D 8188, .uses_ext =3D true, .capture_formats =3D mtk_video_formats_capture_h264, .num_capture_formats =3D ARRAY_SIZE(mtk_video_formats_capture_h264), @@ -429,9 +429,12 @@ static const struct mtk_vcodec_enc_pdata mt8188_pdata = =3D { .max_bitrate =3D 50000000, .core_id =3D VENC_SYS, .uses_34bit =3D true, + .fw_type =3D SCP, + .fw_init =3D mtk_vcodec_fw_scp_init, }; =20 static const struct mtk_vcodec_enc_pdata mt8192_pdata =3D { + .venc_model_num =3D 8192, .uses_ext =3D true, .capture_formats =3D mtk_video_formats_capture_h264, .num_capture_formats =3D ARRAY_SIZE(mtk_video_formats_capture_h264), @@ -440,9 +443,12 @@ static const struct mtk_vcodec_enc_pdata mt8192_pdata = =3D { .min_bitrate =3D 64, .max_bitrate =3D 100000000, .core_id =3D VENC_SYS, + .fw_type =3D SCP, + .fw_init =3D mtk_vcodec_fw_scp_init, }; =20 static const struct mtk_vcodec_enc_pdata mt8195_pdata =3D { + .venc_model_num =3D 8195, .uses_ext =3D true, .capture_formats =3D mtk_video_formats_capture_h264, .num_capture_formats =3D ARRAY_SIZE(mtk_video_formats_capture_h264), @@ -451,6 +457,8 @@ static const struct mtk_vcodec_enc_pdata mt8195_pdata = =3D { .min_bitrate =3D 64, .max_bitrate =3D 100000000, .core_id =3D VENC_SYS, + .fw_type =3D SCP, + .fw_init =3D mtk_vcodec_fw_scp_init, }; =20 static const struct of_device_id mtk_vcodec_enc_match[] =3D { diff --git a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_= drv.h b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h index 934ff648125d..6c7e8da6d8ee 100644 --- a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h +++ b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h @@ -20,6 +20,7 @@ /** * struct mtk_vcodec_enc_pdata - compatible data for each IC * + * @venc_model_num: encoder model number * @uses_ext: whether the encoder uses the extended firmware messaging for= mat * @min_bitrate: minimum supported encoding bitrate * @max_bitrate: maximum supported encoding bitrate @@ -29,8 +30,12 @@ * @num_output_formats: number of entries in output_formats * @core_id: stand for h264 or vp8 encode index * @uses_34bit: whether the encoder uses 34-bit iova + * @fw_type: firmware type (VPU, SCP, or VCP) + * @fw_init: firmware-specific initialization callback + * @ipi_id: IPI ID for encoder communication with firmware */ struct mtk_vcodec_enc_pdata { + u16 venc_model_num; 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charset="utf-8" Introduce a new encoder kernel driver interface to ensure compatibility with the updated encoder software driver running in firmware. The new driver interface is expected to support more encoder formats, share more encode parameters between kernel and firmware. Signed-off-by: Irui Wang Reviewed-by: Nicolas Dufresne --- .../platform/mediatek/vcodec/encoder/Makefile | 1 + .../mediatek/vcodec/encoder/mtk_vcodec_enc.c | 14 +- .../vcodec/encoder/mtk_vcodec_enc_drv.h | 8 +- .../vcodec/encoder/venc/venc_common_if.c | 674 ++++++++++++++++++ .../vcodec/encoder/venc/venc_h264_if.c | 8 +- .../mediatek/vcodec/encoder/venc_drv_if.h | 11 +- 6 files changed, 698 insertions(+), 18 deletions(-) create mode 100644 drivers/media/platform/mediatek/vcodec/encoder/venc/ven= c_common_if.c diff --git a/drivers/media/platform/mediatek/vcodec/encoder/Makefile b/driv= ers/media/platform/mediatek/vcodec/encoder/Makefile index e621b5b7e5e6..9d3229d56e39 100644 --- a/drivers/media/platform/mediatek/vcodec/encoder/Makefile +++ b/drivers/media/platform/mediatek/vcodec/encoder/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_VIDEO_MEDIATEK_VCODEC) +=3D mtk-vcodec-enc.o =20 mtk-vcodec-enc-y :=3D venc/venc_vp8_if.o \ venc/venc_h264_if.o \ + venc/venc_common_if.o \ mtk_vcodec_enc.o \ mtk_vcodec_enc_drv.o \ mtk_vcodec_enc_pm.o \ diff --git a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.= c b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.c index fcf0e4f90429..b2f911746c01 100644 --- a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.c +++ b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.c @@ -81,11 +81,11 @@ static int vidioc_venc_s_ctrl(struct v4l2_ctrl *ctrl) break; case V4L2_CID_MPEG_VIDEO_H264_PROFILE: mtk_v4l2_venc_dbg(2, ctx, "V4L2_CID_MPEG_VIDEO_H264_PROFILE val =3D %d",= ctrl->val); - p->h264_profile =3D ctrl->val; + p->profile =3D ctrl->val; break; case V4L2_CID_MPEG_VIDEO_H264_LEVEL: mtk_v4l2_venc_dbg(2, ctx, "V4L2_CID_MPEG_VIDEO_H264_LEVEL val =3D %d", c= trl->val); - p->h264_level =3D ctrl->val; + p->level =3D ctrl->val; break; case V4L2_CID_MPEG_VIDEO_H264_I_PERIOD: mtk_v4l2_venc_dbg(2, ctx, "V4L2_CID_MPEG_VIDEO_H264_I_PERIOD val =3D %d"= , ctrl->val); @@ -367,8 +367,8 @@ static void mtk_venc_set_param(struct mtk_vcodec_enc_ct= x *ctx, mtk_v4l2_venc_err(ctx, "Unsupported fourcc =3D%d", q_data_src->fmt->four= cc); break; } - param->h264_profile =3D enc_params->h264_profile; - param->h264_level =3D enc_params->h264_level; + param->profile =3D enc_params->profile; + param->level =3D enc_params->level; =20 /* Config visible resolution */ param->width =3D q_data_src->visible_width; @@ -384,8 +384,8 @@ static void mtk_venc_set_param(struct mtk_vcodec_enc_ct= x *ctx, =20 mtk_v4l2_venc_dbg(0, ctx, "fmt 0x%x, P/L %d/%d w/h %d/%d buf %d/%d fps/bps %d/%d gop %d i_per %= d", - param->input_yuv_fmt, param->h264_profile, - param->h264_level, param->width, param->height, + param->input_yuv_fmt, param->profile, + param->level, param->width, param->height, param->buf_width, param->buf_height, param->frm_rate, param->bitrate, param->gop_size, param->intra_period); @@ -1139,6 +1139,8 @@ static void mtk_venc_worker(struct work_struct *work) frm_buf.fb_addr[i].size =3D (size_t)src_buf->vb2_buf.planes[i].length; } + frm_buf.num_planes =3D src_buf->vb2_buf.num_planes; + bs_buf.va =3D vb2_plane_vaddr(&dst_buf->vb2_buf, 0); bs_buf.dma_addr =3D vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); bs_buf.size =3D (size_t)dst_buf->vb2_buf.planes[0].length; diff --git a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_= drv.h b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h index 6c7e8da6d8ee..029133e48073 100644 --- a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h +++ b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h @@ -77,8 +77,8 @@ enum mtk_encode_param { * @framerate_denom: frame rate denominator. ex: framerate_num=3D30 and * framerate_denom=3D1 means FPS is 30 * @h264_max_qp: Max value for H.264 quantization parameter - * @h264_profile: V4L2 defined H.264 profile - * @h264_level: V4L2 defined H.264 level + * @profile: V4L2 defined profile + * @level: V4L2 defined level * @force_intra: force/insert intra frame */ struct mtk_enc_params { @@ -92,8 +92,8 @@ struct mtk_enc_params { unsigned int framerate_num; unsigned int framerate_denom; unsigned int h264_max_qp; - unsigned int h264_profile; - unsigned int h264_level; + unsigned int profile; + unsigned int level; unsigned int force_intra; }; =20 diff --git a/drivers/media/platform/mediatek/vcodec/encoder/venc/venc_commo= n_if.c b/drivers/media/platform/mediatek/vcodec/encoder/venc/venc_common_if= .c new file mode 100644 index 000000000000..0efb13aef8d6 --- /dev/null +++ b/drivers/media/platform/mediatek/vcodec/encoder/venc/venc_common_if.c @@ -0,0 +1,674 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 MediaTek Inc. + */ + +#include "../mtk_vcodec_enc.h" +#include "../mtk_vcodec_enc_drv.h" +#include "../venc_drv_base.h" +#include "../venc_drv_if.h" +#include "../venc_vpu_if.h" +#include "../../common/mtk_vcodec_intr.h" +#include "../../common/mtk_vcodec_util.h" + +#define SEQ_HEADER_SIZE 1024 +#define PPS_SIZE 128 +#define MAX_DPB_SIZE 16 +#define MAX_VENC_CORE 3 +#define VENC_CONFIG_LENGTH 115 +#define VENC_CONFIG_DATA 128 +#define VENC_PIC_BITSTREAM_BYTE_CNT 0x0098 + +/** + * enum venc_bs_mode - encode bitstream mode + * @VENC_BS_MODE_SPS: encode sps + * @VENC_BS_MODE_PPS: encode pps + * @VENC_BS_MODE_VPS: encode vps + * @VENC_BS_MODE_SEQ_HDR: encode sequence header + * @VENC_BS_MODE_FRAME: encode frame + * @VENC_BS_MODE_FRAME_FINAL: encode final frame + * @VENC_BS_MODE_MAX: max value + */ +enum venc_bs_mode { + VENC_BS_MODE_SPS =3D 0, + VENC_BS_MODE_PPS, + VENC_BS_MODE_VPS, + VENC_BS_MODE_SEQ_HDR, + VENC_BS_MODE_FRAME, + VENC_BS_MODE_FRAME_FINAL, + VENC_BS_MODE_MAX +}; + +/** + * struct venc_config - Structure for encoder configuration + * AP-W/R : AP is writer/reader on this item + * MCU-W/R: MCU is write/reader on this item + * @input_fourcc: input format fourcc + * @bitrate: target bitrate (in bps) + * @pic_w: visible width of resolution + * @pic_h: visible height of resolution + * @buf_w: buffer alignment width of resolution + * @buf_h: buffer alignment height of resolution + * @gop_size: group of picture size (IDR frame period) + * @intra_period: I frame period + * @framerate: frame rate in fps + * @profile: profile_idc in SPS + * @level: level_idc in SPS + * @core_num: encoder core num + * @dpb_size: encode dpb size + * @reserved: reserved fields config + */ +struct venc_config { + __u32 input_fourcc; + __u32 bitrate; + __u32 pic_w; + __u32 pic_h; + __u32 buf_w; + __u32 buf_h; + __u32 gop_size; + __u32 intra_period; + __u32 framerate; + __u32 profile; + __u32 level; + __u32 core_num; + __u32 dpb_size; + __u32 reserved[VENC_CONFIG_LENGTH]; +}; + +/** + * struct venc_config_data - Structure for configuration data + * @config_data: extended configuration data besides the basic configurati= on + */ +struct venc_config_data { + unsigned int config_data[VENC_CONFIG_DATA]; +}; + +/** + * struct venc_work_buf - Structure for working buffer information + * AP-W/R : AP is writer/reader on this item + * MCU-W/R: MCU is write/reader on this item + * @iova: IO virtual address + * @pa: physical address + * @pa_64: for 64bit pa padding + * @va: virtual address + * @va_padding: for 64bit va padding + * @size: buffer size + * @size_padding: for 64bit size padding + */ +struct venc_work_buf { + unsigned long long iova; + union { + unsigned int pa; + unsigned long long pa_64; + }; + union { + void *va; + unsigned long long va_padding; + }; + union { + unsigned int size; + unsigned long long size_padding; + }; +}; + +/** + * struct venc_work_buf_list - Structure for encode working buffer list + * @rc_code: RC code buffer + * @rc_info: RC info buffer + * @luma: luma buffer + * @chroma: chroma buffer + * @sub_luma: sub luma buffer + * @sub_write: sub write buffer + * @col_mv: col_mv buffer + * @wpp: wpp buffer + * @wpp_nbm: wpp nbm buffer + * @skip_frame: skip frame buffer + */ +struct venc_work_buf_list { + struct venc_work_buf rc_code; + struct venc_work_buf rc_info[MAX_VENC_CORE]; + struct venc_work_buf luma[MAX_DPB_SIZE]; + struct venc_work_buf chroma[MAX_DPB_SIZE]; + struct venc_work_buf sub_luma[MAX_DPB_SIZE]; + struct venc_work_buf sub_write[MAX_DPB_SIZE]; + struct venc_work_buf col_mv[MAX_DPB_SIZE]; + struct venc_work_buf wpp[MAX_VENC_CORE]; + struct venc_work_buf wpp_nbm[MAX_VENC_CORE]; + struct venc_work_buf skip_frame; +}; + +/** + * struct venc_info - Structure for encode frame and bs information + * @fb_addr: frame buffer address array + * @fb_size: frame buffer size array + * @bs_addr: bitstream buffer address + * @bs_size: bitstream buffer size + */ +struct venc_info { + unsigned long long fb_addr[VIDEO_MAX_PLANES]; + unsigned int fb_size[VIDEO_MAX_PLANES]; + unsigned long long bs_addr; + unsigned long long bs_size; +}; + +/** + * struct venc_vsi - Structure for VCP driver control and info share + * AP-W/R : AP is writer/reader on this item + * VCP-W/R: VCP is write/reader on this item + * @config: encoder configuration + * @data: encoder configuration data + * @bufs: encoder working buffers + * @venc: encoder information + */ +struct venc_vsi { + struct venc_config config; + struct venc_config_data data; + struct venc_work_buf_list bufs; + struct venc_info venc; +}; + +/** + * struct venc_inst - Structure for encoder instance + * @hw_base: hardware io address + * @pps_buf: PPS buffer + * @seq_buf: sequence header buffer + * @work_buf_allocated: work buffer allocated or not + * @frm_cnt: encoded frame count + * @skip_frm_cnt: encoded skip frame count + * @prepend_hdr: prepend header flag + * @vpu_inst: vpu instance + * @vsi: encode vsi + * @ctx: encoder context + */ +struct venc_inst { + void __iomem *hw_base; + struct mtk_vcodec_mem pps_buf; + struct mtk_vcodec_mem seq_buf; + bool work_buf_allocated; + unsigned int frm_cnt; + unsigned int skip_frm_cnt; + unsigned int prepend_hdr; + struct venc_vpu_inst vpu_inst; + struct venc_vsi *vsi; + struct mtk_vcodec_enc_ctx *ctx; +}; + +static int venc_init(struct mtk_vcodec_enc_ctx *ctx) +{ + int ret =3D 0; + struct venc_inst *inst; + + inst =3D kzalloc_obj(*inst, GFP_KERNEL); + if (!inst) + return -ENOMEM; + + inst->ctx =3D ctx; + inst->vpu_inst.ctx =3D ctx; + inst->vpu_inst.id =3D ctx->dev->venc_pdata->ipi_id; + inst->hw_base =3D mtk_vcodec_get_reg_addr(inst->ctx->dev->reg_base, VENC_= SYS); + + ret =3D vpu_enc_init(&inst->vpu_inst); + inst->vsi =3D (struct venc_vsi *)inst->vpu_inst.vsi; + + if (ret) { + kfree(inst); + return ret; + } + + ctx->drv_handle =3D inst; + + return 0; +} + +static inline u32 venc_read_reg(struct venc_inst *inst, u32 addr) +{ + return readl(inst->hw_base + addr); +} + +static unsigned int venc_wait_encode_done(struct venc_inst *inst) +{ + unsigned int irq_status =3D 0; + struct mtk_vcodec_enc_ctx *ctx =3D (struct mtk_vcodec_enc_ctx *)inst->ctx; + + if (!mtk_vcodec_wait_for_done_ctx(ctx, MTK_INST_IRQ_RECEIVED, + WAIT_INTR_TIMEOUT_MS, 0)) { + irq_status =3D ctx->irq_status; + mtk_venc_debug(ctx, "irq_status %x <-", irq_status); + } + return irq_status; +} + +static void venc_set_bufs(struct venc_inst *inst, + struct venc_frm_buf *frm_buf, + struct mtk_vcodec_mem *bs_buf) +{ + unsigned int i; + + if (frm_buf) { + for (i =3D 0; i < frm_buf->num_planes; i++) { + inst->vsi->venc.fb_addr[i] =3D frm_buf->fb_addr[i].dma_addr; + inst->vsi->venc.fb_size[i] =3D frm_buf->fb_addr[i].size; + mtk_venc_debug(inst->ctx, "%s: fb_buf[%d]: %llx(%d)\n", + __func__, i, + inst->vsi->venc.fb_addr[i], + inst->vsi->venc.fb_size[i]); + } + } + + if (bs_buf) { + inst->vsi->venc.bs_addr =3D bs_buf->dma_addr; + inst->vsi->venc.bs_size =3D bs_buf->size; + mtk_venc_debug(inst->ctx, "%s: bs_buf: %llx(%d)\n", + __func__, + inst->vsi->venc.bs_addr, + (unsigned int)inst->vsi->venc.bs_size); + } +} + +static int venc_encode_sps(struct venc_inst *inst, + struct mtk_vcodec_mem *bs_buf, + unsigned int *bs_size) +{ + int ret =3D 0; + unsigned int irq_status; + + venc_set_bufs(inst, NULL, bs_buf); + ret =3D vpu_enc_encode(&inst->vpu_inst, VENC_BS_MODE_SPS, NULL, bs_buf, N= ULL); + if (ret) + return ret; + + irq_status =3D venc_wait_encode_done(inst); + if (irq_status !=3D MTK_VENC_IRQ_STATUS_SPS) { + mtk_venc_err(inst->ctx, "expect irq status %d", MTK_VENC_IRQ_STATUS_SPS); + return -EINVAL; + } + + *bs_size =3D venc_read_reg(inst, VENC_PIC_BITSTREAM_BYTE_CNT); + mtk_venc_debug(inst->ctx, "sps bs size %d <-", *bs_size); + + return ret; +} + +static int venc_encode_pps(struct venc_inst *inst, + struct mtk_vcodec_mem *bs_buf, + unsigned int *bs_size) +{ + int ret =3D 0; + unsigned int irq_status; + + venc_set_bufs(inst, NULL, bs_buf); + ret =3D vpu_enc_encode(&inst->vpu_inst, VENC_BS_MODE_PPS, NULL, bs_buf, N= ULL); + if (ret) + return ret; + + irq_status =3D venc_wait_encode_done(inst); + if (irq_status !=3D MTK_VENC_IRQ_STATUS_PPS) { + mtk_venc_err(inst->ctx, "expect irq status %d", MTK_VENC_IRQ_STATUS_PPS); + return -EINVAL; + } + + *bs_size =3D venc_read_reg(inst, VENC_PIC_BITSTREAM_BYTE_CNT); + mtk_venc_debug(inst->ctx, "pps bs size %d <-", *bs_size); + + return ret; +} + +static int venc_encode_header(struct venc_inst *inst, + struct mtk_vcodec_mem *bs_buf, + unsigned int *bs_size) +{ + int ret =3D 0; + unsigned int bs_size_sps; + unsigned int bs_size_pps; + + ret =3D venc_encode_sps(inst, bs_buf, &bs_size_sps); + if (ret) + return ret; + + ret =3D venc_encode_pps(inst, &inst->pps_buf, &bs_size_pps); + if (ret) + return ret; + + memcpy(bs_buf->va + bs_size_sps, inst->pps_buf.va, bs_size_pps); + *bs_size =3D bs_size_sps + bs_size_pps; + + return ret; +} + +static int venc_encode_frame(struct venc_inst *inst, + struct venc_frm_buf *frm_buf, + struct mtk_vcodec_mem *bs_buf, + unsigned int *bs_size) +{ + int ret =3D 0; + unsigned int irq_status; + + venc_set_bufs(inst, frm_buf, bs_buf); + ret =3D vpu_enc_encode(&inst->vpu_inst, VENC_BS_MODE_FRAME, frm_buf, bs_b= uf, NULL); + if (ret) + return ret; + + irq_status =3D venc_wait_encode_done(inst); + if (irq_status !=3D MTK_VENC_IRQ_STATUS_FRM) { + mtk_venc_err(inst->ctx, "expect irq status %d", MTK_VENC_IRQ_STATUS_FRM); + return -EINVAL; + } + + *bs_size =3D venc_read_reg(inst, VENC_PIC_BITSTREAM_BYTE_CNT); + + ++inst->frm_cnt; + + return ret; +} + +static int venc_encode(void *handle, + enum venc_start_opt opt, + struct venc_frm_buf *frm_buf, + struct mtk_vcodec_mem *bs_buf, + struct venc_done_result *result) +{ + int ret =3D 0; + struct venc_inst *inst =3D (struct venc_inst *)handle; + struct mtk_vcodec_enc_ctx *ctx; + unsigned int bs_size_hdr; + + if (WARN_ON(!inst || !inst->vsi)) + return -EINVAL; + + ctx =3D inst->ctx; + + mtk_venc_debug(ctx, "%s: opt: %d\n", __func__, opt); + + enable_irq(ctx->dev->enc_irq); + switch (opt) { + case VENC_START_OPT_ENCODE_SEQUENCE_HEADER: { + ret =3D venc_encode_header(inst, bs_buf, &bs_size_hdr); + if (ret) + goto encode_err; + + result->bs_size =3D bs_size_hdr; + result->is_key_frm =3D false; + break; + } + + case VENC_START_OPT_ENCODE_FRAME: { + if (!inst->prepend_hdr) { + ret =3D venc_encode_frame(inst, frm_buf, bs_buf, &result->bs_size); + if (ret) + goto encode_err; + + result->is_key_frm =3D inst->vpu_inst.is_key_frm; + break; + } + + ret =3D venc_encode_header(inst, &inst->seq_buf, &bs_size_hdr); + if (ret) + goto encode_err; + + ret =3D venc_encode_frame(inst, frm_buf, bs_buf, &result->bs_size); + if (ret) + goto encode_err; + + memmove(bs_buf->va + bs_size_hdr, bs_buf->va, result->bs_size); + memcpy(bs_buf->va, inst->seq_buf.va, bs_size_hdr); + result->bs_size +=3D bs_size_hdr; + + inst->prepend_hdr =3D 0; + result->is_key_frm =3D inst->vpu_inst.is_key_frm; + break; + } + + default: + mtk_venc_err(inst->ctx, "venc_opt %d not supported", opt); + ret =3D -EINVAL; + break; + } + +encode_err: + disable_irq(ctx->dev->enc_irq); + mtk_venc_debug(ctx, "opt %d, return %d", opt, ret); + + return ret; +} + +static int mtk_venc_mem_alloc(struct venc_inst *inst, + struct device *dev, + struct venc_work_buf *buf) +{ + dma_addr_t dma_addr; + + if (WARN_ON(!dev || !buf)) + return -EINVAL; + + if (buf->size =3D=3D 0) + return 0; + + buf->va =3D dma_alloc_coherent(dev, buf->size, &dma_addr, GFP_KERNEL); + if (!buf->va) + return -ENOMEM; + + buf->iova =3D (unsigned long long)dma_addr; + + mtk_venc_debug(inst->ctx, "allocate buffer, size: %d, va: %p, iova: 0x%ll= x", + buf->size, buf->va, buf->iova); + + return 0; +} + +static void mtk_venc_mem_free(struct venc_inst *inst, + struct device *dev, + struct venc_work_buf *buf) +{ + if (WARN_ON(!dev || !buf)) + return; + + if (!buf->va) + return; + + mtk_venc_debug(inst->ctx, "free buffer, size: %d, va: %p, iova: 0x%llx", + buf->size, buf->va, buf->iova); + + dma_free_coherent(dev, buf->size, buf->va, buf->iova); + buf->va =3D NULL; + buf->iova =3D 0; + buf->size =3D 0; +} + +static void venc_free_rc_buf(struct venc_inst *inst, + struct venc_work_buf_list *bufs, + unsigned int core_num) +{ + int i; + struct device *dev; + + dev =3D &inst->ctx->dev->plat_dev->dev; + mtk_venc_mem_free(inst, dev, &bufs->rc_code); + + for (i =3D 0; i < core_num; i++) + mtk_venc_mem_free(inst, dev, &bufs->rc_info[i]); +} + +static void venc_free_work_buf(struct venc_inst *inst) +{ + int i; + struct venc_work_buf_list *bufs =3D &inst->vsi->bufs; + unsigned int core_num =3D inst->vsi->config.core_num; + unsigned int dpb_size =3D inst->vsi->config.dpb_size; + struct device *dev; + + if (bufs->rc_code.va) + venc_free_rc_buf(inst, bufs, core_num); + + dev =3D &inst->ctx->dev->plat_dev->dev; + + for (i =3D 0; i < core_num; i++) { + mtk_venc_mem_free(inst, dev, &bufs->wpp[i]); + mtk_venc_mem_free(inst, dev, &bufs->wpp_nbm[i]); + } + + for (i =3D 0; i < dpb_size; i++) { + mtk_venc_mem_free(inst, dev, &bufs->luma[i]); + mtk_venc_mem_free(inst, dev, &bufs->chroma[i]); + mtk_venc_mem_free(inst, dev, &bufs->sub_luma[i]); + mtk_venc_mem_free(inst, dev, &bufs->sub_write[i]); + mtk_venc_mem_free(inst, dev, &bufs->col_mv[i]); + } + + if (inst->pps_buf.va) + mtk_vcodec_mem_free(inst->ctx, &inst->pps_buf); + + if (inst->seq_buf.va) + mtk_vcodec_mem_free(inst->ctx, &inst->seq_buf); +} + +static int venc_alloc_rc_buf(struct venc_inst *inst, + struct venc_work_buf_list *bufs, + unsigned int core_num) +{ + int i; + struct mtk_vcodec_fw *fw =3D inst->ctx->dev->fw_handler; + struct device *dev; + void *tmp_va; + + dev =3D &inst->ctx->dev->plat_dev->dev; + if (mtk_venc_mem_alloc(inst, dev, &bufs->rc_code)) + return -ENOMEM; + + tmp_va =3D mtk_vcodec_fw_map_dm_addr(fw, bufs->rc_code.pa); + memcpy(bufs->rc_code.va, tmp_va, bufs->rc_code.size); + + for (i =3D 0; i < core_num; i++) { + if (mtk_venc_mem_alloc(inst, dev, &bufs->rc_info[i])) + goto err_rc_buf; + } + + return 0; + +err_rc_buf: + venc_free_rc_buf(inst, bufs, core_num); + + return -ENOMEM; +} + +static int venc_alloc_work_buf(struct venc_inst *inst) +{ + int i, ret; + struct venc_work_buf_list *bufs =3D &inst->vsi->bufs; + unsigned int core_num =3D inst->vsi->config.core_num; + unsigned int dpb_size =3D inst->vsi->config.dpb_size; + struct device *dev; + + if (bufs->rc_code.size !=3D 0) { + ret =3D venc_alloc_rc_buf(inst, bufs, core_num); + if (ret) { + mtk_venc_err(inst->ctx, "cannot allocate rc buf"); + return -ENOMEM; + } + } + + dev =3D &inst->ctx->dev->plat_dev->dev; + + for (i =3D 0; i < core_num; i++) { + if (mtk_venc_mem_alloc(inst, dev, &bufs->wpp[i]) || + mtk_venc_mem_alloc(inst, dev, &bufs->wpp_nbm[i])) + goto err_alloc; + } + + for (i =3D 0; i < dpb_size; i++) { + if (mtk_venc_mem_alloc(inst, dev, &bufs->luma[i]) || + mtk_venc_mem_alloc(inst, dev, &bufs->chroma[i]) || + mtk_venc_mem_alloc(inst, dev, &bufs->sub_luma[i]) || + mtk_venc_mem_alloc(inst, dev, &bufs->sub_write[i]) || + mtk_venc_mem_alloc(inst, dev, &bufs->col_mv[i])) + goto err_alloc; + } + + /* the pps_buf and seq_buf are used by AP side only */ + inst->pps_buf.size =3D PPS_SIZE; + ret =3D mtk_vcodec_mem_alloc(inst->ctx, &inst->pps_buf); + if (ret) { + mtk_venc_err(inst->ctx, "cannot allocate pps_buf"); + goto err_alloc; + } + + inst->seq_buf.size =3D SEQ_HEADER_SIZE; + ret =3D mtk_vcodec_mem_alloc(inst->ctx, &inst->seq_buf); + if (ret) { + mtk_venc_err(inst->ctx, "cannot allocate seq_buf"); + goto err_alloc; + } + return 0; + +err_alloc: + venc_free_work_buf(inst); + return -ENOMEM; +} + +static int venc_set_param(void *handle, + enum venc_set_param_type type, + struct venc_enc_param *enc_prm) +{ + int ret =3D 0; + struct venc_inst *inst =3D (struct venc_inst *)handle; + + switch (type) { + case VENC_SET_PARAM_ENC: + if (WARN_ON(!inst->vsi)) + return -EINVAL; + inst->vsi->config.input_fourcc =3D enc_prm->input_yuv_fmt; + inst->vsi->config.bitrate =3D enc_prm->bitrate; + inst->vsi->config.pic_w =3D enc_prm->width; + inst->vsi->config.pic_h =3D enc_prm->height; + inst->vsi->config.buf_w =3D enc_prm->buf_width; + inst->vsi->config.buf_h =3D enc_prm->buf_height; + inst->vsi->config.gop_size =3D enc_prm->gop_size; + inst->vsi->config.framerate =3D enc_prm->frm_rate; + inst->vsi->config.intra_period =3D enc_prm->intra_period; + inst->vsi->config.profile =3D enc_prm->profile; + inst->vsi->config.level =3D enc_prm->level; + + ret =3D vpu_enc_set_param(&inst->vpu_inst, type, enc_prm); + if (ret) + break; + + if (inst->work_buf_allocated) { + venc_free_work_buf(inst); + inst->work_buf_allocated =3D false; + } + ret =3D venc_alloc_work_buf(inst); + if (ret) + break; + inst->work_buf_allocated =3D true; + break; + case VENC_SET_PARAM_PREPEND_HEADER: + inst->prepend_hdr =3D 1; + break; + default: + ret =3D vpu_enc_set_param(&inst->vpu_inst, type, enc_prm); + break; + } + + return ret; +} + +static int venc_deinit(void *handle) +{ + int ret =3D 0; + struct venc_inst *inst =3D (struct venc_inst *)handle; + + ret =3D vpu_enc_deinit(&inst->vpu_inst); + + if (inst->work_buf_allocated) + venc_free_work_buf(inst); + + kfree(inst); + + return ret; +} + +const struct venc_common_if venc_if =3D { + .init =3D venc_init, + .encode =3D venc_encode, + .set_param =3D venc_set_param, + .deinit =3D venc_deinit, +}; diff --git a/drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_= if.c b/drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c index d2f4d732d2f7..320c505cdb21 100644 --- a/drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c +++ b/drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c @@ -723,9 +723,9 @@ static void h264_enc_set_vsi_configs(struct venc_h264_i= nst *inst, inst->vsi->config.framerate =3D enc_prm->frm_rate; inst->vsi->config.intra_period =3D enc_prm->intra_period; inst->vsi->config.profile =3D - h264_get_profile(inst, enc_prm->h264_profile); + h264_get_profile(inst, enc_prm->profile); inst->vsi->config.level =3D - h264_get_level(inst, enc_prm->h264_level); + h264_get_level(inst, enc_prm->level); inst->vsi->config.wfd =3D 0; } =20 @@ -742,9 +742,9 @@ static void h264_enc_set_vsi_34_configs(struct venc_h26= 4_inst *inst, inst->vsi_34->config.framerate =3D enc_prm->frm_rate; inst->vsi_34->config.intra_period =3D enc_prm->intra_period; inst->vsi_34->config.profile =3D - h264_get_profile(inst, enc_prm->h264_profile); + h264_get_profile(inst, enc_prm->profile); inst->vsi_34->config.level =3D - h264_get_level(inst, enc_prm->h264_level); + h264_get_level(inst, enc_prm->level); inst->vsi_34->config.wfd =3D 0; } =20 diff --git a/drivers/media/platform/mediatek/vcodec/encoder/venc_drv_if.h b= /drivers/media/platform/mediatek/vcodec/encoder/venc_drv_if.h index 889440a436b6..3c2a1b5e9312 100644 --- a/drivers/media/platform/mediatek/vcodec/encoder/venc_drv_if.h +++ b/drivers/media/platform/mediatek/vcodec/encoder/venc_drv_if.h @@ -66,8 +66,8 @@ enum venc_set_param_type { * struct venc_enc_prm - encoder settings for VENC_SET_PARAM_ENC used in * venc_if_set_param() * @input_fourcc: input yuv format - * @h264_profile: V4L2 defined H.264 profile - * @h264_level: V4L2 defined H.264 level + * @profile: V4L2 defined profile + * @level: V4L2 defined level * @width: image width * @height: image height * @buf_width: buffer width @@ -79,8 +79,8 @@ enum venc_set_param_type { */ struct venc_enc_param { enum venc_yuv_fmt input_yuv_fmt; - unsigned int h264_profile; - unsigned int h264_level; + unsigned int profile; + unsigned int level; unsigned int width; unsigned int height; unsigned int buf_width; @@ -107,9 +107,11 @@ struct venc_frame_info { /* * struct venc_frm_buf - frame buffer information used in venc_if_encode() * @fb_addr: plane frame buffer addresses + * @num_planes: number of planes */ struct venc_frm_buf { struct mtk_vcodec_fb fb_addr[MTK_VCODEC_MAX_PLANES]; + unsigned int num_planes; }; =20 /* @@ -124,6 +126,7 @@ struct venc_done_result { =20 extern const struct venc_common_if venc_h264_if; extern const struct venc_common_if venc_vp8_if; +extern const struct venc_common_if venc_if; =20 /* * venc_if_init - Create the driver handle --=20 2.45.2 From nobody Mon Jun 8 07:22:55 2026 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D7113B71B6; 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charset="utf-8" The existing encoder firmware interface implied just one type of codec: H.264. Future encoders may support additional codecs; however adding entire sets of interfaces for them is not scalable. Instead, a new "common" firmware interface is defined for non codec specific messages. The new messages encapsulate the old ones for backward compatibility. This patch adds support for these new messages. Signed-off-by: Irui Wang Reviewed-by: Nicolas Dufresne --- .../vcodec/encoder/mtk_vcodec_enc_drv.h | 3 ++ .../mediatek/vcodec/encoder/venc_drv_if.c | 3 +- .../mediatek/vcodec/encoder/venc_ipi_msg.h | 26 +++++++++++++++ .../mediatek/vcodec/encoder/venc_vpu_if.c | 33 ++++++++++++------- 4 files changed, 52 insertions(+), 13 deletions(-) diff --git a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_= drv.h b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h index 029133e48073..8a69168c350e 100644 --- a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h +++ b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h @@ -16,6 +16,7 @@ =20 #define MTK_ENC_CTX_IS_EXT(ctx) ((ctx)->dev->venc_pdata->uses_ext) #define MTK_ENC_IOVA_IS_34BIT(ctx) ((ctx)->dev->venc_pdata->uses_34bit) +#define MTK_ENC_DRV_IS_COMM(ctx) (((ctx)->dev->venc_pdata->uses_common_fw_= iface)) =20 /** * struct mtk_vcodec_enc_pdata - compatible data for each IC @@ -30,6 +31,7 @@ * @num_output_formats: number of entries in output_formats * @core_id: stand for h264 or vp8 encode index * @uses_34bit: whether the encoder uses 34-bit iova + * @uses_common_fw_iface: whether the encoder uses common driver interface * @fw_type: firmware type (VPU, SCP, or VCP) * @fw_init: firmware-specific initialization callback * @ipi_id: IPI ID for encoder communication with firmware @@ -45,6 +47,7 @@ struct mtk_vcodec_enc_pdata { size_t num_output_formats; u8 core_id; bool uses_34bit; + bool uses_common_fw_iface; enum mtk_vcodec_fw_type fw_type; struct mtk_vcodec_fw *(*fw_init)(void *priv, enum mtk_vcodec_fw_use fw_us= e); int ipi_id; diff --git a/drivers/media/platform/mediatek/vcodec/encoder/venc_drv_if.c b= /drivers/media/platform/mediatek/vcodec/encoder/venc_drv_if.c index e83747b8d69a..f8c9349c18c0 100644 --- a/drivers/media/platform/mediatek/vcodec/encoder/venc_drv_if.c +++ b/drivers/media/platform/mediatek/vcodec/encoder/venc_drv_if.c @@ -19,13 +19,14 @@ int venc_if_init(struct mtk_vcodec_enc_ctx *ctx, unsigned int fourcc) { int ret =3D 0; + const bool uses_common_fw_iface =3D MTK_ENC_DRV_IS_COMM(ctx); =20 switch (fourcc) { case V4L2_PIX_FMT_VP8: ctx->enc_if =3D &venc_vp8_if; break; case V4L2_PIX_FMT_H264: - ctx->enc_if =3D &venc_h264_if; + ctx->enc_if =3D uses_common_fw_iface ? &venc_if : &venc_h264_if; break; default: return -EINVAL; diff --git a/drivers/media/platform/mediatek/vcodec/encoder/venc_ipi_msg.h = b/drivers/media/platform/mediatek/vcodec/encoder/venc_ipi_msg.h index bb16d96a7f57..ce3c2c8059fb 100644 --- a/drivers/media/platform/mediatek/vcodec/encoder/venc_ipi_msg.h +++ b/drivers/media/platform/mediatek/vcodec/encoder/venc_ipi_msg.h @@ -45,6 +45,20 @@ struct venc_ap_ipi_msg_init { uint64_t venc_inst; }; =20 +/** + * struct venc_ap_ipi_msg_init_comm - AP to VPU init cmd structure + * @base: AP to VPU init cmd structure + * @codec_type: encoder type + * @reserved: reserved field + * @shared_iova: shared iova + */ +struct venc_ap_ipi_msg_init_comm { + struct venc_ap_ipi_msg_init base; + u32 codec_type; + u32 reserved; + u64 shared_iova; +}; + /** * struct venc_ap_ipi_msg_set_param - AP to VPU set_param cmd structure * @msg_id: message id (AP_IPIMSG_XXX_ENC_SET_PARAM) @@ -175,6 +189,18 @@ struct venc_vpu_ipi_msg_init { uint32_t venc_abi_version; }; =20 +/** + * struct venc_vpu_ipi_msg_init_comm - VPU ack AP init cmd structure + * @init_ack: AP init cmd structure + * @vpu_vsi_addr: VSI address from VPU + * @reserved: reserved field + */ +struct venc_vpu_ipi_msg_init_comm { + struct venc_vpu_ipi_msg_init init_ack; + u32 vpu_vsi_addr; + u32 reserved; +}; + /** * struct venc_vpu_ipi_msg_set_param - VPU ack AP set_param cmd structure * @msg_id: message id (VPU_IPIMSG_XXX_ENC_SET_PARAM_DONE) diff --git a/drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c b= /drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c index 0c825aa7224d..7772b8442ebc 100644 --- a/drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c +++ b/drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c @@ -10,24 +10,25 @@ =20 static void handle_enc_init_msg(struct venc_vpu_inst *vpu, const void *dat= a) { - const struct venc_vpu_ipi_msg_init *msg =3D data; + const struct venc_vpu_ipi_msg_init_comm *msg =3D data; + struct mtk_vcodec_fw *fw =3D vpu->ctx->dev->fw_handler; =20 - vpu->inst_addr =3D msg->vpu_inst_addr; - vpu->vsi =3D mtk_vcodec_fw_map_dm_addr(vpu->ctx->dev->fw_handler, - msg->vpu_inst_addr); + vpu->inst_addr =3D msg->init_ack.vpu_inst_addr; + vpu->vsi =3D mtk_vcodec_fw_map_dm_addr(fw, vpu->inst_addr); =20 /* Firmware version field value is unspecified on MT8173. */ - if (mtk_vcodec_fw_get_type(vpu->ctx->dev->fw_handler) =3D=3D VPU) + if (mtk_vcodec_fw_get_type(fw) =3D=3D VPU) return; =20 /* Check firmware version. */ - mtk_venc_debug(vpu->ctx, "firmware version: 0x%x\n", msg->venc_abi_versio= n); - switch (msg->venc_abi_version) { + mtk_venc_debug(vpu->ctx, "firmware version: 0x%x\n", + msg->init_ack.venc_abi_version); + switch (msg->init_ack.venc_abi_version) { case 1: break; default: mtk_venc_err(vpu->ctx, "unhandled firmware version 0x%x\n", - msg->venc_abi_version); + msg->init_ack.venc_abi_version); vpu->failure =3D 1; break; } @@ -133,7 +134,8 @@ static int vpu_enc_send_msg(struct venc_vpu_inst *vpu, = void *msg, int vpu_enc_init(struct venc_vpu_inst *vpu) { int status; - struct venc_ap_ipi_msg_init out =3D { }; + size_t msg_size; + struct venc_ap_ipi_msg_init_comm out =3D { }; =20 init_waitqueue_head(&vpu->wq_hd); vpu->signaled =3D 0; @@ -149,9 +151,16 @@ int vpu_enc_init(struct venc_vpu_inst *vpu) return -EINVAL; } =20 - out.msg_id =3D AP_IPIMSG_ENC_INIT; - out.venc_inst =3D (unsigned long)vpu; - if (vpu_enc_send_msg(vpu, &out, sizeof(out))) { + out.base.msg_id =3D AP_IPIMSG_ENC_INIT; + out.base.venc_inst =3D (unsigned long)vpu; + if (MTK_ENC_DRV_IS_COMM(vpu->ctx)) { + out.codec_type =3D vpu->ctx->q_data[MTK_Q_DATA_DST].fmt->fourcc; + msg_size =3D sizeof(struct venc_ap_ipi_msg_init_comm); + } else { + msg_size =3D sizeof(struct venc_ap_ipi_msg_init); + } + + if (vpu_enc_send_msg(vpu, &out, msg_size)) { mtk_venc_err(vpu->ctx, "AP_IPIMSG_ENC_INIT fail"); return -EINVAL; } --=20 2.45.2 From nobody Mon Jun 8 07:22:55 2026 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ACEAB3D3D18; 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charset="utf-8" Adapt the encoder driver to support VCP firmware interface. Use platform data fw_type to identify VCP firmware and perform VCP-specific operations: - Allocate RC buffers using the VCP device - Send shared memory address to VCP firmware - Map the encoder VSI address to the CPU address space using the VCP shared memory address. Signed-off-by: Irui Wang --- .../mediatek/vcodec/common/mtk_vcodec_fw.c | 6 +++++ .../mediatek/vcodec/common/mtk_vcodec_fw.h | 1 + .../vcodec/common/mtk_vcodec_fw_priv.h | 1 + .../vcodec/common/mtk_vcodec_fw_vcp.c | 6 +++++ .../vcodec/encoder/venc/venc_common_if.c | 22 ++++++++++++++----- .../mediatek/vcodec/encoder/venc_vpu_if.c | 16 ++++++++++++-- 6 files changed, 44 insertions(+), 8 deletions(-) diff --git a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.c = b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.c index 9df64200d933..7619ccd1f538 100644 --- a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.c +++ b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.c @@ -90,3 +90,9 @@ int mtk_vcodec_fw_get_type(struct mtk_vcodec_fw *fw) return fw->type; } EXPORT_SYMBOL_GPL(mtk_vcodec_fw_get_type); + +struct device *mtk_vcodec_fw_get_dev(struct mtk_vcodec_fw *fw) +{ + return fw->ops->get_fw_dev(fw); +} +EXPORT_SYMBOL_GPL(mtk_vcodec_fw_get_dev); diff --git a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.h = b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.h index 142e2e87905c..8ff6fcc114e3 100644 --- a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.h +++ b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.h @@ -42,5 +42,6 @@ int mtk_vcodec_fw_ipi_send(struct mtk_vcodec_fw *fw, int = id, void *buf, unsigned int len, unsigned int wait); int mtk_vcodec_fw_get_type(struct mtk_vcodec_fw *fw); int mtk_vcodec_fw_get_ipi(enum mtk_vcodec_fw_type type, int hw_id); +struct device *mtk_vcodec_fw_get_dev(struct mtk_vcodec_fw *fw); =20 #endif /* _MTK_VCODEC_FW_H_ */ diff --git a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_pr= iv.h b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_priv.h index 0a2a9b010244..710c83c871f4 100644 --- a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_priv.h +++ b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_priv.h @@ -29,6 +29,7 @@ struct mtk_vcodec_fw_ops { int (*ipi_send)(struct mtk_vcodec_fw *fw, int id, void *buf, unsigned int len, unsigned int wait); void (*release)(struct mtk_vcodec_fw *fw); + struct device *(*get_fw_dev)(struct mtk_vcodec_fw *fw); }; =20 #if IS_ENABLED(CONFIG_VIDEO_MEDIATEK_VCODEC_VPU) diff --git a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_vc= p.c b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_vcp.c index 061a61bda33f..72627fef0ac5 100644 --- a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_vcp.c +++ b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_vcp.c @@ -494,6 +494,11 @@ static void mtk_vcodec_vcp_release(struct mtk_vcodec_f= w *fw) fw->vcp->is_register_done =3D false; } =20 +static struct device *mtk_vcodec_vcp_get_fw_dev(struct mtk_vcodec_fw *fw) +{ + return fw->vcp->vcp_device->dev; +} + static const struct mtk_vcodec_fw_ops mtk_vcodec_vcp_msg =3D { .load_firmware =3D mtk_vcodec_vcp_load_firmware, .get_vdec_capa =3D mtk_vcodec_vcp_get_vdec_capa, @@ -501,6 +506,7 @@ static const struct mtk_vcodec_fw_ops mtk_vcodec_vcp_ms= g =3D { .ipi_register =3D mtk_vcodec_vcp_set_ipi_register, .ipi_send =3D mtk_vcodec_vcp_ipi_send, .release =3D mtk_vcodec_vcp_release, + .get_fw_dev =3D mtk_vcodec_vcp_get_fw_dev, }; =20 struct mtk_vcodec_fw *mtk_vcodec_fw_vcp_init(void *priv, enum mtk_vcodec_f= w_use fw_use) diff --git a/drivers/media/platform/mediatek/vcodec/encoder/venc/venc_commo= n_if.c b/drivers/media/platform/mediatek/vcodec/encoder/venc/venc_common_if= .c index 0efb13aef8d6..5ee138f0b2e7 100644 --- a/drivers/media/platform/mediatek/vcodec/encoder/venc/venc_common_if.c +++ b/drivers/media/platform/mediatek/vcodec/encoder/venc/venc_common_if.c @@ -481,7 +481,11 @@ static void venc_free_rc_buf(struct venc_inst *inst, int i; struct device *dev; =20 - dev =3D &inst->ctx->dev->plat_dev->dev; + if (inst->ctx->dev->venc_pdata->fw_type =3D=3D VCP) + dev =3D mtk_vcodec_fw_get_dev(inst->ctx->dev->fw_handler); + else + dev =3D &inst->ctx->dev->plat_dev->dev; + mtk_venc_mem_free(inst, dev, &bufs->rc_code); =20 for (i =3D 0; i < core_num; i++) @@ -530,12 +534,18 @@ static int venc_alloc_rc_buf(struct venc_inst *inst, struct device *dev; void *tmp_va; =20 - dev =3D &inst->ctx->dev->plat_dev->dev; - if (mtk_venc_mem_alloc(inst, dev, &bufs->rc_code)) - return -ENOMEM; + if (inst->ctx->dev->venc_pdata->fw_type =3D=3D VCP) { + dev =3D mtk_vcodec_fw_get_dev(fw); + if (mtk_venc_mem_alloc(inst, dev, &bufs->rc_code)) + return -ENOMEM; + } else { + dev =3D &inst->ctx->dev->plat_dev->dev; + if (mtk_venc_mem_alloc(inst, dev, &bufs->rc_code)) + return -ENOMEM; =20 - tmp_va =3D mtk_vcodec_fw_map_dm_addr(fw, bufs->rc_code.pa); - memcpy(bufs->rc_code.va, tmp_va, bufs->rc_code.size); + tmp_va =3D mtk_vcodec_fw_map_dm_addr(fw, bufs->rc_code.pa); + memcpy(bufs->rc_code.va, tmp_va, bufs->rc_code.size); + } =20 for (i =3D 0; i < core_num; i++) { if (mtk_venc_mem_alloc(inst, dev, &bufs->rc_info[i])) diff --git a/drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c b= /drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c index 7772b8442ebc..1da9043fd4f6 100644 --- a/drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c +++ b/drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c @@ -8,16 +8,26 @@ #include "venc_ipi_msg.h" #include "venc_vpu_if.h" =20 +#define VSI_OFFSET_MASK 0x0FFFFFFF + static void handle_enc_init_msg(struct venc_vpu_inst *vpu, const void *dat= a) { const struct venc_vpu_ipi_msg_init_comm *msg =3D data; struct mtk_vcodec_fw *fw =3D vpu->ctx->dev->fw_handler; + u64 pa_start, vsi_offset; =20 vpu->inst_addr =3D msg->init_ack.vpu_inst_addr; - vpu->vsi =3D mtk_vcodec_fw_map_dm_addr(fw, vpu->inst_addr); + + if (vpu->ctx->dev->venc_pdata->fw_type =3D=3D VCP) { + pa_start =3D (u64)fw->vcp->iova_addr; + vsi_offset =3D (msg->vpu_vsi_addr & VSI_OFFSET_MASK) - (pa_start & VSI_O= FFSET_MASK); + vpu->vsi =3D mtk_vcodec_fw_map_dm_addr(fw, ENCODER_MEM) + vsi_offset; + } else { + vpu->vsi =3D mtk_vcodec_fw_map_dm_addr(fw, msg->vpu_vsi_addr); + } =20 /* Firmware version field value is unspecified on MT8173. */ - if (mtk_vcodec_fw_get_type(fw) =3D=3D VPU) + if (vpu->ctx->dev->venc_pdata->fw_type =3D=3D VPU) return; =20 /* Check firmware version. */ @@ -155,6 +165,8 @@ int vpu_enc_init(struct venc_vpu_inst *vpu) out.base.venc_inst =3D (unsigned long)vpu; if (MTK_ENC_DRV_IS_COMM(vpu->ctx)) { out.codec_type =3D vpu->ctx->q_data[MTK_Q_DATA_DST].fmt->fourcc; + if (vpu->ctx->dev->venc_pdata->fw_type =3D=3D VCP) + out.shared_iova =3D vpu->ctx->dev->fw_handler->vcp->iova_addr; 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Fri, 05 Jun 2026 17:35:41 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by MTKMBS09N1.mediatek.inc (172.21.101.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Fri, 5 Jun 2026 17:35:39 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Fri, 5 Jun 2026 17:35:38 +0800 From: Irui Wang To: Hans Verkuil , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Krzysztof Kozlowski , , , Tiffany Lin , kyrie wu CC: Yunfei Dong , Maoguang Meng , Longfei Wang , Irui Wang , , , , , , Subject: [PATCH v7 6/6] media: mediatek: encoder: Add MT8196 encoder compatible data Date: Fri, 5 Jun 2026 17:35:18 +0800 Message-ID: <20260605093519.13695-7-irui.wang@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20260605093519.13695-1-irui.wang@mediatek.com> References: <20260605093519.13695-1-irui.wang@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" MT8196 encoder use common firmware interface, add compatible data to support MT8196 encoding, and need set dma mask to support 34bit. Signed-off-by: Irui Wang --- .../vcodec/encoder/mtk_vcodec_enc_drv.c | 22 +++++++++++++++++++ .../vcodec/encoder/mtk_vcodec_enc_drv.h | 2 ++ 2 files changed, 24 insertions(+) diff --git a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_= drv.c b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c index 5f1feb3b07a6..bc6dfb564026 100644 --- a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c +++ b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c @@ -20,6 +20,8 @@ #include "mtk_vcodec_enc_pm.h" #include "../common/mtk_vcodec_intr.h" =20 +#define VENC_DMA_BIT_MASK 34 + static const struct mtk_video_fmt mtk_video_formats_output[] =3D { { .fourcc =3D V4L2_PIX_FMT_NV12M, @@ -298,6 +300,9 @@ static int mtk_vcodec_probe(struct platform_device *pde= v) goto err_res; } =20 + if (dev->venc_pdata->set_dma_bit_mask) + dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(VENC_DMA_BIT_MASK)); + mutex_init(&dev->enc_mutex); mutex_init(&dev->dev_mutex); spin_lock_init(&dev->dev_ctx_lock); @@ -461,6 +466,22 @@ static const struct mtk_vcodec_enc_pdata mt8195_pdata = =3D { .fw_init =3D mtk_vcodec_fw_scp_init, }; =20 +static const struct mtk_vcodec_enc_pdata mt8196_pdata =3D { + .venc_model_num =3D 8196, + .capture_formats =3D mtk_video_formats_capture_h264, + .num_capture_formats =3D ARRAY_SIZE(mtk_video_formats_capture_h264), + .output_formats =3D mtk_video_formats_output, + .num_output_formats =3D ARRAY_SIZE(mtk_video_formats_output), + .min_bitrate =3D 64, + .max_bitrate =3D 100000000, + .core_id =3D VENC_SYS, + .uses_common_fw_iface =3D true, + .set_dma_bit_mask =3D true, + .fw_type =3D VCP, + .fw_init =3D mtk_vcodec_fw_vcp_init, + .ipi_id =3D VCP_IPI_ENCODER, +}; + static const struct of_device_id mtk_vcodec_enc_match[] =3D { {.compatible =3D "mediatek,mt8173-vcodec-enc", .data =3D &mt8173_avc_pdata}, @@ -470,6 +491,7 @@ static const struct of_device_id mtk_vcodec_enc_match[]= =3D { {.compatible =3D "mediatek,mt8188-vcodec-enc", .data =3D &mt8188_pdata}, {.compatible =3D "mediatek,mt8192-vcodec-enc", .data =3D &mt8192_pdata}, {.compatible =3D "mediatek,mt8195-vcodec-enc", .data =3D &mt8195_pdata}, + {.compatible =3D "mediatek,mt8196-vcodec-enc", .data =3D &mt8196_pdata}, {}, }; MODULE_DEVICE_TABLE(of, mtk_vcodec_enc_match); diff --git a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_= drv.h b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h index 8a69168c350e..1aad27008ce6 100644 --- a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h +++ b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h @@ -32,6 +32,7 @@ * @core_id: stand for h264 or vp8 encode index * @uses_34bit: whether the encoder uses 34-bit iova * @uses_common_fw_iface: whether the encoder uses common driver interface + * @set_dma_bit_mask: whether the encoder need set extra DMA bit mask * @fw_type: firmware type (VPU, SCP, or VCP) * @fw_init: firmware-specific initialization callback * @ipi_id: IPI ID for encoder communication with firmware @@ -48,6 +49,7 @@ struct mtk_vcodec_enc_pdata { u8 core_id; bool uses_34bit; bool uses_common_fw_iface; + bool set_dma_bit_mask; enum mtk_vcodec_fw_type fw_type; struct mtk_vcodec_fw *(*fw_init)(void *priv, enum mtk_vcodec_fw_use fw_us= e); int ipi_id; --=20 2.45.2