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Peter Anvin" , Tony Luck , "Rafael J. Wysocki" , Viresh Kumar , Guenter Roeck , Daniel Lezcano , Zhang Rui , Lukasz Luba Subject: [PATCH 1/8] x86/msr: Switch rdmsr_on_cpu() to return a 64-bit quantity Date: Fri, 5 Jun 2026 09:08:19 +0200 Message-ID: <20260605070826.2995913-2-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260605070826.2995913-1-jgross@suse.com> References: <20260605070826.2995913-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam-Flag: NO X-Spam-Score: -6.80 X-Spamd-Result: default: False [-6.80 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:helo,suse.com:email,suse.com:mid]; ARC_NA(0.00)[]; MIME_TRACE(0.00)[0:+]; TO_DN_SOME(0.00)[]; RCPT_COUNT_TWELVE(0.00)[18]; RCVD_VIA_SMTP_AUTH(0.00)[]; FUZZY_RATELIMITED(0.00)[rspamd.com]; FROM_HAS_DN(0.00)[]; TO_MATCH_ENVRCPT_ALL(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; R_RATELIMIT(0.00)[to_ip_from(RLfdszjqhz8kzzb9uwpzdm8png)]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; RCVD_TLS_ALL(0.00)[] X-Spam-Level: Content-Type: text/plain; charset="utf-8" In order to prepare retiring rdmsrq_on_cpu() switch rdmsr_on_cpu() to have the same interface as rdmsrq_on_cpu(). Switch all rdmsr_on_cpu() callers to use the new interface. Signed-off-by: Juergen Gross --- arch/x86/include/asm/msr.h | 8 ++--- arch/x86/kernel/cpu/mce/amd.c | 6 ++-- arch/x86/kernel/cpu/mce/inject.c | 8 ++--- arch/x86/lib/msr-smp.c | 5 ++- drivers/cpufreq/amd_freq_sensitivity.c | 4 +-- drivers/cpufreq/p4-clockmod.c | 32 ++++++++++---------- drivers/cpufreq/speedstep-centrino.c | 27 +++++++++-------- drivers/hwmon/coretemp.c | 12 ++++---- drivers/thermal/intel/x86_pkg_temp_thermal.c | 22 ++++++++------ 9 files changed, 63 insertions(+), 61 deletions(-) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 9c2ea29e12a9..fcdaeddf4337 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -256,7 +256,7 @@ int msr_set_bit(u32 msr, u8 bit); int msr_clear_bit(u32 msr, u8 bit); =20 #ifdef CONFIG_SMP -int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); +int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); int rdmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); int wrmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 q); @@ -269,9 +269,9 @@ int wrmsrq_safe_on_cpu(unsigned int cpu, u32 msr_no, u6= 4 q); int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); #else /* CONFIG_SMP */ -static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *= h) +static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) { - rdmsr(msr_no, *l, *h); + rdmsrq(msr_no, *q); return 0; } static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) @@ -292,7 +292,7 @@ static inline int wrmsrq_on_cpu(unsigned int cpu, u32 m= sr_no, u64 q) static inline void rdmsr_on_cpus(const struct cpumask *m, u32 msr_no, struct msr __percpu *msrs) { - rdmsr_on_cpu(0, msr_no, raw_cpu_ptr(&msrs->l), raw_cpu_ptr(&msrs->h)); + rdmsr_on_cpu(0, msr_no, raw_cpu_ptr(&msrs->q)); } static inline void wrmsr_on_cpus(const struct cpumask *m, u32 msr_no, struct msr __percpu *msrs) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 6605a0224659..580e90e74e9e 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -969,13 +969,13 @@ store_threshold_limit(struct threshold_block *b, cons= t char *buf, size_t size) =20 static ssize_t show_error_count(struct threshold_block *b, char *buf) { - u32 lo, hi; + struct msr val; =20 /* CPU might be offline by now */ - if (rdmsr_on_cpu(b->cpu, b->address, &lo, &hi)) + if (rdmsr_on_cpu(b->cpu, b->address, &val.q)) return -ENODEV; =20 - return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) - + return sprintf(buf, "%u\n", ((val.h & THRESHOLD_MAX) - (THRESHOLD_MAX - b->threshold_limit))); } =20 diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inj= ect.c index d02c4f556cd0..fa13a8a4946b 100644 --- a/arch/x86/kernel/cpu/mce/inject.c +++ b/arch/x86/kernel/cpu/mce/inject.c @@ -316,18 +316,18 @@ static struct notifier_block inject_nb =3D { */ static int toggle_hw_mce_inject(unsigned int cpu, bool enable) { - u32 l, h; + struct msr val; int err; =20 - err =3D rdmsr_on_cpu(cpu, MSR_K7_HWCR, &l, &h); + err =3D rdmsr_on_cpu(cpu, MSR_K7_HWCR, &val.q); if (err) { pr_err("%s: error reading HWCR\n", __func__); return err; } =20 - enable ? (l |=3D BIT(18)) : (l &=3D ~BIT(18)); + enable ? (val.l |=3D BIT(18)) : (val.l &=3D ~BIT(18)); =20 - err =3D wrmsr_on_cpu(cpu, MSR_K7_HWCR, l, h); + err =3D wrmsr_on_cpu(cpu, MSR_K7_HWCR, val.l, val.h); if (err) pr_err("%s: error writing HWCR\n", __func__); =20 diff --git a/arch/x86/lib/msr-smp.c b/arch/x86/lib/msr-smp.c index b8f63419e6ae..6e04aabda863 100644 --- a/arch/x86/lib/msr-smp.c +++ b/arch/x86/lib/msr-smp.c @@ -31,7 +31,7 @@ static void __wrmsr_on_cpu(void *info) wrmsr(rv->msr_no, reg->l, reg->h); } =20 -int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) +int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) { int err; struct msr_info rv; @@ -40,8 +40,7 @@ int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u3= 2 *h) =20 rv.msr_no =3D msr_no; err =3D smp_call_function_single(cpu, __rdmsr_on_cpu, &rv, 1); - *l =3D rv.reg.l; - *h =3D rv.reg.h; + *q =3D rv.reg.q; =20 return err; } diff --git a/drivers/cpufreq/amd_freq_sensitivity.c b/drivers/cpufreq/amd_f= req_sensitivity.c index 13fed4b9e02b..63896478dcab 100644 --- a/drivers/cpufreq/amd_freq_sensitivity.c +++ b/drivers/cpufreq/amd_freq_sensitivity.c @@ -52,9 +52,9 @@ static unsigned int amd_powersave_bias_target(struct cpuf= req_policy *policy, return freq_next; =20 rdmsr_on_cpu(policy->cpu, MSR_AMD64_FREQ_SENSITIVITY_ACTUAL, - &actual.l, &actual.h); + &actual.q); rdmsr_on_cpu(policy->cpu, MSR_AMD64_FREQ_SENSITIVITY_REFERENCE, - &reference.l, &reference.h); + &reference.q); actual.h &=3D 0x00ffffff; reference.h &=3D 0x00ffffff; =20 diff --git a/drivers/cpufreq/p4-clockmod.c b/drivers/cpufreq/p4-clockmod.c index 69c19233fcd4..393c4a5d2021 100644 --- a/drivers/cpufreq/p4-clockmod.c +++ b/drivers/cpufreq/p4-clockmod.c @@ -51,24 +51,24 @@ static unsigned int cpufreq_p4_get(unsigned int cpu); =20 static int cpufreq_p4_setdc(unsigned int cpu, unsigned int newstate) { - u32 l, h; + struct msr val; =20 if ((newstate > DC_DISABLE) || (newstate =3D=3D DC_RESV)) return -EINVAL; =20 - rdmsr_on_cpu(cpu, MSR_IA32_THERM_STATUS, &l, &h); + rdmsr_on_cpu(cpu, MSR_IA32_THERM_STATUS, &val.q); =20 - if (l & 0x01) + if (val.l & 0x01) pr_debug("CPU#%d currently thermal throttled\n", cpu); =20 if (has_N44_O17_errata[cpu] && (newstate =3D=3D DC_25PT || newstate =3D=3D DC_DFLT)) newstate =3D DC_38PT; =20 - rdmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, &l, &h); + rdmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, &val.q); if (newstate =3D=3D DC_DISABLE) { pr_debug("CPU#%d disabling modulation\n", cpu); - wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, l & ~(1<<4), h); + wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, val.l & ~(1<<4), val.h); } else { pr_debug("CPU#%d setting duty cycle to %d%%\n", cpu, ((125 * newstate) / 10)); @@ -77,9 +77,9 @@ static int cpufreq_p4_setdc(unsigned int cpu, unsigned in= t newstate) * bits 3-1 : duty cycle * bit 0 : reserved */ - l =3D (l & ~14); - l =3D l | (1<<4) | ((newstate & 0x7)<<1); - wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, l, h); + val.l =3D (val.l & ~14); + val.l =3D val.l | (1<<4) | ((newstate & 0x7)<<1); + wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, val.l, val.h); } =20 return 0; @@ -205,18 +205,18 @@ static int cpufreq_p4_cpu_init(struct cpufreq_policy = *policy) =20 static unsigned int cpufreq_p4_get(unsigned int cpu) { - u32 l, h; + struct msr val; =20 - rdmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, &l, &h); + rdmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, &val.q); =20 - if (l & 0x10) { - l =3D l >> 1; - l &=3D 0x7; + if (val.l & 0x10) { + val.l =3D val.l >> 1; + val.l &=3D 0x7; } else - l =3D DC_DISABLE; + val.l =3D DC_DISABLE; =20 - if (l !=3D DC_DISABLE) - return stock_freq * l / 8; + if (val.l !=3D DC_DISABLE) + return stock_freq * val.l / 8; =20 return stock_freq; } diff --git a/drivers/cpufreq/speedstep-centrino.c b/drivers/cpufreq/speedst= ep-centrino.c index 3e6e85a92212..b74c85128377 100644 --- a/drivers/cpufreq/speedstep-centrino.c +++ b/drivers/cpufreq/speedstep-centrino.c @@ -322,11 +322,11 @@ static unsigned extract_clock(unsigned msr, unsigned = int cpu, int failsafe) /* Return the current CPU frequency in kHz */ static unsigned int get_cur_freq(unsigned int cpu) { - unsigned l, h; + struct msr val; unsigned clock_freq; =20 - rdmsr_on_cpu(cpu, MSR_IA32_PERF_STATUS, &l, &h); - clock_freq =3D extract_clock(l, cpu, 0); + rdmsr_on_cpu(cpu, MSR_IA32_PERF_STATUS, &val.q); + clock_freq =3D extract_clock(val.l, cpu, 0); =20 if (unlikely(clock_freq =3D=3D 0)) { /* @@ -335,8 +335,8 @@ static unsigned int get_cur_freq(unsigned int cpu) * P-state transition (like TM2). Get the last freq set=20 * in PERF_CTL. */ - rdmsr_on_cpu(cpu, MSR_IA32_PERF_CTL, &l, &h); - clock_freq =3D extract_clock(l, cpu, 1); + rdmsr_on_cpu(cpu, MSR_IA32_PERF_CTL, &val.q); + clock_freq =3D extract_clock(val.l, cpu, 1); } return clock_freq; } @@ -417,7 +417,8 @@ static void centrino_cpu_exit(struct cpufreq_policy *po= licy) */ static int centrino_target(struct cpufreq_policy *policy, unsigned int ind= ex) { - unsigned int msr, oldmsr =3D 0, h =3D 0, cpu =3D policy->cpu; + unsigned int msr, cpu =3D policy->cpu; + struct msr oldmsr =3D { .q =3D 0 }; int retval =3D 0; unsigned int j, first_cpu; struct cpufreq_frequency_table *op_points; @@ -459,22 +460,22 @@ static int centrino_target(struct cpufreq_policy *pol= icy, unsigned int index) msr =3D op_points->driver_data; =20 if (first_cpu) { - rdmsr_on_cpu(good_cpu, MSR_IA32_PERF_CTL, &oldmsr, &h); - if (msr =3D=3D (oldmsr & 0xffff)) { + rdmsr_on_cpu(good_cpu, MSR_IA32_PERF_CTL, &oldmsr.q); + if (msr =3D=3D (oldmsr.l & 0xffff)) { pr_debug("no change needed - msr was and needs " - "to be %x\n", oldmsr); + "to be %x\n", oldmsr.l); retval =3D 0; goto out; } =20 first_cpu =3D 0; /* all but 16 LSB are reserved, treat them with care */ - oldmsr &=3D ~0xffff; + oldmsr.l &=3D ~0xffff; msr &=3D 0xffff; - oldmsr |=3D msr; + oldmsr.l |=3D msr; } =20 - wrmsr_on_cpu(good_cpu, MSR_IA32_PERF_CTL, oldmsr, h); + wrmsr_on_cpu(good_cpu, MSR_IA32_PERF_CTL, oldmsr.l, oldmsr.h); if (policy->shared_type =3D=3D CPUFREQ_SHARED_TYPE_ANY) break; =20 @@ -490,7 +491,7 @@ static int centrino_target(struct cpufreq_policy *polic= y, unsigned int index) */ =20 for_each_cpu(j, covered_cpus) - wrmsr_on_cpu(j, MSR_IA32_PERF_CTL, oldmsr, h); + wrmsr_on_cpu(j, MSR_IA32_PERF_CTL, oldmsr.l, oldmsr.h); } retval =3D 0; =20 diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c index 6a0d94711ead..fa02960ffff5 100644 --- a/drivers/hwmon/coretemp.c +++ b/drivers/hwmon/coretemp.c @@ -356,15 +356,15 @@ static ssize_t show_label(struct device *dev, static ssize_t show_crit_alarm(struct device *dev, struct device_attribute *devattr, char *buf) { - u32 eax, edx; + struct msr val; struct temp_data *tdata =3D container_of(devattr, struct temp_data, sd_attrs[ATTR_CRIT_ALARM]); =20 mutex_lock(&tdata->update_lock); - rdmsr_on_cpu(tdata->cpu, tdata->status_reg, &eax, &edx); + rdmsr_on_cpu(tdata->cpu, tdata->status_reg, &val.q); mutex_unlock(&tdata->update_lock); =20 - return sprintf(buf, "%d\n", (eax >> 5) & 1); + return sprintf(buf, "%d\n", (val.l >> 5) & 1); } =20 static ssize_t show_tjmax(struct device *dev, @@ -398,7 +398,7 @@ static ssize_t show_ttarget(struct device *dev, static ssize_t show_temp(struct device *dev, struct device_attribute *devattr, char *buf) { - u32 eax, edx; + struct msr val; struct temp_data *tdata =3D container_of(devattr, struct temp_data, sd_at= trs[ATTR_TEMP]); int tjmax; =20 @@ -407,14 +407,14 @@ static ssize_t show_temp(struct device *dev, tjmax =3D get_tjmax(tdata, dev); /* Check whether the time interval has elapsed */ if (time_after(jiffies, tdata->last_updated + HZ)) { - rdmsr_on_cpu(tdata->cpu, tdata->status_reg, &eax, &edx); + rdmsr_on_cpu(tdata->cpu, tdata->status_reg, &val.q); /* * Ignore the valid bit. In all observed cases the register * value is either low or zero if the valid bit is 0. * Return it instead of reporting an error which doesn't * really help at all. */ - tdata->temp =3D tjmax - ((eax >> 16) & 0xff) * 1000; + tdata->temp =3D tjmax - ((val.l >> 16) & 0xff) * 1000; tdata->last_updated =3D jiffies; } =20 diff --git a/drivers/thermal/intel/x86_pkg_temp_thermal.c b/drivers/thermal= /intel/x86_pkg_temp_thermal.c index 540109761f0a..fc7dbba4f9ca 100644 --- a/drivers/thermal/intel/x86_pkg_temp_thermal.c +++ b/drivers/thermal/intel/x86_pkg_temp_thermal.c @@ -125,8 +125,9 @@ sys_set_trip_temp(struct thermal_zone_device *tzd, { struct zone_device *zonedev =3D thermal_zone_device_priv(tzd); unsigned int trip_index =3D THERMAL_TRIP_PRIV_TO_INT(trip->priv); - u32 l, h, mask, shift, intr; + u32 mask, shift, intr; int tj_max, val, ret; + struct msr v; =20 if (temp =3D=3D THERMAL_TEMP_INVALID) temp =3D 0; @@ -142,7 +143,7 @@ sys_set_trip_temp(struct thermal_zone_device *tzd, return -EINVAL; =20 ret =3D rdmsr_on_cpu(zonedev->cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, - &l, &h); + &v.q); if (ret < 0) return ret; =20 @@ -155,20 +156,20 @@ sys_set_trip_temp(struct thermal_zone_device *tzd, shift =3D THERM_SHIFT_THRESHOLD0; intr =3D THERM_INT_THRESHOLD0_ENABLE; } - l &=3D ~mask; + v.l &=3D ~mask; /* * When users space sets a trip temperature =3D=3D 0, which is indication * that, it is no longer interested in receiving notifications. */ if (!temp) { - l &=3D ~intr; + v.l &=3D ~intr; } else { - l |=3D val << shift; - l |=3D intr; + v.l |=3D val << shift; + v.l |=3D intr; } =20 return wrmsr_on_cpu(zonedev->cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, - l, h); + v.l, v.h); } =20 /* Thermal zone callback registry */ @@ -277,7 +278,8 @@ static int pkg_temp_thermal_trips_init(int cpu, int tj_= max, struct thermal_trip *trips, int num_trips) { unsigned long thres_reg_value; - u32 mask, shift, eax, edx; + u32 mask, shift; + struct msr val; int ret, i; =20 for (i =3D 0; i < num_trips; i++) { @@ -291,11 +293,11 @@ static int pkg_temp_thermal_trips_init(int cpu, int t= j_max, } =20 ret =3D rdmsr_on_cpu(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, - &eax, &edx); + &val.q); if (ret < 0) return ret; =20 - thres_reg_value =3D (eax & mask) >> shift; + thres_reg_value =3D (val.l & mask) >> shift; =20 trips[i].temperature =3D thres_reg_value ? tj_max - thres_reg_value * 1000 : THERMAL_TEMP_INVALID; --=20 2.54.0 From nobody Mon Jun 8 06:36:45 2026 Received: from smtp-out1.suse.de (smtp-out1.suse.de [195.135.223.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C75F44E045 for ; Fri, 5 Jun 2026 07:08:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.135.223.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780643328; cv=none; b=nSocAaeyvo0+pL+2rZECGGLFqj+1Qm+c6sKnfYfXPBfyqkrLKlqJIg/w7gzaEhdr9lg3E7fmwbReYge8w6xggwDA9Iq4eknLHxCZjUektZa8ThUFlUPQzPACzplYm30sXiijTt0wrsUeN/5P4r8wd6y1I7IMmGIfhlsWt0KOvVM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780643328; c=relaxed/simple; bh=43XmXWjuSra01MQPnCKH7CvkNgX2R5nVh2AxfG9stAE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DDC4RYTN/A4X9q1Nr1DwhG72WJGicpAI+HtvSrQd/2/EEEvxckVZWUYOYBHhemwv/6ds+bG8gO1vYNWA0OPrO53f85maQCVg3PqvLWNO5LdmOAwxXFUZiwh6hfTBVdoBCVtw5KkNIuId8uLOn7c1JxpBZPDRUYiDEFpxPxpr0S0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; arc=none smtp.client-ip=195.135.223.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Received: from imap1.dmz-prg2.suse.org (imap1.dmz-prg2.suse.org [IPv6:2a07:de40:b281:104:10:150:64:97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id AEFC96B110; Fri, 5 Jun 2026 07:08:41 +0000 (UTC) Authentication-Results: smtp-out1.suse.de; none Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id 057F7779A8; Fri, 5 Jun 2026 07:08:41 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id aYgvAPl1ImqSHQAAD6G6ig (envelope-from ); Fri, 05 Jun 2026 07:08:41 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org, linux-perf-users@vger.kernel.org, linux-edac@vger.kernel.org, linux-pm@vger.kernel.org, platform-driver-x86@vger.kernel.org Cc: Juergen Gross , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Thomas Gleixner , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Tony Luck , "Rafael J. Wysocki" , Viresh Kumar , Huang Rui , Mario Limonciello , Perry Yuan , K Prateek Nayak , Srinivas Pandruvada , Len Brown , Hans de Goede , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 2/8] x86/msr: Switch all callers of rdmsrq_on_cpu() to use rdmsr_on_cpu() Date: Fri, 5 Jun 2026 09:08:20 +0200 Message-ID: <20260605070826.2995913-3-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260605070826.2995913-1-jgross@suse.com> References: <20260605070826.2995913-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Queue-Id: AEFC96B110 X-Spam-Flag: NO X-Spam-Score: -4.00 X-Spam-Level: X-Rspamd-Action: no action X-Rspamd-Server: rspamd1.dmz-prg2.suse.org X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[] Content-Type: text/plain; charset="utf-8" Now that rdmsr_on_cpu() has the same interface as rdmsrq_on_cpu(), the callers of rdmsrq_on_cpu() can be switched to rdmsr_on_cpu() and rdmsrq_on_cpu() can be removed. At the same time switch the only user of rdmsrl_on_cpu() to rdmsr_on_cpu() and drop rdmsrl_on_cpu(), too. Signed-off-by: Juergen Gross --- arch/x86/events/intel/uncore_snbep.c | 2 +- arch/x86/include/asm/msr.h | 7 ------ arch/x86/kernel/cpu/intel_epb.c | 4 ++-- arch/x86/kernel/cpu/mce/inject.c | 4 ++-- arch/x86/kernel/cpu/microcode/intel.c | 2 +- arch/x86/lib/msr-smp.c | 15 ------------- drivers/cpufreq/acpi-cpufreq.c | 4 ++-- drivers/cpufreq/amd-pstate.c | 8 +++---- drivers/cpufreq/intel_pstate.c | 22 +++++++++---------- .../intel/uncore-frequency/uncore-frequency.c | 6 ++--- 10 files changed, 26 insertions(+), 48 deletions(-) diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/u= ncore_snbep.c index 215d33e260ed..fee94698b611 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -3695,7 +3695,7 @@ static int skx_msr_cpu_bus_read(int cpu, u64 *topolog= y) { u64 msr_value; =20 - if (rdmsrq_on_cpu(cpu, SKX_MSR_CPU_BUS_NUMBER, &msr_value) || + if (rdmsr_on_cpu(cpu, SKX_MSR_CPU_BUS_NUMBER, &msr_value) || !(msr_value & SKX_MSR_CPU_BUS_VALID_BIT)) return -ENXIO; =20 diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index fcdaeddf4337..8c96fc5c6169 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -258,7 +258,6 @@ int msr_clear_bit(u32 msr, u8 bit); #ifdef CONFIG_SMP int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); -int rdmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); int wrmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 q); void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr __pe= rcpu *msrs); void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr __pe= rcpu *msrs); @@ -279,11 +278,6 @@ static inline int wrmsr_on_cpu(unsigned int cpu, u32 m= sr_no, u32 l, u32 h) wrmsr(msr_no, l, h); return 0; } -static inline int rdmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) -{ - rdmsrq(msr_no, *q); - return 0; -} static inline int wrmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 q) { wrmsrq(msr_no, q); @@ -329,7 +323,6 @@ static inline int wrmsr_safe_regs_on_cpu(unsigned int c= pu, u32 regs[8]) /* Compatibility wrappers: */ #define rdmsrl(msr, val) rdmsrq(msr, val) #define wrmsrl(msr, val) wrmsrq(msr, val) -#define rdmsrl_on_cpu(cpu, msr, q) rdmsrq_on_cpu(cpu, msr, q) =20 #endif /* __ASSEMBLER__ */ #endif /* _ASM_X86_MSR_H */ diff --git a/arch/x86/kernel/cpu/intel_epb.c b/arch/x86/kernel/cpu/intel_ep= b.c index 2c56f8730f59..cb5a3c299f26 100644 --- a/arch/x86/kernel/cpu/intel_epb.c +++ b/arch/x86/kernel/cpu/intel_epb.c @@ -139,7 +139,7 @@ static ssize_t energy_perf_bias_show(struct device *dev, u64 epb; int ret; =20 - ret =3D rdmsrq_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); + ret =3D rdmsr_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); if (ret < 0) return ret; =20 @@ -161,7 +161,7 @@ static ssize_t energy_perf_bias_store(struct device *de= v, else if (kstrtou64(buf, 0, &val) || val > MAX_EPB) return -EINVAL; =20 - ret =3D rdmsrq_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); + ret =3D rdmsr_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); if (ret < 0) return ret; =20 diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inj= ect.c index fa13a8a4946b..78649651c987 100644 --- a/arch/x86/kernel/cpu/mce/inject.c +++ b/arch/x86/kernel/cpu/mce/inject.c @@ -590,7 +590,7 @@ static int inj_bank_set(void *data, u64 val) u64 cap; =20 /* Get bank count on target CPU so we can handle non-uniform values. */ - rdmsrq_on_cpu(m->extcpu, MSR_IA32_MCG_CAP, &cap); + rdmsr_on_cpu(m->extcpu, MSR_IA32_MCG_CAP, &cap); n_banks =3D cap & MCG_BANKCNT_MASK; =20 if (val >=3D n_banks) { @@ -614,7 +614,7 @@ static int inj_bank_set(void *data, u64 val) if (cpu_feature_enabled(X86_FEATURE_SMCA)) { u64 ipid; =20 - if (rdmsrq_on_cpu(m->extcpu, MSR_AMD64_SMCA_MCx_IPID(val), &ipid)) { + if (rdmsr_on_cpu(m->extcpu, MSR_AMD64_SMCA_MCx_IPID(val), &ipid)) { pr_err("Error reading IPID on CPU%d\n", m->extcpu); return -EINVAL; } diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/mi= crocode/intel.c index a4c0a0cf928b..0b49ee6ddd2e 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -663,7 +663,7 @@ static void stage_microcode(void) =20 pkg_id =3D topology_logical_package_id(cpu); =20 - err =3D rdmsrq_on_cpu(cpu, MSR_IA32_MCU_STAGING_MBOX_ADDR, &mmio_pa); + err =3D rdmsr_on_cpu(cpu, MSR_IA32_MCU_STAGING_MBOX_ADDR, &mmio_pa); if (WARN_ON_ONCE(err)) return; =20 diff --git a/arch/x86/lib/msr-smp.c b/arch/x86/lib/msr-smp.c index 6e04aabda863..7c96f003bfe0 100644 --- a/arch/x86/lib/msr-smp.c +++ b/arch/x86/lib/msr-smp.c @@ -46,21 +46,6 @@ int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) } EXPORT_SYMBOL(rdmsr_on_cpu); =20 -int rdmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) -{ - int err; - struct msr_info rv; - - memset(&rv, 0, sizeof(rv)); - - rv.msr_no =3D msr_no; - err =3D smp_call_function_single(cpu, __rdmsr_on_cpu, &rv, 1); - *q =3D rv.reg.q; - - return err; -} -EXPORT_SYMBOL(rdmsrq_on_cpu); - int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) { int err; diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c index 21639d9ac753..43bf1c21c4ca 100644 --- a/drivers/cpufreq/acpi-cpufreq.c +++ b/drivers/cpufreq/acpi-cpufreq.c @@ -79,11 +79,11 @@ static bool boost_state(unsigned int cpu) case X86_VENDOR_INTEL: case X86_VENDOR_CENTAUR: case X86_VENDOR_ZHAOXIN: - rdmsrq_on_cpu(cpu, MSR_IA32_MISC_ENABLE, &msr); + rdmsr_on_cpu(cpu, MSR_IA32_MISC_ENABLE, &msr); return !(msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE); case X86_VENDOR_HYGON: case X86_VENDOR_AMD: - rdmsrq_on_cpu(cpu, MSR_K7_HWCR, &msr); + rdmsr_on_cpu(cpu, MSR_K7_HWCR, &msr); return !(msr & MSR_K7_HWCR_CPB_DIS); } return false; diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 62b5d995281d..8da4f0f034e2 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -204,7 +204,7 @@ static u8 msr_get_epp(struct amd_cpudata *cpudata) u64 value; int ret; =20 - ret =3D rdmsrq_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &value); + ret =3D rdmsr_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &value); if (ret < 0) { pr_debug("Could not retrieve energy perf value (%d)\n", ret); return ret; @@ -378,7 +378,7 @@ static int amd_pstate_init_floor_perf(struct cpufreq_po= licy *policy) if (!cpu_feature_enabled(X86_FEATURE_CPPC_PERF_PRIO)) return 0; =20 - ret =3D rdmsrq_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ2, &value); + ret =3D rdmsr_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ2, &value); if (ret) { pr_err("failed to read CPPC REQ2 value. Error (%d)\n", ret); return ret; @@ -476,7 +476,7 @@ static int msr_init_perf(struct amd_cpudata *cpudata) if (ret) return ret; =20 - ret =3D rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &cppc_req); + ret =3D rdmsr_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &cppc_req); if (ret) return ret; =20 @@ -877,7 +877,7 @@ static int amd_pstate_init_boost_support(struct amd_cpu= data *cpudata) goto exit_err; } =20 - ret =3D rdmsrq_on_cpu(cpudata->cpu, MSR_K7_HWCR, &boost_val); + ret =3D rdmsr_on_cpu(cpudata->cpu, MSR_K7_HWCR, &boost_val); if (ret) { pr_err_once("failed to read initial CPU boost state!\n"); ret =3D -EIO; diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c index 1f093e346430..4cd3686f194a 100644 --- a/drivers/cpufreq/intel_pstate.c +++ b/drivers/cpufreq/intel_pstate.c @@ -632,8 +632,8 @@ static s16 intel_pstate_get_epp(struct cpudata *cpu_dat= a, u64 hwp_req_data) * MSR_HWP_REQUEST, so need to read and get EPP. */ if (!hwp_req_data) { - epp =3D rdmsrq_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, - &hwp_req_data); + epp =3D rdmsr_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, + &hwp_req_data); if (epp) return epp; } @@ -886,7 +886,7 @@ static ssize_t show_base_frequency(struct cpufreq_polic= y *policy, char *buf) if (ratio <=3D 0) { u64 cap; =20 - rdmsrq_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap); + rdmsr_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap); ratio =3D HWP_GUARANTEED_PERF(cap); } =20 @@ -1187,7 +1187,7 @@ static void __intel_pstate_get_hwp_cap(struct cpudata= *cpu) { u64 cap; =20 - rdmsrq_on_cpu(cpu->cpu, MSR_HWP_CAPABILITIES, &cap); + rdmsr_on_cpu(cpu->cpu, MSR_HWP_CAPABILITIES, &cap); WRITE_ONCE(cpu->hwp_cap_cached, cap); cpu->pstate.max_pstate =3D HWP_GUARANTEED_PERF(cap); cpu->pstate.turbo_pstate =3D HWP_HIGHEST_PERF(cap); @@ -1269,7 +1269,7 @@ static void intel_pstate_hwp_set(unsigned int cpu) if (cpu_data->policy =3D=3D CPUFREQ_POLICY_PERFORMANCE) min =3D max; =20 - rdmsrq_on_cpu(cpu, MSR_HWP_REQUEST, &value); + rdmsr_on_cpu(cpu, MSR_HWP_REQUEST, &value); =20 value &=3D ~HWP_MIN_PERF(~0L); value |=3D HWP_MIN_PERF(min); @@ -2156,7 +2156,7 @@ static int core_get_min_pstate(int cpu) { u64 value; =20 - rdmsrq_on_cpu(cpu, MSR_PLATFORM_INFO, &value); + rdmsr_on_cpu(cpu, MSR_PLATFORM_INFO, &value); return (value >> 40) & 0xFF; } =20 @@ -2164,7 +2164,7 @@ static int core_get_max_pstate_physical(int cpu) { u64 value; =20 - rdmsrq_on_cpu(cpu, MSR_PLATFORM_INFO, &value); + rdmsr_on_cpu(cpu, MSR_PLATFORM_INFO, &value); return (value >> 8) & 0xFF; } =20 @@ -2209,7 +2209,7 @@ static int core_get_max_pstate(int cpu) int tdp_ratio; int err; =20 - rdmsrq_on_cpu(cpu, MSR_PLATFORM_INFO, &plat_info); + rdmsr_on_cpu(cpu, MSR_PLATFORM_INFO, &plat_info); max_pstate =3D (plat_info >> 8) & 0xFF; =20 tdp_ratio =3D core_get_tdp_ratio(cpu, plat_info); @@ -2241,7 +2241,7 @@ static int core_get_turbo_pstate(int cpu) u64 value; int nont, ret; =20 - rdmsrq_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value); + rdmsr_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value); nont =3D core_get_max_pstate(cpu); ret =3D (value) & 255; if (ret <=3D nont) @@ -2264,7 +2264,7 @@ static int knl_get_turbo_pstate(int cpu) u64 value; int nont, ret; =20 - rdmsrq_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value); + rdmsr_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value); nont =3D core_get_max_pstate(cpu); ret =3D (((value) >> 8) & 0xFF); if (ret <=3D nont) @@ -3318,7 +3318,7 @@ static int intel_cpufreq_cpu_init(struct cpufreq_poli= cy *policy) =20 intel_pstate_get_hwp_cap(cpu); =20 - rdmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value); + rdmsr_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value); WRITE_ONCE(cpu->hwp_req_cached, value); =20 cpu->epp_cached =3D intel_pstate_get_epp(cpu, value); diff --git a/drivers/platform/x86/intel/uncore-frequency/uncore-frequency.c= b/drivers/platform/x86/intel/uncore-frequency/uncore-frequency.c index 667f2c8b9594..b9878a4d391b 100644 --- a/drivers/platform/x86/intel/uncore-frequency/uncore-frequency.c +++ b/drivers/platform/x86/intel/uncore-frequency/uncore-frequency.c @@ -52,7 +52,7 @@ static int uncore_read_control_freq(struct uncore_data *d= ata, unsigned int *valu if (data->control_cpu < 0) return -ENXIO; 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Fri, 05 Jun 2026 07:08:47 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org, linux-perf-users@vger.kernel.org, linux-edac@vger.kernel.org, linux-pm@vger.kernel.org Cc: Juergen Gross , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Thomas Gleixner , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Tony Luck , "Rafael J. Wysocki" , Viresh Kumar , Daniel Lezcano , Zhang Rui , Lukasz Luba Subject: [PATCH 3/8] x86/msr: Switch wrmsr_on_cpu() to use a 64-bit quantity Date: Fri, 5 Jun 2026 09:08:21 +0200 Message-ID: <20260605070826.2995913-4-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260605070826.2995913-1-jgross@suse.com> References: <20260605070826.2995913-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Queue-Id: A35276B10F X-Spam-Flag: NO X-Spam-Score: -4.00 X-Spam-Level: X-Rspamd-Action: no action X-Rspamd-Server: rspamd1.dmz-prg2.suse.org X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[] Content-Type: text/plain; charset="utf-8" In order to prepare retiring wrmsrq_on_cpu() switch wrmsr_on_cpu() to have the same interface as wrmsrq_on_cpu(). Switch all wrmsr_on_cpu() callers to use the new interface. Signed-off-by: Juergen Gross --- arch/x86/events/intel/ds.c | 11 ++++------- arch/x86/include/asm/msr.h | 8 ++++---- arch/x86/kernel/cpu/mce/inject.c | 2 +- arch/x86/lib/msr-smp.c | 5 ++--- drivers/cpufreq/p4-clockmod.c | 4 ++-- drivers/cpufreq/speedstep-centrino.c | 4 ++-- drivers/thermal/intel/x86_pkg_temp_thermal.c | 2 +- 7 files changed, 16 insertions(+), 20 deletions(-) diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index 7f0d515c07c5..06d6d06c7a75 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -780,9 +780,7 @@ void init_debug_store_on_cpu(int cpu) if (!ds) return; =20 - wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, - (u32)((u64)(unsigned long)ds), - (u32)((u64)(unsigned long)ds >> 32)); + wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, (u64)(unsigned long)ds); } =20 void fini_debug_store_on_cpu(int cpu) @@ -790,7 +788,7 @@ void fini_debug_store_on_cpu(int cpu) if (!per_cpu(cpu_hw_events, cpu).ds) return; =20 - wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0); + wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0); } =20 static DEFINE_PER_CPU(void *, insn_buffer); @@ -1095,8 +1093,7 @@ void init_arch_pebs_on_cpu(int cpu) * contiguous physical buffer (__alloc_pages_node() with order) */ arch_pebs_base =3D virt_to_phys(cpuc->pebs_vaddr) | PEBS_BUFFER_SHIFT; - wrmsr_on_cpu(cpu, MSR_IA32_PEBS_BASE, (u32)arch_pebs_base, - (u32)(arch_pebs_base >> 32)); + wrmsr_on_cpu(cpu, MSR_IA32_PEBS_BASE, arch_pebs_base); x86_pmu.pebs_active =3D 1; } =20 @@ -1105,7 +1102,7 @@ inline void fini_arch_pebs_on_cpu(int cpu) if (!x86_pmu.arch_pebs) return; =20 - wrmsr_on_cpu(cpu, MSR_IA32_PEBS_BASE, 0, 0); + wrmsr_on_cpu(cpu, MSR_IA32_PEBS_BASE, 0); } =20 /* diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 8c96fc5c6169..a004440b4c0a 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -257,7 +257,7 @@ int msr_clear_bit(u32 msr, u8 bit); =20 #ifdef CONFIG_SMP int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); -int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); +int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u64 q); int wrmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 q); void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr __pe= rcpu *msrs); void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr __pe= rcpu *msrs); @@ -273,9 +273,9 @@ static inline int rdmsr_on_cpu(unsigned int cpu, u32 ms= r_no, u64 *q) rdmsrq(msr_no, *q); return 0; } -static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) +static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u64 q) { - wrmsr(msr_no, l, h); + wrmsrq(msr_no, q); return 0; } static inline int wrmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 q) @@ -291,7 +291,7 @@ static inline void rdmsr_on_cpus(const struct cpumask *= m, u32 msr_no, static inline void wrmsr_on_cpus(const struct cpumask *m, u32 msr_no, struct msr __percpu *msrs) { - wrmsr_on_cpu(0, msr_no, raw_cpu_read(msrs->l), raw_cpu_read(msrs->h)); + wrmsrq_on_cpu(0, msr_no, raw_cpu_read(msrs->q)); } static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inj= ect.c index 78649651c987..2d75098211b3 100644 --- a/arch/x86/kernel/cpu/mce/inject.c +++ b/arch/x86/kernel/cpu/mce/inject.c @@ -327,7 +327,7 @@ static int toggle_hw_mce_inject(unsigned int cpu, bool = enable) =20 enable ? (val.l |=3D BIT(18)) : (val.l &=3D ~BIT(18)); =20 - err =3D wrmsr_on_cpu(cpu, MSR_K7_HWCR, val.l, val.h); + err =3D wrmsr_on_cpu(cpu, MSR_K7_HWCR, val.q); if (err) pr_err("%s: error writing HWCR\n", __func__); =20 diff --git a/arch/x86/lib/msr-smp.c b/arch/x86/lib/msr-smp.c index 7c96f003bfe0..0b4f3c4e4f82 100644 --- a/arch/x86/lib/msr-smp.c +++ b/arch/x86/lib/msr-smp.c @@ -46,7 +46,7 @@ int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) } EXPORT_SYMBOL(rdmsr_on_cpu); =20 -int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) +int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u64 q) { int err; struct msr_info rv; @@ -54,8 +54,7 @@ int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32= h) memset(&rv, 0, sizeof(rv)); =20 rv.msr_no =3D msr_no; - rv.reg.l =3D l; - rv.reg.h =3D h; + rv.reg.q =3D q; err =3D smp_call_function_single(cpu, __wrmsr_on_cpu, &rv, 1); =20 return err; diff --git a/drivers/cpufreq/p4-clockmod.c b/drivers/cpufreq/p4-clockmod.c index 393c4a5d2021..409c0210e48a 100644 --- a/drivers/cpufreq/p4-clockmod.c +++ b/drivers/cpufreq/p4-clockmod.c @@ -68,7 +68,7 @@ static int cpufreq_p4_setdc(unsigned int cpu, unsigned in= t newstate) rdmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, &val.q); if (newstate =3D=3D DC_DISABLE) { pr_debug("CPU#%d disabling modulation\n", cpu); - wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, val.l & ~(1<<4), val.h); + wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, val.q & ~(1ULL << 4)); } else { pr_debug("CPU#%d setting duty cycle to %d%%\n", cpu, ((125 * newstate) / 10)); @@ -79,7 +79,7 @@ static int cpufreq_p4_setdc(unsigned int cpu, unsigned in= t newstate) */ val.l =3D (val.l & ~14); val.l =3D val.l | (1<<4) | ((newstate & 0x7)<<1); - wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, val.l, val.h); + wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, val.q); } =20 return 0; diff --git a/drivers/cpufreq/speedstep-centrino.c b/drivers/cpufreq/speedst= ep-centrino.c index b74c85128377..121cddb1430f 100644 --- a/drivers/cpufreq/speedstep-centrino.c +++ b/drivers/cpufreq/speedstep-centrino.c @@ -475,7 +475,7 @@ static int centrino_target(struct cpufreq_policy *polic= y, unsigned int index) oldmsr.l |=3D msr; } =20 - wrmsr_on_cpu(good_cpu, MSR_IA32_PERF_CTL, oldmsr.l, oldmsr.h); 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Fri, 5 Jun 2026 07:08:52 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id oFnAOAR2ImodHgAAD6G6ig (envelope-from ); Fri, 05 Jun 2026 07:08:52 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org, linux-pm@vger.kernel.org, platform-driver-x86@vger.kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Huang Rui , Mario Limonciello , Perry Yuan , K Prateek Nayak , "Rafael J. Wysocki" , Viresh Kumar , Srinivas Pandruvada , Len Brown , Hans de Goede , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 4/8] x86/msr: Switch all callers of wrmsrq_on_cpu() to use wrmsr_on_cpu() Date: Fri, 5 Jun 2026 09:08:22 +0200 Message-ID: <20260605070826.2995913-5-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260605070826.2995913-1-jgross@suse.com> References: <20260605070826.2995913-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam-Flag: NO X-Spam-Score: -6.80 X-Spamd-Result: default: False [-6.80 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.com:email,suse.com:mid,imap1.dmz-prg2.suse.org:helo]; ARC_NA(0.00)[]; MIME_TRACE(0.00)[0:+]; TO_DN_SOME(0.00)[]; RCPT_COUNT_TWELVE(0.00)[20]; RCVD_VIA_SMTP_AUTH(0.00)[]; FUZZY_RATELIMITED(0.00)[rspamd.com]; FROM_HAS_DN(0.00)[]; TO_MATCH_ENVRCPT_ALL(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; R_RATELIMIT(0.00)[to_ip_from(RLfdszjqhz8kzzb9uwpzdm8png)]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; RCVD_TLS_ALL(0.00)[] X-Spam-Level: Content-Type: text/plain; charset="utf-8" Now that wrmsr_on_cpu() has the same interface as wrmsrq_on_cpu(), the callers of wrmsrq_on_cpu() can be switched to wrmsr_on_cpu() and wrmsrq_on_cpu() can be removed. Signed-off-by: Juergen Gross --- arch/x86/include/asm/msr.h | 8 +---- arch/x86/kernel/cpu/intel_epb.c | 4 +-- arch/x86/lib/msr-smp.c | 16 --------- drivers/cpufreq/amd-pstate.c | 8 ++--- drivers/cpufreq/intel_pstate.c | 36 +++++++++---------- drivers/platform/x86/amd/hfi/hfi.c | 4 +-- .../intel/uncore-frequency/uncore-frequency.c | 6 ++-- 7 files changed, 30 insertions(+), 52 deletions(-) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index a004440b4c0a..c0a3bfba6b56 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -258,7 +258,6 @@ int msr_clear_bit(u32 msr, u8 bit); #ifdef CONFIG_SMP int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u64 q); -int wrmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 q); void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr __pe= rcpu *msrs); void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr __pe= rcpu *msrs); int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); @@ -278,11 +277,6 @@ static inline int wrmsr_on_cpu(unsigned int cpu, u32 m= sr_no, u64 q) wrmsrq(msr_no, q); return 0; } -static inline int wrmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 q) -{ - wrmsrq(msr_no, q); - return 0; -} static inline void rdmsr_on_cpus(const struct cpumask *m, u32 msr_no, struct msr __percpu *msrs) { @@ -291,7 +285,7 @@ static inline void rdmsr_on_cpus(const struct cpumask *= m, u32 msr_no, static inline void wrmsr_on_cpus(const struct cpumask *m, u32 msr_no, struct msr __percpu *msrs) { - wrmsrq_on_cpu(0, msr_no, raw_cpu_read(msrs->q)); + wrmsr_on_cpu(0, msr_no, raw_cpu_read(msrs->q)); } static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) diff --git a/arch/x86/kernel/cpu/intel_epb.c b/arch/x86/kernel/cpu/intel_ep= b.c index cb5a3c299f26..7533f47bf63d 100644 --- a/arch/x86/kernel/cpu/intel_epb.c +++ b/arch/x86/kernel/cpu/intel_epb.c @@ -165,8 +165,8 @@ static ssize_t energy_perf_bias_store(struct device *de= v, if (ret < 0) return ret; =20 - ret =3D wrmsrq_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, - (epb & ~EPB_MASK) | val); + ret =3D wrmsr_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, + (epb & ~EPB_MASK) | val); if (ret < 0) return ret; =20 diff --git a/arch/x86/lib/msr-smp.c b/arch/x86/lib/msr-smp.c index 0b4f3c4e4f82..42d42641f2aa 100644 --- a/arch/x86/lib/msr-smp.c +++ b/arch/x86/lib/msr-smp.c @@ -61,22 +61,6 @@ int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u64 q) } EXPORT_SYMBOL(wrmsr_on_cpu); =20 -int wrmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 q) -{ - int err; - struct msr_info rv; - - memset(&rv, 0, sizeof(rv)); - - rv.msr_no =3D msr_no; - rv.reg.q =3D q; - - err =3D smp_call_function_single(cpu, __wrmsr_on_cpu, &rv, 1); - - return err; -} -EXPORT_SYMBOL(wrmsrq_on_cpu); - static void __rwmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr __percpu *msrs, void (*msr_func) (void *info)) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 8da4f0f034e2..c98ead520224 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -267,7 +267,7 @@ static int msr_update_perf(struct cpufreq_policy *polic= y, u8 min_perf, if (fast_switch) { wrmsrq(MSR_AMD_CPPC_REQ, value); } else { - int ret =3D wrmsrq_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); + int ret =3D wrmsr_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); =20 if (ret) return ret; @@ -315,7 +315,7 @@ static int msr_set_epp(struct cpufreq_policy *policy, u= 8 epp) if (value =3D=3D prev) return 0; =20 - ret =3D wrmsrq_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); + ret =3D wrmsr_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); if (ret) { pr_err("failed to set energy perf value (%d)\n", ret); return ret; @@ -353,7 +353,7 @@ static int amd_pstate_set_floor_perf(struct cpufreq_pol= icy *policy, u8 perf) goto out_trace; } =20 - ret =3D wrmsrq_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ2, value); + ret =3D wrmsr_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ2, value); if (ret) { changed =3D false; pr_err("failed to set CPPC REQ2 value. Error (%d)\n", ret); @@ -896,7 +896,7 @@ static int amd_pstate_init_boost_support(struct amd_cpu= data *cpudata) =20 static void amd_perf_ctl_reset(unsigned int cpu) { - wrmsrq_on_cpu(cpu, MSR_AMD_PERF_CTL, 0); + wrmsr_on_cpu(cpu, MSR_AMD_PERF_CTL, 0); } =20 #define CPPC_MAX_PERF U8_MAX diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c index 4cd3686f194a..3adc033a3492 100644 --- a/drivers/cpufreq/intel_pstate.c +++ b/drivers/cpufreq/intel_pstate.c @@ -736,7 +736,7 @@ static int intel_pstate_set_epp(struct cpudata *cpu, u3= 2 epp) * function, so it cannot run in parallel with the update below. */ WRITE_ONCE(cpu->hwp_req_cached, value); - ret =3D wrmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); + ret =3D wrmsr_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); if (!ret) cpu->epp_cached =3D epp; =20 @@ -1315,7 +1315,7 @@ static void intel_pstate_hwp_set(unsigned int cpu) =20 skip_epp: WRITE_ONCE(cpu_data->hwp_req_cached, value); - wrmsrq_on_cpu(cpu, MSR_HWP_REQUEST, value); + wrmsr_on_cpu(cpu, MSR_HWP_REQUEST, value); } =20 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata); @@ -1362,7 +1362,7 @@ static void intel_pstate_hwp_offline(struct cpudata *= cpu) if (boot_cpu_has(X86_FEATURE_HWP_EPP)) value |=3D HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE); =20 - wrmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); + wrmsr_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); =20 mutex_lock(&hybrid_capacity_lock); =20 @@ -1411,7 +1411,7 @@ static void intel_pstate_hwp_enable(struct cpudata *c= pudata); static void intel_pstate_hwp_reenable(struct cpudata *cpu) { intel_pstate_hwp_enable(cpu); - wrmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached)); + wrmsr_on_cpu(cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached)); } =20 static int intel_pstate_suspend(struct cpufreq_policy *policy) @@ -1919,7 +1919,7 @@ static void intel_pstate_notify_work(struct work_stru= ct *work) hybrid_update_capacity(cpudata); } =20 - wrmsrq_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0); + wrmsr_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0); } =20 static DEFINE_RAW_SPINLOCK(hwp_notify_lock); @@ -1969,8 +1969,8 @@ static void intel_pstate_disable_hwp_interrupt(struct= cpudata *cpudata) if (!cpu_feature_enabled(X86_FEATURE_HWP_NOTIFY)) return; =20 - /* wrmsrq_on_cpu has to be outside spinlock as this can result in IPC */ - wrmsrq_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); + /* wrmsr_on_cpu has to be outside spinlock as this can result in IPC */ + wrmsr_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); =20 raw_spin_lock_irq(&hwp_notify_lock); cancel_work =3D cpumask_test_and_clear_cpu(cpudata->cpu, &hwp_intr_enable= _mask); @@ -1997,9 +1997,9 @@ static void intel_pstate_enable_hwp_interrupt(struct = cpudata *cpudata) if (cpu_feature_enabled(X86_FEATURE_HWP_HIGHEST_PERF_CHANGE)) interrupt_mask |=3D HWP_HIGHEST_PERF_CHANGE_REQ; =20 - /* wrmsrq_on_cpu has to be outside spinlock as this can result in IPC */ - wrmsrq_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, interrupt_mask); - wrmsrq_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0); + /* wrmsr_on_cpu has to be outside spinlock as this can result in IPC */ + wrmsr_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, interrupt_mask); + wrmsr_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0); } } =20 @@ -2038,9 +2038,9 @@ static void intel_pstate_hwp_enable(struct cpudata *c= pudata) { /* First disable HWP notification interrupt till we activate again */ if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) - wrmsrq_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); + wrmsr_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); =20 - wrmsrq_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); + wrmsr_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); =20 intel_pstate_enable_hwp_interrupt(cpudata); =20 @@ -2306,8 +2306,8 @@ static void intel_pstate_set_pstate(struct cpudata *c= pu, int pstate) * the CPU being updated, so force the register update to run on the * right CPU. */ - wrmsrq_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, - pstate_funcs.get_val(cpu, pstate)); + wrmsr_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, + pstate_funcs.get_val(cpu, pstate)); } =20 static void intel_pstate_set_min_pstate(struct cpudata *cpu) @@ -3164,7 +3164,7 @@ static void intel_cpufreq_hwp_update(struct cpudata *= cpu, u32 min, u32 max, if (fast_switch) wrmsrq(MSR_HWP_REQUEST, value); else - wrmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); + wrmsr_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); } =20 static void intel_cpufreq_perf_ctl_update(struct cpudata *cpu, @@ -3174,8 +3174,8 @@ static void intel_cpufreq_perf_ctl_update(struct cpud= ata *cpu, wrmsrq(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, target_pstate)); else - wrmsrq_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, - pstate_funcs.get_val(cpu, target_pstate)); + wrmsr_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, + pstate_funcs.get_val(cpu, target_pstate)); } =20 static int intel_cpufreq_update_pstate(struct cpufreq_policy *policy, @@ -3385,7 +3385,7 @@ static int intel_cpufreq_suspend(struct cpufreq_polic= y *policy) * written by it may not be suitable. */ value &=3D ~HWP_DESIRED_PERF(~0L); - wrmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); + wrmsr_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); WRITE_ONCE(cpu->hwp_req_cached, value); } =20 diff --git a/drivers/platform/x86/amd/hfi/hfi.c b/drivers/platform/x86/amd/= hfi/hfi.c index 83863a5e0fbc..580fbc3648bf 100644 --- a/drivers/platform/x86/amd/hfi/hfi.c +++ b/drivers/platform/x86/amd/hfi/hfi.c @@ -260,11 +260,11 @@ static int amd_hfi_set_state(unsigned int cpu, bool s= tate) { int ret; =20 - ret =3D wrmsrq_on_cpu(cpu, MSR_AMD_WORKLOAD_CLASS_CONFIG, state ? 1 : 0); + ret =3D wrmsr_on_cpu(cpu, MSR_AMD_WORKLOAD_CLASS_CONFIG, state ? 1 : 0); if (ret) return ret; =20 - return wrmsrq_on_cpu(cpu, MSR_AMD_WORKLOAD_HRST, 0x1); + return wrmsr_on_cpu(cpu, MSR_AMD_WORKLOAD_HRST, 0x1); } =20 /** diff --git a/drivers/platform/x86/intel/uncore-frequency/uncore-frequency.c= b/drivers/platform/x86/intel/uncore-frequency/uncore-frequency.c index b9878a4d391b..c4c24a355854 100644 --- a/drivers/platform/x86/intel/uncore-frequency/uncore-frequency.c +++ b/drivers/platform/x86/intel/uncore-frequency/uncore-frequency.c @@ -89,7 +89,7 @@ static int uncore_write_control_freq(struct uncore_data *= data, unsigned int inpu cap |=3D FIELD_PREP(UNCORE_MIN_RATIO_MASK, input); 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Fri, 5 Jun 2026 07:08:58 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id 0up/KQp2ImojHgAAD6G6ig (envelope-from ); Fri, 05 Jun 2026 07:08:58 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org, linux-hwmon@vger.kernel.org, linux-pm@vger.kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Guenter Roeck , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba Subject: [PATCH 5/8] x86/msr: Switch rdmsr_safe_on_cpu() to return a 64-bit quantity Date: Fri, 5 Jun 2026 09:08:23 +0200 Message-ID: <20260605070826.2995913-6-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260605070826.2995913-1-jgross@suse.com> References: <20260605070826.2995913-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam-Flag: NO X-Spam-Score: -6.80 X-Spamd-Result: default: False [-6.80 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.com:email,suse.com:mid,intel.com:url,imap1.dmz-prg2.suse.org:helo]; ARC_NA(0.00)[]; MIME_TRACE(0.00)[0:+]; TO_DN_SOME(0.00)[]; RCPT_COUNT_TWELVE(0.00)[15]; RCVD_VIA_SMTP_AUTH(0.00)[]; FUZZY_RATELIMITED(0.00)[rspamd.com]; FROM_HAS_DN(0.00)[]; TO_MATCH_ENVRCPT_ALL(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; R_RATELIMIT(0.00)[to_ip_from(RLfdszjqhz8kzzb9uwpzdm8png)]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; RCVD_TLS_ALL(0.00)[] X-Spam-Level: Content-Type: text/plain; charset="utf-8" In order to prepare retiring rdmsrq_safe_on_cpu() switch rdmsr_safe_on_cpu() to have the same interface as rdmsrq_safe_on_cpu(). Switch all rdmsr_safe_on_cpu() callers to use the new interface. Signed-off-by: Juergen Gross --- arch/x86/include/asm/msr.h | 7 +++-- arch/x86/kernel/msr.c | 4 +-- arch/x86/lib/msr-smp.c | 9 +++---- drivers/hwmon/coretemp.c | 32 +++++++++++------------ drivers/hwmon/via-cputemp.c | 16 ++++++------ drivers/thermal/intel/intel_tcc.c | 43 ++++++++++++++++--------------- 6 files changed, 54 insertions(+), 57 deletions(-) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index c0a3bfba6b56..b3b43bc04b69 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -260,7 +260,7 @@ int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u64 q); void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr __pe= rcpu *msrs); void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr __pe= rcpu *msrs); -int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); +int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); int rdmsrq_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); int wrmsrq_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q); @@ -287,10 +287,9 @@ static inline void wrmsr_on_cpus(const struct cpumask = *m, u32 msr_no, { wrmsr_on_cpu(0, msr_no, raw_cpu_read(msrs->q)); } -static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, - u32 *l, u32 *h) +static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) { - return rdmsr_safe(msr_no, l, h); + return rdmsrq_safe(msr_no, q); } static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u= 32 h) { diff --git a/arch/x86/kernel/msr.c b/arch/x86/kernel/msr.c index 4469c784eaa0..c9429a718810 100644 --- a/arch/x86/kernel/msr.c +++ b/arch/x86/kernel/msr.c @@ -53,7 +53,7 @@ static ssize_t msr_read(struct file *file, char __user *b= uf, size_t count, loff_t *ppos) { u32 __user *tmp =3D (u32 __user *) buf; - u32 data[2]; + u64 data; u32 reg =3D *ppos; int cpu =3D iminor(file_inode(file)); int err =3D 0; @@ -63,7 +63,7 @@ static ssize_t msr_read(struct file *file, char __user *b= uf, return -EINVAL; /* Invalid chunk size */ =20 for (; count; count -=3D 8) { - err =3D rdmsr_safe_on_cpu(cpu, reg, &data[0], &data[1]); + err =3D rdmsr_safe_on_cpu(cpu, reg, &data); if (err) break; if (copy_to_user(tmp, &data, 8)) { diff --git a/arch/x86/lib/msr-smp.c b/arch/x86/lib/msr-smp.c index 42d42641f2aa..0dc3921e0259 100644 --- a/arch/x86/lib/msr-smp.c +++ b/arch/x86/lib/msr-smp.c @@ -131,7 +131,7 @@ static void __wrmsr_safe_on_cpu(void *info) rv->err =3D wrmsr_safe(rv->msr_no, rv->reg.l, rv->reg.h); } =20 -int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) +int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) { struct msr_info_completion rv; call_single_data_t csd; @@ -148,8 +148,7 @@ int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32= *l, u32 *h) wait_for_completion(&rv.done); err =3D rv.msr.err; } - *l =3D rv.msr.reg.l; - *h =3D rv.msr.reg.h; + *q =3D rv.msr.reg.q; =20 return err; } @@ -189,11 +188,9 @@ EXPORT_SYMBOL(wrmsrq_safe_on_cpu); =20 int rdmsrq_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) { - u32 low, high; int err; =20 - err =3D rdmsr_safe_on_cpu(cpu, msr_no, &low, &high); - *q =3D (u64)high << 32 | low; + err =3D rdmsr_safe_on_cpu(cpu, msr_no, q); =20 return err; } diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c index fa02960ffff5..506e79eb4d76 100644 --- a/drivers/hwmon/coretemp.c +++ b/drivers/hwmon/coretemp.c @@ -169,7 +169,7 @@ static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id, = struct device *dev) int tjmax_ee =3D 85000; int usemsr_ee =3D 1; int err; - u32 eax, edx; + u64 val; int i; u16 devfn =3D PCI_DEVFN(0, 0); struct pci_dev *host_bridge =3D pci_get_domain_bus_and_slot(0, 0, devfn); @@ -220,14 +220,14 @@ static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id= , struct device *dev) * http://softwarecommunity.intel.com/Wiki/Mobility/720.htm * For Core2 cores, check MSR 0x17, bit 28 1 =3D Mobile CPU */ - err =3D rdmsr_safe_on_cpu(id, 0x17, &eax, &edx); + err =3D rdmsr_safe_on_cpu(id, 0x17, &val); if (err) { dev_warn(dev, "Unable to access MSR 0x17, assuming desktop" " CPU\n"); usemsr_ee =3D 0; } else if (c->x86_vfm < INTEL_CORE2_PENRYN && - !(eax & 0x10000000)) { + !(val & 0x10000000)) { /* * Trust bit 28 up to Penryn, I could not find any * documentation on that; if you happen to know @@ -235,8 +235,8 @@ static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id, = struct device *dev) */ usemsr_ee =3D 0; } else { - /* Platform ID bits 52:50 (EDX starts at bit 32) */ - platform_id =3D (edx >> 18) & 0x7; + /* Platform ID bits 52:50 */ + platform_id =3D (val >> 50) & 0x7; =20 /* * Mobile Penryn CPU seems to be platform ID 7 or 5 @@ -255,12 +255,12 @@ static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id= , struct device *dev) } =20 if (usemsr_ee) { - err =3D rdmsr_safe_on_cpu(id, 0xee, &eax, &edx); + err =3D rdmsr_safe_on_cpu(id, 0xee, &val); if (err) { dev_warn(dev, "Unable to access MSR 0xEE, for Tjmax, left" " at default\n"); - } else if (eax & 0x40000000) { + } else if (val & 0x40000000) { tjmax =3D tjmax_ee; } } else if (tjmax =3D=3D 100000) { @@ -278,7 +278,7 @@ static int get_tjmax(struct temp_data *tdata, struct de= vice *dev) { struct cpuinfo_x86 *c =3D &cpu_data(tdata->cpu); int err; - u32 eax, edx; + u64 msrval; u32 val; =20 /* use static tjmax once it is set */ @@ -289,11 +289,11 @@ static int get_tjmax(struct temp_data *tdata, struct = device *dev) * A new feature of current Intel(R) processors, the * IA32_TEMPERATURE_TARGET contains the TjMax value */ - err =3D rdmsr_safe_on_cpu(tdata->cpu, MSR_IA32_TEMPERATURE_TARGET, &eax, = &edx); + err =3D rdmsr_safe_on_cpu(tdata->cpu, MSR_IA32_TEMPERATURE_TARGET, &msrva= l); if (err) { dev_warn_once(dev, "Unable to read TjMax from CPU %u\n", tdata->cpu); } else { - val =3D (eax >> 16) & 0xff; + val =3D (msrval >> 16) & 0xff; if (val) return val * 1000; } @@ -314,7 +314,7 @@ static int get_tjmax(struct temp_data *tdata, struct de= vice *dev) =20 static int get_ttarget(struct temp_data *tdata, struct device *dev) { - u32 eax, edx; + u64 val; int tjmax, ttarget_offset, ret; =20 /* @@ -324,14 +324,14 @@ static int get_ttarget(struct temp_data *tdata, struc= t device *dev) if (tdata->tjmax) return -ENODEV; =20 - ret =3D rdmsr_safe_on_cpu(tdata->cpu, MSR_IA32_TEMPERATURE_TARGET, &eax, = &edx); + ret =3D rdmsr_safe_on_cpu(tdata->cpu, MSR_IA32_TEMPERATURE_TARGET, &val); if (ret) return ret; =20 - tjmax =3D (eax >> 16) & 0xff; + tjmax =3D (val >> 16) & 0xff; =20 /* Read the still undocumented bits 8:15 of IA32_TEMPERATURE_TARGET. */ - ttarget_offset =3D (eax >> 8) & 0xff; + ttarget_offset =3D (val >> 8) & 0xff; =20 return (tjmax - ttarget_offset) * 1000; } @@ -560,7 +560,7 @@ static int create_core_data(struct platform_device *pde= v, unsigned int cpu, struct temp_data *tdata; struct platform_data *pdata =3D platform_get_drvdata(pdev); struct cpuinfo_x86 *c =3D &cpu_data(cpu); - u32 eax, edx; + u64 val; int err; =20 if (!housekeeping_cpu(cpu, HK_TYPE_MISC)) @@ -571,7 +571,7 @@ static int create_core_data(struct platform_device *pde= v, unsigned int cpu, return -ENOMEM; =20 /* Test if we can access the status register */ - err =3D rdmsr_safe_on_cpu(cpu, tdata->status_reg, &eax, &edx); + err =3D rdmsr_safe_on_cpu(cpu, tdata->status_reg, &val); if (err) goto err; =20 diff --git a/drivers/hwmon/via-cputemp.c b/drivers/hwmon/via-cputemp.c index a5c03ed59c1f..e239e0a388f7 100644 --- a/drivers/hwmon/via-cputemp.c +++ b/drivers/hwmon/via-cputemp.c @@ -65,28 +65,28 @@ static ssize_t temp_show(struct device *dev, struct dev= ice_attribute *devattr, char *buf) { struct via_cputemp_data *data =3D dev_get_drvdata(dev); - u32 eax, edx; + u64 val; int err; =20 - err =3D rdmsr_safe_on_cpu(data->id, data->msr_temp, &eax, &edx); + err =3D rdmsr_safe_on_cpu(data->id, data->msr_temp, &val); if (err) return -EAGAIN; =20 - return sprintf(buf, "%lu\n", ((unsigned long)eax & 0xffffff) * 1000); + return sprintf(buf, "%lu\n", ((unsigned long)val & 0xffffff) * 1000); } =20 static ssize_t cpu0_vid_show(struct device *dev, struct device_attribute *devattr, char *buf) { struct via_cputemp_data *data =3D dev_get_drvdata(dev); - u32 eax, edx; + u64 val; int err; =20 - err =3D rdmsr_safe_on_cpu(data->id, data->msr_vid, &eax, &edx); + err =3D rdmsr_safe_on_cpu(data->id, data->msr_vid, &val); if (err) return -EAGAIN; =20 - return sprintf(buf, "%d\n", vid_from_reg(~edx & 0x7f, data->vrm)); + return sprintf(buf, "%d\n", vid_from_reg(~(val >> 32) & 0x7f, data->vrm)); } =20 static SENSOR_DEVICE_ATTR_RO(temp1_input, temp, SHOW_TEMP); @@ -112,7 +112,7 @@ static int via_cputemp_probe(struct platform_device *pd= ev) struct via_cputemp_data *data; struct cpuinfo_x86 *c =3D &cpu_data(pdev->id); int err; - u32 eax, edx; + u64 val; =20 data =3D devm_kzalloc(&pdev->dev, sizeof(struct via_cputemp_data), GFP_KERNEL); @@ -143,7 +143,7 @@ static int via_cputemp_probe(struct platform_device *pd= ev) } =20 /* test if we can access the TEMPERATURE MSR */ - err =3D rdmsr_safe_on_cpu(data->id, data->msr_temp, &eax, &edx); + err =3D rdmsr_safe_on_cpu(data->id, data->msr_temp, &val); if (err) { dev_err(&pdev->dev, "Unable to access TEMPERATURE MSR, giving up\n"); diff --git a/drivers/thermal/intel/intel_tcc.c b/drivers/thermal/intel/inte= l_tcc.c index ab61fb122937..9a8f2f101efc 100644 --- a/drivers/thermal/intel/intel_tcc.c +++ b/drivers/thermal/intel/intel_tcc.c @@ -181,17 +181,17 @@ static u32 get_temp_mask(bool pkg) */ int intel_tcc_get_tjmax(int cpu) { - u32 low, high; + struct msr msrval; int val, err; =20 if (cpu < 0) - err =3D rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &low, &high); + err =3D rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &msrval.l, &msrval.h); else - err =3D rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &low, &high); + err =3D rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &msrval.q); if (err) return err; =20 - val =3D (low >> 16) & 0xff; + val =3D (msrval.l >> 16) & 0xff; =20 return val ? val : -ENODATA; } @@ -208,17 +208,17 @@ EXPORT_SYMBOL_NS_GPL(intel_tcc_get_tjmax, "INTEL_TCC"= ); */ int intel_tcc_get_offset(int cpu) { - u32 low, high; + struct msr val; int err; =20 if (cpu < 0) - err =3D rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &low, &high); + err =3D rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &val.l, &val.h); else - err =3D rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &low, &high); + err =3D rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &val.q); if (err) return err; =20 - return (low >> 24) & intel_tcc_temp_masks.tcc_offset; + return (val.l >> 24) & intel_tcc_temp_masks.tcc_offset; } EXPORT_SYMBOL_NS_GPL(intel_tcc_get_offset, "INTEL_TCC"); =20 @@ -235,7 +235,7 @@ EXPORT_SYMBOL_NS_GPL(intel_tcc_get_offset, "INTEL_TCC"); =20 int intel_tcc_set_offset(int cpu, int offset) { - u32 low, high; + struct msr val; int err; =20 if (!intel_tcc_temp_masks.tcc_offset) @@ -245,23 +245,23 @@ int intel_tcc_set_offset(int cpu, int offset) return -EINVAL; =20 if (cpu < 0) - err =3D rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &low, &high); + err =3D rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &val.l, &val.h); else - err =3D rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &low, &high); + err =3D rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &val.q); if (err) return err; =20 /* MSR Locked */ - if (low & BIT(31)) + if (val.l & BIT(31)) return -EPERM; =20 - low &=3D ~(intel_tcc_temp_masks.tcc_offset << 24); - low |=3D offset << 24; + val.l &=3D ~(intel_tcc_temp_masks.tcc_offset << 24); + val.l |=3D offset << 24; =20 if (cpu < 0) - return wrmsr_safe(MSR_IA32_TEMPERATURE_TARGET, low, high); + return wrmsr_safe(MSR_IA32_TEMPERATURE_TARGET, val.l, val.h); else - return wrmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, low, high); + return wrmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, val.l, val.h); } EXPORT_SYMBOL_NS_GPL(intel_tcc_set_offset, "INTEL_TCC"); =20 @@ -279,7 +279,8 @@ EXPORT_SYMBOL_NS_GPL(intel_tcc_set_offset, "INTEL_TCC"); int intel_tcc_get_temp(int cpu, int *temp, bool pkg) { u32 msr =3D pkg ? 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Peter Anvin" , "Rafael J. Wysocki" , Len Brown , Huang Rui , Mario Limonciello , Perry Yuan , K Prateek Nayak , Viresh Kumar , Srinivas Pandruvada , Hans de Goede , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 6/8] x86/msr: Switch all callers of rdmsrq_safe_on_cpu() to use rdmsr_safe_on_cpu() Date: Fri, 5 Jun 2026 09:08:24 +0200 Message-ID: <20260605070826.2995913-7-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260605070826.2995913-1-jgross@suse.com> References: <20260605070826.2995913-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Queue-Id: 0265C75814 X-Spam-Flag: NO X-Spam-Score: -4.00 X-Spam-Level: X-Rspamd-Action: no action X-Rspamd-Server: rspamd1.dmz-prg2.suse.org X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[] Content-Type: text/plain; charset="utf-8" Now that rdmsr_safe_on_cpu() has the same interface as rdmsrq_safe_on_cpu(), the callers of rdmsrq_safe_on_cpu() can be switched to rdmsr_safe_on_cpu() and rdmsrq_safe_on_cpu() can be removed. Signed-off-by: Juergen Gross --- arch/x86/events/intel/pt.c | 2 +- arch/x86/events/intel/uncore_discovery.c | 2 +- arch/x86/include/asm/msr.h | 5 ----- arch/x86/kernel/acpi/cppc.c | 6 +++--- arch/x86/lib/msr-smp.c | 10 ---------- drivers/cpufreq/amd-pstate-ut.c | 2 +- drivers/cpufreq/amd-pstate.c | 3 +-- drivers/cpufreq/intel_pstate.c | 6 +++--- .../x86/intel/speed_select_if/isst_if_common.c | 4 ++-- drivers/powercap/intel_rapl_msr.c | 2 +- 10 files changed, 13 insertions(+), 29 deletions(-) diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c index b5726b50e77d..7c92146b06ea 100644 --- a/arch/x86/events/intel/pt.c +++ b/arch/x86/events/intel/pt.c @@ -1840,7 +1840,7 @@ static __init int pt_init(void) for_each_online_cpu(cpu) { u64 ctl; =20 - ret =3D rdmsrq_safe_on_cpu(cpu, MSR_IA32_RTIT_CTL, &ctl); + ret =3D rdmsr_safe_on_cpu(cpu, MSR_IA32_RTIT_CTL, &ctl); if (!ret && (ctl & RTIT_CTL_TRACEEN)) prior_warn++; } diff --git a/arch/x86/events/intel/uncore_discovery.c b/arch/x86/events/int= el/uncore_discovery.c index 583cbd06b9b8..0853a9e02fda 100644 --- a/arch/x86/events/intel/uncore_discovery.c +++ b/arch/x86/events/intel/uncore_discovery.c @@ -405,7 +405,7 @@ static bool uncore_discovery_msr(struct uncore_discover= y_domain *domain) if (__test_and_set_bit(die, die_mask)) continue; =20 - if (rdmsrq_safe_on_cpu(cpu, domain->discovery_base, &base)) + if (rdmsr_safe_on_cpu(cpu, domain->discovery_base, &base)) continue; =20 if (!base) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index b3b43bc04b69..f2d14c670140 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -262,7 +262,6 @@ void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_= no, struct msr __percpu * void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr __pe= rcpu *msrs); int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); -int rdmsrq_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); int wrmsrq_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q); int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); @@ -295,10 +294,6 @@ static inline int wrmsr_safe_on_cpu(unsigned int cpu, = u32 msr_no, u32 l, u32 h) { return wrmsr_safe(msr_no, l, h); } -static inline int rdmsrq_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) -{ - return rdmsrq_safe(msr_no, q); -} static inline int wrmsrq_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q) { return wrmsrq_safe(msr_no, q); diff --git a/arch/x86/kernel/acpi/cppc.c b/arch/x86/kernel/acpi/cppc.c index be4c5e9e5ff6..86bf2dafdf72 100644 --- a/arch/x86/kernel/acpi/cppc.c +++ b/arch/x86/kernel/acpi/cppc.c @@ -49,7 +49,7 @@ int cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *va= l) { int err; =20 - err =3D rdmsrq_safe_on_cpu(cpunum, reg->address, val); + err =3D rdmsr_safe_on_cpu(cpunum, reg->address, val); if (!err) { u64 mask =3D GENMASK_ULL(reg->bit_offset + reg->bit_width - 1, reg->bit_offset); @@ -65,7 +65,7 @@ int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 va= l) u64 rd_val; int err; =20 - err =3D rdmsrq_safe_on_cpu(cpunum, reg->address, &rd_val); + err =3D rdmsr_safe_on_cpu(cpunum, reg->address, &rd_val); if (!err) { u64 mask =3D GENMASK_ULL(reg->bit_offset + reg->bit_width - 1, reg->bit_offset); @@ -147,7 +147,7 @@ int amd_get_highest_perf(unsigned int cpu, u32 *highest= _perf) int ret; =20 if (cpu_feature_enabled(X86_FEATURE_CPPC)) { - ret =3D rdmsrq_safe_on_cpu(cpu, MSR_AMD_CPPC_CAP1, &val); + ret =3D rdmsr_safe_on_cpu(cpu, MSR_AMD_CPPC_CAP1, &val); if (ret) goto out; =20 diff --git a/arch/x86/lib/msr-smp.c b/arch/x86/lib/msr-smp.c index 0dc3921e0259..fa22ac662c1d 100644 --- a/arch/x86/lib/msr-smp.c +++ b/arch/x86/lib/msr-smp.c @@ -186,16 +186,6 @@ int wrmsrq_safe_on_cpu(unsigned int cpu, u32 msr_no, u= 64 q) } EXPORT_SYMBOL(wrmsrq_safe_on_cpu); =20 -int rdmsrq_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) -{ - int err; - - err =3D rdmsr_safe_on_cpu(cpu, msr_no, q); - - return err; -} -EXPORT_SYMBOL(rdmsrq_safe_on_cpu); - /* * These variants are significantly slower, but allows control over * the entire 32-bit GPR set. diff --git a/drivers/cpufreq/amd-pstate-ut.c b/drivers/cpufreq/amd-pstate-u= t.c index 735b29f76438..b59cb8d95f55 100644 --- a/drivers/cpufreq/amd-pstate-ut.c +++ b/drivers/cpufreq/amd-pstate-ut.c @@ -170,7 +170,7 @@ static int amd_pstate_ut_check_perf(u32 index) lowest_nonlinear_perf =3D cppc_perf.lowest_nonlinear_perf; lowest_perf =3D cppc_perf.lowest_perf; } else { - ret =3D rdmsrq_safe_on_cpu(cpu, MSR_AMD_CPPC_CAP1, &cap1); + ret =3D rdmsr_safe_on_cpu(cpu, MSR_AMD_CPPC_CAP1, &cap1); if (ret) { pr_err("%s read CPPC_CAP1 ret=3D%d error!\n", __func__, ret); return ret; diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index c98ead520224..36c9c1e98115 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -467,8 +467,7 @@ static int msr_init_perf(struct amd_cpudata *cpudata) u64 cap1, numerator, cppc_req; u8 min_perf; =20 - int ret =3D rdmsrq_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1, - &cap1); + int ret =3D rdmsr_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1, &cap1); if (ret) return ret; =20 diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c index 3adc033a3492..f91c6b264f93 100644 --- a/drivers/cpufreq/intel_pstate.c +++ b/drivers/cpufreq/intel_pstate.c @@ -2178,13 +2178,13 @@ static int core_get_tdp_ratio(int cpu, u64 plat_inf= o) int err; =20 /* Get the TDP level (0, 1, 2) to get ratios */ - err =3D rdmsrq_safe_on_cpu(cpu, MSR_CONFIG_TDP_CONTROL, &tdp_ctrl); + err =3D rdmsr_safe_on_cpu(cpu, MSR_CONFIG_TDP_CONTROL, &tdp_ctrl); if (err) return err; =20 /* TDP MSR are continuous starting at 0x648 */ tdp_msr =3D MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03); - err =3D rdmsrq_safe_on_cpu(cpu, tdp_msr, &tdp_ratio); + err =3D rdmsr_safe_on_cpu(cpu, tdp_msr, &tdp_ratio); if (err) return err; =20 @@ -2221,7 +2221,7 @@ static int core_get_max_pstate(int cpu) return tdp_ratio; } =20 - err =3D rdmsrq_safe_on_cpu(cpu, MSR_TURBO_ACTIVATION_RATIO, &tar); + err =3D rdmsr_safe_on_cpu(cpu, MSR_TURBO_ACTIVATION_RATIO, &tar); if (!err) { int tar_levels; =20 diff --git a/drivers/platform/x86/intel/speed_select_if/isst_if_common.c b/= drivers/platform/x86/intel/speed_select_if/isst_if_common.c index 1c48bf6d5457..b15a798454dc 100644 --- a/drivers/platform/x86/intel/speed_select_if/isst_if_common.c +++ b/drivers/platform/x86/intel/speed_select_if/isst_if_common.c @@ -511,8 +511,8 @@ static long isst_if_msr_cmd_req(u8 *cmd_ptr, int *write= _only, int resume) } else { u64 data; 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Fri, 5 Jun 2026 07:09:10 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id yYL3EBZ2ImowHgAAD6G6ig (envelope-from ); Fri, 05 Jun 2026 07:09:10 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org, linux-pm@vger.kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba Subject: [PATCH 7/8] x86/msr: Switch wrmsr_safe_on_cpu() to use a 64-bit quantity Date: Fri, 5 Jun 2026 09:08:25 +0200 Message-ID: <20260605070826.2995913-8-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260605070826.2995913-1-jgross@suse.com> References: <20260605070826.2995913-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam-Flag: NO X-Spamd-Result: default: False [-6.80 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:helo,suse.com:email,suse.com:mid]; ARC_NA(0.00)[]; MIME_TRACE(0.00)[0:+]; TO_DN_SOME(0.00)[]; RCPT_COUNT_TWELVE(0.00)[13]; RCVD_VIA_SMTP_AUTH(0.00)[]; FUZZY_RATELIMITED(0.00)[rspamd.com]; FROM_HAS_DN(0.00)[]; TO_MATCH_ENVRCPT_ALL(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; R_RATELIMIT(0.00)[to_ip_from(RLfdszjqhz8kzzb9uwpzdm8png)]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; RCVD_TLS_ALL(0.00)[] X-Spam-Level: X-Spam-Score: -6.80 Content-Type: text/plain; charset="utf-8" In order to prepare retiring wrmsrq_safe_on_cpu() switch wrmsr_safe_on_cpu() to have the same interface as wrmsrq_safe_on_cpu(). Switch all wrmsr_safe_on_cpu() callers to use the new interface. Signed-off-by: Juergen Gross --- arch/x86/include/asm/msr.h | 6 +++--- arch/x86/kernel/msr.c | 4 ++-- arch/x86/lib/msr-smp.c | 5 ++--- drivers/thermal/intel/intel_tcc.c | 2 +- 4 files changed, 8 insertions(+), 9 deletions(-) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index f2d14c670140..cb14ede8f587 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -261,7 +261,7 @@ int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u64 q); void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr __pe= rcpu *msrs); void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr __pe= rcpu *msrs); int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); -int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); +int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q); int wrmsrq_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q); int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); @@ -290,9 +290,9 @@ static inline int rdmsr_safe_on_cpu(unsigned int cpu, u= 32 msr_no, u64 *q) { return rdmsrq_safe(msr_no, q); } -static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u= 32 h) +static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q) { - return wrmsr_safe(msr_no, l, h); + return wrmsrq_safe(msr_no, q); } static inline int wrmsrq_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q) { diff --git a/arch/x86/kernel/msr.c b/arch/x86/kernel/msr.c index c9429a718810..db4b5c07ba22 100644 --- a/arch/x86/kernel/msr.c +++ b/arch/x86/kernel/msr.c @@ -109,7 +109,7 @@ static ssize_t msr_write(struct file *file, const char = __user *buf, size_t count, loff_t *ppos) { const u32 __user *tmp =3D (const u32 __user *)buf; - u32 data[2]; + u64 data; u32 reg =3D *ppos; int cpu =3D iminor(file_inode(file)); int err =3D 0; @@ -134,7 +134,7 @@ static ssize_t msr_write(struct file *file, const char = __user *buf, =20 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); =20 - err =3D wrmsr_safe_on_cpu(cpu, reg, data[0], data[1]); + err =3D wrmsr_safe_on_cpu(cpu, reg, data); if (err) break; =20 diff --git a/arch/x86/lib/msr-smp.c b/arch/x86/lib/msr-smp.c index fa22ac662c1d..b2859435f4af 100644 --- a/arch/x86/lib/msr-smp.c +++ b/arch/x86/lib/msr-smp.c @@ -154,7 +154,7 @@ int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u64= *q) } EXPORT_SYMBOL(rdmsr_safe_on_cpu); =20 -int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) +int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q) { int err; struct msr_info rv; @@ -162,8 +162,7 @@ int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32= l, u32 h) memset(&rv, 0, sizeof(rv)); =20 rv.msr_no =3D msr_no; - rv.reg.l =3D l; - rv.reg.h =3D h; + rv.reg.q =3D q; err =3D smp_call_function_single(cpu, __wrmsr_safe_on_cpu, &rv, 1); =20 return err ? err : rv.err; diff --git a/drivers/thermal/intel/intel_tcc.c b/drivers/thermal/intel/inte= l_tcc.c index 9a8f2f101efc..8c80f9bfbea4 100644 --- a/drivers/thermal/intel/intel_tcc.c +++ b/drivers/thermal/intel/intel_tcc.c @@ -261,7 +261,7 @@ int intel_tcc_set_offset(int cpu, int offset) if (cpu < 0) return wrmsr_safe(MSR_IA32_TEMPERATURE_TARGET, val.l, val.h); else - return wrmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, val.l, val.h); + return wrmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, val.q); } EXPORT_SYMBOL_NS_GPL(intel_tcc_set_offset, "INTEL_TCC"); =20 --=20 2.54.0 From nobody Mon Jun 8 06:36:45 2026 Received: from smtp-out2.suse.de (smtp-out2.suse.de [195.135.223.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF3CE477983 for ; Fri, 5 Jun 2026 07:09:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.135.223.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780643359; cv=none; b=pDPgAgc7FE6nheXV84Yl6I1Jsd9pmlgbnA6WfRSufP75OtqDGSYzCtUpC6HjS1l7gIr2a0I8gm/R74j2wVy77QmmRuVrqzH7UR+w6jUyZn6lwp6eOTfvwt/kVJw4SLf9oGxhwpJJVSSRm262omHr4W9Rp3zr1BTsm6N7FHVCit0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780643359; c=relaxed/simple; bh=kR4LNuPs6sRNL3Cz/R3SgtN14fjPcG0Vz5lrtcDtJPM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BmHduOHv+VPEYPrYiQv1uATafvti9+NIExT2BK68nVmvmSeVPQs4Mn3EojUfnmbthtZKejP29VsYCUIBeRbB8fCnq9ZUw51QNaK+uUCTaXrthgB+7kFWptFk5jV4uzETrIf06P0jCE5XyqxVrZAHwsEnPN/75MXm3a38ZccRwp8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; arc=none smtp.client-ip=195.135.223.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Received: from imap1.dmz-prg2.suse.org (imap1.dmz-prg2.suse.org [IPv6:2a07:de40:b281:104:10:150:64:97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id 5718C758EE; Fri, 5 Jun 2026 07:09:16 +0000 (UTC) Authentication-Results: smtp-out2.suse.de; none Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id DCBE8779A8; Fri, 5 Jun 2026 07:09:15 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id cGTSNBt2Imo2HgAAD6G6ig (envelope-from ); Fri, 05 Jun 2026 07:09:15 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org, linux-acpi@vger.kernel.org, linux-pm@vger.kernel.org, platform-driver-x86@vger.kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , "Rafael J. Wysocki" , Len Brown , Huang Rui , Mario Limonciello , Perry Yuan , K Prateek Nayak , Viresh Kumar , Srinivas Pandruvada , Hans de Goede , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 8/8] x86/msr: Switch all callers of wrmsrq_safe_on_cpu() to use wrmsr_safe_on_cpu() Date: Fri, 5 Jun 2026 09:08:26 +0200 Message-ID: <20260605070826.2995913-9-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260605070826.2995913-1-jgross@suse.com> References: <20260605070826.2995913-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Spam-Flag: NO X-Spam-Score: -4.00 X-Spam-Level: X-Rspamd-Server: rspamd2.dmz-prg2.suse.org X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[] X-Rspamd-Queue-Id: 5718C758EE X-Rspamd-Action: no action Content-Type: text/plain; charset="utf-8" Now that wrmsr_safe_on_cpu() has the same interface as wrmsrq_safe_on_cpu(), the callers of wrmsrq_safe_on_cpu() can be switched to wrmsr_safe_on_cpu() and wrmsrq_safe_on_cpu() can be removed. Signed-off-by: Juergen Gross --- arch/x86/include/asm/msr.h | 5 ----- arch/x86/kernel/acpi/cppc.c | 2 +- arch/x86/lib/msr-smp.c | 16 ---------------- drivers/cpufreq/amd-pstate.c | 2 +- .../x86/intel/speed_select_if/isst_if_common.c | 9 ++++----- 5 files changed, 6 insertions(+), 28 deletions(-) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index cb14ede8f587..a5596d268053 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -262,7 +262,6 @@ void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_= no, struct msr __percpu * void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr __pe= rcpu *msrs); int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q); -int wrmsrq_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q); int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); #else /* CONFIG_SMP */ @@ -294,10 +293,6 @@ static inline int wrmsr_safe_on_cpu(unsigned int cpu, = u32 msr_no, u64 q) { return wrmsrq_safe(msr_no, q); } -static inline int wrmsrq_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q) -{ - return wrmsrq_safe(msr_no, q); -} static inline int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) { return rdmsr_safe_regs(regs); diff --git a/arch/x86/kernel/acpi/cppc.c b/arch/x86/kernel/acpi/cppc.c index 86bf2dafdf72..327fdcecfa3b 100644 --- a/arch/x86/kernel/acpi/cppc.c +++ b/arch/x86/kernel/acpi/cppc.c @@ -74,7 +74,7 @@ int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 va= l) val &=3D mask; rd_val &=3D ~mask; rd_val |=3D val; - err =3D wrmsrq_safe_on_cpu(cpunum, reg->address, rd_val); + err =3D wrmsr_safe_on_cpu(cpunum, reg->address, rd_val); } return err; } diff --git a/arch/x86/lib/msr-smp.c b/arch/x86/lib/msr-smp.c index b2859435f4af..9ae9ff11f1f1 100644 --- a/arch/x86/lib/msr-smp.c +++ b/arch/x86/lib/msr-smp.c @@ -169,22 +169,6 @@ int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u6= 4 q) } EXPORT_SYMBOL(wrmsr_safe_on_cpu); =20 -int wrmsrq_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q) -{ - int err; - struct msr_info rv; - - memset(&rv, 0, sizeof(rv)); - - rv.msr_no =3D msr_no; - rv.reg.q =3D q; - - err =3D smp_call_function_single(cpu, __wrmsr_safe_on_cpu, &rv, 1); - - return err ? err : rv.err; -} -EXPORT_SYMBOL(wrmsrq_safe_on_cpu); - /* * These variants are significantly slower, but allows control over * the entire 32-bit GPR set. diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 36c9c1e98115..355c5fb9313a 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -446,7 +446,7 @@ static int shmem_set_epp(struct cpufreq_policy *policy,= u8 epp) =20 static inline int msr_cppc_enable(struct cpufreq_policy *policy) { - return wrmsrq_safe_on_cpu(policy->cpu, MSR_AMD_CPPC_ENABLE, 1); + return wrmsr_safe_on_cpu(policy->cpu, MSR_AMD_CPPC_ENABLE, 1); } =20 static int shmem_cppc_enable(struct cpufreq_policy *policy) diff --git a/drivers/platform/x86/intel/speed_select_if/isst_if_common.c b/= drivers/platform/x86/intel/speed_select_if/isst_if_common.c index b15a798454dc..9d730e6f155d 100644 --- a/drivers/platform/x86/intel/speed_select_if/isst_if_common.c +++ b/drivers/platform/x86/intel/speed_select_if/isst_if_common.c @@ -192,8 +192,8 @@ void isst_resume_common(void) if (cb->registered) isst_mbox_resume_command(cb, sst_cmd); } else { - wrmsrq_safe_on_cpu(sst_cmd->cpu, sst_cmd->cmd, - sst_cmd->data); + wrmsr_safe_on_cpu(sst_cmd->cpu, sst_cmd->cmd, + sst_cmd->data); } } } @@ -500,9 +500,8 @@ static long isst_if_msr_cmd_req(u8 *cmd_ptr, int *write= _only, int resume) if (!capable(CAP_SYS_ADMIN)) return -EPERM; =20 - ret =3D wrmsrq_safe_on_cpu(msr_cmd->logical_cpu, - msr_cmd->msr, - msr_cmd->data); + ret =3D wrmsr_safe_on_cpu(msr_cmd->logical_cpu, + msr_cmd->msr, msr_cmd->data); *write_only =3D 1; if (!ret && !resume) ret =3D isst_store_cmd(0, msr_cmd->msr, --=20 2.54.0