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charset="utf-8" From: Joakim Zhang The Cix Sky1 Audio Subsystem (AUDSS) groups audio-related clock, reset and control registers in a dedicated CRU block. Software reset lines are exposed on the syscon parent via #reset-cells, following the same model as the existing Sky1 FCH and S5 system control bindings. Add the cix,sky1-audss-system-control compatible to cix,sky1-system-control.yaml for the MFD/syscon parent node, and define AUDSS software reset indices in include/dt-bindings/reset/cix,sky1-audss-system-control.h for I2S, HDA, DMAC, mailbox, watchdog and timer blocks. Signed-off-by: Joakim Zhang --- .../soc/cix/cix,sky1-system-control.yaml | 39 ++++++++++++++++--- .../reset/cix,sky1-audss-system-control.h | 27 +++++++++++++ 2 files changed, 61 insertions(+), 5 deletions(-) create mode 100644 include/dt-bindings/reset/cix,sky1-audss-system-control= .h diff --git a/Documentation/devicetree/bindings/soc/cix/cix,sky1-system-cont= rol.yaml b/Documentation/devicetree/bindings/soc/cix/cix,sky1-system-contro= l.yaml index a01a515222c6..3b243b02a7e8 100644 --- a/Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml +++ b/Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml @@ -15,11 +15,16 @@ description: =20 properties: compatible: - items: - - enum: - - cix,sky1-system-control - - cix,sky1-s5-system-control - - const: syscon + oneOf: + - items: + - enum: + - cix,sky1-system-control + - cix,sky1-s5-system-control + - const: syscon + - items: + - const: cix,sky1-audss-system-control + - const: simple-mfd + - const: syscon =20 reg: maxItems: 1 @@ -27,6 +32,11 @@ properties: '#reset-cells': const: 1 =20 + clock-controller: + $ref: /schemas/clock/cix,sky1-audss-clock.yaml# + description: + AUDSS internal clock provider (cix,sky1-audss-system-control only). + required: - compatible - reg @@ -40,3 +50,22 @@ examples: reg =3D <0x4160000 0x100>; #reset-cells =3D <1>; }; + - | + #include + + audss_syscon: system-controller@7110000 { + compatible =3D "cix,sky1-audss-system-control", "simple-mfd", "sys= con"; + reg =3D <0x7110000 0x10000>; + #reset-cells =3D <1>; + + clock-controller { + compatible =3D "cix,sky1-audss-clock"; + power-domains =3D <&smc_devpd 0>; + #clock-cells =3D <1>; + clocks =3D <&scmi_clk 0>, <&scmi_clk 1>, <&scmi_clk 2>, + <&scmi_clk 3>, <&scmi_clk 4>, <&scmi_clk 5>; + clock-names =3D "audio_clk0", "audio_clk1", "audio_clk2", + "audio_clk3", "audio_clk4", "audio_clk5"; + resets =3D <&src 0>; + }; + }; diff --git a/include/dt-bindings/reset/cix,sky1-audss-system-control.h b/in= clude/dt-bindings/reset/cix,sky1-audss-system-control.h new file mode 100644 index 000000000000..2ebc5c4f10cd --- /dev/null +++ b/include/dt-bindings/reset/cix,sky1-audss-system-control.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright 2026 Cix Technology Group Co., Ltd. + */ +#ifndef DT_BINDING_RESET_CIX_SKY1_AUDSS_SYSTEM_CONTROL_H +#define DT_BINDING_RESET_CIX_SKY1_AUDSS_SYSTEM_CONTROL_H + +#define AUDSS_I2S0_SW_RST_N 0 +#define AUDSS_I2S1_SW_RST_N 1 +#define AUDSS_I2S2_SW_RST_N 2 +#define AUDSS_I2S3_SW_RST_N 3 +#define AUDSS_I2S4_SW_RST_N 4 +#define AUDSS_I2S5_SW_RST_N 5 +#define AUDSS_I2S6_SW_RST_N 6 +#define AUDSS_I2S7_SW_RST_N 7 +#define AUDSS_I2S8_SW_RST_N 8 +#define AUDSS_I2S9_SW_RST_N 9 +#define AUDSS_WDT_SW_RST_N 10 +#define AUDSS_TIMER_SW_RST_N 11 +#define AUDSS_MB0_SW_RST_N 12 +#define AUDSS_MB1_SW_RST_N 13 +#define AUDSS_HDA_SW_RST_N 14 +#define AUDSS_DMAC_SW_RST_N 15 + +#define SKY1_AUDSS_SW_RESET_NUM 16 + +#endif --=20 2.50.1 From nobody Mon Jun 8 07:23:00 2026 Received: from SEYPR02CU001.outbound.protection.outlook.com (mail-koreacentralazon11023085.outbound.protection.outlook.com [40.107.44.85]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7BCAA3655ED; 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charset="utf-8" From: Joakim Zhang Extend the Sky1 reset controller driver for the AUDSS CRU syscon. The AUDSS block provides sixteen active-low software reset bits in one register for audio subsystem peripherals. Add a device tree match for cix,sky1-audss-system-control and the corresponding reset signal table in reset-sky1.c, reusing the existing regmap-based reset ops used by the FCH and S5 system control variants. Signed-off-by: Joakim Zhang --- drivers/reset/reset-sky1.c | 36 ++++++++++++++++++++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) diff --git a/drivers/reset/reset-sky1.c b/drivers/reset/reset-sky1.c index 78e80a533c39..ff91ce93c16b 100644 --- a/drivers/reset/reset-sky1.c +++ b/drivers/reset/reset-sky1.c @@ -16,6 +16,7 @@ =20 #include #include +#include =20 #define SKY1_RESET_SLEEP_MIN_US 50 #define SKY1_RESET_SLEEP_MAX_US 100 @@ -258,6 +259,34 @@ static const struct sky1_src_variant variant_sky1_fch = =3D { .signals_num =3D ARRAY_SIZE(sky1_src_fch_signals), }; =20 +enum { + AUDSS_SW_RST =3D 0x78, +}; + +static const struct sky1_src_signal sky1_audss_signals[SKY1_AUDSS_SW_RESET= _NUM] =3D { + [AUDSS_I2S0_SW_RST_N] =3D { AUDSS_SW_RST, BIT(0) }, + [AUDSS_I2S1_SW_RST_N] =3D { AUDSS_SW_RST, BIT(1) }, + [AUDSS_I2S2_SW_RST_N] =3D { AUDSS_SW_RST, BIT(2) }, + [AUDSS_I2S3_SW_RST_N] =3D { AUDSS_SW_RST, BIT(3) }, + [AUDSS_I2S4_SW_RST_N] =3D { AUDSS_SW_RST, BIT(4) }, + [AUDSS_I2S5_SW_RST_N] =3D { AUDSS_SW_RST, BIT(5) }, + [AUDSS_I2S6_SW_RST_N] =3D { AUDSS_SW_RST, BIT(6) }, + [AUDSS_I2S7_SW_RST_N] =3D { AUDSS_SW_RST, BIT(7) }, + [AUDSS_I2S8_SW_RST_N] =3D { AUDSS_SW_RST, BIT(8) }, + [AUDSS_I2S9_SW_RST_N] =3D { AUDSS_SW_RST, BIT(9) }, + [AUDSS_WDT_SW_RST_N] =3D { AUDSS_SW_RST, BIT(10) }, + [AUDSS_TIMER_SW_RST_N] =3D { AUDSS_SW_RST, BIT(11) }, + [AUDSS_MB0_SW_RST_N] =3D { AUDSS_SW_RST, BIT(12) }, + [AUDSS_MB1_SW_RST_N] =3D { AUDSS_SW_RST, BIT(13) }, + [AUDSS_HDA_SW_RST_N] =3D { AUDSS_SW_RST, BIT(14) }, + [AUDSS_DMAC_SW_RST_N] =3D { AUDSS_SW_RST, BIT(15) }, +}; + +static const struct sky1_src_variant variant_sky1_audss =3D { + .signals =3D sky1_audss_signals, + .signals_num =3D ARRAY_SIZE(sky1_audss_signals), +}; + static struct sky1_src *to_sky1_src(struct reset_controller_dev *rcdev) { return container_of(rcdev, struct sky1_src, rcdev); @@ -329,6 +358,8 @@ static int sky1_reset_probe(struct platform_device *pde= v) return -ENOMEM; =20 variant =3D of_device_get_match_data(dev); + if (!variant) + return -ENODEV; =20 sky1src->regmap =3D device_node_to_regmap(dev->of_node); if (IS_ERR(sky1src->regmap)) { @@ -347,8 +378,9 @@ static int sky1_reset_probe(struct platform_device *pde= v) } =20 static const struct of_device_id sky1_sysreg_of_match[] =3D { - { .compatible =3D "cix,sky1-system-control", .data =3D &variant_sky1_fch}, - { .compatible =3D "cix,sky1-s5-system-control", .data =3D &variant_sky1}, + { .compatible =3D "cix,sky1-system-control", .data =3D &variant_sky1_fch = }, + { .compatible =3D "cix,sky1-s5-system-control", .data =3D &variant_sky1 }, + { .compatible =3D "cix,sky1-audss-system-control", .data =3D &variant_sky= 1_audss }, {}, }; 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Fri, 5 Jun 2026 11:23:41 +0800 (CST) From: joakim.zhang@cixtech.com To: mturquette@baylibre.com, sboyd@kernel.org, bmasney@redhat.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, gary.yang@cixtech.com Cc: cix-kernel-upstream@cixtech.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Joakim Zhang Subject: [PATCH v2 3/5] dt-bindings: clock: cix,sky1-audss-clock: add audss clock controller Date: Fri, 5 Jun 2026 11:22:23 +0800 Message-ID: <20260605032225.523669-4-joakim.zhang@cixtech.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260605032225.523669-1-joakim.zhang@cixtech.com> References: <20260605032225.523669-1-joakim.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: OSA0EPF000000C9:EE_|KU2PPF0C4CE1E54:EE_ X-MS-Office365-Filtering-Correlation-Id: a7ececbb-b89f-4b78-5133-08dec2b1d9a4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|1800799024|36860700016|22082099003|18002099003|6133799003|56012099006|3023799007; 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charset="utf-8" From: Joakim Zhang The AUDSS CRU contains an internal clock tree of muxes, dividers and gates for DSP, I2S, HDA, DMAC and related blocks. The clock provider is a child node of the cix,sky1-audss-system-control syscon and accesses registers through the parent MMIO region. Add the devicetree binding for cix,sky1-audss-clock and clock indices in include/dt-bindings/clock/cix,sky1-audss.h. Document the parent syscon indices. Signed-off-by: Joakim Zhang --- .../bindings/clock/cix,sky1-audss-clock.yaml | 92 +++++++++++++++++++ include/dt-bindings/clock/cix,sky1-audss.h | 62 +++++++++++++ 2 files changed, 154 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/cix,sky1-audss-= clock.yaml create mode 100644 include/dt-bindings/clock/cix,sky1-audss.h diff --git a/Documentation/devicetree/bindings/clock/cix,sky1-audss-clock.y= aml b/Documentation/devicetree/bindings/clock/cix,sky1-audss-clock.yaml new file mode 100644 index 000000000000..22b4cc72f395 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/cix,sky1-audss-clock.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/cix,sky1-audss-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cix Sky1 audio subsystem clock controller + +maintainers: + - Joakim Zhang + +description: | + Clock provider for the Cix Sky1 audio subsystem (AUDSS). + + This node is a child of a cix,sky1-audss-system-control MFD/syscon node + (see cix,sky1-system-control.yaml). It does not have a reg property; clo= ck + mux, divider and gate fields are accessed through the parent register bl= ock. + + Software reset lines for AUDSS blocks are exposed on the parent syscon v= ia + #reset-cells. Reset indices are defined in + include/dt-bindings/reset/cix,sky1-audss-system-control.h. + + Six SoC-level reference clocks listed in clocks/clock-names feed the AUD= SS + clock tree. The provider exposes the internal AUDSS clocks to other devi= ces + via #clock-cells; indices are defined in cix,sky1-audss.h. + +properties: + compatible: + const: cix,sky1-audss-clock + + '#clock-cells': + const: 1 + description: + Clock indices are defined in include/dt-bindings/clock/cix,sky1-auds= s.h. + + clocks: + minItems: 6 + maxItems: 6 + description: + Six SoC-level audio reference clocks that feed the audio subsystem, + in the same order as clock-names. + + clock-names: + items: + - const: audio_clk0 + - const: audio_clk1 + - const: audio_clk2 + - const: audio_clk3 + - const: audio_clk4 + - const: audio_clk5 + + resets: + maxItems: 1 + description: Audio subsystem NoC (or bus) reset line. + + power-domains: + maxItems: 1 + description: Audio subsystem power domain. + +required: + - compatible + - '#clock-cells' + - clocks + - clock-names + - resets + - power-domains + +additionalProperties: false + +examples: + - | + #include + #include + #include + + audss_syscon: system-controller@7110000 { + compatible =3D "cix,sky1-audss-system-control", "simple-mfd", "sys= con"; + reg =3D <0x7110000 0x10000>; + #reset-cells =3D <1>; + + audss_clk: clock-controller { + compatible =3D "cix,sky1-audss-clock"; + power-domains =3D <&smc_devpd 0>; + #clock-cells =3D <1>; + clocks =3D <&scmi_clk CLK_TREE_AUDIO_CLK0>, <&scmi_clk CLK_TRE= E_AUDIO_CLK1>, + <&scmi_clk CLK_TREE_AUDIO_CLK2>, <&scmi_clk CLK_TREE_= AUDIO_CLK3>, + <&scmi_clk CLK_TREE_AUDIO_CLK4>, <&scmi_clk CLK_TREE_= AUDIO_CLK5>; + clock-names =3D "audio_clk0", "audio_clk1", "audio_clk2", + "audio_clk3", "audio_clk4", "audio_clk5"; + resets =3D <&src SKY1_AUDIO_HIFI5_NOC_RESET_N>; + }; + }; diff --git a/include/dt-bindings/clock/cix,sky1-audss.h b/include/dt-bindin= gs/clock/cix,sky1-audss.h new file mode 100644 index 000000000000..041f9daa1ee4 --- /dev/null +++ b/include/dt-bindings/clock/cix,sky1-audss.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright 2026 Cix Technology Group Co., Ltd. + */ + +#ifndef _DT_BINDINGS_CLK_CIX_SKY1_AUDSS_H +#define _DT_BINDINGS_CLK_CIX_SKY1_AUDSS_H + +#define CLK_AUD_CLK4_DIV2 0 +#define CLK_AUD_CLK4_DIV4 1 +#define CLK_AUD_CLK5_DIV2 2 + +#define CLK_DSP_CLK 3 +#define CLK_DSP_BCLK 4 +#define CLK_DSP_PBCLK 5 + +#define CLK_SRAM_AXI 6 + +#define CLK_HDA_SYS 7 +#define CLK_HDA_HDA 8 + +#define CLK_DMAC_AXI 9 + +#define CLK_WDG_APB 10 +#define CLK_WDG_WDG 11 + +#define CLK_TIMER_APB 12 +#define CLK_TIMER_TIMER 13 + +#define CLK_MB_0_APB 14 /* MB0: ap->dsp */ +#define CLK_MB_1_APB 15 /* MB1: dsp->ap */ + +#define CLK_I2S0_APB 16 +#define CLK_I2S1_APB 17 +#define CLK_I2S2_APB 18 +#define CLK_I2S3_APB 19 +#define CLK_I2S4_APB 20 +#define CLK_I2S5_APB 21 +#define CLK_I2S6_APB 22 +#define CLK_I2S7_APB 23 +#define CLK_I2S8_APB 24 +#define CLK_I2S9_APB 25 +#define CLK_I2S0 26 +#define CLK_I2S1 27 +#define CLK_I2S2 28 +#define CLK_I2S3 29 +#define CLK_I2S4 30 +#define CLK_I2S5 31 +#define CLK_I2S6 32 +#define CLK_I2S7 33 +#define CLK_I2S8 34 +#define CLK_I2S9 35 + +#define CLK_MCLK0 36 +#define CLK_MCLK1 37 +#define CLK_MCLK2 38 +#define CLK_MCLK3 39 +#define CLK_MCLK4 40 + +#define AUDSS_MAX_CLKS 41 + +#endif --=20 2.50.1 From nobody Mon Jun 8 07:23:00 2026 Received: from TYDPR03CU002.outbound.protection.outlook.com (mail-japaneastazon11023099.outbound.protection.outlook.com [52.101.127.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3EEC53542F6; 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charset="utf-8" From: Joakim Zhang Add a platform driver for the Cix Sky1 Audio Subsystem (AUDSS) internal clock controller. The driver binds to a cix,sky1-audss-clock device tree node under the AUDSS syscon, obtains the parent regmap via syscon_node_to_regmap(), and registers mux/divider/gate composite clocks for DSP, SRAM, HDA, DMAC, watchdog, timer, mailbox and I2S outputs. Six SoC-level audio reference clocks are brought up as inputs to the tree. Signed-off-by: Joakim Zhang --- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/cix/Kconfig | 16 + drivers/clk/cix/Makefile | 3 + drivers/clk/cix/clk-sky1-audss.c | 1129 ++++++++++++++++++++++++++++++ 5 files changed, 1150 insertions(+) create mode 100644 drivers/clk/cix/Kconfig create mode 100644 drivers/clk/cix/Makefile create mode 100644 drivers/clk/cix/clk-sky1-audss.c diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index b2efbe9f6acb..ead41e45c0f6 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -503,6 +503,7 @@ source "drivers/clk/actions/Kconfig" source "drivers/clk/analogbits/Kconfig" source "drivers/clk/aspeed/Kconfig" source "drivers/clk/bcm/Kconfig" +source "drivers/clk/cix/Kconfig" source "drivers/clk/eswin/Kconfig" source "drivers/clk/hisilicon/Kconfig" source "drivers/clk/imgtec/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index a3e2862ebd7e..9135ea6e5a8f 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -118,6 +118,7 @@ obj-$(CONFIG_ARCH_ARTPEC) +=3D axis/ obj-$(CONFIG_ARC_PLAT_AXS10X) +=3D axs10x/ obj-y +=3D bcm/ obj-$(CONFIG_ARCH_BERLIN) +=3D berlin/ +obj-y +=3D cix/ obj-$(CONFIG_ARCH_DAVINCI) +=3D davinci/ obj-$(CONFIG_COMMON_CLK_ESWIN) +=3D eswin/ obj-$(CONFIG_ARCH_HISI) +=3D hisilicon/ diff --git a/drivers/clk/cix/Kconfig b/drivers/clk/cix/Kconfig new file mode 100644 index 000000000000..3909796f8656 --- /dev/null +++ b/drivers/clk/cix/Kconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0 +# Audio subsystem clock support for Cixtech SoC family +menu "Clock support for Cixtech audss" + +config CLK_SKY1_AUDSS + tristate "Cixtech Sky1 Audio Subsystem Clock Driver" + depends on ARCH_CIX || COMPILE_TEST + select MFD_SYSCON + select REGMAP_MMIO + select RESET_CONTROLLER + help + Support for the Audio Subsystem clock controller present on + Cixtech Sky1 SoC. This driver provides mux, divider and gate + clocks for DSP, I2S, HDA and related blocks in the audio + subsystem. Say M or Y here if you want to build this driver. +endmenu diff --git a/drivers/clk/cix/Makefile b/drivers/clk/cix/Makefile new file mode 100644 index 000000000000..bc612f1d08b2 --- /dev/null +++ b/drivers/clk/cix/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_CLK_SKY1_AUDSS) +=3D clk-sky1-audss.o diff --git a/drivers/clk/cix/clk-sky1-audss.c b/drivers/clk/cix/clk-sky1-au= dss.c new file mode 100644 index 000000000000..899452d5ed14 --- /dev/null +++ b/drivers/clk/cix/clk-sky1-audss.c @@ -0,0 +1,1129 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright 2026 Cix Technology Group Co., Ltd. + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define INFO_HIFI0 0x00 +#define INFO_CLK_GATE 0x10 +#define INFO_CLK_DIV 0x14 +#define INFO_CLK_MUX 0x18 +#define INFO_MCLK 0x70 + +#define SKY1_AUDSS_CLK_PARENTS_CNT 6 +#define AUDSS_CLK_PARENTS_MAX SKY1_AUDSS_CLK_PARENTS_CNT + +static u32 sky1_reg_save[][2] =3D { + { INFO_HIFI0, 0 }, + { INFO_CLK_GATE, 0 }, + { INFO_CLK_DIV, 0 }, + { INFO_CLK_MUX, 0 }, + { INFO_MCLK, 0 }, +}; + +static const char * const sky1_audss_clk_names[SKY1_AUDSS_CLK_PARENTS_CNT]= =3D { + "audio_clk0", "audio_clk1", "audio_clk2", + "audio_clk3", "audio_clk4", "audio_clk5", +}; + +static const u32 sky1_clk_rate_default[SKY1_AUDSS_CLK_PARENTS_CNT] =3D { + 294912000, + 344064000, + 270950400, + 316108800, + 800000000, + 48000000, +}; + +static const char * const dsp_clk_parent[] =3D { + "audio_clk4" +}; + +static const char * const dsp_bclk_parent[] =3D { + "audio_clk4_div2" +}; + +static const char * const dsp_pbclk_parent[] =3D { + "audio_clk4_div4" +}; + +static const char * const sram_axi_parent[] =3D { + "audio_clk4_div2" +}; + +static const char * const hda_sys_parent[] =3D { + "audio_clk4_div2" +}; + +static const char * const hda_hda_parent[] =3D { + "audio_clk5" +}; + +static const char * const dmac_axi_parent[] =3D { + "audio_clk4_div2" +}; + +static const char * const wdg_apb_parent[] =3D { + "audio_clk5_div2" +}; + +static const char * const wdg_wdg_parent[] =3D { + "audio_clk5_div2" +}; + +static const char * const timer_apb_parent[] =3D { + "audio_clk4_div4" +}; + +static const char * const timer_timer_parent[] =3D { + "audio_clk5_div2" +}; + +static const char * const mailbox_apb_parent[] =3D { + "audio_clk4_div4" +}; + +static const char * const i2s_apb_parent[] =3D { + "audio_clk4_div4" +}; + +static const char * const i2s0_parents[] =3D { + "audio_clk0", "audio_clk2" +}; + +static const char * const i2s1_parents[] =3D { + "audio_clk0", "audio_clk2" +}; + +static const char * const i2s2_parents[] =3D { + "audio_clk0", "audio_clk2" +}; + +static const char * const i2s3_parents[] =3D { + "audio_clk0", "audio_clk1", "audio_clk2", "audio_clk3" +}; + +static const char * const i2s4_parents[] =3D { + "audio_clk0", "audio_clk1", "audio_clk2", "audio_clk3" +}; + +static const char * const i2s5_parents[] =3D { + "audio_clk0", "audio_clk2" +}; + +static const char * const i2s6_parents[] =3D { + "audio_clk0", "audio_clk2" +}; + +static const char * const i2s7_parents[] =3D { + "audio_clk0", "audio_clk2" +}; + +static const char * const i2s8_parents[] =3D { + "audio_clk0", "audio_clk2" +}; + +static const char * const i2s9_parents[] =3D { + "audio_clk0", "audio_clk2" +}; + +static const char * const mclk_parents[] =3D { + "audio_clk0", "audio_clk2" +}; + +/* + * audss composite clock definition + */ +struct muxdiv_cfg { + int offset; + u8 shift; + u8 width; + u8 flags; +}; + +struct gate_cfg { + int offset; + u8 shift; + u8 flags; +}; + +struct composite_clk_cfg { + u32 id; + const char * const name; + const char * const *parent_names; + int num_parents; + struct muxdiv_cfg *mux_cfg; + struct muxdiv_cfg *div_cfg; + struct gate_cfg *gate_cfg; + unsigned long flags; +}; + +#define CFG(_id,\ + _name,\ + _parent_names,\ + _mux_offset, _mux_shift, _mux_width, _mux_flags,\ + _div_offset, _div_shift, _div_width, _div_flags,\ + _gate_offset, _gate_shift, _gate_flags,\ + _flags)\ +{\ + .id =3D _id,\ + .name =3D _name,\ + .parent_names =3D _parent_names,\ + .num_parents =3D ARRAY_SIZE(_parent_names),\ + .mux_cfg =3D &(struct muxdiv_cfg) { _mux_offset, _mux_shift, _mux_width, = _mux_flags },\ + .div_cfg =3D &(struct muxdiv_cfg) { _div_offset, _div_shift, _div_width, = _div_flags },\ + .gate_cfg =3D &(struct gate_cfg) { _gate_offset, _gate_shift, _gate_flags= },\ + .flags =3D _flags,\ +} + +static const struct composite_clk_cfg sky1_audss_clks[] =3D { + /* dsp */ + CFG(CLK_DSP_CLK, + "audss_dsp_clk", + dsp_clk_parent, + -1, 0, 0, 0, + INFO_CLK_DIV, 0, 2, 0, + INFO_HIFI0, 0, 0, + 0), + CFG(CLK_DSP_BCLK, + "audss_dsp_bclk", + dsp_bclk_parent, + -1, 0, 0, 0, + INFO_CLK_DIV, 0, 2, 0, + -1, 0, 0, + 0), + CFG(CLK_DSP_PBCLK, + "audss_dsp_pbclk", + dsp_pbclk_parent, + -1, 0, 0, 0, + INFO_CLK_DIV, 0, 2, 0, + -1, 0, 0, + 0), + /* sram */ + CFG(CLK_SRAM_AXI, + "audss_sram_axi", + sram_axi_parent, + -1, 0, 0, 0, + INFO_CLK_DIV, 0, 2, 0, + INFO_CLK_GATE, 16, 0, + 0), + /* hda */ + CFG(CLK_HDA_SYS, + "audss_hda_sys", + hda_sys_parent, + -1, 0, 0, 0, + INFO_CLK_DIV, 0, 2, 0, + INFO_CLK_GATE, 14, 0, + 0), + CFG(CLK_HDA_HDA, + "audss_hda_hda", + hda_hda_parent, + -1, 0, 0, 0, + -1, 0, 0, 0, + INFO_CLK_GATE, 14, 0, + 0), + /* dmac */ + CFG(CLK_DMAC_AXI, + "audss_dmac_axi", + dmac_axi_parent, + -1, 0, 0, 0, + INFO_CLK_DIV, 0, 2, 0, + INFO_CLK_GATE, 15, 0, + 0), + /* wdg */ + CFG(CLK_WDG_APB, + "audss_wdg_apb", + wdg_apb_parent, + -1, 0, 0, 0, + -1, 0, 0, 0, + INFO_CLK_GATE, 10, 0, + 0), + CFG(CLK_WDG_WDG, + "audss_wdg_wdg", + wdg_wdg_parent, + -1, 0, 0, 0, + -1, 0, 0, 0, + INFO_CLK_GATE, 10, 0, + 0), + /* timer */ + CFG(CLK_TIMER_APB, + "audss_timer_apb", + timer_apb_parent, + -1, 0, 0, 0, + INFO_CLK_DIV, 0, 2, 0, + INFO_CLK_GATE, 11, 0, + 0), + CFG(CLK_TIMER_TIMER, + "audss_timer_timer", + timer_timer_parent, + -1, 0, 0, 0, + -1, 0, 0, 0, + INFO_CLK_GATE, 11, 0, + 0), + /* mailbox: mb0(ap->dsp), mb1(dsp->ap) */ + CFG(CLK_MB_0_APB, + "audss_mb_0_apb", + mailbox_apb_parent, + -1, 0, 0, 0, + -1, 0, 0, 0, + INFO_CLK_GATE, 12, 0, + 0), + CFG(CLK_MB_1_APB, + "audss_mb_1_apb", + mailbox_apb_parent, + -1, 0, 0, 0, + -1, 0, 0, 0, + INFO_CLK_GATE, 13, 0, + 0), + /* i2s */ + CFG(CLK_I2S0_APB, + "audss_i2s0_apb", + i2s_apb_parent, + -1, 0, 0, 0, + INFO_CLK_DIV, 0, 2, 0, + INFO_CLK_GATE, 0, 0, + 0), + CFG(CLK_I2S1_APB, + "audss_i2s1_apb", + i2s_apb_parent, + -1, 0, 0, 0, + INFO_CLK_DIV, 0, 2, 0, + INFO_CLK_GATE, 1, 0, + 0), + CFG(CLK_I2S2_APB, + "audss_i2s2_apb", + i2s_apb_parent, + -1, 0, 0, 0, + INFO_CLK_DIV, 0, 2, 0, + INFO_CLK_GATE, 2, 0, + 0), + CFG(CLK_I2S3_APB, + "audss_i2s3_apb", + i2s_apb_parent, + -1, 0, 0, 0, + INFO_CLK_DIV, 0, 2, 0, + INFO_CLK_GATE, 3, 0, + 0), + CFG(CLK_I2S4_APB, + "audss_i2s4_apb", + i2s_apb_parent, + -1, 0, 0, 0, + INFO_CLK_DIV, 0, 2, 0, + INFO_CLK_GATE, 4, 0, + 0), + CFG(CLK_I2S5_APB, + "audss_i2s5_apb", + i2s_apb_parent, + -1, 0, 0, 0, + INFO_CLK_DIV, 0, 2, 0, + INFO_CLK_GATE, 5, 0, + 0), + CFG(CLK_I2S6_APB, + "audss_i2s6_apb", + i2s_apb_parent, + -1, 0, 0, 0, + INFO_CLK_DIV, 0, 2, 0, + INFO_CLK_GATE, 6, 0, + 0), + CFG(CLK_I2S7_APB, + "audss_i2s7_apb", + i2s_apb_parent, + -1, 0, 0, 0, + INFO_CLK_DIV, 0, 2, 0, + INFO_CLK_GATE, 7, 0, + 0), + CFG(CLK_I2S8_APB, + "audss_i2s8_apb", + i2s_apb_parent, + -1, 0, 0, 0, + INFO_CLK_DIV, 0, 2, 0, + INFO_CLK_GATE, 8, 0, + 0), + CFG(CLK_I2S9_APB, + "audss_i2s9_apb", + i2s_apb_parent, + -1, 0, 0, 0, + INFO_CLK_DIV, 0, 2, 0, + INFO_CLK_GATE, 9, 0, + 0), + CFG(CLK_I2S0, + "audss_i2s0", + i2s0_parents, + INFO_CLK_MUX, 0, 2, 0, + INFO_CLK_DIV, 2, 2, 0, + INFO_CLK_GATE, 0, 0, + 0), + CFG(CLK_I2S1, + "audss_i2s1", + i2s1_parents, + INFO_CLK_MUX, 2, 2, 0, + INFO_CLK_DIV, 4, 2, 0, + INFO_CLK_GATE, 1, 0, + 0), + CFG(CLK_I2S2, + "audss_i2s2", + i2s2_parents, + INFO_CLK_MUX, 4, 2, 0, + INFO_CLK_DIV, 6, 2, 0, + INFO_CLK_GATE, 2, 0, + 0), + CFG(CLK_I2S3, + "audss_i2s3", + i2s3_parents, + INFO_CLK_MUX, 6, 2, 0, + INFO_CLK_DIV, 8, 2, 0, + INFO_CLK_GATE, 3, 0, + 0), + CFG(CLK_I2S4, + "audss_i2s4", + i2s4_parents, + INFO_CLK_MUX, 8, 2, 0, + INFO_CLK_DIV, 10, 2, 0, + INFO_CLK_GATE, 4, 0, + 0), + CFG(CLK_I2S5, + "audss_i2s5", + i2s5_parents, + INFO_CLK_MUX, 10, 2, 0, + INFO_CLK_DIV, 12, 2, 0, + INFO_CLK_GATE, 5, 0, + 0), + CFG(CLK_I2S6, + "audss_i2s6", + i2s6_parents, + INFO_CLK_MUX, 12, 2, 0, + INFO_CLK_DIV, 14, 2, 0, + INFO_CLK_GATE, 6, 0, + 0), + CFG(CLK_I2S7, + "audss_i2s7", + i2s7_parents, + INFO_CLK_MUX, 14, 2, 0, + INFO_CLK_DIV, 16, 2, 0, + INFO_CLK_GATE, 7, 0, + 0), + CFG(CLK_I2S8, + "audss_i2s8", + i2s8_parents, + INFO_CLK_MUX, 16, 2, 0, + INFO_CLK_DIV, 18, 2, 0, + INFO_CLK_GATE, 8, 0, + 0), + CFG(CLK_I2S9, + "audss_i2s9", + i2s9_parents, + INFO_CLK_MUX, 18, 2, 0, + INFO_CLK_DIV, 20, 2, 0, + INFO_CLK_GATE, 9, 0, + 0), + /* mclk */ + CFG(CLK_MCLK0, + "audss_mclk0", + mclk_parents, + INFO_MCLK, 5, 1, 0, + -1, 0, 0, 0, + INFO_MCLK, 0, 0, + 0), + CFG(CLK_MCLK1, + "audss_mclk1", + mclk_parents, + INFO_MCLK, 6, 1, 0, + -1, 0, 0, 0, + INFO_MCLK, 1, 0, + 0), + CFG(CLK_MCLK2, + "audss_mclk2", + mclk_parents, + INFO_MCLK, 7, 1, 0, + -1, 0, 0, 0, + INFO_MCLK, 2, 0, + 0), + CFG(CLK_MCLK3, + "audss_mclk3", + mclk_parents, + INFO_MCLK, 8, 1, 0, + -1, 0, 0, 0, + INFO_MCLK, 3, 0, + 0), + CFG(CLK_MCLK4, + "audss_mclk4", + mclk_parents, + INFO_MCLK, 9, 1, 0, + -1, 0, 0, 0, + INFO_MCLK, 4, 0, + 0), +}; + +struct sky1_audss_clks_devtype_data { + u32 (*reg_save)[2]; + size_t reg_save_size; + const char * const *clk_names; + size_t clk_num; + const u32 *clk_rate_default; + const struct composite_clk_cfg *clk_cfg; + size_t clk_cfg_size; +}; + +struct sky1_audss_clks_priv { + struct device *dev; + struct regmap *regmap_cru; + struct clk *clks[AUDSS_CLK_PARENTS_MAX]; + struct reset_control *rst_noc; + const struct sky1_audss_clks_devtype_data *devtype_data; + spinlock_t lock; + struct clk_hw_onecell_data *clk_data; +}; + +/* + * clk_ops for audss clock mux/divider/gate + */ +struct sky1_clk_divider { + struct clk_divider div; + struct regmap *regmap; + int offset; +}; + +struct sky1_clk_gate { + struct clk_gate gate; + struct regmap *regmap; + int offset; +}; + +struct sky1_clk_mux { + struct clk_mux mux; + struct regmap *regmap; + int offset; +}; + +static inline struct sky1_clk_mux *to_sky1_clk_mux(struct clk_mux *mux) +{ + return container_of(mux, struct sky1_clk_mux, mux); +} + +static u8 sky1_audss_clk_mux_get_parent(struct clk_hw *hw) +{ + struct clk_mux *mux =3D to_clk_mux(hw); + struct sky1_clk_mux *sky1_mux =3D to_sky1_clk_mux(mux); + u32 val; + + regmap_read(sky1_mux->regmap, sky1_mux->offset, &val); + val =3D val >> mux->shift; + val &=3D mux->mask; + + return clk_mux_val_to_index(hw, mux->table, mux->flags, val); +} + +static int sky1_audss_clk_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct clk_mux *mux =3D to_clk_mux(hw); + u32 val =3D clk_mux_index_to_val(mux->table, mux->flags, index); + struct sky1_clk_mux *sky1_mux =3D to_sky1_clk_mux(mux); + unsigned long flags =3D 0; + u32 reg; + + if (mux->lock) + spin_lock_irqsave(mux->lock, flags); + else + __acquire(mux->lock); + + if (mux->flags & CLK_MUX_HIWORD_MASK) { + reg =3D mux->mask << (mux->shift + 16); + } else { + regmap_read(sky1_mux->regmap, sky1_mux->offset, ®); + reg &=3D ~(mux->mask << mux->shift); + } + val =3D val << mux->shift; + reg |=3D val; + regmap_write(sky1_mux->regmap, sky1_mux->offset, reg); + + if (mux->lock) + spin_unlock_irqrestore(mux->lock, flags); + else + __release(mux->lock); + + return 0; +} + +static int sky1_audss_clk_mux_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_mux *mux =3D to_clk_mux(hw); + + return clk_mux_determine_rate_flags(hw, req, mux->flags); +} + +static const struct clk_ops sky1_audss_clk_mux_ops =3D { + .get_parent =3D sky1_audss_clk_mux_get_parent, + .set_parent =3D sky1_audss_clk_mux_set_parent, + .determine_rate =3D sky1_audss_clk_mux_determine_rate, +}; + +static inline struct sky1_clk_divider *to_sky1_clk_divider(struct clk_divi= der *div) +{ + return container_of(div, struct sky1_clk_divider, div); +} + +static unsigned long sky1_audss_clk_divider_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_divider *divider =3D to_clk_divider(hw); + struct sky1_clk_divider *sky1_div =3D to_sky1_clk_divider(divider); + unsigned int val; + + regmap_read(sky1_div->regmap, sky1_div->offset, &val); + val =3D val >> divider->shift; + val &=3D clk_div_mask(divider->width); + + return divider_recalc_rate(hw, parent_rate, val, divider->table, + divider->flags, divider->width); +} + +static int sky1_audss_clk_divider_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_divider *divider =3D to_clk_divider(hw); + struct sky1_clk_divider *sky1_div =3D to_sky1_clk_divider(divider); + + /* if read only, just return current value */ + if (divider->flags & CLK_DIVIDER_READ_ONLY) { + u32 val; + + regmap_read(sky1_div->regmap, sky1_div->offset, &val); + val =3D val >> divider->shift; + val &=3D clk_div_mask(divider->width); + + return divider_ro_determine_rate(hw, req, divider->table, + divider->width, + divider->flags, val); + } + + return divider_determine_rate(hw, req, divider->table, divider->width, + divider->flags); +} + +static int sky1_audss_clk_divider_set_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate) +{ + struct clk_divider *divider =3D to_clk_divider(hw); + struct sky1_clk_divider *sky1_div =3D to_sky1_clk_divider(divider); + int value; + unsigned long flags =3D 0; + u32 val; + + value =3D divider_get_val(rate, parent_rate, divider->table, + divider->width, divider->flags); + if (value < 0) + return value; + + if (divider->lock) + spin_lock_irqsave(divider->lock, flags); + else + __acquire(divider->lock); + + if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { + val =3D clk_div_mask(divider->width) << (divider->shift + 16); + } else { + regmap_read(sky1_div->regmap, sky1_div->offset, &val); + val &=3D ~(clk_div_mask(divider->width) << divider->shift); + } + val |=3D (u32)value << divider->shift; + regmap_write(sky1_div->regmap, sky1_div->offset, val); + + if (divider->lock) + spin_unlock_irqrestore(divider->lock, flags); + else + __release(divider->lock); + + return 0; +} + +static const struct clk_ops sky1_audss_clk_divider_ops =3D { + .recalc_rate =3D sky1_audss_clk_divider_recalc_rate, + .determine_rate =3D sky1_audss_clk_divider_determine_rate, + .set_rate =3D sky1_audss_clk_divider_set_rate, +}; + +static inline struct sky1_clk_gate *to_sky1_clk_gate(struct clk_gate *gate) +{ + return container_of(gate, struct sky1_clk_gate, gate); +} + +static void sky1_audss_clk_gate_endisable(struct clk_hw *hw, int enable) +{ + struct clk_gate *gate =3D to_clk_gate(hw); + struct sky1_clk_gate *sky1_gate =3D to_sky1_clk_gate(gate); + int set =3D gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0; + unsigned long flags =3D 0; + u32 reg; + + set ^=3D enable; + + if (gate->lock) + spin_lock_irqsave(gate->lock, flags); + else + __acquire(gate->lock); + + if (gate->flags & CLK_GATE_HIWORD_MASK) { + reg =3D BIT(gate->bit_idx + 16); + if (set) + reg |=3D BIT(gate->bit_idx); + } else { + regmap_read(sky1_gate->regmap, sky1_gate->offset, ®); + + if (set) + reg |=3D BIT(gate->bit_idx); + else + reg &=3D ~BIT(gate->bit_idx); + } + + regmap_write(sky1_gate->regmap, sky1_gate->offset, reg); + + if (gate->lock) + spin_unlock_irqrestore(gate->lock, flags); + else + __release(gate->lock); +} + +static int sky1_audss_clk_gate_enable(struct clk_hw *hw) +{ + sky1_audss_clk_gate_endisable(hw, 1); + + return 0; +} + +static void sky1_audss_clk_gate_disable(struct clk_hw *hw) +{ + sky1_audss_clk_gate_endisable(hw, 0); +} + +static int sky1_audss_clk_gate_is_enabled(struct clk_hw *hw) +{ + struct clk_gate *gate =3D to_clk_gate(hw); + struct sky1_clk_gate *sky1_gate =3D to_sky1_clk_gate(gate); + u32 reg; + + regmap_read(sky1_gate->regmap, sky1_gate->offset, ®); + + /* if a set bit disables this clk, flip it before masking */ + if (gate->flags & CLK_GATE_SET_TO_DISABLE) + reg ^=3D BIT(gate->bit_idx); + + reg &=3D BIT(gate->bit_idx); + + return !!reg; +} + +static const struct clk_ops sky1_audss_clk_gate_ops =3D { + .enable =3D sky1_audss_clk_gate_enable, + .disable =3D sky1_audss_clk_gate_disable, + .is_enabled =3D sky1_audss_clk_gate_is_enabled, +}; + +static struct clk_hw *sky1_audss_clk_register(struct device *dev, + const char *name, + const char * const *parent_names, + int num_parents, + struct regmap *regmap, + struct muxdiv_cfg *mux_cfg, + struct muxdiv_cfg *div_cfg, + struct gate_cfg *gate_cfg, + unsigned long flags, + spinlock_t *lock) +{ + const struct clk_ops *sky1_mux_ops =3D NULL; + const struct clk_ops *sky1_div_ops =3D NULL; + const struct clk_ops *sky1_gate_ops =3D NULL; + struct clk_hw *hw =3D ERR_PTR(-ENOMEM); + struct sky1_clk_divider *sky1_div =3D NULL; + struct sky1_clk_gate *sky1_gate =3D NULL; + struct sky1_clk_mux *sky1_mux =3D NULL; + + if (mux_cfg->offset >=3D 0) { + sky1_mux =3D devm_kzalloc(dev, sizeof(*sky1_mux), GFP_KERNEL); + if (!sky1_mux) + return ERR_PTR(-ENOMEM); + + sky1_mux->mux.reg =3D NULL; + sky1_mux->mux.shift =3D mux_cfg->shift; + sky1_mux->mux.mask =3D BIT(mux_cfg->width) - 1; + sky1_mux->mux.flags =3D mux_cfg->flags; + sky1_mux->mux.lock =3D lock; + sky1_mux_ops =3D &sky1_audss_clk_mux_ops; + sky1_mux->regmap =3D regmap; + sky1_mux->offset =3D mux_cfg->offset; + } + + if (div_cfg->offset >=3D 0) { + sky1_div =3D devm_kzalloc(dev, sizeof(*sky1_div), GFP_KERNEL); + if (!sky1_div) + return ERR_PTR(-ENOMEM); + + sky1_div->div.reg =3D NULL; + sky1_div->div.shift =3D div_cfg->shift; + sky1_div->div.width =3D div_cfg->width; + sky1_div->div.flags =3D div_cfg->flags | CLK_DIVIDER_POWER_OF_TWO; + sky1_div->div.lock =3D lock; + sky1_div_ops =3D &sky1_audss_clk_divider_ops; + sky1_div->regmap =3D regmap; + sky1_div->offset =3D div_cfg->offset; + } + + if (gate_cfg->offset >=3D 0) { + sky1_gate =3D devm_kzalloc(dev, sizeof(*sky1_gate), GFP_KERNEL); + if (!sky1_gate) + return ERR_PTR(-ENOMEM); + + sky1_gate->gate.reg =3D NULL; + sky1_gate->gate.bit_idx =3D gate_cfg->shift; + sky1_gate->gate.flags =3D gate_cfg->flags; + sky1_gate->gate.lock =3D lock; + sky1_gate_ops =3D &sky1_audss_clk_gate_ops; + sky1_gate->regmap =3D regmap; + sky1_gate->offset =3D gate_cfg->offset; + } + + hw =3D clk_hw_register_composite(dev, name, parent_names, num_parents, + sky1_mux ? &sky1_mux->mux.hw : NULL, sky1_mux_ops, + sky1_div ? &sky1_div->div.hw : NULL, sky1_div_ops, + sky1_gate ? &sky1_gate->gate.hw : NULL, sky1_gate_ops, + flags); + if (IS_ERR(hw)) { + dev_err(dev, "register %s clock failed with err =3D %ld\n", + name, PTR_ERR(hw)); + return hw; + } + + return hw; +} + +static int sky1_audss_clks_get(struct sky1_audss_clks_priv *priv) +{ + const struct sky1_audss_clks_devtype_data *devtype_data =3D priv->devtype= _data; + int i; + + for (i =3D 0; i < devtype_data->clk_num; i++) { + priv->clks[i] =3D devm_clk_get(priv->dev, devtype_data->clk_names[i]); + if (IS_ERR(priv->clks[i])) + return dev_err_probe(priv->dev, PTR_ERR(priv->clks[i]), + "failed to get clock %s", devtype_data->clk_names[i]); + } + + return 0; +} + +static int sky1_audss_clks_enable(struct sky1_audss_clks_priv *priv) +{ + const struct sky1_audss_clks_devtype_data *devtype_data =3D priv->devtype= _data; + int i, err; + + for (i =3D 0; i < devtype_data->clk_num; i++) { + err =3D clk_prepare_enable(priv->clks[i]); + if (err) { + dev_err(priv->dev, "failed to enable clock %s\n", + devtype_data->clk_names[i]); + goto err_clks; + } + } + + return 0; + +err_clks: + while (--i >=3D 0) + clk_disable_unprepare(priv->clks[i]); + + return err; +} + +static void sky1_audss_clks_disable(struct sky1_audss_clks_priv *priv) +{ + const struct sky1_audss_clks_devtype_data *devtype_data =3D priv->devtype= _data; + int i; + + for (i =3D 0; i < devtype_data->clk_num; i++) + clk_disable_unprepare(priv->clks[i]); +} + +static int sky1_audss_clks_set_rate(struct sky1_audss_clks_priv *priv) +{ + const struct sky1_audss_clks_devtype_data *devtype_data =3D priv->devtype= _data; + int i, err; + + for (i =3D 0; i < devtype_data->clk_num; i++) { + err =3D clk_set_rate(priv->clks[i], devtype_data->clk_rate_default[i]); + if (err) { + dev_err(priv->dev, "failed to set clock rate %s\n", + devtype_data->clk_names[i]); + return err; + } + } + + return 0; +} + +/* register sky1 audio subsystem clocks */ +static int sky1_audss_clk_probe(struct platform_device *pdev) +{ + const struct sky1_audss_clks_devtype_data *devtype_data; + struct sky1_audss_clks_priv *priv; + struct device_node *parent_np; + struct device *dev =3D &pdev->dev; + struct reset_control *rst_noc; + struct clk_hw **clk_table; + struct regmap *regmap_cru; + int i, ret; + + parent_np =3D of_get_parent(pdev->dev.of_node); + regmap_cru =3D syscon_node_to_regmap(parent_np); + of_node_put(parent_np); + if (IS_ERR(regmap_cru)) + return dev_err_probe(dev, PTR_ERR(regmap_cru), + "unable to get audss cru regmap"); + + devtype_data =3D device_get_match_data(dev); + if (!devtype_data) + return -ENODEV; + + priv =3D devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + spin_lock_init(&priv->lock); + + priv->clk_data =3D devm_kzalloc(&pdev->dev, + struct_size(priv->clk_data, hws, AUDSS_MAX_CLKS), + GFP_KERNEL); + if (!priv->clk_data) + return -ENOMEM; + + priv->clk_data->num =3D AUDSS_MAX_CLKS; + clk_table =3D priv->clk_data->hws; + + priv->dev =3D dev; + priv->regmap_cru =3D regmap_cru; + priv->devtype_data =3D devtype_data; + + ret =3D sky1_audss_clks_get(priv); + if (ret) + return ret; + + rst_noc =3D devm_reset_control_get(dev, NULL); + if (IS_ERR(rst_noc)) + return dev_err_probe(dev, PTR_ERR(rst_noc), + "failed to get noc reset"); + priv->rst_noc =3D rst_noc; + + platform_set_drvdata(pdev, priv); + + ret =3D sky1_audss_clks_enable(priv); + if (ret) { + dev_err(dev, "failed to enable clocks\n"); + return ret; + } + + /* + * Enable runtime PM here to allow the clock core using runtime PM + * for the registered clocks. + */ + pm_runtime_get_noresume(dev); + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + + ret =3D sky1_audss_clks_set_rate(priv); + if (ret) { + dev_err(dev, "failed to set clocks rate\n"); + goto fail_clks_set; + } + + /* assert reset */ + reset_control_assert(rst_noc); + usleep_range(1, 2); + + /* deassert reset */ + reset_control_deassert(rst_noc); + + /* audio_clk4 clock fixed divider */ + clk_table[CLK_AUD_CLK4_DIV2] =3D + devm_clk_hw_register_fixed_factor(dev, + "audio_clk4_div2", + "audio_clk4", + 0, + 1, 2); + if (IS_ERR(clk_table[CLK_AUD_CLK4_DIV2])) { + ret =3D PTR_ERR(clk_table[CLK_AUD_CLK4_DIV2]); + dev_err(dev, "failed to register clock %d, ret:%d\n", CLK_AUD_CLK4_DIV2,= ret); + goto fail_fixed_clk; + } + + clk_table[CLK_AUD_CLK4_DIV4] =3D + devm_clk_hw_register_fixed_factor(dev, + "audio_clk4_div4", + "audio_clk4", + 0, + 1, 4); + if (IS_ERR(clk_table[CLK_AUD_CLK4_DIV4])) { + ret =3D PTR_ERR(clk_table[CLK_AUD_CLK4_DIV4]); + dev_err(dev, "failed to register clock %d, ret:%d\n", CLK_AUD_CLK4_DIV4,= ret); + goto fail_fixed_clk; + } + + /* audio_clk5 clock fixed divider */ + clk_table[CLK_AUD_CLK5_DIV2] =3D + devm_clk_hw_register_fixed_factor(dev, + "audio_clk5_div2", + "audio_clk5", + 0, + 1, 2); + if (IS_ERR(clk_table[CLK_AUD_CLK5_DIV2])) { + ret =3D PTR_ERR(clk_table[CLK_AUD_CLK5_DIV2]); + dev_err(dev, "failed to register clock %d, ret:%d\n", CLK_AUD_CLK5_DIV2,= ret); + goto fail_fixed_clk; + } + + for (i =3D 0; i < devtype_data->clk_cfg_size; i++) { + clk_table[devtype_data->clk_cfg[i].id] =3D + sky1_audss_clk_register(dev, + devtype_data->clk_cfg[i].name, + devtype_data->clk_cfg[i].parent_names, + devtype_data->clk_cfg[i].num_parents, + regmap_cru, + devtype_data->clk_cfg[i].mux_cfg, + devtype_data->clk_cfg[i].div_cfg, + devtype_data->clk_cfg[i].gate_cfg, + devtype_data->clk_cfg[i].flags, + &priv->lock); + if (IS_ERR(clk_table[devtype_data->clk_cfg[i].id])) { + ret =3D PTR_ERR(clk_table[devtype_data->clk_cfg[i].id]); + dev_err(dev, "failed to register clock %d, ret:%d\n", + devtype_data->clk_cfg[i].id, ret); + goto fail_array_clk; + } + } + + ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, priv->clk= _data); + if (ret) { + dev_err(dev, "failed to add clock provider: %d\n", ret); + goto fail_register; + } + + pm_runtime_put_sync(dev); + + return 0; + +fail_register: +fail_array_clk: + while (i--) + clk_hw_unregister_composite(clk_table[devtype_data->clk_cfg[i].id]); +fail_fixed_clk: +fail_clks_set: + pm_runtime_put_sync(dev); + pm_runtime_disable(dev); + return ret; +} + +static void sky1_audss_clk_remove(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct sky1_audss_clks_priv *priv =3D dev_get_drvdata(dev); + const struct sky1_audss_clks_devtype_data *devtype_data =3D priv->devtype= _data; + int i =3D 0; + + for (i =3D 0; i < devtype_data->clk_cfg_size; i++) + clk_hw_unregister_composite(priv->clk_data->hws[devtype_data->clk_cfg[i]= .id]); + + if (!pm_runtime_status_suspended(dev)) + pm_runtime_force_suspend(dev); + + pm_runtime_disable(dev); +} + +static int __maybe_unused sky1_audss_clk_runtime_suspend(struct device *de= v) +{ + struct sky1_audss_clks_priv *priv =3D dev_get_drvdata(dev); + const struct sky1_audss_clks_devtype_data *devtype_data =3D priv->devtype= _data; + unsigned long flags; + int i; + + spin_lock_irqsave(&priv->lock, flags); + for (i =3D 0; i < devtype_data->reg_save_size; i++) + regmap_read(priv->regmap_cru, + devtype_data->reg_save[i][0], &devtype_data->reg_save[i][1]); + spin_unlock_irqrestore(&priv->lock, flags); + + sky1_audss_clks_disable(priv); + + return 0; +} + +static int __maybe_unused sky1_audss_clk_runtime_resume(struct device *dev) +{ + struct sky1_audss_clks_priv *priv =3D dev_get_drvdata(dev); + const struct sky1_audss_clks_devtype_data *devtype_data =3D priv->devtype= _data; + unsigned long flags; + int i, ret; + + ret =3D sky1_audss_clks_enable(priv); + if (ret) { + dev_err(dev, "failed to enable clocks\n"); + return ret; + } + + reset_control_deassert(priv->rst_noc); + + spin_lock_irqsave(&priv->lock, flags); + for (i =3D 0; i < devtype_data->reg_save_size; i++) + regmap_write(priv->regmap_cru, + devtype_data->reg_save[i][0], devtype_data->reg_save[i][1]); + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static const struct dev_pm_ops sky1_audss_clk_pm_ops =3D { + SET_RUNTIME_PM_OPS(sky1_audss_clk_runtime_suspend, + sky1_audss_clk_runtime_resume, NULL) + SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) +}; + +static const struct sky1_audss_clks_devtype_data sky1_devtype_data =3D { + .reg_save =3D sky1_reg_save, + .reg_save_size =3D ARRAY_SIZE(sky1_reg_save), + .clk_names =3D sky1_audss_clk_names, + .clk_num =3D ARRAY_SIZE(sky1_audss_clk_names), + .clk_rate_default =3D sky1_clk_rate_default, + .clk_cfg =3D sky1_audss_clks, + .clk_cfg_size =3D ARRAY_SIZE(sky1_audss_clks), +}; + +static const struct of_device_id sky1_audss_clk_of_match[] =3D { + { .compatible =3D "cix,sky1-audss-clock", .data =3D &sky1_devtype_data, }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, sky1_audss_clk_of_match); + +static struct platform_driver sky1_audss_clk_driver =3D { + .probe =3D sky1_audss_clk_probe, + .remove =3D sky1_audss_clk_remove, + .driver =3D { + .name =3D "sky1-audss-clk", + .suppress_bind_attrs =3D true, + .of_match_table =3D sky1_audss_clk_of_match, + .pm =3D &sky1_audss_clk_pm_ops, + }, +}; +module_platform_driver(sky1_audss_clk_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Joakim Zhang "); +MODULE_DESCRIPTION("Cixtech Sky1 Audio Subsystem Clock Controller Driver"); --=20 2.50.1 From nobody Mon Jun 8 07:23:00 2026 Received: from SEYPR02CU001.outbound.protection.outlook.com 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TY2PEPF0000AB88.mail.protection.outlook.com (10.167.253.11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.92.5 via Frontend Transport; Fri, 5 Jun 2026 03:23:44 +0000 Received: from cix (unknown [172.18.64.61]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 66A464084272; Fri, 5 Jun 2026 11:23:43 +0800 (CST) From: joakim.zhang@cixtech.com To: mturquette@baylibre.com, sboyd@kernel.org, bmasney@redhat.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, gary.yang@cixtech.com Cc: cix-kernel-upstream@cixtech.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Joakim Zhang Subject: [PATCH v2 5/5] arm64: dts: cix: sky1: add audss system control Date: Fri, 5 Jun 2026 11:22:25 +0800 Message-ID: <20260605032225.523669-6-joakim.zhang@cixtech.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: 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X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: TY2PEPF0000AB88.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: OSNPR06MB8810 Content-Type: text/plain; charset="utf-8" From: Joakim Zhang Add audss system control device node, which would provides clocks and resets for devices in audss domain. Signed-off-by: Joakim Zhang --- arch/arm64/boot/dts/cix/sky1.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sk= y1.dtsi index bb5cfb1f2113..0edc35523c71 100644 --- a/arch/arm64/boot/dts/cix/sky1.dtsi +++ b/arch/arm64/boot/dts/cix/sky1.dtsi @@ -6,6 +6,10 @@ =20 #include #include +#include +#include +#include +#include #include "sky1-power.h" =20 / { @@ -488,6 +492,30 @@ mbox_pm2ap: mailbox@65a0080 { cix,mbox-dir =3D "rx"; }; =20 + audss_cru: system-controller@7110000 { + compatible =3D "cix,sky1-audss-system-control", "simple-mfd", "syscon"; + reg =3D <0x0 0x07110000 0x0 0x10000>; + #reset-cells =3D <1>; + status =3D "okay"; + + audss_clk: clock-controller { + compatible =3D "cix,sky1-audss-clock"; + power-domains =3D <&smc_devpd SKY1_PD_AUDIO>; + resets =3D <&s5_syscon SKY1_AUDIO_HIFI5_NOC_RESET_N>; + clocks =3D <&scmi_clk CLK_TREE_AUDIO_CLK0>, + <&scmi_clk CLK_TREE_AUDIO_CLK1>, + <&scmi_clk CLK_TREE_AUDIO_CLK2>, + <&scmi_clk CLK_TREE_AUDIO_CLK3>, + <&scmi_clk CLK_TREE_AUDIO_CLK4>, + <&scmi_clk CLK_TREE_AUDIO_CLK5>; + clock-names =3D "audio_clk0", "audio_clk1", + "audio_clk2", "audio_clk3", + "audio_clk4", "audio_clk5"; + #clock-cells =3D <1>; + status =3D "okay"; + }; + }; + mbox_sfh2ap: mailbox@8090000 { compatible =3D "cix,sky1-mbox"; reg =3D <0x0 0x08090000 0x0 0x10000>; --=20 2.50.1