From nobody Mon Jun 8 06:36:43 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1502F14883F; Fri, 5 Jun 2026 22:49:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780699790; cv=none; b=UH/YBSj4p2EUcOXWPBIOpvFvi9PvpFlkBZFG28bfzsNq754c/Y5zdzBNdTbRizTpi6jeCUrhcYcovDmCHMFLoENGknPRwfaPUG6bGhAuKw7I0b/HkqAWKMgBu2mZsWDoHhFVt5+RC+9e63H8I12GXCYF4oUrvc4ssGTbcL1NN34= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780699790; c=relaxed/simple; bh=sDCKE9eSkIGYSAz6jCq1raSQ3l07ooG0KR4VQCm+6Ns=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:To:Cc; b=b7Hg4L9HxU5geXKlhFmHFYfxThFF877Am6kWcvuyBp2skzbwffsS2E+4EuTXC28V5CO0/mFnQ6ZA6S8lfSelibILaz32NY9XVEAUyCmckcbbZ8UcgOAxJBuo4SCmrEmhWedE21fZJyCp56hdVhtZjXSm8zaRamjG+4IxPbVO0QI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=dN9Rt3nF; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dN9Rt3nF" Received: by smtp.kernel.org (Postfix) with ESMTPS id 929B0C2BCB4; Fri, 5 Jun 2026 22:49:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1780699789; bh=sDCKE9eSkIGYSAz6jCq1raSQ3l07ooG0KR4VQCm+6Ns=; h=From:Date:Subject:To:Cc:Reply-To:From; b=dN9Rt3nFvJi2B6tE46Eus9Ja+vQ0/JTu+xYjzXgLNiOP6+EZLX8NV2xiX2kY9ohFj q74xkkvoeDUVimyHMD/oWc/nGOdv5ZyGeMK4qHfJnVtUDfImohKkgmxURvlse8Gv9k 5zLWxoLRQgtQXSYjEf2XalbSgiEEcrHZSo2M3wh5oxw0a0YWUOF4nRfrfDa+0gMkpO VRePFMlD6nkDBgkNBeu8BYzgHZK9ZLZwy91C0XuB6JtmOBd/h87kJTBsXu4Tmd9eeF /NSUL0sGRrEGvx6fGlAha4Wwsx4PdKdqwlilsxQVp2vpV8iRwlN0uxrl+2bZDlhuw/ AU8hHJzfK3qZQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75955CD6E7E; Fri, 5 Jun 2026 22:49:49 +0000 (UTC) From: Aaron Kling via B4 Relay Date: Fri, 05 Jun 2026 17:49:39 -0500 Subject: [PATCH] arm64: dts: qcom: sm8750: Add UART15 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260605-sm8750-uart15-v1-1-93e660722e61@gmail.com> X-B4-Tracking: v=1; b=H4sIAAAAAAAC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDIzMDMwNT3eJcC3NTA93SxKISQ1PdVIsk41QDi9Q0c+NkJaCegqLUtMwKsHn RsbW1AOmha7RfAAAA X-Change-ID: 20260605-sm8750-uart15-e8b3e08ef73c To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Teguh Sobirin , Aaron Kling X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780699788; l=1912; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=cnBDgWatb+kdVa9LW2HFaAdpkUIfcK/vxUADNmoNfHU=; b=QoVvI1ABaISVQU2ftzSbF0cIwLI2Ra8zvNpyX3GCxMWG+S/D/GizN1QTg1ySudIsGE5O9fmF0 79SPeJapK0pDz3lnRGFk4x5AmM2U6TLDCrCXZ93dzcCkivY8yTNi2nM X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Teguh Sobirin Add uart15 node for the UART bus present on the sm8750 SoC. Signed-off-by: Teguh Sobirin Signed-off-by: Aaron Kling Reviewed-by: Dmitry Baryshkov --- arm64: dts: qcom: sm8750: Add UART15 --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qco= m/sm8750.dtsi index fafed417c66fc2..7591ebb7086f91 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -1218,6 +1218,28 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, =20 status =3D "disabled"; }; + + uart15: serial@89c000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x0089c000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart15_default>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; }; =20 i2c_master_hub_0: geniqup@9c0000 { @@ -4055,6 +4077,14 @@ qup_uart14_cts_rts: qup-uart14-cts-rts-state { bias-pull-down; }; =20 + qup_uart15_default: qup-uart15-default-state { + /* TX, RX */ + pins =3D "gpio30", "gpio31"; + function =3D "qup2_se7"; + drive-strength =3D <2>; + bias-pull-up; + }; + sdc2_sleep: sdc2-sleep-state { clk-pins { pins =3D "sdc2_clk"; --- base-commit: 6e845bcb78c95af935094040bd4edc3c2b6dd784 change-id: 20260605-sm8750-uart15-e8b3e08ef73c Best regards, --=20 Aaron Kling