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Avoid registering a reset controller when desc->num_resets is zero by making the registration conditional. Signed-off-by: Imran Shaik --- drivers/clk/qcom/common.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c index eec369d2173b5ce24bc1ca860d2ac1bbdce04524..be9b6ebb2fffde05e3f209571c5= 3b601d823d479 100644 --- a/drivers/clk/qcom/common.c +++ b/drivers/clk/qcom/common.c @@ -359,17 +359,19 @@ int qcom_cc_really_probe(struct device *dev, qcom_cc_clk_regs_configure(dev, desc->driver_data, regmap); } =20 - reset =3D &cc->reset; - reset->rcdev.of_node =3D dev->of_node; - reset->rcdev.ops =3D &qcom_reset_ops; - reset->rcdev.owner =3D dev->driver->owner; - reset->rcdev.nr_resets =3D desc->num_resets; - reset->regmap =3D regmap; - reset->reset_map =3D desc->resets; - - ret =3D devm_reset_controller_register(dev, &reset->rcdev); - if (ret) - goto put_rpm; + if (desc->num_resets) { + reset =3D &cc->reset; + reset->rcdev.of_node =3D dev->of_node; + reset->rcdev.ops =3D &qcom_reset_ops; + reset->rcdev.owner =3D dev->driver->owner; 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Fri, 05 Jun 2026 04:27:20 -0700 (PDT) X-Received: by 2002:a05:6a00:1d89:b0:842:4f49:6bfd with SMTP id d2e1a72fcca58-842b10677admr3048259b3a.26.1780658840115; Fri, 05 Jun 2026 04:27:20 -0700 (PDT) Received: from hu-imrashai-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-842828e21c8sm10626246b3a.49.2026.06.05.04.27.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Jun 2026 04:27:19 -0700 (PDT) From: Imran Shaik Date: Fri, 05 Jun 2026 16:56:31 +0530 Subject: [PATCH 2/4] dt-bindings: clock: qcom: Add Qualcomm Shikra Audio Core Clock Controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260605-shikra-audiocorecc-v1-2-7ee6b5f2d928@oss.qualcomm.com> References: <20260605-shikra-audiocorecc-v1-0-7ee6b5f2d928@oss.qualcomm.com> In-Reply-To: <20260605-shikra-audiocorecc-v1-0-7ee6b5f2d928@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: Ajit Pandey , Taniya Das , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Imran Shaik X-Mailer: b4 0.14.2 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjA1MDExMSBTYWx0ZWRfXw1eHZjsQB0Ic c6COPxy6UoWfn20ppdfehyB4VorQgTE1kJzOqtvfSilijG/pVvxwq96LIKn15QjOsyoSUT8H2fC EBCf5NQSZz50o6fxwfhSNGwMU8ZiekiT9EYPawTjJtduWNd5br2ic0EjutfvHDBSE8VSUhsZpHG cOXrD4As2BpXgdxuqj248TuF9Zol2o+MX764yK4jDYAZex8DZqwGaoxmps5tRKuSeqAA4G2Bnqw 0PkkbnvtqJDcgjCTSNn/6Iw/HE+vbBFVdEDeLJXSz+TyDLPUGMgkHbFUzwKILQuOTf/Mps7FRUk N/TXev0s7dlgBDLwSYI1Bbn/qo1qGGy7XZ3VFbGMACnCQ7MZZzr2Rl4fWJjRqb+C9pc0guY2LzF UrK0XFJogOkf4osMKQHidChDvKF6PvrCmjHoIBSySVhzuZwMh0O23ilbdbJrDK8SBSsV7qeKZvA n7wYlDPFIk+coD+IO5A== X-Proofpoint-ORIG-GUID: JDRbH-MVKGWTzfY7hFJ10AxFON34w8JZ X-Authority-Analysis: v=2.4 cv=dfmwG3Xe c=1 sm=1 tr=0 ts=6a22b299 cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=PWWK3QiPue6MOfw6qxEA:9 a=QEXdDO2ut3YA:10 a=3WC7DwWrALyhR5TkjVHa:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-GUID: JDRbH-MVKGWTzfY7hFJ10AxFON34w8JZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-05_01,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 adultscore=0 impostorscore=0 phishscore=0 priorityscore=1501 spamscore=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606050111 Add device tree bindings for the Audio Core Clock Controller (AUDIOCORECC) on Qualcomm Shikra SoC. The AUDIOCORECC clocks and resets support differs across variants based on Audio subsystem enablement as follows: CQM (qcom,shikra-cqm-audiocorecc): need clocks and resets; audio on APPS CQS (qcom,shikra-cqs-audiocorecc): need resets only; audio on Modem IQS: no clocks/resets needed; no SoundWire codecs To handle these requirements, variant-specific compatibles are introduced. Signed-off-by: Imran Shaik --- .../bindings/clock/qcom,shikra-audiocorecc.yaml | 62 ++++++++++++++++++= ++++ .../dt-bindings/clock/qcom,shikra-audiocorecc.h | 49 +++++++++++++++++ 2 files changed, 111 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,shikra-audiocorec= c.yaml b/Documentation/devicetree/bindings/clock/qcom,shikra-audiocorecc.ya= ml new file mode 100644 index 0000000000000000000000000000000000000000..2ed1d9d871175ff868584cfd606= e14c5779f1766 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,shikra-audiocorecc.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,shikra-audiocorecc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Audio Core Clock & Reset Controller for Qualcomm Shikra SoC + +maintainers: + - Imran Shaik + +description: | + Audio core clock control module provides the clocks and resets + on Qualcomm Shikra SoC platform. + + See also: + - include/dt-bindings/clock/qcom,shikra-audiocorecc.h + +properties: + compatible: + enum: + - qcom,shikra-cqm-audiocorecc + - qcom,shikra-cqs-audiocorecc + + clocks: + items: + - description: Board XO source + - description: Board sleep clock + - description: Audio ref clock source + + reg: + maxItems: 2 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + #include + clock-controller@a0a0000 { + compatible =3D "qcom,shikra-cqm-audiocorecc"; + reg =3D <0x0a0a0000 0x10000>, + <0x0a0b4000 0x1000>; + clocks =3D <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&sleep_clk>, + <&aud_ref_clk_src>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,shikra-audiocorecc.h b/include/= dt-bindings/clock/qcom,shikra-audiocorecc.h new file mode 100644 index 0000000000000000000000000000000000000000..3052feb627ff3dc8beb405534ff= 94bf75525fcb2 --- /dev/null +++ b/include/dt-bindings/clock/qcom,shikra-audiocorecc.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_AUDIO_CORE_CC_SHIKRA_H +#define _DT_BINDINGS_CLK_QCOM_AUDIO_CORE_CC_SHIKRA_H + +/* AUDIO_CORE_CC clocks */ +#define AUDIO_CORE_CC_DIG_PLL_OUT_AUX 0 +#define AUDIO_CORE_CC_DIG_PLL_OUT_AUX2 1 +#define AUDIO_CORE_CC_DIG_PLL 2 +#define AUDIO_CORE_CC_AIF_IF0_CLK_SRC 3 +#define AUDIO_CORE_CC_AIF_IF0_EBIT_CLK 4 +#define AUDIO_CORE_CC_AIF_IF0_IBIT_CLK 5 +#define AUDIO_CORE_CC_AIF_IF1_CLK_SRC 6 +#define AUDIO_CORE_CC_AIF_IF1_EBIT_CLK 7 +#define AUDIO_CORE_CC_AIF_IF1_IBIT_CLK 8 +#define AUDIO_CORE_CC_AIF_IF2_CLK_SRC 9 +#define AUDIO_CORE_CC_AIF_IF2_EBIT_CLK 10 +#define AUDIO_CORE_CC_AIF_IF2_IBIT_CLK 11 +#define AUDIO_CORE_CC_AIF_IF3_CLK_SRC 12 +#define AUDIO_CORE_CC_AIF_IF3_EBIT_CLK 13 +#define AUDIO_CORE_CC_AIF_IF3_IBIT_CLK 14 +#define AUDIO_CORE_CC_AUD_DMA_CLK 15 +#define AUDIO_CORE_CC_AUD_DMA_CLK_SRC 16 +#define AUDIO_CORE_CC_AUD_DMA_MEM_CLK 17 +#define AUDIO_CORE_CC_BUS_CLK 18 +#define AUDIO_CORE_CC_BUS_CLK_SRC 19 +#define AUDIO_CORE_CC_CDIV_TX_MCLK_DIV_CLK_SRC 20 +#define AUDIO_CORE_CC_EXT_MCLKA_CLK_SRC 21 +#define AUDIO_CORE_CC_EXT_MCLKA_OUT_CLK 22 +#define AUDIO_CORE_CC_EXT_MCLKB_CLK_SRC 23 +#define AUDIO_CORE_CC_EXT_MCLKB_OUT_CLK 24 +#define AUDIO_CORE_CC_IM_SLEEP_CLK 25 +#define AUDIO_CORE_CC_LPAIF_PCMOE_CLK 26 +#define AUDIO_CORE_CC_LPAIF_PCMOE_CLK_SRC 27 +#define AUDIO_CORE_CC_RX_MCLK_2X_CLK 28 +#define AUDIO_CORE_CC_RX_MCLK_CLK 29 +#define AUDIO_CORE_CC_SAMPLING_CLK 30 +#define AUDIO_CORE_CC_TX_MCLK_2X_CLK 31 +#define AUDIO_CORE_CC_TX_MCLK_CLK 32 +#define AUDIO_CORE_CC_TX_MCLK_RCG_CLK_SRC 33 + +/* AUDIO_CORE_CC resets */ +#define AUDIO_CORE_CSR_RX_SWR_CGCR 0 +#define AUDIO_CORE_CSR_TX_SWR_CGCR 1 + +#endif --=20 2.34.1 From nobody Mon Jun 8 06:38:18 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B5AC54D8D87 for ; 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The AUDIOCORECC clocks and resets support differs based on Audio subsystem enablement. In the CQM variant, both clocks and resets are required as Audio is on APPS, while in the CQS variant only reset control is required since Audio is handled on Modem. Handle these requirements using variant specific compatibles. Signed-off-by: Imran Shaik --- drivers/clk/qcom/Kconfig | 10 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/audiocorecc-shikra.c | 813 ++++++++++++++++++++++++++++++= ++++ 3 files changed, 824 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 72e172ee0e6eaeccf709c0110e1d24fb555d894d..08e10feeaffa9a05daed5a2c5db= 8cb9f5eff76f3 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -155,6 +155,16 @@ config CLK_NORD_GCC SPI, I2C, USB, SD/UFS, PCIe etc. The clock controller is a combination of GCC, SE_GCC, NE_GCC and NW_GCC. =20 +config CLK_SHIKRA_AUDIOCORECC + tristate "Shikra Audio Core Clock Controller" + depends on ARM64 || COMPILE_TEST + select CLK_SHIKRA_GCC + default m if ARCH_QCOM + help + Support for the Audio Core clock controller on Qualcomm Shikra devices. + Say Y if you want to use AudioCoreCC clocks required to support audio + devices and it's functionality. + config CLK_SHIKRA_GCC tristate "Shikra Global Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 910add09b3b2fe64bb21a18f4e1e445a702e283b..c03cd721bb8d2736d1bb5e6249d= fc27e3af7cb48 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -39,6 +39,7 @@ obj-$(CONFIG_CLK_KAANAPALI_TCSRCC) +=3D tcsrcc-kaanapali.o obj-$(CONFIG_CLK_KAANAPALI_VIDEOCC) +=3D videocc-kaanapali.o obj-$(CONFIG_CLK_NORD_GCC) +=3D gcc-nord.o negcc-nord.o nwgcc-nord.o segcc= -nord.o obj-$(CONFIG_CLK_NORD_TCSRCC) +=3D tcsrcc-nord.o +obj-$(CONFIG_CLK_SHIKRA_AUDIOCORECC) +=3D audiocorecc-shikra.o obj-$(CONFIG_CLK_SHIKRA_GCC) +=3D gcc-shikra.o obj-$(CONFIG_CLK_X1E80100_CAMCC) +=3D camcc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_DISPCC) +=3D dispcc-x1e80100.o diff --git a/drivers/clk/qcom/audiocorecc-shikra.c b/drivers/clk/qcom/audio= corecc-shikra.c new file mode 100644 index 0000000000000000000000000000000000000000..a6756076e6421b35b424060f2f8= e881403e65813 --- /dev/null +++ b/drivers/clk/qcom/audiocorecc-shikra.c @@ -0,0 +1,813 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_SLEEP_CLK, + DT_AUD_REF_CLK_SRC, +}; + +enum { + P_AUD_REF_CLK_SRC, + P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, + P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, + P_BI_TCXO, + P_SLEEP_CLK, +}; + +static const struct pll_vco spark_vco[] =3D { + { 500000000, 1000000000, 2 }, +}; + +/* 614.4 MHz Configuration */ +static const struct alpha_pll_config audio_core_cc_dig_pll_config =3D { + .l =3D 0x20, + .alpha =3D 0x0, + .vco_val =3D BIT(21), + .post_div_val =3D 0x28100, + .post_div_mask =3D GENMASK(17, 8), + .vco_mask =3D GENMASK(21, 20), + .main_output_mask =3D BIT(0), + .aux_output_mask =3D BIT(1), + .aux2_output_mask =3D BIT(2), + .config_ctl_val =3D 0x4001055b, + .test_ctl_hi_val =3D 0x1, + .test_ctl_hi_mask =3D 0x1, +}; + +static struct clk_alpha_pll audio_core_cc_dig_pll =3D { + .offset =3D 0x0, + .config =3D &audio_core_cc_dig_pll_config, + .vco_table =3D spark_vco, + .num_vco =3D ARRAY_SIZE(spark_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_dig_pll", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_ops, + }, + }, +}; + +static struct clk_fixed_factor audio_core_cc_dig_pll_out_aux =3D { + .mult =3D 1, + .div =3D 5, + .hw.init =3D &(struct clk_init_data) { + .name =3D "audio_core_cc_dig_pll_out_aux", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &audio_core_cc_dig_pll.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_fixed_factor_ops, + }, +}; + +static struct clk_fixed_factor audio_core_cc_dig_pll_out_aux2 =3D { + .mult =3D 1, + .div =3D 2, + .hw.init =3D &(struct clk_init_data) { + .name =3D "audio_core_cc_dig_pll_out_aux2", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &audio_core_cc_dig_pll.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_fixed_factor_ops, + }, +}; + +static const struct parent_map audio_core_cc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_AUD_REF_CLK_SRC, 1 }, + { P_SLEEP_CLK, 2 }, + { P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 4 }, + { P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, 6 }, +}; + +static const struct clk_parent_data audio_core_cc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_AUD_REF_CLK_SRC }, + { .index =3D DT_SLEEP_CLK }, + { .hw =3D &audio_core_cc_dig_pll_out_aux.hw }, + { .hw =3D &audio_core_cc_dig_pll_out_aux2.hw }, +}; + +static const struct freq_tbl ftbl_audio_core_cc_aif_if0_clk_src[] =3D { + F(240000, P_BI_TCXO, 10, 1, 8), + F(256000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 32), + F(512000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 16), + F(768000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 16), + F(1024000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 8), + F(1536000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 8), + F(2048000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 4), + F(3072000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 4), + F(4096000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 2), + F(6144000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 2), + F(8192000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 0, 0), + F(9600000, P_BI_TCXO, 2, 0, 0), + F(12288000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 0, 0), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(24576000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 5, 0, 0), + { } +}; + +static struct clk_rcg2 audio_core_cc_aif_if0_clk_src =3D { + .cmd_rcgr =3D 0x104c, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D audio_core_cc_parent_map_0, + .freq_tbl =3D ftbl_audio_core_cc_aif_if0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_aif_if0_clk_src", + .parent_data =3D audio_core_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(audio_core_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 audio_core_cc_aif_if1_clk_src =3D { + .cmd_rcgr =3D 0x10b0, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D audio_core_cc_parent_map_0, + .freq_tbl =3D ftbl_audio_core_cc_aif_if0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_aif_if1_clk_src", + .parent_data =3D audio_core_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(audio_core_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 audio_core_cc_aif_if2_clk_src =3D { + .cmd_rcgr =3D 0x1114, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D audio_core_cc_parent_map_0, + .freq_tbl =3D ftbl_audio_core_cc_aif_if0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_aif_if2_clk_src", + .parent_data =3D audio_core_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(audio_core_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_audio_core_cc_aif_if3_clk_src[] =3D { + F(240000, P_BI_TCXO, 10, 1, 8), + F(256000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 32), + F(512000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 16), + F(768000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 16), + F(1024000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 8), + F(1536000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 8), + F(2048000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 4), + F(3072000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 4), + F(4096000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 2), + F(6144000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 2), + F(8192000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 0, 0), + F(9600000, P_BI_TCXO, 2, 0, 0), + F(12288000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 0, 0), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(24576000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 5, 0, 0), + F(49152000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 audio_core_cc_aif_if3_clk_src =3D { + .cmd_rcgr =3D 0x1178, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D audio_core_cc_parent_map_0, + .freq_tbl =3D ftbl_audio_core_cc_aif_if3_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_aif_if3_clk_src", + .parent_data =3D audio_core_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(audio_core_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_audio_core_cc_aud_dma_clk_src[] =3D { + F(102400000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, 3, 0, 0), + F(153600000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, 2, 0, 0), + F(307200000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, 1, 0, 0), + { } +}; + +static struct clk_rcg2 audio_core_cc_aud_dma_clk_src =3D { + .cmd_rcgr =3D 0x1028, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D audio_core_cc_parent_map_0, + .freq_tbl =3D ftbl_audio_core_cc_aud_dma_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_aud_dma_clk_src", + .parent_data =3D audio_core_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(audio_core_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_audio_core_cc_bus_clk_src[] =3D { + F(38400000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, 8, 0, 0), + F(76800000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, 4, 0, 0), + { } +}; + +static struct clk_rcg2 audio_core_cc_bus_clk_src =3D { + .cmd_rcgr =3D 0x1008, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D audio_core_cc_parent_map_0, + .freq_tbl =3D ftbl_audio_core_cc_bus_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_bus_clk_src", + .parent_data =3D audio_core_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(audio_core_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 audio_core_cc_ext_mclka_clk_src =3D { + .cmd_rcgr =3D 0x123c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D audio_core_cc_parent_map_0, + .freq_tbl =3D ftbl_audio_core_cc_aif_if0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_ext_mclka_clk_src", + .parent_data =3D audio_core_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(audio_core_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 audio_core_cc_ext_mclkb_clk_src =3D { + .cmd_rcgr =3D 0x125c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D audio_core_cc_parent_map_0, + .freq_tbl =3D ftbl_audio_core_cc_aif_if0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_ext_mclkb_clk_src", + .parent_data =3D audio_core_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(audio_core_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_audio_core_cc_lpaif_pcmoe_clk_src[] =3D { + F(9600000, P_BI_TCXO, 2, 0, 0), + F(15360000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 8, 0, 0), + F(30720000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 4, 0, 0), + F(61440000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 2, 0, 0), + { } +}; + +static struct clk_rcg2 audio_core_cc_lpaif_pcmoe_clk_src =3D { + .cmd_rcgr =3D 0x12ac, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D audio_core_cc_parent_map_0, + .freq_tbl =3D ftbl_audio_core_cc_lpaif_pcmoe_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_lpaif_pcmoe_clk_src", + .parent_data =3D audio_core_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(audio_core_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_audio_core_cc_tx_mclk_rcg_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(24576000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 5, 0, 0), + { } +}; + +static struct clk_rcg2 audio_core_cc_tx_mclk_rcg_clk_src =3D { + .cmd_rcgr =3D 0x127c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D audio_core_cc_parent_map_0, + .freq_tbl =3D ftbl_audio_core_cc_tx_mclk_rcg_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_tx_mclk_rcg_clk_src", + .parent_data =3D audio_core_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(audio_core_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div audio_core_cc_cdiv_tx_mclk_div_clk_src =3D { + .reg =3D 0x129c, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_cdiv_tx_mclk_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &audio_core_cc_tx_mclk_rcg_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch audio_core_cc_aif_if0_ebit_clk =3D { + .halt_reg =3D 0x1068, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x1068, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_aif_if0_ebit_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_aif_if0_ibit_clk =3D { + .halt_reg =3D 0x1064, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1064, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_aif_if0_ibit_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &audio_core_cc_aif_if0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_aif_if1_ebit_clk =3D { + .halt_reg =3D 0x10cc, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x10cc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_aif_if1_ebit_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_aif_if1_ibit_clk =3D { + .halt_reg =3D 0x10c8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x10c8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_aif_if1_ibit_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &audio_core_cc_aif_if1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_aif_if2_ebit_clk =3D { + .halt_reg =3D 0x1130, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x1130, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_aif_if2_ebit_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_aif_if2_ibit_clk =3D { + .halt_reg =3D 0x112c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x112c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_aif_if2_ibit_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &audio_core_cc_aif_if2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_aif_if3_ebit_clk =3D { + .halt_reg =3D 0x1194, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x1194, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_aif_if3_ebit_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_aif_if3_ibit_clk =3D { + .halt_reg =3D 0x1190, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1190, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_aif_if3_ibit_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &audio_core_cc_aif_if3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_aud_dma_clk =3D { + .halt_reg =3D 0x1040, + .halt_check =3D BRANCH_HALT, + .hwcg_reg =3D 0x1040, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x1040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_aud_dma_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &audio_core_cc_aud_dma_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_aud_dma_mem_clk =3D { + .halt_reg =3D 0x1044, + .halt_check =3D BRANCH_HALT, + .hwcg_reg =3D 0x1044, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x1044, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_aud_dma_mem_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &audio_core_cc_aud_dma_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_bus_clk =3D { + .halt_reg =3D 0x1020, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x1020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_bus_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &audio_core_cc_bus_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_ext_mclka_out_clk =3D { + .halt_reg =3D 0x1254, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1254, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_ext_mclka_out_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &audio_core_cc_ext_mclka_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_ext_mclkb_out_clk =3D { + .halt_reg =3D 0x1274, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1274, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_ext_mclkb_out_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &audio_core_cc_ext_mclkb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_im_sleep_clk =3D { + .halt_reg =3D 0x12cc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x12cc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_im_sleep_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_lpaif_pcmoe_clk =3D { + .halt_reg =3D 0x12c4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x12c4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_lpaif_pcmoe_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &audio_core_cc_lpaif_pcmoe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_rx_mclk_2x_clk =3D { + .halt_reg =3D 0x1298, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1298, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_rx_mclk_2x_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &audio_core_cc_tx_mclk_rcg_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_rx_mclk_clk =3D { + .halt_reg =3D 0x12a4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x12a4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_rx_mclk_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &audio_core_cc_cdiv_tx_mclk_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_sampling_clk =3D { + .halt_reg =3D 0x1000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_sampling_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_tx_mclk_2x_clk =3D { + .halt_reg =3D 0x1294, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1294, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_tx_mclk_2x_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &audio_core_cc_tx_mclk_rcg_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_tx_mclk_clk =3D { + .halt_reg =3D 0x12a0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x12a0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_tx_mclk_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &audio_core_cc_cdiv_tx_mclk_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_hw *audio_core_cc_shikra_hws[] =3D { + [AUDIO_CORE_CC_DIG_PLL_OUT_AUX] =3D &audio_core_cc_dig_pll_out_aux.hw, + [AUDIO_CORE_CC_DIG_PLL_OUT_AUX2] =3D &audio_core_cc_dig_pll_out_aux2.hw, +}; + +static struct clk_regmap *audio_core_cc_shikra_clocks[] =3D { + [AUDIO_CORE_CC_AIF_IF0_CLK_SRC] =3D &audio_core_cc_aif_if0_clk_src.clkr, + [AUDIO_CORE_CC_AIF_IF0_EBIT_CLK] =3D &audio_core_cc_aif_if0_ebit_clk.clkr, + [AUDIO_CORE_CC_AIF_IF0_IBIT_CLK] =3D &audio_core_cc_aif_if0_ibit_clk.clkr, + [AUDIO_CORE_CC_AIF_IF1_CLK_SRC] =3D &audio_core_cc_aif_if1_clk_src.clkr, + [AUDIO_CORE_CC_AIF_IF1_EBIT_CLK] =3D &audio_core_cc_aif_if1_ebit_clk.clkr, + [AUDIO_CORE_CC_AIF_IF1_IBIT_CLK] =3D &audio_core_cc_aif_if1_ibit_clk.clkr, + [AUDIO_CORE_CC_AIF_IF2_CLK_SRC] =3D &audio_core_cc_aif_if2_clk_src.clkr, + [AUDIO_CORE_CC_AIF_IF2_EBIT_CLK] =3D &audio_core_cc_aif_if2_ebit_clk.clkr, + [AUDIO_CORE_CC_AIF_IF2_IBIT_CLK] =3D &audio_core_cc_aif_if2_ibit_clk.clkr, + [AUDIO_CORE_CC_AIF_IF3_CLK_SRC] =3D &audio_core_cc_aif_if3_clk_src.clkr, + [AUDIO_CORE_CC_AIF_IF3_EBIT_CLK] =3D &audio_core_cc_aif_if3_ebit_clk.clkr, + [AUDIO_CORE_CC_AIF_IF3_IBIT_CLK] =3D &audio_core_cc_aif_if3_ibit_clk.clkr, + [AUDIO_CORE_CC_AUD_DMA_CLK] =3D &audio_core_cc_aud_dma_clk.clkr, + [AUDIO_CORE_CC_AUD_DMA_CLK_SRC] =3D &audio_core_cc_aud_dma_clk_src.clkr, + [AUDIO_CORE_CC_AUD_DMA_MEM_CLK] =3D &audio_core_cc_aud_dma_mem_clk.clkr, + [AUDIO_CORE_CC_BUS_CLK] =3D &audio_core_cc_bus_clk.clkr, + [AUDIO_CORE_CC_BUS_CLK_SRC] =3D &audio_core_cc_bus_clk_src.clkr, + [AUDIO_CORE_CC_CDIV_TX_MCLK_DIV_CLK_SRC] =3D &audio_core_cc_cdiv_tx_mclk_= div_clk_src.clkr, + [AUDIO_CORE_CC_DIG_PLL] =3D &audio_core_cc_dig_pll.clkr, + [AUDIO_CORE_CC_EXT_MCLKA_CLK_SRC] =3D &audio_core_cc_ext_mclka_clk_src.cl= kr, + [AUDIO_CORE_CC_EXT_MCLKA_OUT_CLK] =3D &audio_core_cc_ext_mclka_out_clk.cl= kr, + [AUDIO_CORE_CC_EXT_MCLKB_CLK_SRC] =3D &audio_core_cc_ext_mclkb_clk_src.cl= kr, + [AUDIO_CORE_CC_EXT_MCLKB_OUT_CLK] =3D &audio_core_cc_ext_mclkb_out_clk.cl= kr, + [AUDIO_CORE_CC_IM_SLEEP_CLK] =3D &audio_core_cc_im_sleep_clk.clkr, + [AUDIO_CORE_CC_LPAIF_PCMOE_CLK] =3D &audio_core_cc_lpaif_pcmoe_clk.clkr, + [AUDIO_CORE_CC_LPAIF_PCMOE_CLK_SRC] =3D &audio_core_cc_lpaif_pcmoe_clk_sr= c.clkr, + [AUDIO_CORE_CC_RX_MCLK_2X_CLK] =3D &audio_core_cc_rx_mclk_2x_clk.clkr, + [AUDIO_CORE_CC_RX_MCLK_CLK] =3D &audio_core_cc_rx_mclk_clk.clkr, + [AUDIO_CORE_CC_SAMPLING_CLK] =3D &audio_core_cc_sampling_clk.clkr, + [AUDIO_CORE_CC_TX_MCLK_2X_CLK] =3D &audio_core_cc_tx_mclk_2x_clk.clkr, + [AUDIO_CORE_CC_TX_MCLK_CLK] =3D &audio_core_cc_tx_mclk_clk.clkr, + [AUDIO_CORE_CC_TX_MCLK_RCG_CLK_SRC] =3D &audio_core_cc_tx_mclk_rcg_clk_sr= c.clkr, +}; + +static struct clk_alpha_pll *audio_core_cc_shikra_plls[] =3D { + &audio_core_cc_dig_pll, +}; + +static const struct regmap_config audio_core_cc_shikra_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x305c, + .fast_io =3D true, +}; + +static const struct qcom_reset_map audio_core_cc_shikra_resets[] =3D { + [AUDIO_CORE_CSR_RX_SWR_CGCR] =3D { 0x1c }, + [AUDIO_CORE_CSR_TX_SWR_CGCR] =3D { 0x30 }, +}; + +static const struct regmap_config audio_core_cc_shikra_reset_regmap_config= =3D { + .name =3D "audio_core_cc_shikra_reset", + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .fast_io =3D true, + .max_register =3D 0x34, +}; + +static const struct qcom_cc_driver_data audio_core_cc_shikra_driver_data = =3D { + .alpha_plls =3D audio_core_cc_shikra_plls, + .num_alpha_plls =3D ARRAY_SIZE(audio_core_cc_shikra_plls), +}; + +static const struct qcom_cc_desc audio_core_cc_shikra_reset_desc =3D { + .config =3D &audio_core_cc_shikra_reset_regmap_config, + .resets =3D audio_core_cc_shikra_resets, + .num_resets =3D ARRAY_SIZE(audio_core_cc_shikra_resets), +}; + +static const struct qcom_cc_desc audio_core_cc_shikra_desc =3D { + .config =3D &audio_core_cc_shikra_regmap_config, + .clk_hws =3D audio_core_cc_shikra_hws, + .num_clk_hws =3D ARRAY_SIZE(audio_core_cc_shikra_hws), + .clks =3D audio_core_cc_shikra_clocks, + .num_clks =3D ARRAY_SIZE(audio_core_cc_shikra_clocks), + .driver_data =3D &audio_core_cc_shikra_driver_data, +}; + +static const struct of_device_id audio_core_cc_shikra_match_table[] =3D { + { .compatible =3D "qcom,shikra-cqm-audiocorecc" }, + { .compatible =3D "qcom,shikra-cqs-audiocorecc" }, + { } +}; +MODULE_DEVICE_TABLE(of, audio_core_cc_shikra_match_table); + +static int audio_core_cc_shikra_probe(struct platform_device *pdev) +{ + int ret; + + ret =3D qcom_cc_probe_by_index(pdev, 1, &audio_core_cc_shikra_reset_desc); + if (ret) + return ret; + + if (device_is_compatible(&pdev->dev, "qcom,shikra-cqs-audiocorecc")) + return 0; + + return qcom_cc_probe(pdev, &audio_core_cc_shikra_desc); +} + +static struct platform_driver audio_core_cc_shikra_driver =3D { + .probe =3D audio_core_cc_shikra_probe, + .driver =3D { + .name =3D "audiocorecc-shikra", + .of_match_table =3D audio_core_cc_shikra_match_table, + }, +}; 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Fri, 05 Jun 2026 04:27:31 -0700 (PDT) Received: from hu-imrashai-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-842828e21c8sm10626246b3a.49.2026.06.05.04.27.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Jun 2026 04:27:30 -0700 (PDT) From: Imran Shaik Date: Fri, 05 Jun 2026 16:56:33 +0530 Subject: [PATCH 4/4] arm64: dts: qcom: shikra: Add support for AudioCoreCC node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260605-shikra-audiocorecc-v1-4-7ee6b5f2d928@oss.qualcomm.com> References: <20260605-shikra-audiocorecc-v1-0-7ee6b5f2d928@oss.qualcomm.com> In-Reply-To: <20260605-shikra-audiocorecc-v1-0-7ee6b5f2d928@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: Ajit Pandey , Taniya Das , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Imran Shaik X-Mailer: b4 0.14.2 X-Proofpoint-ORIG-GUID: ebEavnvIbA1u2GZThLx-bT_rMqfIv2P7 X-Proofpoint-GUID: ebEavnvIbA1u2GZThLx-bT_rMqfIv2P7 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjA1MDExMSBTYWx0ZWRfX40z6cTF3VnAi a/q5Vl/CfckaU1YVFvATShE5yAWuwARw1kKnIMLtIlVMtStzlpLwkIvvB8s9m9ZALvsLcMOBvDW DpZTM72ZqUxaAIWuEXzq86hQZCJSztWSt89rDomKlyh96R3ZRuncQYMVveJ9cKnGp5zkDaark4J zC4HaDPXiGLh9OMFr8GhxTfjkWETIJ8UKlWeZSs8qTKq7t1DX2TbsspY/C7Tw10OwgijqpOA6o4 WWXRaAznP1lfBjKcGuj/6UiBNt1ikykVXm1p5HiOMKMnkD7sorQ0d883ljGIeaY1rmaTvrsQz60 P6JAln9PH1eIrYmTxdqMaYPwnmIxsesZ6EEcrZRzvvCrFJSG0tqHYunG1zEpkf66NvSOkT7G5fA j32zjaiqwYgJW1l/CcRfRNXdIXZJB9kWp88+z2NvVa96f6PyM6XXGWhvQB3nZNgmGvFFQsGIl3J ETEA3Vd5hVA1sbqrEZw== X-Authority-Analysis: v=2.4 cv=T9a8ifKQ c=1 sm=1 tr=0 ts=6a22b2a4 cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=rDU0rDU2gfLWSAyRyQ0A:9 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-05_01,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 clxscore=1015 bulkscore=0 adultscore=0 priorityscore=1501 phishscore=0 spamscore=0 lowpriorityscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606050111 Add support for Audio Core Clock Controller (AudioCoreCC) node on Qualcomm Shikra SoC. The CQM variant requires both clock and reset support, while the CQS variant requires only reset support. Update the respective device tree variants to enable and override the node as per variant requirements. Signed-off-by: Imran Shaik --- arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 4 ++++ arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 5 +++++ arch/arm64/boot/dts/qcom/shikra.dtsi | 13 +++++++++++++ 3 files changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/= dts/qcom/shikra-cqm-evk.dts index 0a52ab9b7a4c34d371f5ac23efe59d1c9d2723f4..0883c480bfbc80d7bead966b9ba= 932dee8a77bbf 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts @@ -23,6 +23,10 @@ chosen { }; }; =20 +&audiocorecc { + status =3D "okay"; +}; + &sdhc_1 { vmmc-supply =3D <&pm4125_l20>; vqmmc-supply =3D <&pm4125_l14>; diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/= dts/qcom/shikra-cqs-evk.dts index b3f19a64d7aed3121ef092df684b19a4de39b497..b5e3d573868a836ad5e5e8eb302= 4cb5fb71dbb4e 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts @@ -23,6 +23,11 @@ chosen { }; }; =20 +&audiocorecc { + compatible =3D "qcom,shikra-cqs-audiocorecc"; + status =3D "okay"; +}; + &sdhc_1 { vmmc-supply =3D <&pm4125_l20>; vqmmc-supply =3D <&pm4125_l14>; diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qco= m/shikra.dtsi index a4334d99c1f35ee851ca8266ec37d4a200a07ee5..f15757d52af04d8cb5540354a23= 9127cb0d174a3 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -4,6 +4,7 @@ */ =20 #include +#include #include #include #include @@ -640,6 +641,18 @@ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, }; }; =20 + audiocorecc: clock-controller@a0a0000 { + compatible =3D "qcom,shikra-cqm-audiocorecc"; + reg =3D <0x0 0x0a0a0000 0x0 0x10000>, + <0x0 0x0a0b4000 0x0 0x1000>; + clocks =3D <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&sleep_clk>, + <0>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + status =3D "disabled"; + }; + sram@c11e000 { compatible =3D "qcom,shikra-imem", "mmio-sram"; reg =3D <0x0 0x0c11e000 0x0 0x1000>; --=20 2.34.1