From nobody Mon Jun 8 06:37:54 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9DED12F7F00; Sat, 6 Jun 2026 05:42:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780724569; cv=none; b=QyHmjTKb7vpBTI6FTVeLbUTc+Vci2zcdp27cfw7TmKkm3lFqogMIkrZ79AWxhLioWxb/G+0iAQS053XD3OHg9BoPztePjOivQr2GnDUGh4CZ8Qaq2fpDM6UbxtGBS/dc980aUetfpV/8NtLIgvMerw7XKFyOijWp23JmevnvpNo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780724569; c=relaxed/simple; bh=LjX0iNDA1QuH0fa/aAzAd20F0ug7JO+NaJvzlquleo4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nSnLRwrdah8mKV0wi2jQRfntDDp3J9rRN7q/peoiBIC33+DNRKyngtmhlA98va1f04DD6r3fF+9JIeZl/a7Jn/epGr6y6uDAZnW3qBOhI1PoLbv/peMf2i79xDjghwZ+kHaXVGCOlJjnWLIm7Ee66KvvXFzsbqGHBTwFVkaNjL4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=b3lOqoZH; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="b3lOqoZH" Received: by smtp.kernel.org (Postfix) with ESMTPS id 273CCC2BCC7; Sat, 6 Jun 2026 05:42:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1780724569; bh=LjX0iNDA1QuH0fa/aAzAd20F0ug7JO+NaJvzlquleo4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=b3lOqoZHf/c6KTKbDNiZLpO1GWlrjRkUEm4I4L1Q+fcoLzrn1Ea7H4gxee1ob3JF7 vJJ56vNwDacXzB9iAFmCfJZ1qQxQNfl7IYaF7dkxNdTMFBgqdwZIdFAUy5PHMzIBjX h831BuTHPSfXxa/ZVs0MH0ZSo9CuoKDc2e6TAQAREdFqhYSt/+oAVlWuC9jSBbbsYw u7LSGqEq77hLnTKxfuG8P8eDDtyZr7xoWrbZBC47IC2Y3gqjViQWEfTgmK5aSvySqi zVbzwxmCp2okzWVpCMhr7OlgjIVyecGu8kGayvu9x4bceFy6PsmzLgCwByffOSdvYg NeX4obGw7WBNA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1242BCD8C85; Sat, 6 Jun 2026 05:42:49 +0000 (UTC) From: Selvamani Rajagopal via B4 Relay Date: Fri, 05 Jun 2026 22:42:32 -0700 Subject: [PATCH net-next v4 01/16] net: phy: Helper to read and write through C45 without lock Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260605-s2500-mac-phy-support-v4-1-de0fbc13c6d8@onsemi.com> References: <20260605-s2500-mac-phy-support-v4-0-de0fbc13c6d8@onsemi.com> In-Reply-To: <20260605-s2500-mac-phy-support-v4-0-de0fbc13c6d8@onsemi.com> To: Andrew Lunn , Piergiorgio Beruto , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Parthiban Veerasooran , Selva Rajagopal , Richard Cochran , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Simon Horman , Jonathan Corbet , Shuah Khan Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, Jerry Ray , Selvamani Rajagopal X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780724562; l=3459; i=Selvamani.Rajagopal@onsemi.com; s=20260531; h=from:subject:message-id; bh=JvvJXQtiELpn1FGIsjj4sr5oo2VlfTINRAZf1k5i42I=; b=y6DMdh9smhvvWef/6NBQQFDz0anPehbu1rQUl6u/PaXM+u/UUKbuu9HObang8430hF8xDin9w yS0GcRb19+qAIVJLzQr2yRfdG0nTHd44a0VfZijWHNbf1iCZ1+7mkuy X-Developer-Key: i=Selvamani.Rajagopal@onsemi.com; a=ed25519; pk=5QRdM0HS/LGWWcUZZ9hVfZ+qbPQGZCumcTXOiN7Fyug= X-Endpoint-Received: by B4 Relay for Selvamani.Rajagopal@onsemi.com/20260531 with auth_id=803 X-Original-From: Selvamani Rajagopal Reply-To: Selvamani.Rajagopal@onsemi.com From: Selvamani Rajagopal Generic helper function to initiate read and write through C45 bus protocol without mdio bus lock. This will help PHYs to avoid indirect C22 API calls for C45 bus protocol which may not be supported by the PHY. Signed-off-by: Selvamani Rajagopal --- drivers/net/phy/phy_device.c | 55 ++++++++++++++++++++++++++++++++++++++++= ++++ include/linux/phy.h | 4 ++++ 2 files changed, 59 insertions(+) diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index 3370eb822017..20c92fde4fbb 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -2781,6 +2781,61 @@ int genphy_write_mmd_unsupported(struct phy_device *= phdev, int devnum, } EXPORT_SYMBOL(genphy_write_mmd_unsupported); =20 +/** + * genphy_phy_read_mmd - Helper for reading a register without lock + * from the given MMD and PHY. + * @phydev: The phy_device struct + * @devnum: The MMD to read from + * @regnum: The register on the MMD to read + * + * Description: PHYs can have both C22 and C45 registers space. Once PHY + * is discovered via C22 bus protocol, it uses C22 indirect access to + * access C45 registers. Some PHYs, like 10Base-T1S PHYs defined by OPEN + * Alliance 10BASE=E2=80=91T1x, support only direct access. + * + * If PHY indicates C45 support through DTS entry, it avoid C22 APIs + * entirely and therefore generic MDIO registers are inaccessible. + * + * MDIO bus isn't locked here because when called through read_mmd + * callback of phy_driver, caller is expected to lock the bus as + * implemented in phy_read_mmd. + * + * Returns: Register value if successful, negative error code on failure. + */ +int genphy_phy_read_mmd(struct phy_device *phydev, int devnum, + u16 regnum) +{ + struct mii_bus *bus =3D phydev->mdio.bus; + int addr =3D phydev->mdio.addr; + + lockdep_assert_held(&bus->mdio_lock); + return __mdiobus_c45_read(bus, addr, devnum, regnum); +} +EXPORT_SYMBOL(genphy_phy_read_mmd); + +/** + * genphy_phy_write_mmd - Helper for writing a register without lock + * to the given MMD and PHY. + * @phydev: The phy_device struct + * @devnum: The MMD to write to + * @regnum: The register on the MMD to write + * @val: Value to write + * + * Description: Similar to genphy_phy_read_mmd + * + * Returns: 0 if successful, negative error code on failure. + */ +int genphy_phy_write_mmd(struct phy_device *phydev, int devnum, + u16 regnum, u16 val) +{ + struct mii_bus *bus =3D phydev->mdio.bus; + int addr =3D phydev->mdio.addr; + + lockdep_assert_held(&bus->mdio_lock); + return __mdiobus_c45_write(bus, addr, devnum, regnum, val); +} +EXPORT_SYMBOL(genphy_phy_write_mmd); + int genphy_suspend(struct phy_device *phydev) { return phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN); diff --git a/include/linux/phy.h b/include/linux/phy.h index 199a7aaa341b..8266dd4a8dbe 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -2301,6 +2301,10 @@ int genphy_read_mmd_unsupported(struct phy_device *p= hdev, int devad, u16 regnum); int genphy_write_mmd_unsupported(struct phy_device *phdev, int devnum, u16 regnum, u16 val); +int genphy_phy_write_mmd(struct phy_device *phydev, int devnum, + u16 regnum, u16 val); +int genphy_phy_read_mmd(struct phy_device *phydev, int devnum, + u16 regnum); =20 /* Clause 37 */ int genphy_c37_config_aneg(struct phy_device *phydev); --=20 2.43.0 From nobody Mon Jun 8 06:37:54 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D8621D5CFB; Sat, 6 Jun 2026 05:42:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780724569; cv=none; b=j2XboKYmJKYnQ2ldAnINHg4/iRryzbNcL2/6COhus7g+mbHGkaF9dfzzjh4dXVqyv+cbomBgTgyFuCOYbF23mFBlvijYKGyS/qYd/1zxM3SmELWyqiSBR3g8Dft6UJYn9c3QDy7djeW22RnMLhglSxP0WnUUMWh5gHEF04cPudk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780724569; c=relaxed/simple; bh=ZC9Iv73sePAEW9EIbEE/P0wqIfCOcMGUzI/pjgcrFRM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GaaDIxaQRFfKqay9BWBKDANnCqRTFsW2Rvo4UA85EoQfEYV/OvpWvLVxKdpWcZEIZKKURRmvW1RQ5ZwP+6nrsizPf4DqaRQkYNkXaDrFzSAqdZGDre/ZvE7FFppiP4sFM8ZYivOaxVu5HPxM8G5RuDvZEKzLhZ8ixdizKu4UAl4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Pk03GiUb; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Pk03GiUb" Received: by smtp.kernel.org (Postfix) with ESMTPS id 370B2C2BCC9; Sat, 6 Jun 2026 05:42:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1780724569; bh=ZC9Iv73sePAEW9EIbEE/P0wqIfCOcMGUzI/pjgcrFRM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Pk03GiUbeX73nfqmkPO0zCCt+ibvZbE2OOjkL5pYMDFHQQ0CkxLVHeSaAmBpl3YGr zxnuMIiPVz7bjMgaH4/4HKED7BV2Rwlz5gBf1YuscbNuaDI1JwnuBBEmie14p8G3hm McvlJGjDIrUPyp1AOI6mFz/I/UvaxcIvkWH9XyQADm0ATU5bK+bDThH6RCNdf854u4 wvk4a38wpOZAu0bAsA/WdfyBn43I/WJ0LP2/w2ZlnlJuVn0VTrZD92Py1KqSQ4tBZm is2CdGmicFcfr+Ek4uYLa7/tQ2qlWgt8Y3i9DY9YMCvGGBiYYxJ4hxuerRry/M6kxm lvxeJpTLca8AA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23B05CD6E55; Sat, 6 Jun 2026 05:42:49 +0000 (UTC) From: Selvamani Rajagopal via B4 Relay Date: Fri, 05 Jun 2026 22:42:33 -0700 Subject: [PATCH net-next v4 02/16] net: phy: Helper to modify PHY loopback mode only. Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260605-s2500-mac-phy-support-v4-2-de0fbc13c6d8@onsemi.com> References: <20260605-s2500-mac-phy-support-v4-0-de0fbc13c6d8@onsemi.com> In-Reply-To: <20260605-s2500-mac-phy-support-v4-0-de0fbc13c6d8@onsemi.com> To: Andrew Lunn , Piergiorgio Beruto , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Parthiban Veerasooran , Selva Rajagopal , Richard Cochran , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Simon Horman , Jonathan Corbet , Shuah Khan Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, Jerry Ray , Selvamani Rajagopal X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780724562; l=3209; i=Selvamani.Rajagopal@onsemi.com; s=20260531; h=from:subject:message-id; bh=QFlNGDq2qBU9Dz3lBBmjbo5FS53f0zd8GFs5ucZ/t5o=; b=cBCxfDAUn3mw+TZzZG7myc4Jw3MgR+2ppDD/Nb3CmgKcYxqPID8t1piZxnZdC+ukdgJ3fNB1J hesWwabsixjC1YY1UeHyvF0bEFR190Z+SJfiyI6FBOfXtu8njBhCD8Z X-Developer-Key: i=Selvamani.Rajagopal@onsemi.com; a=ed25519; pk=5QRdM0HS/LGWWcUZZ9hVfZ+qbPQGZCumcTXOiN7Fyug= X-Endpoint-Received: by B4 Relay for Selvamani.Rajagopal@onsemi.com/20260531 with auth_id=803 X-Original-From: Selvamani Rajagopal Reply-To: Selvamani.Rajagopal@onsemi.com From: Selvamani Rajagopal Generic helper function to modify loopback bit of the PHY without modifying any other bit. This will help the PHYs that may have fixed speed, like 10Base-T1S or PHYs that don't need any other settings to set them in loopback mode. Signed-off-by: Selvamani Rajagopal --- drivers/net/phy/dp83867.c | 11 +---------- drivers/net/phy/phy_device.c | 20 ++++++++++++++++++++ include/linux/phy.h | 2 ++ 3 files changed, 23 insertions(+), 10 deletions(-) diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index 88255e92b4cd..01ea2e8dd253 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -991,15 +991,6 @@ static void dp83867_link_change_notify(struct phy_devi= ce *phydev) } } =20 -static int dp83867_loopback(struct phy_device *phydev, bool enable, int sp= eed) -{ - if (enable && speed) - return -EOPNOTSUPP; - - return phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK, - enable ? BMCR_LOOPBACK : 0); -} - static int dp83867_led_brightness_set(struct phy_device *phydev, u8 index, enum led_brightness brightness) @@ -1204,7 +1195,7 @@ static struct phy_driver dp83867_driver[] =3D { .resume =3D dp83867_resume, =20 .link_change_notify =3D dp83867_link_change_notify, - .set_loopback =3D dp83867_loopback, + .set_loopback =3D genphy_loopback_fixed_speed, =20 .led_brightness_set =3D dp83867_led_brightness_set, .led_hw_is_supported =3D dp83867_led_hw_is_supported, diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index 20c92fde4fbb..738c995e11d2 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -2836,6 +2836,26 @@ int genphy_phy_write_mmd(struct phy_device *phydev, = int devnum, } EXPORT_SYMBOL(genphy_phy_write_mmd); =20 +/** + * genphy_loopback_fixed_speed - Helper to modify the PHY loopback mode + * without affecting any other settings. + * @phydev: The phy_device struct + * @enable: Flag to enable or disable the PHY level loopback. + * @speed: Speed setting. Not expected to be set. Error if it is set. + * + * Returns: 0 if successful, negative error code on failure. + */ +int genphy_loopback_fixed_speed(struct phy_device *phydev, bool enable, + int speed) +{ + if (enable && speed) + return -EOPNOTSUPP; + + return phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK, + enable ? BMCR_LOOPBACK : 0); +} +EXPORT_SYMBOL(genphy_loopback_fixed_speed); + int genphy_suspend(struct phy_device *phydev) { return phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN); diff --git a/include/linux/phy.h b/include/linux/phy.h index 8266dd4a8dbe..61bcd71a3143 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -2301,6 +2301,8 @@ int genphy_read_mmd_unsupported(struct phy_device *ph= dev, int devad, u16 regnum); int genphy_write_mmd_unsupported(struct phy_device *phdev, int devnum, u16 regnum, u16 val); +int genphy_loopback_fixed_speed(struct phy_device *phydev, bool enable, + int speed); int genphy_phy_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, u16 val); int genphy_phy_read_mmd(struct phy_device *phydev, int devnum, --=20 2.43.0 From nobody Mon Jun 8 06:37:54 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D8001A6813; Sat, 6 Jun 2026 05:42:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780724569; cv=none; b=IJFkrtBst58rYJO/z7BqmsM/+doKEEBYezXsmyx2lTSP6R7q8SoVx6+OUpSl8Ghf5N6d46JmA+2pKwRQptrZq+UPi4mOhyYMRJ01ceBTYppN5c8RRMyP83SHXQOH+OaMoJRkXy4Kr4tndvDWw4VdGXfASbtSowIwNk8aft38uIA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780724569; c=relaxed/simple; bh=+H+1R9OZ+SESM1gdy+ACCMkcS6fHa2p+8fepjhlqHBE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ov1mXrMweQ8o4Zsb6//cKh2feg/X/PQ+Mxc+/qA1U1hDdchDbG0QMZyflMIja734yrhmoTz6PxL7r0Af+pkdXbPsUQTQwYnlJY4TvKfAqrD9MF3kfivC5O9YX9viI8uM7211kqZnt1ROJ8zzCaEc2DkWtD1lVzur1tWGzKPb7wo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=f8QJ5Ej2; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="f8QJ5Ej2" Received: by smtp.kernel.org (Postfix) with ESMTPS id 4912DC2BCC4; Sat, 6 Jun 2026 05:42:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1780724569; bh=+H+1R9OZ+SESM1gdy+ACCMkcS6fHa2p+8fepjhlqHBE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=f8QJ5Ej2pe2J5YRucmvvfC93qyQyHNvEa3LBf+Z/cOSmxY0dPlBheolB2428dfjPH kxjmuofUmM5uUPz84tlpEPCbXXXCVE/s8ONRD1KSGQhwqf4EPQTtsF/kefvVcenKYL 4jU13zxvUVmGdLdTGnt0Df41hEsuABTdopiPH3GGstQj7PXFGpsZOp74MwQRz9SoPR rsCpeV5trOiLikNYSuElnO0nJtFJfHndw7HJUVAsg7Fi0fKCBfpkyMQpw0flPGTfP7 vwMSDb1HEBouzWU0+sHkj/JMbVZzvm+2Wmrn+046GZ0Q7B89jZ0Za3d4LquREV2irH gl0gq5c7akiaw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F71DCD8C8F; Sat, 6 Jun 2026 05:42:49 +0000 (UTC) From: Selvamani Rajagopal via B4 Relay Date: Fri, 05 Jun 2026 22:42:34 -0700 Subject: [PATCH net-next v4 03/16] net: ethernet: oa_tc6: Move oa_tc6.c to its own directory Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260605-s2500-mac-phy-support-v4-3-de0fbc13c6d8@onsemi.com> References: <20260605-s2500-mac-phy-support-v4-0-de0fbc13c6d8@onsemi.com> In-Reply-To: <20260605-s2500-mac-phy-support-v4-0-de0fbc13c6d8@onsemi.com> To: Andrew Lunn , Piergiorgio Beruto , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Parthiban Veerasooran , Selva Rajagopal , Richard Cochran , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Simon Horman , Jonathan Corbet , Shuah Khan Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, Jerry Ray , Selvamani Rajagopal X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780724562; l=4480; i=Selvamani.Rajagopal@onsemi.com; s=20260531; h=from:subject:message-id; bh=TddEWdaAcBzTr+dxkU5ER4ZrAEWHz31C6KRwvs3G1ro=; b=CGhyURyY5vFb4OqomOoRzHes+kH4uojl1unGce3AG6BllfuWvM2jeUreK8N5KQWtiKQTt2/Lb gXERlWouw+lAu4HCkbEGkBCjOt5uZdab2OhQS8tA7MFH4fOoNKBEdK5 X-Developer-Key: i=Selvamani.Rajagopal@onsemi.com; a=ed25519; pk=5QRdM0HS/LGWWcUZZ9hVfZ+qbPQGZCumcTXOiN7Fyug= X-Endpoint-Received: by B4 Relay for Selvamani.Rajagopal@onsemi.com/20260531 with auth_id=803 X-Original-From: Selvamani Rajagopal Reply-To: Selvamani.Rajagopal@onsemi.com From: Selvamani Rajagopal Moving oa_tc6.c to its own directory, drivers/net/ethernet/oa_tc6. This will facilitate adding more files to support other features defined by OPEN Alliance 10BASE-T1x Serial Interface specification This patch series is adding two files, one for hardware timestamp related functions and one for PTP related APIs. Signed-off-by: Selvamani Rajagopal --- MAINTAINERS | 2 +- drivers/net/ethernet/Kconfig | 12 +----------- drivers/net/ethernet/Makefile | 2 +- drivers/net/ethernet/oa_tc6/Kconfig | 16 ++++++++++++++++ drivers/net/ethernet/oa_tc6/Makefile | 7 +++++++ drivers/net/ethernet/{ =3D> oa_tc6}/oa_tc6.c | 0 6 files changed, 26 insertions(+), 13 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index eb8cdcc76324..7e6b28202e88 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20001,7 +20001,7 @@ M: Parthiban Veerasooran L: netdev@vger.kernel.org S: Maintained F: Documentation/networking/oa-tc6-framework.rst -F: drivers/net/ethernet/oa_tc6.c +F: drivers/net/ethernet/oa_tc6/oa_tc6* F: include/linux/oa_tc6.h =20 OPEN FIRMWARE AND FLATTENED DEVICE TREE diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig index 78c79ad7bba5..49d93488ba52 100644 --- a/drivers/net/ethernet/Kconfig +++ b/drivers/net/ethernet/Kconfig @@ -134,6 +134,7 @@ source "drivers/net/ethernet/netronome/Kconfig" source "drivers/net/ethernet/8390/Kconfig" source "drivers/net/ethernet/nvidia/Kconfig" source "drivers/net/ethernet/nxp/Kconfig" +source "drivers/net/ethernet/oa_tc6/Kconfig" source "drivers/net/ethernet/oki-semi/Kconfig" =20 config ETHOC @@ -146,17 +147,6 @@ config ETHOC help Say Y here if you want to use the OpenCores 10/100 Mbps Ethernet MAC. =20 -config OA_TC6 - tristate "OPEN Alliance TC6 10BASE-T1x MAC-PHY support" if COMPILE_TEST - depends on SPI - select PHYLIB - help - This library implements OPEN Alliance TC6 10BASE-T1x MAC-PHY - Serial Interface protocol for supporting 10BASE-T1x MAC-PHYs. - - To know the implementation details, refer documentation in - . - source "drivers/net/ethernet/pasemi/Kconfig" source "drivers/net/ethernet/pensando/Kconfig" source "drivers/net/ethernet/qlogic/Kconfig" diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile index bba55d9af387..77b11d5a7abf 100644 --- a/drivers/net/ethernet/Makefile +++ b/drivers/net/ethernet/Makefile @@ -71,6 +71,7 @@ obj-$(CONFIG_NET_VENDOR_NETRONOME) +=3D netronome/ obj-$(CONFIG_NET_VENDOR_NI) +=3D ni/ obj-$(CONFIG_NET_VENDOR_NVIDIA) +=3D nvidia/ obj-$(CONFIG_LPC_ENET) +=3D nxp/ +obj-$(CONFIG_OA_TC6) +=3D oa_tc6/ obj-$(CONFIG_NET_VENDOR_OKI) +=3D oki-semi/ obj-$(CONFIG_ETHOC) +=3D ethoc.o obj-$(CONFIG_NET_VENDOR_PASEMI) +=3D pasemi/ @@ -104,4 +105,3 @@ obj-$(CONFIG_NET_VENDOR_XILINX) +=3D xilinx/ obj-$(CONFIG_NET_VENDOR_XIRCOM) +=3D xircom/ obj-$(CONFIG_NET_VENDOR_SYNOPSYS) +=3D synopsys/ obj-$(CONFIG_NET_VENDOR_PENSANDO) +=3D pensando/ -obj-$(CONFIG_OA_TC6) +=3D oa_tc6.o diff --git a/drivers/net/ethernet/oa_tc6/Kconfig b/drivers/net/ethernet/oa_= tc6/Kconfig new file mode 100644 index 000000000000..97345f345fb9 --- /dev/null +++ b/drivers/net/ethernet/oa_tc6/Kconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# OA TC6 10BASE-T1x MAC-PHY configuration +# + +config OA_TC6 + tristate "OPEN Alliance TC6 10BASE-T1x MAC-PHY support" + depends on SPI + select PHYLIB + help + This library implements OPEN Alliance TC6 10BASE-T1x MAC-PHY + Serial Interface protocol for supporting 10BASE-T1x MAC-PHYs. + + To know the implementation details, refer documentation in + . + diff --git a/drivers/net/ethernet/oa_tc6/Makefile b/drivers/net/ethernet/oa= _tc6/Makefile new file mode 100644 index 000000000000..f24aae852ef2 --- /dev/null +++ b/drivers/net/ethernet/oa_tc6/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Makefile for OA TC6 10BASE-T1x MAC-PHY +# + +obj-$(CONFIG_OA_TC6) :=3D oa_tc6_mod.o +oa_tc6_mod-objs :=3D oa_tc6.o diff --git a/drivers/net/ethernet/oa_tc6.c b/drivers/net/ethernet/oa_tc6/oa= _tc6.c similarity index 100% rename from drivers/net/ethernet/oa_tc6.c rename to drivers/net/ethernet/oa_tc6/oa_tc6.c --=20 2.43.0 From nobody Mon Jun 8 06:37:54 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3DE62F8EA3; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Parthiban Veerasooran , Selva Rajagopal , Richard Cochran , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Simon Horman , Jonathan Corbet , Shuah Khan Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, Jerry Ray , Selvamani Rajagopal X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780724562; l=2443; i=Selvamani.Rajagopal@onsemi.com; s=20260531; h=from:subject:message-id; bh=6sTUcccS7JT5OwyvQOGywuignQ32VFAFjNX0fljOxUI=; b=itPmpMHWoPWnso/Qb9QuMMu3T6jnObSBOWOdQYubTo9lEaCWR4sEp24QGd3dC7wQXbUd3CyNC Cq6XtW7R34ABTMB+YMKyJsbxyNkRtUUvA4wnS9vHc0/5/3yVvG81sV3 X-Developer-Key: i=Selvamani.Rajagopal@onsemi.com; a=ed25519; pk=5QRdM0HS/LGWWcUZZ9hVfZ+qbPQGZCumcTXOiN7Fyug= X-Endpoint-Received: by B4 Relay for Selvamani.Rajagopal@onsemi.com/20260531 with auth_id=803 X-Original-From: Selvamani Rajagopal Reply-To: Selvamani.Rajagopal@onsemi.com From: Selvamani Rajagopal Replace vendor implementation with generic API to read and write PHY registers using C45 bus protocol. Signed-off-by: Selvamani Rajagopal --- drivers/net/phy/microchip_t1s.c | 32 ++------------------------------ 1 file changed, 2 insertions(+), 30 deletions(-) diff --git a/drivers/net/phy/microchip_t1s.c b/drivers/net/phy/microchip_t1= s.c index e601d56b2507..0c4dc70641d8 100644 --- a/drivers/net/phy/microchip_t1s.c +++ b/drivers/net/phy/microchip_t1s.c @@ -506,34 +506,6 @@ static int lan86xx_read_status(struct phy_device *phyd= ev) return 0; } =20 -/* OPEN Alliance 10BASE-T1x compliance MAC-PHYs will have both C22 and - * C45 registers space. If the PHY is discovered via C22 bus protocol it a= ssumes - * it uses C22 protocol and always uses C22 registers indirect access to a= ccess - * C45 registers. This is because, we don't have a clean separation between - * C22/C45 register space and C22/C45 MDIO bus protocols. Resulting, PHY C= 45 - * registers direct access can't be used which can save multiple SPI bus a= ccess. - * To support this feature, set .read_mmd/.write_mmd in the PHY driver to = call - * .read_c45/.write_c45 in the OPEN Alliance framework - * drivers/net/ethernet/oa_tc6.c - */ -static int lan865x_phy_read_mmd(struct phy_device *phydev, int devnum, - u16 regnum) -{ - struct mii_bus *bus =3D phydev->mdio.bus; - int addr =3D phydev->mdio.addr; - - return __mdiobus_c45_read(bus, addr, devnum, regnum); -} - -static int lan865x_phy_write_mmd(struct phy_device *phydev, int devnum, - u16 regnum, u16 val) -{ - struct mii_bus *bus =3D phydev->mdio.bus; - int addr =3D phydev->mdio.addr; - - return __mdiobus_c45_write(bus, addr, devnum, regnum, val); -} - static struct phy_driver microchip_t1s_driver[] =3D { { PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVB1), @@ -584,8 +556,8 @@ static struct phy_driver microchip_t1s_driver[] =3D { .features =3D PHY_BASIC_T1S_P2MP_FEATURES, .config_init =3D lan865x_revb_config_init, .read_status =3D lan86xx_read_status, - .read_mmd =3D lan865x_phy_read_mmd, - .write_mmd =3D lan865x_phy_write_mmd, + .read_mmd =3D genphy_phy_read_mmd, + .write_mmd =3D genphy_phy_write_mmd, .get_plca_cfg =3D genphy_c45_plca_get_cfg, .set_plca_cfg =3D lan86xx_plca_set_cfg, .get_plca_status =3D genphy_c45_plca_get_status, --=20 2.43.0 From nobody Mon Jun 8 06:37:54 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD0C730569E; Sat, 6 Jun 2026 05:42:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780724569; cv=none; b=FWIZpHxDvySAUzJq/9uTzHR8kNXBzxS7MyqtNb3+uD74qQOSuX/9uLu/8tkDVrzLifuIICWiNXtTwUX7X0dTi9WihDQQWJDNbdRYO2AiTXg1Z+14NkHY9DiN4x/h1yC1ShFmFXd0rKoDxhH2qye/Tv7sLqY2VyG5E3wHS25Gb9c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780724569; c=relaxed/simple; bh=mKQoM1tv8RXprV8THVMxouHKboyYRpKLR8ZPyw0fMv8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Gg8H11Zhv4q4vKWDo9wE2ArWHVuwIAdBZrwNsoQwSYnnPyEzEcs2u8yNYBsuOqPazwtTXxQFrwrgVZ6LHDpQh0lcD7rAITgCc6dKrllGyBp1nSdjuTaUU1cHRoPuihUSxIk7amvK8pB8vB2yKC9Vlop9gfgq+jv7zmuj4uJQvw0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=FgYNFEII; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FgYNFEII" Received: by smtp.kernel.org (Postfix) with ESMTPS id 6D41DC2BD05; Sat, 6 Jun 2026 05:42:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1780724569; bh=mKQoM1tv8RXprV8THVMxouHKboyYRpKLR8ZPyw0fMv8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=FgYNFEIIeadWPLwndXNhG+CMiKZq7ZY45uIMOGb1ss8Yce1J6QhLdaPLfwRmGS+Ql GZEjh4fO0h6q3cAJ5vAUpyim2YgEhE6YNOsMWK+pKRW+Dl2TgqRDoN8ju/qenXozsx +U6LHPgrUp26swoiHhewyjCMD9W6lAMQV55LB78S/NJ/9CPbWvIu3xHaKMwijmaYM+ POnBcuLPlqD4q5mzJ1ZxtqAeDeQwJSg0HQNlKTTY0UZS8cSSYTQsTI3z20PRoLOfEi b8810Vd4qYy4/Vz/4vcZS9WdgQ/+OQ3cBUbREudrmCxxU49Zf5IS/DPo0qSI6glcPR nJ0gDRglbhR7g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63E75CD8C85; Sat, 6 Jun 2026 05:42:49 +0000 (UTC) From: Selvamani Rajagopal via B4 Relay Date: Fri, 05 Jun 2026 22:42:36 -0700 Subject: [PATCH net-next v4 05/16] net: ethernet: oa_tc6: Move constant definitions to header file Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260605-s2500-mac-phy-support-v4-5-de0fbc13c6d8@onsemi.com> References: <20260605-s2500-mac-phy-support-v4-0-de0fbc13c6d8@onsemi.com> In-Reply-To: <20260605-s2500-mac-phy-support-v4-0-de0fbc13c6d8@onsemi.com> To: Andrew Lunn , Piergiorgio Beruto , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Parthiban Veerasooran , Selva Rajagopal , Richard Cochran , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Simon Horman , Jonathan Corbet , Shuah Khan Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, Jerry Ray , Selvamani Rajagopal X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780724562; l=12577; i=Selvamani.Rajagopal@onsemi.com; s=20260531; h=from:subject:message-id; bh=V9/p26HuvjVIzSu/3awlHVeh7NO/NgV0TeoDAwfwULI=; b=Hc8VRQZQsguwQ9JjqCaF3OeMNKNUf/D0QX7dTMzV2SP8B+L9/yuDhHM5W263BavSJfbVg/1Ug yDmqPWjNncxAHT6SnKFg/YEkuk5K1qmcfhflQzO8HB70ZxbKRniFdu/ X-Developer-Key: i=Selvamani.Rajagopal@onsemi.com; a=ed25519; pk=5QRdM0HS/LGWWcUZZ9hVfZ+qbPQGZCumcTXOiN7Fyug= X-Endpoint-Received: by B4 Relay for Selvamani.Rajagopal@onsemi.com/20260531 with auth_id=803 X-Original-From: Selvamani Rajagopal Reply-To: Selvamani.Rajagopal@onsemi.com From: Selvamani Rajagopal To help other source files within the module share the constant definitions, they are moved to a header file. Signed-off-by: Selvamani Rajagopal --- drivers/net/ethernet/oa_tc6/oa_tc6.c | 145 +----------------------= -- drivers/net/ethernet/oa_tc6/oa_tc6_std_def.h | 157 +++++++++++++++++++++++= ++++ include/linux/oa_tc6.h | 15 +++ 3 files changed, 173 insertions(+), 144 deletions(-) diff --git a/drivers/net/ethernet/oa_tc6/oa_tc6.c b/drivers/net/ethernet/oa= _tc6/oa_tc6.c index 91a906a7918a..c7d70d37ba53 100644 --- a/drivers/net/ethernet/oa_tc6/oa_tc6.c +++ b/drivers/net/ethernet/oa_tc6/oa_tc6.c @@ -11,150 +11,7 @@ #include #include =20 -/* OPEN Alliance TC6 registers */ -/* Standard Capabilities Register */ -#define OA_TC6_REG_STDCAP 0x0002 -#define STDCAP_DIRECT_PHY_REG_ACCESS BIT(8) - -/* Reset Control and Status Register */ -#define OA_TC6_REG_RESET 0x0003 -#define RESET_SWRESET BIT(0) /* Software Reset */ - -/* Configuration Register #0 */ -#define OA_TC6_REG_CONFIG0 0x0004 -#define CONFIG0_SYNC BIT(15) -#define CONFIG0_ZARFE_ENABLE BIT(12) - -/* Status Register #0 */ -#define OA_TC6_REG_STATUS0 0x0008 -#define STATUS0_RESETC BIT(6) /* Reset Complete */ -#define STATUS0_HEADER_ERROR BIT(5) -#define STATUS0_LOSS_OF_FRAME_ERROR BIT(4) -#define STATUS0_RX_BUFFER_OVERFLOW_ERROR BIT(3) -#define STATUS0_TX_PROTOCOL_ERROR BIT(0) - -/* Buffer Status Register */ -#define OA_TC6_REG_BUFFER_STATUS 0x000B -#define BUFFER_STATUS_TX_CREDITS_AVAILABLE GENMASK(15, 8) -#define BUFFER_STATUS_RX_CHUNKS_AVAILABLE GENMASK(7, 0) - -/* Interrupt Mask Register #0 */ -#define OA_TC6_REG_INT_MASK0 0x000C -#define INT_MASK0_HEADER_ERR_MASK BIT(5) -#define INT_MASK0_LOSS_OF_FRAME_ERR_MASK BIT(4) -#define INT_MASK0_RX_BUFFER_OVERFLOW_ERR_MASK BIT(3) -#define INT_MASK0_TX_PROTOCOL_ERR_MASK BIT(0) - -/* PHY Clause 22 registers base address and mask */ -#define OA_TC6_PHY_STD_REG_ADDR_BASE 0xFF00 -#define OA_TC6_PHY_STD_REG_ADDR_MASK 0x1F - -/* Control command header */ -#define OA_TC6_CTRL_HEADER_DATA_NOT_CTRL BIT(31) -#define OA_TC6_CTRL_HEADER_WRITE_NOT_READ BIT(29) -#define OA_TC6_CTRL_HEADER_MEM_MAP_SELECTOR GENMASK(27, 24) -#define OA_TC6_CTRL_HEADER_ADDR GENMASK(23, 8) -#define OA_TC6_CTRL_HEADER_LENGTH GENMASK(7, 1) -#define OA_TC6_CTRL_HEADER_PARITY BIT(0) - -/* Data header */ -#define OA_TC6_DATA_HEADER_DATA_NOT_CTRL BIT(31) -#define OA_TC6_DATA_HEADER_DATA_VALID BIT(21) -#define OA_TC6_DATA_HEADER_START_VALID BIT(20) -#define OA_TC6_DATA_HEADER_START_WORD_OFFSET GENMASK(19, 16) -#define OA_TC6_DATA_HEADER_END_VALID BIT(14) -#define OA_TC6_DATA_HEADER_END_BYTE_OFFSET GENMASK(13, 8) -#define OA_TC6_DATA_HEADER_PARITY BIT(0) - -/* Data footer */ -#define OA_TC6_DATA_FOOTER_EXTENDED_STS BIT(31) -#define OA_TC6_DATA_FOOTER_RXD_HEADER_BAD BIT(30) -#define OA_TC6_DATA_FOOTER_CONFIG_SYNC BIT(29) -#define OA_TC6_DATA_FOOTER_RX_CHUNKS GENMASK(28, 24) -#define OA_TC6_DATA_FOOTER_DATA_VALID BIT(21) -#define OA_TC6_DATA_FOOTER_START_VALID BIT(20) -#define OA_TC6_DATA_FOOTER_START_WORD_OFFSET GENMASK(19, 16) -#define OA_TC6_DATA_FOOTER_END_VALID BIT(14) -#define OA_TC6_DATA_FOOTER_END_BYTE_OFFSET GENMASK(13, 8) -#define OA_TC6_DATA_FOOTER_TX_CREDITS GENMASK(5, 1) - -/* PHY =E2=80=93 Clause 45 registers memory map selector (MMS) as per tabl= e 6 in the - * OPEN Alliance specification. - */ -#define OA_TC6_PHY_C45_PCS_MMS2 2 /* MMD 3 */ -#define OA_TC6_PHY_C45_PMA_PMD_MMS3 3 /* MMD 1 */ -#define OA_TC6_PHY_C45_VS_PLCA_MMS4 4 /* MMD 31 */ -#define OA_TC6_PHY_C45_AUTO_NEG_MMS5 5 /* MMD 7 */ -#define OA_TC6_PHY_C45_POWER_UNIT_MMS6 6 /* MMD 13 */ - -#define OA_TC6_CTRL_HEADER_SIZE 4 -#define OA_TC6_CTRL_REG_VALUE_SIZE 4 -#define OA_TC6_CTRL_IGNORED_SIZE 4 -#define OA_TC6_CTRL_MAX_REGISTERS 128 -#define OA_TC6_CTRL_SPI_BUF_SIZE (OA_TC6_CTRL_HEADER_SIZE +\ - (OA_TC6_CTRL_MAX_REGISTERS *\ - OA_TC6_CTRL_REG_VALUE_SIZE) +\ - OA_TC6_CTRL_IGNORED_SIZE) -#define OA_TC6_CHUNK_PAYLOAD_SIZE 64 -#define OA_TC6_DATA_HEADER_SIZE 4 -#define OA_TC6_CHUNK_SIZE (OA_TC6_DATA_HEADER_SIZE +\ - OA_TC6_CHUNK_PAYLOAD_SIZE) -#define OA_TC6_MAX_TX_CHUNKS 48 -#define OA_TC6_SPI_DATA_BUF_SIZE (OA_TC6_MAX_TX_CHUNKS *\ - OA_TC6_CHUNK_SIZE) -#define STATUS0_RESETC_POLL_DELAY 1000 -#define STATUS0_RESETC_POLL_TIMEOUT 1000000 - -/* Internal structure for MAC-PHY drivers */ -struct oa_tc6 { - struct device *dev; - struct net_device *netdev; - struct phy_device *phydev; - struct mii_bus *mdiobus; - struct spi_device *spi; - struct mutex spi_ctrl_lock; /* Protects spi control transfer */ - spinlock_t tx_skb_lock; /* Protects tx skb handling */ - void *spi_ctrl_tx_buf; - void *spi_ctrl_rx_buf; - void *spi_data_tx_buf; - void *spi_data_rx_buf; - struct sk_buff *ongoing_tx_skb; - struct sk_buff *waiting_tx_skb; - struct sk_buff *rx_skb; - struct task_struct *spi_thread; - wait_queue_head_t spi_wq; - u16 tx_skb_offset; - u16 spi_data_tx_buf_offset; - u16 tx_credits; - u8 rx_chunks_available; - bool rx_buf_overflow; - bool int_flag; -}; - -enum oa_tc6_header_type { - OA_TC6_CTRL_HEADER, - OA_TC6_DATA_HEADER, -}; - -enum oa_tc6_register_op { - OA_TC6_CTRL_REG_READ =3D 0, - OA_TC6_CTRL_REG_WRITE =3D 1, -}; - -enum oa_tc6_data_valid_info { - OA_TC6_DATA_INVALID, - OA_TC6_DATA_VALID, -}; - -enum oa_tc6_data_start_valid_info { - OA_TC6_DATA_START_INVALID, - OA_TC6_DATA_START_VALID, -}; - -enum oa_tc6_data_end_valid_info { - OA_TC6_DATA_END_INVALID, - OA_TC6_DATA_END_VALID, -}; +#include "oa_tc6_std_def.h" =20 static int oa_tc6_spi_transfer(struct oa_tc6 *tc6, enum oa_tc6_header_type header_type, u16 length) diff --git a/drivers/net/ethernet/oa_tc6/oa_tc6_std_def.h b/drivers/net/eth= ernet/oa_tc6/oa_tc6_std_def.h new file mode 100644 index 000000000000..2d8e28fb46fc --- /dev/null +++ b/drivers/net/ethernet/oa_tc6/oa_tc6_std_def.h @@ -0,0 +1,157 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Register and driver related definitions to support + * OPEN Alliance 10BASE=E2=80=91T1x MAC=E2=80=91PHY Serial Interface frame= work. + * + * Author: Selva Rajagopal + */ + +#ifndef OA_TC6_STD_DEF_H +#define OA_TC6_STD_DEF_H + +#include +#include +#include +#include +#include +#include +#include +#include + +/* OPEN Alliance TC6 registers */ +/* Standard Capabilities Register */ +#define OA_TC6_REG_STDCAP 0x0002 +#define STDCAP_DIRECT_PHY_REG_ACCESS BIT(8) + +/* Reset Control and Status Register */ +#define OA_TC6_REG_RESET 0x0003 +#define RESET_SWRESET BIT(0) /* Software Reset */ + +/* Configuration Register #0 */ +#define OA_TC6_REG_CONFIG0 0x0004 +#define CONFIG0_SYNC BIT(15) +#define CONFIG0_ZARFE_ENABLE BIT(12) + +/* Status Register #0 */ +#define OA_TC6_REG_STATUS0 0x0008 +#define STATUS0_RESETC BIT(6) /* Reset Complete */ +#define STATUS0_HEADER_ERROR BIT(5) +#define STATUS0_LOSS_OF_FRAME_ERROR BIT(4) +#define STATUS0_RX_BUFFER_OVERFLOW_ERROR BIT(3) +#define STATUS0_TX_PROTOCOL_ERROR BIT(0) + +/* Buffer Status Register */ +#define OA_TC6_REG_BUFFER_STATUS 0x000B +#define BUFFER_STATUS_TX_CREDITS_AVAILABLE GENMASK(15, 8) +#define BUFFER_STATUS_RX_CHUNKS_AVAILABLE GENMASK(7, 0) + +/* Interrupt Mask Register #0 */ +#define OA_TC6_REG_INT_MASK0 0x000C +#define INT_MASK0_HEADER_ERR_MASK BIT(5) +#define INT_MASK0_LOSS_OF_FRAME_ERR_MASK BIT(4) +#define INT_MASK0_RX_BUFFER_OVERFLOW_ERR_MASK BIT(3) +#define INT_MASK0_TX_PROTOCOL_ERR_MASK BIT(0) + +/* PHY Clause 22 registers base address and mask */ +#define OA_TC6_PHY_STD_REG_ADDR_BASE 0xFF00 +#define OA_TC6_PHY_STD_REG_ADDR_MASK 0x1F + +/* Control command header */ +#define OA_TC6_CTRL_HEADER_DATA_NOT_CTRL BIT(31) +#define OA_TC6_CTRL_HEADER_WRITE_NOT_READ BIT(29) +#define OA_TC6_CTRL_HEADER_MEM_MAP_SELECTOR GENMASK(27, 24) +#define OA_TC6_CTRL_HEADER_ADDR GENMASK(23, 8) +#define OA_TC6_CTRL_HEADER_LENGTH GENMASK(7, 1) +#define OA_TC6_CTRL_HEADER_PARITY BIT(0) + +/* Data header */ +#define OA_TC6_DATA_HEADER_DATA_NOT_CTRL BIT(31) +#define OA_TC6_DATA_HEADER_DATA_VALID BIT(21) +#define OA_TC6_DATA_HEADER_START_VALID BIT(20) +#define OA_TC6_DATA_HEADER_START_WORD_OFFSET GENMASK(19, 16) +#define OA_TC6_DATA_HEADER_END_VALID BIT(14) +#define OA_TC6_DATA_HEADER_END_BYTE_OFFSET GENMASK(13, 8) +#define OA_TC6_DATA_HEADER_PARITY BIT(0) + +/* Data footer */ +#define OA_TC6_DATA_FOOTER_EXTENDED_STS BIT(31) +#define OA_TC6_DATA_FOOTER_RXD_HEADER_BAD BIT(30) +#define OA_TC6_DATA_FOOTER_CONFIG_SYNC BIT(29) +#define OA_TC6_DATA_FOOTER_RX_CHUNKS GENMASK(28, 24) +#define OA_TC6_DATA_FOOTER_DATA_VALID BIT(21) +#define OA_TC6_DATA_FOOTER_START_VALID BIT(20) +#define OA_TC6_DATA_FOOTER_START_WORD_OFFSET GENMASK(19, 16) +#define OA_TC6_DATA_FOOTER_END_VALID BIT(14) +#define OA_TC6_DATA_FOOTER_END_BYTE_OFFSET GENMASK(13, 8) +#define OA_TC6_DATA_FOOTER_TX_CREDITS GENMASK(5, 1) + +#define OA_TC6_CTRL_HEADER_SIZE 4 +#define OA_TC6_CTRL_REG_VALUE_SIZE 4 +#define OA_TC6_CTRL_IGNORED_SIZE 4 +#define OA_TC6_CTRL_MAX_REGISTERS 128 +#define OA_TC6_CTRL_SPI_BUF_SIZE (OA_TC6_CTRL_HEADER_SIZE +\ + (OA_TC6_CTRL_MAX_REGISTERS *\ + OA_TC6_CTRL_REG_VALUE_SIZE) +\ + OA_TC6_CTRL_IGNORED_SIZE) +#define OA_TC6_CHUNK_PAYLOAD_SIZE 64 +#define OA_TC6_DATA_HEADER_SIZE 4 +#define OA_TC6_CHUNK_SIZE (OA_TC6_DATA_HEADER_SIZE +\ + OA_TC6_CHUNK_PAYLOAD_SIZE) +#define OA_TC6_MAX_TX_CHUNKS 48 +#define OA_TC6_SPI_DATA_BUF_SIZE (OA_TC6_MAX_TX_CHUNKS *\ + OA_TC6_CHUNK_SIZE) +#define STATUS0_RESETC_POLL_DELAY 1000 +#define STATUS0_RESETC_POLL_TIMEOUT 1000000 + +/* Internal structure for MAC-PHY drivers */ +struct oa_tc6 { + struct device *dev; + struct net_device *netdev; + struct phy_device *phydev; + struct mii_bus *mdiobus; + struct spi_device *spi; + struct mutex spi_ctrl_lock; /* Protects spi control transfer */ + spinlock_t tx_skb_lock; /* Protects tx skb handling */ + void *spi_ctrl_tx_buf; + void *spi_ctrl_rx_buf; + void *spi_data_tx_buf; + void *spi_data_rx_buf; + struct sk_buff *ongoing_tx_skb; + struct sk_buff *waiting_tx_skb; + struct sk_buff *rx_skb; + struct task_struct *spi_thread; + wait_queue_head_t spi_wq; + u16 tx_skb_offset; + u16 spi_data_tx_buf_offset; + u16 tx_credits; + u8 rx_chunks_available; + bool rx_buf_overflow; + bool int_flag; +}; + +enum oa_tc6_header_type { + OA_TC6_CTRL_HEADER, + OA_TC6_DATA_HEADER, +}; + +enum oa_tc6_register_op { + OA_TC6_CTRL_REG_READ =3D 0, + OA_TC6_CTRL_REG_WRITE =3D 1, +}; + +enum oa_tc6_data_valid_info { + OA_TC6_DATA_INVALID, + OA_TC6_DATA_VALID, +}; + +enum oa_tc6_data_start_valid_info { + OA_TC6_DATA_START_INVALID, + OA_TC6_DATA_START_VALID, +}; + +enum oa_tc6_data_end_valid_info { + OA_TC6_DATA_END_INVALID, + OA_TC6_DATA_END_VALID, +}; +#endif /* OA_TC6_STD_DEF_H */ + diff --git a/include/linux/oa_tc6.h b/include/linux/oa_tc6.h index 15f58e3c56c7..39b80033dfa9 100644 --- a/include/linux/oa_tc6.h +++ b/include/linux/oa_tc6.h @@ -7,9 +7,23 @@ * Author: Parthiban Veerasooran */ =20 +#ifndef _LINUX_OA_TC6_H +#define _LINUX_OA_TC6_H + #include #include =20 +/* PHY =E2=80=93 Clause 45 registers memory map selector (MMS) as per tabl= e 6 in + * the OPEN Alliance specification. + */ +#define OA_TC6_PHY_C45_MAC_MMS1 1 /* No MMD */ +#define OA_TC6_PHY_C45_PCS_MMS2 2 /* MMD 3 */ +#define OA_TC6_PHY_C45_PMA_PMD_MMS3 3 /* MMD 1 */ +#define OA_TC6_PHY_C45_VS_PLCA_MMS4 4 /* MMD 31 */ +#define OA_TC6_PHY_C45_AUTO_NEG_MMS5 5 /* MMD 7 */ +#define OA_TC6_PHY_C45_POWER_UNIT_MMS6 6 /* MMD 13 */ +#define OA_TC6_PHY_C45_VS_MMS12 12 /* for vendors */ + struct oa_tc6; =20 struct oa_tc6 *oa_tc6_init(struct spi_device *spi, struct net_device *netd= ev); @@ -22,3 +36,4 @@ int oa_tc6_read_registers(struct oa_tc6 *tc6, u32 address= , u32 value[], u8 length); netdev_tx_t oa_tc6_start_xmit(struct oa_tc6 *tc6, struct sk_buff *skb); int oa_tc6_zero_align_receive_frame_enable(struct oa_tc6 *tc6); +#endif /* _LINUX_OA_TC6_H */ --=20 2.43.0 From nobody Mon Jun 8 06:37:54 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C830F305679; Sat, 6 Jun 2026 05:42:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780724569; cv=none; b=BLg3T5nDk6VzLzZPkTYIAKLVYVQxAwo/UkQEddWNvaDS/drZifWEmpAzGKz9VsEohUShHS7lQC55cTvwEZ++BrtdmVGG2fnwuR0937k0Y/esiQMzub+sL3z1C2MSN5AwGN+H/GZhqIFmwwETY/SSUCTfchfvLkAMwbhglV/oRvE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780724569; c=relaxed/simple; bh=BmntVjL1h05s6JCzjMfrAVHNRVrxlevE//+d1+io9n0=; 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Sat, 6 Jun 2026 05:42:49 +0000 (UTC) From: Selvamani Rajagopal via B4 Relay Date: Fri, 05 Jun 2026 22:42:37 -0700 Subject: [PATCH net-next v4 06/16] net: ethernet: oa_tc6: Support for hardware timestamp Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260605-s2500-mac-phy-support-v4-6-de0fbc13c6d8@onsemi.com> References: <20260605-s2500-mac-phy-support-v4-0-de0fbc13c6d8@onsemi.com> In-Reply-To: <20260605-s2500-mac-phy-support-v4-0-de0fbc13c6d8@onsemi.com> To: Andrew Lunn , Piergiorgio Beruto , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Parthiban Veerasooran , Selva Rajagopal , Richard Cochran , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Simon Horman , Jonathan Corbet , Shuah Khan Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, Jerry Ray , Selvamani Rajagopal X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780724562; l=26333; i=Selvamani.Rajagopal@onsemi.com; s=20260531; h=from:subject:message-id; bh=DiQqzt0UrLpzYnNOzt1lbzMz9CkM+dy+ZMV1Vg0AaLQ=; b=enWeIlhL82dkevkqhgb974e9nzeczRRH69QkmdarYS6yqKzws6d7I5gokosNSftNBvtJuZHm7 7DkJ2JY/nfVBcX0KGJDeQaq8Eqjq79zY+TBcQKh5/+csxy2Kf6Kdn92 X-Developer-Key: i=Selvamani.Rajagopal@onsemi.com; a=ed25519; pk=5QRdM0HS/LGWWcUZZ9hVfZ+qbPQGZCumcTXOiN7Fyug= X-Endpoint-Received: by B4 Relay for Selvamani.Rajagopal@onsemi.com/20260531 with auth_id=803 X-Original-From: Selvamani Rajagopal Reply-To: Selvamani.Rajagopal@onsemi.com From: Selvamani Rajagopal PTP register/unregister calls are implemented in oa_tc6_ptp.c. The APIs that work with the hardware for timestamp is provided by vendor code as it may be vendor dependent. Interface for ndo_hwtstamp_set/get, ioctl, control and status callback for ethtool are provided to support hardware timestamp feature. Besides ioctl interface, hardware timestamp functions that handles header and footer data are in oa_tc6.c. Helper functions are in oa_tc6_tstamp.c. Signed-off-by: Selvamani Rajagopal --- MAINTAINERS | 1 + drivers/net/ethernet/oa_tc6/Makefile | 2 +- drivers/net/ethernet/oa_tc6/oa_tc6.c | 214 +++++++++++++++++++++++= ++-- drivers/net/ethernet/oa_tc6/oa_tc6_ptp.c | 67 +++++++++ drivers/net/ethernet/oa_tc6/oa_tc6_std_def.h | 33 +++++ drivers/net/ethernet/oa_tc6/oa_tc6_tstamp.c | 202 +++++++++++++++++++++++= ++ include/linux/oa_tc6.h | 12 ++ 7 files changed, 516 insertions(+), 15 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 7e6b28202e88..63b71197d385 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19998,6 +19998,7 @@ F: drivers/rtc/rtc-optee.c =20 OPEN ALLIANCE 10BASE-T1S MACPHY SERIAL INTERFACE FRAMEWORK M: Parthiban Veerasooran +M: Selva Rajagopal (timestamp support) L: netdev@vger.kernel.org S: Maintained F: Documentation/networking/oa-tc6-framework.rst diff --git a/drivers/net/ethernet/oa_tc6/Makefile b/drivers/net/ethernet/oa= _tc6/Makefile index f24aae852ef2..964f668efc2d 100644 --- a/drivers/net/ethernet/oa_tc6/Makefile +++ b/drivers/net/ethernet/oa_tc6/Makefile @@ -4,4 +4,4 @@ # =20 obj-$(CONFIG_OA_TC6) :=3D oa_tc6_mod.o -oa_tc6_mod-objs :=3D oa_tc6.o +oa_tc6_mod-objs :=3D oa_tc6.o oa_tc6_ptp.o oa_tc6_tstamp.o diff --git a/drivers/net/ethernet/oa_tc6/oa_tc6.c b/drivers/net/ethernet/oa= _tc6/oa_tc6.c index c7d70d37ba53..9410cecfdc2a 100644 --- a/drivers/net/ethernet/oa_tc6/oa_tc6.c +++ b/drivers/net/ethernet/oa_tc6/oa_tc6.c @@ -13,6 +13,15 @@ =20 #include "oa_tc6_std_def.h" =20 +struct oa_tc6_ts_info_rx { + bool rtsa; + bool rtsp; +}; + +struct oa_tc6_ts_info_tx { + u8 tsc; +}; + static int oa_tc6_spi_transfer(struct oa_tc6 *tc6, enum oa_tc6_header_type header_type, u16 length) { @@ -47,6 +56,152 @@ static int oa_tc6_get_parity(u32 p) return !((p >> 28) & 1); } =20 +static struct oa_tc6_ts_info_tx *oa_tc6_tsinfo_tx(struct sk_buff *skb) +{ + return (struct oa_tc6_ts_info_tx *)(skb->cb); +} + +static struct oa_tc6_ts_info_rx *oa_tc6_tsinfo_rx(struct sk_buff *skb) +{ + return (struct oa_tc6_ts_info_rx *)(skb->cb); +} + +static void oa_tc6_defer_for_hwtstamp(struct oa_tc6 *tc6, + struct sk_buff *skb) +{ + if (!tc6->hw_tstamp_enabled) + return; + if (!skb || (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) =3D=3D 0) + return; + if (tc6->ts_config.tx_type !=3D HWTSTAMP_TX_ON) { + tc6->tx_hwtstamp_lost++; + return; + } + + skb_shinfo(skb)->tx_flags |=3D SKBTX_IN_PROGRESS; + u8 ret =3D tc6->tx_ts_idx++; + + if (ret =3D=3D OA_TC6_TTSCC_REG_ID) + tc6->tx_ts_idx =3D OA_TC6_TTSCA_REG_ID; + oa_tc6_tsinfo_tx(skb)->tsc =3D ret; + + list_add_tail(&skb->list, &tc6->tx_ts_skb_q); +} + +static int oa_tc6_process_deferred_skb(struct oa_tc6 *tc6, u8 tsc) +{ + struct skb_shared_hwtstamps tstamp; + struct oa_tc6_ts_info_tx *ski; + struct sk_buff *skb, *tmp; + bool found =3D false; + int ret =3D 0; + + /* Size of data must match OA_TC6_TSTAMP_SZ */ + u32 data[2]; + + list_for_each_entry_safe(skb, tmp, &tc6->tx_ts_skb_q, list) { + ski =3D oa_tc6_tsinfo_tx(skb); + if (ski->tsc !=3D tsc) + continue; + if (found) { + dev_warn_ratelimited(&tc6->spi->dev, + "Multiple skbs. tsc =3D %d\n", + tsc); + tc6->tx_hwtstamp_err++; + } + found =3D true; + list_del(&skb->list); + + /* Retrieve the timestamping info */ + ret =3D oa_tc6_read_registers(tc6, + OA_TC6_REG_TTSCA_HIGH + + 2 * (tsc - 1), &data[0], 2); + + if (!ret) { + tstamp.hwtstamp =3D ktime_set(data[0], data[1]); + skb_tstamp_tx(skb, &tstamp); + tc6->tx_hwtstamp_pkts++; + } + + dev_kfree_skb(skb); + } + return ret; +} + +static void oa_tc6_events_handle(struct oa_tc6 *tc6, u32 val) +{ + /* Check TX timestamping */ + if (val & STATUS0_TTSCAA) + oa_tc6_process_deferred_skb(tc6, OA_TC6_TTSCA_REG_ID); + + if (val & STATUS0_TTSCAB) + oa_tc6_process_deferred_skb(tc6, OA_TC6_TTSCB_REG_ID); + + if (val & STATUS0_TTSCAC) + oa_tc6_process_deferred_skb(tc6, OA_TC6_TTSCC_REG_ID); +} + +static void oa_tc6_update_ts_in_rx_skb(struct oa_tc6 *tc6) +{ + struct sk_buff *skb =3D tc6->rx_skb; + struct oa_tc6_ts_info_rx *ski; + u32 ts[2]; + + if (!tc6->hw_tstamp_enabled) + return; + ski =3D oa_tc6_tsinfo_rx(skb); + if (!ski->rtsa) + return; + + ts[0] =3D be32_to_cpu(*((u32 *)(skb->data))); + ts[1] =3D be32_to_cpu(*((u32 *)(skb->data) + 1)); + + /* Check parity */ + if ((oa_tc6_get_parity(ts[0]) ^ oa_tc6_get_parity(ts[1])) =3D=3D + !ski->rtsp) { + struct skb_shared_hwtstamps *hw_ts; + + /* Report timestamp to the upper layers */ + hw_ts =3D skb_hwtstamps(skb); + memset(hw_ts, 0, sizeof(*hw_ts)); + hw_ts->hwtstamp =3D ktime_set(ts[0], ts[1]); + } + skb_pull(skb, sizeof(ts)); +} + +static int oa_tc6_update_standard_capability(struct oa_tc6 *tc6) +{ + u32 regval =3D 0; + int ret; + + ret =3D oa_tc6_read_register(tc6, OA_TC6_REG_STDCAP, ®val); + if (ret) + return ret; + if (regval & STDCAP_FRAME_TIMESTAMP_CAPABILITY) + tc6->hw_tstamp_supported =3D true; + return 0; +} + +/** + * oa_tc6_ioctl - generic ioctl interface for MAC-PHY drivers. + * @tc6: oa_tc6 struct. + * @rq: request from socket interface + * @cmd: value to set/get timestamp configuration + * + * Return: 0 on success otherwise failed. + */ +int oa_tc6_ioctl(struct oa_tc6 *tc6, struct ifreq *rq, int cmd) +{ + if (!netif_running(tc6->netdev)) + return -EINVAL; + + if (cmd =3D=3D SIOCSHWTSTAMP || cmd =3D=3D SIOCGHWTSTAMP) + return oa_tc6_tstamp_ioctl(tc6, rq, cmd); + else + return phy_do_ioctl_running(tc6->netdev, rq, cmd); +} +EXPORT_SYMBOL_GPL(oa_tc6_ioctl); + static __be32 oa_tc6_prepare_ctrl_header(u32 addr, u8 length, enum oa_tc6_register_op reg_op) { @@ -538,6 +693,9 @@ static int oa_tc6_process_extended_status(struct oa_tc6= *tc6) return ret; } =20 + if ((value & STATUS0_TTSCA_MASK) !=3D 0) + oa_tc6_events_handle(tc6, value & STATUS0_TTSCA_MASK); + /* Clear the error interrupts status */ ret =3D oa_tc6_write_register(tc6, OA_TC6_REG_STATUS0, value); if (ret) { @@ -609,6 +767,8 @@ static int oa_tc6_process_rx_chunk_footer(struct oa_tc6= *tc6, u32 footer) =20 static void oa_tc6_submit_rx_skb(struct oa_tc6 *tc6) { + oa_tc6_update_ts_in_rx_skb(tc6); + tc6->rx_skb->protocol =3D eth_type_trans(tc6->rx_skb, tc6->netdev); tc6->netdev->stats.rx_packets++; tc6->netdev->stats.rx_bytes +=3D tc6->rx_skb->len; @@ -623,24 +783,29 @@ static void oa_tc6_update_rx_skb(struct oa_tc6 *tc6, = u8 *payload, u8 length) memcpy(skb_put(tc6->rx_skb, length), payload, length); } =20 -static int oa_tc6_allocate_rx_skb(struct oa_tc6 *tc6) +static int oa_tc6_allocate_rx_skb(struct oa_tc6 *tc6, u32 footer) { + struct oa_tc6_ts_info_rx *ski; + tc6->rx_skb =3D netdev_alloc_skb_ip_align(tc6->netdev, tc6->netdev->mtu + - ETH_HLEN + ETH_FCS_LEN); + ETH_HLEN + ETH_FCS_LEN + OA_TC6_TSTAMP_SZ); if (!tc6->rx_skb) { tc6->netdev->stats.rx_dropped++; return -ENOMEM; } =20 + ski =3D oa_tc6_tsinfo_rx(tc6->rx_skb); + ski->rtsa =3D FIELD_GET(OA_TC6_DATA_FOOTER_RTSA_VALID, footer); + ski->rtsp =3D FIELD_GET(OA_TC6_DATA_FOOTER_RTSP_VALID, footer); return 0; } =20 static int oa_tc6_prcs_complete_rx_frame(struct oa_tc6 *tc6, u8 *payload, - u16 size) + u16 size, u32 footer) { int ret; =20 - ret =3D oa_tc6_allocate_rx_skb(tc6); + ret =3D oa_tc6_allocate_rx_skb(tc6, footer); if (ret) return ret; =20 @@ -651,11 +816,11 @@ static int oa_tc6_prcs_complete_rx_frame(struct oa_tc= 6 *tc6, u8 *payload, return 0; } =20 -static int oa_tc6_prcs_rx_frame_start(struct oa_tc6 *tc6, u8 *payload, u16= size) +static int oa_tc6_prcs_rx_frame_start(struct oa_tc6 *tc6, u8 *payload, u16= size, u32 footer) { int ret; =20 - ret =3D oa_tc6_allocate_rx_skb(tc6); + ret =3D oa_tc6_allocate_rx_skb(tc6, footer); if (ret) return ret; =20 @@ -700,7 +865,7 @@ static int oa_tc6_prcs_rx_chunk_payload(struct oa_tc6 *= tc6, u8 *data, size =3D end_byte_offset + 1 - start_byte_offset; return oa_tc6_prcs_complete_rx_frame(tc6, &data[start_byte_offset], - size); + size, footer); } =20 /* Process the chunk with only rx frame start */ @@ -708,7 +873,7 @@ static int oa_tc6_prcs_rx_chunk_payload(struct oa_tc6 *= tc6, u8 *data, size =3D OA_TC6_CHUNK_PAYLOAD_SIZE - start_byte_offset; return oa_tc6_prcs_rx_frame_start(tc6, &data[start_byte_offset], - size); + size, footer); } =20 /* Process the chunk with only rx frame end */ @@ -733,7 +898,7 @@ static int oa_tc6_prcs_rx_chunk_payload(struct oa_tc6 *= tc6, u8 *data, size =3D OA_TC6_CHUNK_PAYLOAD_SIZE - start_byte_offset; return oa_tc6_prcs_rx_frame_start(tc6, &data[start_byte_offset], - size); + size, footer); } =20 /* Process the chunk with ongoing rx frame data */ @@ -787,13 +952,15 @@ static int oa_tc6_process_spi_data_rx_buf(struct oa_t= c6 *tc6, u16 length) } =20 static __be32 oa_tc6_prepare_data_header(bool data_valid, bool start_valid, - bool end_valid, u8 end_byte_offset) + bool end_valid, u8 end_byte_offset, + u8 tsc) { u32 header =3D FIELD_PREP(OA_TC6_DATA_HEADER_DATA_NOT_CTRL, OA_TC6_DATA_HEADER) | FIELD_PREP(OA_TC6_DATA_HEADER_DATA_VALID, data_valid) | FIELD_PREP(OA_TC6_DATA_HEADER_START_VALID, start_valid) | FIELD_PREP(OA_TC6_DATA_HEADER_END_VALID, end_valid) | + FIELD_PREP(OA_TC6_DATA_HEADER_TSC_OFFSET, tsc) | FIELD_PREP(OA_TC6_DATA_HEADER_END_BYTE_OFFSET, end_byte_offset); =20 @@ -812,6 +979,7 @@ static void oa_tc6_add_tx_skb_to_spi_buf(struct oa_tc6 = *tc6) enum oa_tc6_data_start_valid_info start_valid; u8 end_byte_offset =3D 0; u16 length_to_copy; + u8 tsc =3D 0; =20 /* Initial value is assigned here to avoid more than 80 characters in * the declaration place. @@ -821,8 +989,10 @@ static void oa_tc6_add_tx_skb_to_spi_buf(struct oa_tc6= *tc6) /* Set start valid if the current tx chunk contains the start of the tx * ethernet frame. */ - if (!tc6->tx_skb_offset) + if (!tc6->tx_skb_offset) { start_valid =3D OA_TC6_DATA_START_VALID; + tsc =3D oa_tc6_tsinfo_tx(tc6->ongoing_tx_skb)->tsc; + } =20 /* If the remaining tx skb length is more than the chunk payload size of * 64 bytes then copy only 64 bytes and leave the ongoing tx skb for @@ -843,12 +1013,17 @@ static void oa_tc6_add_tx_skb_to_spi_buf(struct oa_t= c6 *tc6) tc6->tx_skb_offset =3D 0; tc6->netdev->stats.tx_bytes +=3D tc6->ongoing_tx_skb->len; tc6->netdev->stats.tx_packets++; - kfree_skb(tc6->ongoing_tx_skb); + + /* Free the ones that are not saved for later processing, + * like timestamping. + */ + if (!(skb_shinfo(tc6->ongoing_tx_skb)->tx_flags & SKBTX_IN_PROGRESS)) + kfree_skb(tc6->ongoing_tx_skb); tc6->ongoing_tx_skb =3D NULL; } =20 *tx_buf =3D oa_tc6_prepare_data_header(OA_TC6_DATA_VALID, start_valid, - end_valid, end_byte_offset); + end_valid, end_byte_offset, tsc); tc6->spi_data_tx_buf_offset +=3D OA_TC6_CHUNK_SIZE; } =20 @@ -866,6 +1041,8 @@ static u16 oa_tc6_prepare_spi_tx_buf_for_tx_skbs(struc= t oa_tc6 *tc6) tc6->ongoing_tx_skb =3D tc6->waiting_tx_skb; tc6->waiting_tx_skb =3D NULL; spin_unlock_bh(&tc6->tx_skb_lock); + oa_tc6_defer_for_hwtstamp(tc6, + tc6->ongoing_tx_skb); } if (!tc6->ongoing_tx_skb) break; @@ -882,7 +1059,7 @@ static void oa_tc6_add_empty_chunks_to_spi_buf(struct = oa_tc6 *tc6, =20 header =3D oa_tc6_prepare_data_header(OA_TC6_DATA_INVALID, OA_TC6_DATA_START_INVALID, - OA_TC6_DATA_END_INVALID, 0); + OA_TC6_DATA_END_INVALID, 0, false); =20 while (needed_empty_chunks--) { __be32 *tx_buf =3D tc6->spi_data_tx_buf + @@ -1073,6 +1250,7 @@ netdev_tx_t oa_tc6_start_xmit(struct oa_tc6 *tc6, str= uct sk_buff *skb) spin_lock_bh(&tc6->tx_skb_lock); tc6->waiting_tx_skb =3D skb; spin_unlock_bh(&tc6->tx_skb_lock); + oa_tc6_tsinfo_tx(skb)->tsc =3D 0; =20 /* Wake spi kthread to perform spi transfer */ wake_up_interruptible(&tc6->spi_wq); @@ -1103,6 +1281,8 @@ struct oa_tc6 *oa_tc6_init(struct spi_device *spi, st= ruct net_device *netdev) SET_NETDEV_DEV(netdev, &spi->dev); mutex_init(&tc6->spi_ctrl_lock); spin_lock_init(&tc6->tx_skb_lock); + tc6->tx_ts_idx =3D OA_TC6_TTSCA_REG_ID; + INIT_LIST_HEAD(&tc6->tx_ts_skb_q); =20 /* Set the SPI controller to pump at realtime priority */ tc6->spi->rt =3D true; @@ -1168,6 +1348,12 @@ struct oa_tc6 *oa_tc6_init(struct spi_device *spi, s= truct net_device *netdev) goto phy_exit; } =20 + ret =3D oa_tc6_update_standard_capability(tc6); + if (ret) { + dev_err(&tc6->spi->dev, "Failed to read capability\n"); + goto phy_exit; + } + init_waitqueue_head(&tc6->spi_wq); =20 tc6->spi_thread =3D kthread_run(oa_tc6_spi_thread_handler, tc6, diff --git a/drivers/net/ethernet/oa_tc6/oa_tc6_ptp.c b/drivers/net/etherne= t/oa_tc6/oa_tc6_ptp.c new file mode 100644 index 000000000000..921191ec6829 --- /dev/null +++ b/drivers/net/ethernet/oa_tc6/oa_tc6_ptp.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Support for hardware timestamping feature for OPEN Alliance + * 10BASE=E2=80=91T1x MAC=E2=80=91PHY Serial Interface framework + * + * Author: Selva Rajagopal + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "oa_tc6_std_def.h" + +/** + * oa_tc6_ptp_register - Registers clock related callbacks + * @tc6: oa_tc6 struct. + * @info: Describes a PTP hardware clock + * + * Description: Vendors are expected to set the hardware timestamp + * related callbacks before calling this function. + */ +int oa_tc6_ptp_register(struct oa_tc6 *tc6, struct ptp_clock_info *info) +{ + /* Not supporting hardware timestamp isn't an error */ + if (!tc6->hw_tstamp_supported) + return 0; + + snprintf(info->name, sizeof(info->name), "%s", + "OA TC6 PTP clock"); + tc6->ptp_clock =3D ptp_clock_register(info, &tc6->spi->dev); + if (IS_ERR(tc6->ptp_clock)) { + dev_err(&tc6->spi->dev, "Registration of %s failed", + info->name); + return -EFAULT; + } + dev_info(&tc6->spi->dev, "%s registered. index %d", info->name, + ptp_clock_index(tc6->ptp_clock)); + return 0; +} +EXPORT_SYMBOL_GPL(oa_tc6_ptp_register); + +/** + * oa_tc6_ptp_unregister - Unregisters clock related callbacks + * @tc6: oa_tc6 struct. + */ +void oa_tc6_ptp_unregister(struct oa_tc6 *tc6) +{ + if (tc6->ptp_clock) + ptp_clock_unregister(tc6->ptp_clock); +} +EXPORT_SYMBOL_GPL(oa_tc6_ptp_unregister); + +MODULE_DESCRIPTION("OPEN Alliance 10BASE=E2=80=91T1x MAC=E2=80=91PHY Seria= l Interface Lib"); +MODULE_AUTHOR("Selva Rajagopal "); +MODULE_LICENSE("GPL"); diff --git a/drivers/net/ethernet/oa_tc6/oa_tc6_std_def.h b/drivers/net/eth= ernet/oa_tc6/oa_tc6_std_def.h index 2d8e28fb46fc..3a12b3228f30 100644 --- a/drivers/net/ethernet/oa_tc6/oa_tc6_std_def.h +++ b/drivers/net/ethernet/oa_tc6/oa_tc6_std_def.h @@ -22,6 +22,7 @@ /* Standard Capabilities Register */ #define OA_TC6_REG_STDCAP 0x0002 #define STDCAP_DIRECT_PHY_REG_ACCESS BIT(8) +#define STDCAP_FRAME_TIMESTAMP_CAPABILITY BIT(6) =20 /* Reset Control and Status Register */ #define OA_TC6_REG_RESET 0x0003 @@ -31,9 +32,14 @@ #define OA_TC6_REG_CONFIG0 0x0004 #define CONFIG0_SYNC BIT(15) #define CONFIG0_ZARFE_ENABLE BIT(12) +#define CONFIG0_FTSE_ENABLE BIT(7) =20 /* Status Register #0 */ #define OA_TC6_REG_STATUS0 0x0008 +#define STATUS0_TTSCAC BIT(10) +#define STATUS0_TTSCAB BIT(9) +#define STATUS0_TTSCAA BIT(8) +#define STATUS0_TTSCA_MASK GENMASK(10, 8) #define STATUS0_RESETC BIT(6) /* Reset Complete */ #define STATUS0_HEADER_ERROR BIT(5) #define STATUS0_LOSS_OF_FRAME_ERROR BIT(4) @@ -47,6 +53,7 @@ =20 /* Interrupt Mask Register #0 */ #define OA_TC6_REG_INT_MASK0 0x000C +#define INT_MASK0_TTSCA_MASK GENMASK(10, 8) #define INT_MASK0_HEADER_ERR_MASK BIT(5) #define INT_MASK0_LOSS_OF_FRAME_ERR_MASK BIT(4) #define INT_MASK0_RX_BUFFER_OVERFLOW_ERR_MASK BIT(3) @@ -56,6 +63,9 @@ #define OA_TC6_PHY_STD_REG_ADDR_BASE 0xFF00 #define OA_TC6_PHY_STD_REG_ADDR_MASK 0x1F =20 +/* Tx timestamp capture register A (high) */ +#define OA_TC6_REG_TTSCA_HIGH (0x1010) + /* Control command header */ #define OA_TC6_CTRL_HEADER_DATA_NOT_CTRL BIT(31) #define OA_TC6_CTRL_HEADER_WRITE_NOT_READ BIT(29) @@ -71,6 +81,7 @@ #define OA_TC6_DATA_HEADER_START_WORD_OFFSET GENMASK(19, 16) #define OA_TC6_DATA_HEADER_END_VALID BIT(14) #define OA_TC6_DATA_HEADER_END_BYTE_OFFSET GENMASK(13, 8) +#define OA_TC6_DATA_HEADER_TSC_OFFSET GENMASK(7, 6) #define OA_TC6_DATA_HEADER_PARITY BIT(0) =20 /* Data footer */ @@ -82,6 +93,8 @@ #define OA_TC6_DATA_FOOTER_START_VALID BIT(20) #define OA_TC6_DATA_FOOTER_START_WORD_OFFSET GENMASK(19, 16) #define OA_TC6_DATA_FOOTER_END_VALID BIT(14) +#define OA_TC6_DATA_FOOTER_RTSA_VALID BIT(7) +#define OA_TC6_DATA_FOOTER_RTSP_VALID BIT(6) #define OA_TC6_DATA_FOOTER_END_BYTE_OFFSET GENMASK(13, 8) #define OA_TC6_DATA_FOOTER_TX_CREDITS GENMASK(5, 1) =20 @@ -103,6 +116,12 @@ #define STATUS0_RESETC_POLL_DELAY 1000 #define STATUS0_RESETC_POLL_TIMEOUT 1000000 =20 +#define OA_TC6_TSTAMP_SZ 8 + +#define OA_TC6_TTSCA_REG_ID 1 +#define OA_TC6_TTSCB_REG_ID 2 +#define OA_TC6_TTSCC_REG_ID 3 + /* Internal structure for MAC-PHY drivers */ struct oa_tc6 { struct device *dev; @@ -127,6 +146,17 @@ struct oa_tc6 { u8 rx_chunks_available; bool rx_buf_overflow; bool int_flag; + struct ptp_clock_info ptp_clock_info; + struct hwtstamp_config ts_config; + struct list_head tx_ts_skb_q; + struct ptp_clock *ptp_clock; + bool hw_tstamp_supported; + bool hw_tstamp_enabled; + u32 tx_hwtstamp_pkts; + u32 tx_hwtstamp_lost; + u32 tx_hwtstamp_err; + int vend1_mms; + u8 tx_ts_idx; }; =20 enum oa_tc6_header_type { @@ -153,5 +183,8 @@ enum oa_tc6_data_end_valid_info { OA_TC6_DATA_END_INVALID, OA_TC6_DATA_END_VALID, }; + +int oa_tc6_tstamp_ioctl(struct oa_tc6 *tc6, struct ifreq *rq, int cmd); + #endif /* OA_TC6_STD_DEF_H */ =20 diff --git a/drivers/net/ethernet/oa_tc6/oa_tc6_tstamp.c b/drivers/net/ethe= rnet/oa_tc6/oa_tc6_tstamp.c new file mode 100644 index 000000000000..272701a4081d --- /dev/null +++ b/drivers/net/ethernet/oa_tc6/oa_tc6_tstamp.c @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * OPEN Alliance 10BASE=E2=80=91T1x MAC=E2=80=91PHY Serial Interface frame= work + * + * Author: Selva Rajagopal + */ + +#include +#include +#include +#include +#include + +#include "oa_tc6_std_def.h" + +static int oa_tc6_set_hwtstamp_settings(struct oa_tc6 *tc6) +{ + u32 cfg0, irqm, status0; + int ret; + + ret =3D oa_tc6_read_register(tc6, OA_TC6_REG_CONFIG0, &cfg0); + if (ret) { + dev_err(&tc6->spi->dev, "Failed to read CFG0 register\n"); + goto out; + } + + ret =3D oa_tc6_read_register(tc6, OA_TC6_REG_INT_MASK0, &irqm); + if (ret) { + dev_err(&tc6->spi->dev, "failed to read IRQM register\n"); + goto out; + } + + if (tc6->ts_config.tx_type =3D=3D HWTSTAMP_TX_ON || + tc6->ts_config.rx_filter =3D=3D HWTSTAMP_FILTER_ALL) + cfg0 |=3D CONFIG0_FTSE_ENABLE; + else + cfg0 &=3D ~CONFIG0_FTSE_ENABLE; + + if (tc6->ts_config.tx_type =3D=3D HWTSTAMP_TX_ON) + irqm &=3D ~INT_MASK0_TTSCA_MASK; + else + irqm |=3D INT_MASK0_TTSCA_MASK; + + /* Clear timestamp related IRQs */ + status0 =3D STATUS0_TTSCA_MASK; + ret =3D oa_tc6_write_register(tc6, OA_TC6_REG_STATUS0, status0); + if (ret) { + dev_err(&tc6->spi->dev, "failed to write STATUS0 register\n"); + goto out; + } + + ret =3D oa_tc6_write_register(tc6, OA_TC6_REG_INT_MASK0, irqm); + if (ret) { + dev_err(&tc6->spi->dev, "failed to write IRQM register\n"); + goto out; + } + + ret =3D oa_tc6_write_register(tc6, OA_TC6_REG_CONFIG0, cfg0); + if (ret) { + dev_err(&tc6->spi->dev, "failed to write CFG0 register\n"); + goto out; + } + if (cfg0 & CONFIG0_FTSE_ENABLE) + tc6->hw_tstamp_enabled =3D true; + else + tc6->hw_tstamp_enabled =3D false; +out: + return ret; +} + +/** + * oa_tc6_hwtstamp_get - gets hardware timestamp config + * @tc6: oa_tc6 struct. + * @cfg: kernel copy of hardware timestamp config + */ +void oa_tc6_hwtstamp_get(struct oa_tc6 *tc6, + struct kernel_hwtstamp_config *cfg) +{ + hwtstamp_config_to_kernel(cfg, &tc6->ts_config); +} +EXPORT_SYMBOL_GPL(oa_tc6_hwtstamp_get); + +/** + * oa_tc6_hwtstamp_set - sets hardware timestamp config + * @tc6: oa_tc6 struct. + * @cfg: kernel copy of hardware timestamp config + * + * Return: 0 on success otherwise failed. + */ +int oa_tc6_hwtstamp_set(struct oa_tc6 *tc6, + struct kernel_hwtstamp_config *cfg) +{ + if (!netif_running(tc6->netdev)) + return -EIO; + + if (!tc6->hw_tstamp_supported) + return -EOPNOTSUPP; + + switch (cfg->tx_type) { + case HWTSTAMP_TX_OFF: + case HWTSTAMP_TX_ON: + break; + default: + return -ERANGE; + } + + switch (cfg->rx_filter) { + case HWTSTAMP_FILTER_NONE: + case HWTSTAMP_FILTER_ALL: + case HWTSTAMP_FILTER_SOME: + case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: + case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: + case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: + case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: + case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: + case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: + case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: + case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: + case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: + case HWTSTAMP_FILTER_PTP_V2_EVENT: + case HWTSTAMP_FILTER_PTP_V2_SYNC: + case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: + case HWTSTAMP_FILTER_NTP_ALL: + break; + default: + return -ERANGE; + } + hwtstamp_config_from_kernel(&tc6->ts_config, cfg); + + /* Supports timestamping all traffic */ + if (cfg->rx_filter !=3D HWTSTAMP_FILTER_NONE) + tc6->ts_config.rx_filter =3D HWTSTAMP_FILTER_ALL; + return oa_tc6_set_hwtstamp_settings(tc6); +} +EXPORT_SYMBOL_GPL(oa_tc6_hwtstamp_set); + +/** + * oa_tc6_get_ts_stats - Provides timestamping stats + * @tc6: oa_tc6 struct. + * @ts_stats: ethtool data structure to fill in + */ +void oa_tc6_get_ts_stats(struct oa_tc6 *tc6, + struct ethtool_ts_stats *stats) +{ + stats->pkts =3D tc6->tx_hwtstamp_pkts; + stats->err =3D tc6->tx_hwtstamp_err; + stats->lost =3D tc6->tx_hwtstamp_lost; +} +EXPORT_SYMBOL_GPL(oa_tc6_get_ts_stats); + +int oa_tc6_tstamp_ioctl(struct oa_tc6 *tc6, struct ifreq *rq, int cmd) +{ + struct kernel_hwtstamp_config kcfg; + struct hwtstamp_config tscfg; + int ret =3D 0; + + if (!tc6->hw_tstamp_supported) + return -EOPNOTSUPP; + + if (cmd =3D=3D SIOCSHWTSTAMP) { + if (copy_from_user(&tscfg, rq->ifr_data, + sizeof(tscfg))) + return -EFAULT; + + if (tscfg.flags) + return -EINVAL; + hwtstamp_config_to_kernel(&kcfg, &tscfg); + ret =3D oa_tc6_hwtstamp_set(tc6, &kcfg); + if (ret) + return ret; + } + if (copy_to_user(rq->ifr_data, &tc6->ts_config, + sizeof(tc6->ts_config))) + ret =3D -EFAULT; + return ret; +} + +/** + * oa_tc6_get_ts_info - Provides timestamp info for ethtool + * @tc6: oa_tc6 struct. + * @info: ethtool timestamping info structure + * @ts_stats: ethtool data structure to fill in + */ +int oa_tc6_get_ts_info(struct oa_tc6 *tc6, + struct kernel_ethtool_ts_info *info) +{ + if (!tc6->ptp_clock) + return ethtool_op_get_ts_info(tc6->netdev, info); + + info->so_timestamping =3D SOF_TIMESTAMPING_RAW_HARDWARE | + SOF_TIMESTAMPING_TX_HARDWARE | + SOF_TIMESTAMPING_RX_HARDWARE; + info->phc_index =3D ptp_clock_index(tc6->ptp_clock); + info->tx_types =3D BIT(HWTSTAMP_TX_ON); + info->rx_filters =3D BIT(HWTSTAMP_FILTER_ALL); + return 0; +} +EXPORT_SYMBOL_GPL(oa_tc6_get_ts_info); + +MODULE_DESCRIPTION("OPEN Alliance 10BASE=E2=80=91T1x MAC=E2=80=91PHY Seria= l Interface Lib"); +MODULE_AUTHOR("Selva Rajagopal "); +MODULE_LICENSE("GPL"); diff --git a/include/linux/oa_tc6.h b/include/linux/oa_tc6.h index 39b80033dfa9..4047c22a366a 100644 --- a/include/linux/oa_tc6.h +++ b/include/linux/oa_tc6.h @@ -12,6 +12,7 @@ =20 #include #include +#include =20 /* PHY =E2=80=93 Clause 45 registers memory map selector (MMS) as per tabl= e 6 in * the OPEN Alliance specification. @@ -36,4 +37,15 @@ int oa_tc6_read_registers(struct oa_tc6 *tc6, u32 addres= s, u32 value[], u8 length); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260605-s2500-mac-phy-support-v4-7-de0fbc13c6d8@onsemi.com> References: <20260605-s2500-mac-phy-support-v4-0-de0fbc13c6d8@onsemi.com> In-Reply-To: <20260605-s2500-mac-phy-support-v4-0-de0fbc13c6d8@onsemi.com> To: Andrew Lunn , Piergiorgio Beruto , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Parthiban Veerasooran , Selva Rajagopal , Richard Cochran , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Simon Horman , Jonathan Corbet , Shuah Khan Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, Jerry Ray , Selvamani Rajagopal X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780724562; l=3139; i=Selvamani.Rajagopal@onsemi.com; s=20260531; h=from:subject:message-id; bh=nbQfy8zsWMbmAyspM8wQU+sSMRnj53ReA9nG6bU9G9A=; b=ckfq+FmcO98bmlF271aK9dudpewPWOwYZLOqjE0b9ajRHJWt4VAFWPAVNDYZrUM9bwn8WIbsk nLNC+Vr9MJVD2K36i0f9XwMV0KbLKadaTI2vVTU3fuKwWyOe77vF8vh X-Developer-Key: i=Selvamani.Rajagopal@onsemi.com; a=ed25519; pk=5QRdM0HS/LGWWcUZZ9hVfZ+qbPQGZCumcTXOiN7Fyug= X-Endpoint-Received: by B4 Relay for Selvamani.Rajagopal@onsemi.com/20260531 with auth_id=803 X-Original-From: Selvamani Rajagopal Reply-To: Selvamani.Rajagopal@onsemi.com From: Selvamani Rajagopal OPEN Alliance 10BASE-T1x Serial Interface specification, table 6 allows vendors to use any memory map select (MMS) value between 10 and 15. This new API interface enables vendor to map one of thes MMS values to MDIO_MMD_VEND1. Signed-off-by: Selvamani Rajagopal --- drivers/net/ethernet/oa_tc6/oa_tc6.c | 20 +++++++++++++++++--- include/linux/oa_tc6.h | 1 + 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/oa_tc6/oa_tc6.c b/drivers/net/ethernet/oa= _tc6/oa_tc6.c index 9410cecfdc2a..2f9ace655e81 100644 --- a/drivers/net/ethernet/oa_tc6/oa_tc6.c +++ b/drivers/net/ethernet/oa_tc6/oa_tc6.c @@ -202,6 +202,17 @@ int oa_tc6_ioctl(struct oa_tc6 *tc6, struct ifreq *rq,= int cmd) } EXPORT_SYMBOL_GPL(oa_tc6_ioctl); =20 +/** + * Add vendor specific MDIO_MMD to OA TC6 MMS mapper value. + * @tc6: oa_tc6 struct. + * @mms: vendor defined MMS value for VEND1 mdio device. + */ +void oa_tc6_set_vend1_mms(struct oa_tc6 *tc6, int mms) +{ + tc6->vend1_mms =3D mms; +} +EXPORT_SYMBOL_GPL(oa_tc6_set_vend1_mms); + static __be32 oa_tc6_prepare_ctrl_header(u32 addr, u8 length, enum oa_tc6_register_op reg_op) { @@ -455,7 +466,7 @@ static int oa_tc6_mdiobus_write(struct mii_bus *bus, in= t addr, int regnum, val); } =20 -static int oa_tc6_get_phy_c45_mms(int devnum) +static int oa_tc6_get_phy_c45_mms(struct oa_tc6 *tc6, int devnum) { switch (devnum) { case MDIO_MMD_PCS: @@ -468,6 +479,8 @@ static int oa_tc6_get_phy_c45_mms(int devnum) return OA_TC6_PHY_C45_AUTO_NEG_MMS5; case MDIO_MMD_POWER_UNIT: return OA_TC6_PHY_C45_POWER_UNIT_MMS6; + case MDIO_MMD_VEND1: + return tc6->vend1_mms; default: return -EOPNOTSUPP; } @@ -480,7 +493,7 @@ static int oa_tc6_mdiobus_read_c45(struct mii_bus *bus,= int addr, int devnum, u32 regval; int ret; =20 - ret =3D oa_tc6_get_phy_c45_mms(devnum); + ret =3D oa_tc6_get_phy_c45_mms(tc6, devnum); if (ret < 0) return ret; =20 @@ -497,7 +510,7 @@ static int oa_tc6_mdiobus_write_c45(struct mii_bus *bus= , int addr, int devnum, struct oa_tc6 *tc6 =3D bus->priv; int ret; =20 - ret =3D oa_tc6_get_phy_c45_mms(devnum); + ret =3D oa_tc6_get_phy_c45_mms(tc6, devnum); if (ret < 0) return ret; =20 @@ -1281,6 +1294,7 @@ struct oa_tc6 *oa_tc6_init(struct spi_device *spi, st= ruct net_device *netdev) SET_NETDEV_DEV(netdev, &spi->dev); mutex_init(&tc6->spi_ctrl_lock); spin_lock_init(&tc6->tx_skb_lock); + tc6->vend1_mms =3D -EOPNOTSUPP; tc6->tx_ts_idx =3D OA_TC6_TTSCA_REG_ID; INIT_LIST_HEAD(&tc6->tx_ts_skb_q); =20 diff --git a/include/linux/oa_tc6.h b/include/linux/oa_tc6.h index 4047c22a366a..a89151267713 100644 --- a/include/linux/oa_tc6.h +++ b/include/linux/oa_tc6.h @@ -47,5 +47,6 @@ void oa_tc6_get_ts_stats(struct oa_tc6 *tc6, struct ethtool_ts_stats *ts_stats); int oa_tc6_hwtstamp_set(struct oa_tc6 *tc6, struct kernel_hwtstamp_config *cfg); +void oa_tc6_set_vend1_mms(struct oa_tc6 *tc6, int mms); void oa_tc6_ptp_unregister(struct oa_tc6 *tc6); #endif /* _LINUX_OA_TC6_H */ --=20 2.43.0 From nobody Mon Jun 8 06:37:54 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8294305676; Sat, 6 Jun 2026 05:42:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260605-s2500-mac-phy-support-v4-8-de0fbc13c6d8@onsemi.com> References: <20260605-s2500-mac-phy-support-v4-0-de0fbc13c6d8@onsemi.com> In-Reply-To: <20260605-s2500-mac-phy-support-v4-0-de0fbc13c6d8@onsemi.com> To: Andrew Lunn , Piergiorgio Beruto , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Parthiban Veerasooran , Selva Rajagopal , Richard Cochran , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Simon Horman , Jonathan Corbet , Shuah Khan Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, Jerry Ray , Selvamani Rajagopal X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780724562; l=1396; i=Selvamani.Rajagopal@onsemi.com; s=20260531; h=from:subject:message-id; bh=Nwz8ph63R7fgKGIZDndf/9epwjHtj0F853lNYFbk53o=; b=EkPoE0N561Rn6mpFwlh2B8OkMCBA4T9JKP5di9atN9IusrrG4l799ud9ZyAEVXZYpc5C9VJS3 +mSc/YXu2pyAT0kjQIiCQ85m8Tqggx1D5x6K486h+gwMsU2u0b79nSm X-Developer-Key: i=Selvamani.Rajagopal@onsemi.com; a=ed25519; pk=5QRdM0HS/LGWWcUZZ9hVfZ+qbPQGZCumcTXOiN7Fyug= X-Endpoint-Received: by B4 Relay for Selvamani.Rajagopal@onsemi.com/20260531 with auth_id=803 X-Original-From: Selvamani Rajagopal Reply-To: Selvamani.Rajagopal@onsemi.com From: Selvamani Rajagopal OA TC6 MAC-PHY appends FCS to the incoming frame. It is removed from the frame before being passed to the stack. Signed-off-by: Selvamani Rajagopal --- drivers/net/ethernet/oa_tc6/oa_tc6.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/oa_tc6/oa_tc6.c b/drivers/net/ethernet/oa= _tc6/oa_tc6.c index 2f9ace655e81..26033373f16f 100644 --- a/drivers/net/ethernet/oa_tc6/oa_tc6.c +++ b/drivers/net/ethernet/oa_tc6/oa_tc6.c @@ -782,12 +782,22 @@ static void oa_tc6_submit_rx_skb(struct oa_tc6 *tc6) { oa_tc6_update_ts_in_rx_skb(tc6); =20 + /* MAC-PHY delivers each frame with its Ethernet FCS attached. + * Strip it before handing over to the stack, unless the user + * has asked to keep it via NETIF_F_RXFCS. Keeping the FCS + * in the frame is harmless for IP traffic, but is parsed as + * a (malformed) suffix TLV by PTP, which makes ptp4l reject + * every message with "bad message" error. + */ + if (!(tc6->netdev->features & NETIF_F_RXFCS) && + tc6->rx_skb->len > ETH_FCS_LEN) + skb_trim(tc6->rx_skb, tc6->rx_skb->len - ETH_FCS_LEN); + tc6->rx_skb->protocol =3D eth_type_trans(tc6->rx_skb, tc6->netdev); tc6->netdev->stats.rx_packets++; tc6->netdev->stats.rx_bytes +=3D tc6->rx_skb->len; =20 netif_rx(tc6->rx_skb); - tc6->rx_skb =3D NULL; } =20 --=20 2.43.0 From nobody Mon Jun 8 06:37:54 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E8BEC309DDF; Sat, 6 Jun 2026 05:42:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780724570; cv=none; b=ArQ/WJGTAcLXVENkP6bVb3oe9aGqvk3KZvuIaNdG2B+XaSaUB2UM5y37M2j4vs5E4f1WpBTpczZxYfGzQm5D6I+rCsYMJQJawPnipQSdSwKn9023t36DwL6DaGfa+tTOeKdFr5SYsz4ruinGt7Gp7oEo5ioJjkDpOttQCQHRj30= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780724570; c=relaxed/simple; bh=VKo/KdBMt3l77WXwQ+vYFe76M/n/dMN4jksF6CUquSM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pO2FEe8FTAtUej+gJtKhBzp/Vi9ZwM44Go8TBgmmS0mm/fjAFutTnaTISRXzlzFNt7Xs3IEj9Iv+ceqSoU3iZkIdM5yGh0cULCrxlp2XAeyqdD0SHjRwnE4MpjYLVcEK3Z7EM0mxkHUmCvdgC+j+bwIl7/Cueom1wex6glzTycI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=EG3OfGT7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="EG3OfGT7" Received: by smtp.kernel.org (Postfix) with ESMTPS id B02D6C2BD00; Sat, 6 Jun 2026 05:42:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1780724569; bh=VKo/KdBMt3l77WXwQ+vYFe76M/n/dMN4jksF6CUquSM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=EG3OfGT7L5GVBx+hOmFT/wh8cM+e8HchWFyB0BfiuwAj1/JXEHGud8quUC+fEOeeM BPgfanvSbpyhvp8PWTsGy+8o5JWdz8FIpw2fuJ8xztpHcpyb2y9s+CmPHOs21NMDj0 09K907wLDLjVQqCIFQqIMmxLUhRr07irkqctdMpHiv5YHduAFJaGtcNx8xGDhikdhi kXiGekZQ5r0gUVzA23MrwDDWu7CPNpLKLslAFbyi6KGYFWCFOSnOtJ78qHa9mdKN9n uHvCpqqP2jjfCWaffLhw3nMdMHHMBCj4jtvtqFE8vV7MPDTKcqmws2jwPlFjY/XzJc R25zjGxn7d+Kw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A92E2CD8C85; Sat, 6 Jun 2026 05:42:49 +0000 (UTC) From: Selvamani Rajagopal via B4 Relay Date: Fri, 05 Jun 2026 22:42:40 -0700 Subject: [PATCH net-next v4 09/16] net: ethernet: oa_tc6: read, write interface with MMS option Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260605-s2500-mac-phy-support-v4-9-de0fbc13c6d8@onsemi.com> References: <20260605-s2500-mac-phy-support-v4-0-de0fbc13c6d8@onsemi.com> In-Reply-To: <20260605-s2500-mac-phy-support-v4-0-de0fbc13c6d8@onsemi.com> To: Andrew Lunn , Piergiorgio Beruto , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Parthiban Veerasooran , Selva Rajagopal , Richard Cochran , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Simon Horman , Jonathan Corbet , Shuah Khan Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, Jerry Ray , Selvamani Rajagopal X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780724562; l=13151; i=Selvamani.Rajagopal@onsemi.com; s=20260531; h=from:subject:message-id; bh=6gf7mflhJ8D0twLwo1deSPFhe13HotYFkXHHYzefZ0o=; b=oSZjfjamdqshA0QzFunE54jeYkKdbPtS7XZDcanl4CKrFswgce2GpAL967Cofo3/6f9SifWpp KVdIiYolTwABTk3QLT0bxZKv+2R9GwWzV15W+zBvSkwLZ0a0TUcbuLX X-Developer-Key: i=Selvamani.Rajagopal@onsemi.com; a=ed25519; pk=5QRdM0HS/LGWWcUZZ9hVfZ+qbPQGZCumcTXOiN7Fyug= X-Endpoint-Received: by B4 Relay for Selvamani.Rajagopal@onsemi.com/20260531 with auth_id=803 X-Original-From: Selvamani Rajagopal Reply-To: Selvamani.Rajagopal@onsemi.com From: Selvamani Rajagopal Vendors are allowed to use any memory map selector that is between 10 and 15. Current read/write API interface expects register address with the value of MMS (memory map selector) embedded in it. This requires vendors to encoding the address whenever the call to read/write register is made. To avoid this extra step, and to bring consistency in usage of the API by different vendors, new APIs have been added to write and read registers with MMS as one of the parameters. Signed-off-by: Selvamani Rajagopal --- drivers/net/ethernet/microchip/lan865x/lan865x.c | 61 +++++++++------ drivers/net/ethernet/oa_tc6/oa_tc6.c | 97 ++++++++++++++++++++= +--- include/linux/oa_tc6.h | 8 ++ 3 files changed, 131 insertions(+), 35 deletions(-) diff --git a/drivers/net/ethernet/microchip/lan865x/lan865x.c b/drivers/net= /ethernet/microchip/lan865x/lan865x.c index 0277d9737369..3b555ee69804 100644 --- a/drivers/net/ethernet/microchip/lan865x/lan865x.c +++ b/drivers/net/ethernet/microchip/lan865x/lan865x.c @@ -13,27 +13,27 @@ #define DRV_NAME "lan8650" =20 /* MAC Network Control Register */ -#define LAN865X_REG_MAC_NET_CTL 0x00010000 +#define LAN865X_REG_MAC_NET_CTL 0x0 #define MAC_NET_CTL_TXEN BIT(3) /* Transmit Enable */ #define MAC_NET_CTL_RXEN BIT(2) /* Receive Enable */ =20 /* MAC Network Configuration Reg */ -#define LAN865X_REG_MAC_NET_CFG 0x00010001 +#define LAN865X_REG_MAC_NET_CFG 0x1 #define MAC_NET_CFG_PROMISCUOUS_MODE BIT(4) #define MAC_NET_CFG_MULTICAST_MODE BIT(6) #define MAC_NET_CFG_UNICAST_MODE BIT(7) =20 /* MAC Hash Register Bottom */ -#define LAN865X_REG_MAC_L_HASH 0x00010020 +#define LAN865X_REG_MAC_L_HASH 0x20 /* MAC Hash Register Top */ -#define LAN865X_REG_MAC_H_HASH 0x00010021 +#define LAN865X_REG_MAC_H_HASH 0x21 /* MAC Specific Addr 1 Bottom Reg */ -#define LAN865X_REG_MAC_L_SADDR1 0x00010022 +#define LAN865X_REG_MAC_L_SADDR1 0x22 /* MAC Specific Addr 1 Top Reg */ -#define LAN865X_REG_MAC_H_SADDR1 0x00010023 +#define LAN865X_REG_MAC_H_SADDR1 0x23 =20 /* MAC TSU Timer Increment Register */ -#define LAN865X_REG_MAC_TSU_TIMER_INCR 0x00010077 +#define LAN865X_REG_MAC_TSU_TIMER_INCR 0x77 #define MAC_TSU_TIMER_INCR_COUNT_NANOSECONDS 0x0028 =20 struct lan865x_priv { @@ -49,7 +49,8 @@ static int lan865x_set_hw_macaddr_low_bytes(struct oa_tc6= *tc6, const u8 *mac) =20 regval =3D (mac[3] << 24) | (mac[2] << 16) | (mac[1] << 8) | mac[0]; =20 - return oa_tc6_write_register(tc6, LAN865X_REG_MAC_L_SADDR1, regval); + return oa_tc6_write_register_mms(tc6, LAN865X_REG_MAC_L_SADDR1, + OA_TC6_PHY_C45_MAC_MMS1, regval); } =20 static int lan865x_set_hw_macaddr(struct lan865x_priv *priv, const u8 *mac) @@ -65,8 +66,8 @@ static int lan865x_set_hw_macaddr(struct lan865x_priv *pr= iv, const u8 *mac) =20 /* Prepare and configure MAC address high bytes */ regval =3D (mac[5] << 8) | mac[4]; - ret =3D oa_tc6_write_register(priv->tc6, LAN865X_REG_MAC_H_SADDR1, - regval); + ret =3D oa_tc6_write_register_mms(priv->tc6, LAN865X_REG_MAC_H_SADDR1, + OA_TC6_PHY_C45_MAC_MMS1, regval); if (!ret) return 0; =20 @@ -146,14 +147,16 @@ static int lan865x_set_specific_multicast_addr(struct= lan865x_priv *priv) } =20 /* Enabling specific multicast addresses */ - ret =3D oa_tc6_write_register(priv->tc6, LAN865X_REG_MAC_H_HASH, hash_hi); + ret =3D oa_tc6_write_register_mms(priv->tc6, LAN865X_REG_MAC_H_HASH, + OA_TC6_PHY_C45_MAC_MMS1, hash_hi); if (ret) { netdev_err(priv->netdev, "Failed to write reg_hashh: %d\n", ret); return ret; } =20 - ret =3D oa_tc6_write_register(priv->tc6, LAN865X_REG_MAC_L_HASH, hash_lo); + ret =3D oa_tc6_write_register_mms(priv->tc6, LAN865X_REG_MAC_L_HASH, + OA_TC6_PHY_C45_MAC_MMS1, hash_lo); if (ret) netdev_err(priv->netdev, "Failed to write reg_hashl: %d\n", ret); @@ -166,16 +169,16 @@ static int lan865x_set_all_multicast_addr(struct lan8= 65x_priv *priv) int ret; =20 /* Enabling all multicast addresses */ - ret =3D oa_tc6_write_register(priv->tc6, LAN865X_REG_MAC_H_HASH, - 0xffffffff); + ret =3D oa_tc6_write_register_mms(priv->tc6, LAN865X_REG_MAC_H_HASH, + OA_TC6_PHY_C45_MAC_MMS1, 0xffffffff); if (ret) { netdev_err(priv->netdev, "Failed to write reg_hashh: %d\n", ret); return ret; } =20 - ret =3D oa_tc6_write_register(priv->tc6, LAN865X_REG_MAC_L_HASH, - 0xffffffff); + ret =3D oa_tc6_write_register_mms(priv->tc6, LAN865X_REG_MAC_L_HASH, + OA_TC6_PHY_C45_MAC_MMS1, 0xffffffff); if (ret) netdev_err(priv->netdev, "Failed to write reg_hashl: %d\n", ret); @@ -187,14 +190,16 @@ static int lan865x_clear_all_multicast_addr(struct la= n865x_priv *priv) { int ret; =20 - ret =3D oa_tc6_write_register(priv->tc6, LAN865X_REG_MAC_H_HASH, 0); + ret =3D oa_tc6_write_register_mms(priv->tc6, LAN865X_REG_MAC_H_HASH, + OA_TC6_PHY_C45_MAC_MMS1, 0); if (ret) { netdev_err(priv->netdev, "Failed to write reg_hashh: %d\n", ret); return ret; } =20 - ret =3D oa_tc6_write_register(priv->tc6, LAN865X_REG_MAC_L_HASH, 0); + ret =3D oa_tc6_write_register_mms(priv->tc6, LAN865X_REG_MAC_L_HASH, + OA_TC6_PHY_C45_MAC_MMS1, 0); if (ret) netdev_err(priv->netdev, "Failed to write reg_hashl: %d\n", ret); @@ -235,7 +240,8 @@ static void lan865x_multicast_work_handler(struct work_= struct *work) if (lan865x_clear_all_multicast_addr(priv)) return; } - ret =3D oa_tc6_write_register(priv->tc6, LAN865X_REG_MAC_NET_CFG, regval); + ret =3D oa_tc6_write_register_mms(priv->tc6, LAN865X_REG_MAC_NET_CFG, + OA_TC6_PHY_C45_MAC_MMS1, regval); if (ret) netdev_err(priv->netdev, "Failed to enable promiscuous/multicast/normal = mode: %d\n", ret); @@ -260,12 +266,14 @@ static int lan865x_hw_disable(struct lan865x_priv *pr= iv) { u32 regval; =20 - if (oa_tc6_read_register(priv->tc6, LAN865X_REG_MAC_NET_CTL, ®val)) + if (oa_tc6_read_register_mms(priv->tc6, LAN865X_REG_MAC_NET_CTL, + OA_TC6_PHY_C45_MAC_MMS1, ®val)) return -ENODEV; =20 regval &=3D ~(MAC_NET_CTL_TXEN | MAC_NET_CTL_RXEN); =20 - if (oa_tc6_write_register(priv->tc6, LAN865X_REG_MAC_NET_CTL, regval)) + if (oa_tc6_write_register_mms(priv->tc6, LAN865X_REG_MAC_NET_CTL, + OA_TC6_PHY_C45_MAC_MMS1, regval)) return -ENODEV; =20 return 0; @@ -291,12 +299,14 @@ static int lan865x_hw_enable(struct lan865x_priv *pri= v) { u32 regval; =20 - if (oa_tc6_read_register(priv->tc6, LAN865X_REG_MAC_NET_CTL, ®val)) + if (oa_tc6_read_register_mms(priv->tc6, LAN865X_REG_MAC_NET_CTL, + OA_TC6_PHY_C45_MAC_MMS1, ®val)) return -ENODEV; =20 regval |=3D MAC_NET_CTL_TXEN | MAC_NET_CTL_RXEN; =20 - if (oa_tc6_write_register(priv->tc6, LAN865X_REG_MAC_NET_CTL, regval)) + if (oa_tc6_write_register_mms(priv->tc6, LAN865X_REG_MAC_NET_CTL, + OA_TC6_PHY_C45_MAC_MMS1, regval)) return -ENODEV; =20 return 0; @@ -359,8 +369,9 @@ static int lan865x_probe(struct spi_device *spi) * stamping at the end of the Start of Frame Delimiter (SFD) and set the * Timer Increment reg to 40 ns to be used as a 25 MHz internal clock. */ - ret =3D oa_tc6_write_register(priv->tc6, LAN865X_REG_MAC_TSU_TIMER_INCR, - MAC_TSU_TIMER_INCR_COUNT_NANOSECONDS); + ret =3D oa_tc6_write_register_mms(priv->tc6, LAN865X_REG_MAC_TSU_TIMER_IN= CR, + OA_TC6_PHY_C45_MAC_MMS1, + MAC_TSU_TIMER_INCR_COUNT_NANOSECONDS); if (ret) { dev_err(&spi->dev, "Failed to config TSU Timer Incr reg: %d\n", ret); diff --git a/drivers/net/ethernet/oa_tc6/oa_tc6.c b/drivers/net/ethernet/oa= _tc6/oa_tc6.c index 26033373f16f..a7d8c9bb1f28 100644 --- a/drivers/net/ethernet/oa_tc6/oa_tc6.c +++ b/drivers/net/ethernet/oa_tc6/oa_tc6.c @@ -377,6 +377,83 @@ int oa_tc6_read_register(struct oa_tc6 *tc6, u32 addre= ss, u32 *value) } EXPORT_SYMBOL_GPL(oa_tc6_read_register); =20 +/** + * oa_tc6_read_registers_mms - function for reading multiple consecutive + * registers for the given address, memory map selector pair. + * @tc6: oa_tc6 struct. + * @address: address of the first register to be read in the MAC-PHY. + * @mms: Memory map selector for the registers to be read. + * @value: values to be read from the starting register address @address. + * @length: number of consecutive registers to be read from @address. + * + * Return: 0 on success otherwise failed. + */ +int oa_tc6_read_registers_mms(struct oa_tc6 *tc6, u16 address, u16 mms, + u32 value[], u8 length) +{ + u32 mms_addr =3D (u32)mms << 16 | (u32)address; + + return oa_tc6_read_registers(tc6, mms_addr, value, length); +} +EXPORT_SYMBOL_GPL(oa_tc6_read_registers_mms); + +/** + * oa_tc6_read_register_mms - function for reading a MAC-PHY register + * for the given address, memory map selector pair. + * @tc6: oa_tc6 struct. + * @address: register address of the MAC-PHY to be read. + * @mms: Memory Map Selector for the given address + * @value: value read from the @address register address of the MAC-PHY. + * + * Return: 0 on success otherwise failed. + */ +int oa_tc6_read_register_mms(struct oa_tc6 *tc6, u16 address, u16 mms, + u32 *value) +{ + return oa_tc6_read_registers_mms(tc6, address, mms, value, 1); +} +EXPORT_SYMBOL_GPL(oa_tc6_read_register_mms); + +/** + * oa_tc6_write_registers_mms - function for writing multiple consecutive + * registers for the given address, memory map selector pair. + * @tc6: oa_tc6 struct. + * @address: address of the first register to be written in the MAC-PHY. + * @mms: memory map Selector for the given register. + * @value: values to be written from the starting register address @addres= s. + * @length: number of consecutive registers to be written from @address. + * + * Maximum of 128 consecutive registers can be written starting at @addres= s. + * + * Return: 0 on success otherwise failed. + */ +int oa_tc6_write_registers_mms(struct oa_tc6 *tc6, u16 address, u16 mms, + u32 value[], u8 length) +{ + u32 mms_addr =3D (u32)mms << 16 | (u32)address; + + return oa_tc6_write_registers(tc6, mms_addr, value, length); +} +EXPORT_SYMBOL_GPL(oa_tc6_write_registers_mms); + +/** + * oa_tc6_write_register_mms - function for writing a MAC-PHY register + * associated with the given memory map selector. + * @tc6: oa_tc6 struct. + * @address: register address of the MAC-PHY to be written. + * @mms: memory map selector for the given register. + * @value: value to be written in the @address register address of + * the MAC-PHY. + * + * Return: 0 on success otherwise failed. + */ +int oa_tc6_write_register_mms(struct oa_tc6 *tc6, u16 address, u16 mms, + u32 value) +{ + return oa_tc6_write_registers_mms(tc6, address, mms, &value, 1); +} +EXPORT_SYMBOL_GPL(oa_tc6_write_register_mms); + /** * oa_tc6_write_registers - function for writing multiple consecutive regi= sters. * @tc6: oa_tc6 struct. @@ -490,14 +567,14 @@ static int oa_tc6_mdiobus_read_c45(struct mii_bus *bu= s, int addr, int devnum, int regnum) { struct oa_tc6 *tc6 =3D bus->priv; + int mms, ret; u32 regval; - int ret; =20 - ret =3D oa_tc6_get_phy_c45_mms(tc6, devnum); - if (ret < 0) - return ret; + mms =3D oa_tc6_get_phy_c45_mms(tc6, devnum); + if (mms < 0) + return mms; =20 - ret =3D oa_tc6_read_register(tc6, (ret << 16) | regnum, ®val); + ret =3D oa_tc6_read_register_mms(tc6, (u16)regnum, (u16)mms, ®val); if (ret) return ret; =20 @@ -508,13 +585,13 @@ static int oa_tc6_mdiobus_write_c45(struct mii_bus *b= us, int addr, int devnum, int regnum, u16 val) { struct oa_tc6 *tc6 =3D bus->priv; - int ret; + int mms; =20 - ret =3D oa_tc6_get_phy_c45_mms(tc6, devnum); - if (ret < 0) - return ret; + mms =3D oa_tc6_get_phy_c45_mms(tc6, devnum); + if (mms < 0) + return mms; =20 - return oa_tc6_write_register(tc6, (ret << 16) | regnum, val); + return oa_tc6_write_register_mms(tc6, (u16)regnum, (u16)mms, val); } =20 static int oa_tc6_mdiobus_register(struct oa_tc6 *tc6) diff --git a/include/linux/oa_tc6.h b/include/linux/oa_tc6.h index a89151267713..3d50971f0f5b 100644 --- a/include/linux/oa_tc6.h +++ b/include/linux/oa_tc6.h @@ -37,6 +37,14 @@ int oa_tc6_read_registers(struct oa_tc6 *tc6, u32 addres= s, u32 value[], u8 length); netdev_tx_t oa_tc6_start_xmit(struct oa_tc6 *tc6, struct sk_buff *skb); int oa_tc6_zero_align_receive_frame_enable(struct oa_tc6 *tc6); +int oa_tc6_write_registers_mms(struct oa_tc6 *tc6, u16 address, u16 mms, + u32 value[], u8 length); +int oa_tc6_write_register_mms(struct oa_tc6 *tc6, u16 address, u16 mms, + u32 value); +int oa_tc6_read_registers_mms(struct oa_tc6 *tc6, u16 address, u16 mms, + u32 value[], u8 length); +int oa_tc6_read_register_mms(struct oa_tc6 *tc6, u16 address, u16 mms, + u32 *value); int oa_tc6_ptp_register(struct oa_tc6 *tc6, struct ptp_clock_info *info); int oa_tc6_ioctl(struct oa_tc6 *tc6, struct ifreq *rq, int cmd); int oa_tc6_get_ts_info(struct oa_tc6 *tc6, --=20 2.43.0 From nobody Mon Jun 8 06:37:54 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E98FC309EEC; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dPCbdQJ9" Received: by smtp.kernel.org (Postfix) with ESMTPS id C2F73C2BCC4; Sat, 6 Jun 2026 05:42:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1780724569; bh=QD/tMI+3HqbXuI+rJJGENkSbFca+vBGc5G87cC7Xw1M=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=dPCbdQJ95r/5VeuZmiKDz8lzo5wWhaYcCHH/trBKizueNx4Mr1wkCyAtBxB6yqrqT bZ772j/XnY/Wmv+lkLqsrUvdCTKKqxhdmBls1m6pBNkBn3VBHNv5TfzlFolBBAtWyK 3D6zuFYWEGAyReZjWHw9HjvEJAWvZZy9NGEuJNZ+9JALt6piBbbol/ieZQiuOSNZZB YBJHIJ1BfZ8ha+NIvi4GJUDiug3pKdkeSXN8xfZeMamFGZqWMeTJ4fgqYix8McJMDC N4AkIK8L9RGLcHhlO+SbO/uVWppSToBJEPdKIe6vqSppR855Y9pAHumeUmXaKuOYU/ aLpOtUaV73gbQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9D7FCD8C8E; Sat, 6 Jun 2026 05:42:49 +0000 (UTC) From: Selvamani Rajagopal via B4 Relay Date: Fri, 05 Jun 2026 22:42:41 -0700 Subject: [PATCH net-next v4 10/16] net: phy: ncn26000: Support for onsemi's S2500 internal phy Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260605-s2500-mac-phy-support-v4-10-de0fbc13c6d8@onsemi.com> References: <20260605-s2500-mac-phy-support-v4-0-de0fbc13c6d8@onsemi.com> In-Reply-To: <20260605-s2500-mac-phy-support-v4-0-de0fbc13c6d8@onsemi.com> To: Andrew Lunn , Piergiorgio Beruto , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Parthiban Veerasooran , Selva Rajagopal , Richard Cochran , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Simon Horman , Jonathan Corbet , Shuah Khan Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, Jerry Ray , Selvamani Rajagopal X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780724562; l=4175; i=Selvamani.Rajagopal@onsemi.com; s=20260531; h=from:subject:message-id; bh=cRnAyVwtbp6ha34dqi6BLuh05VYIe+6qSsKj5F4v594=; b=9pcj2s+nevdqnX8fMX3H39qoe3+BHUqO8Q2u8KjotAnPpi4Nb3ANCvuu9gRkLP7Puz3Z7xyxY /i1nSngu+DkDXLZUOuKwqc3wL78rZDOFT/wo8MG7LDQqnwAp7fKr3n0 X-Developer-Key: i=Selvamani.Rajagopal@onsemi.com; a=ed25519; pk=5QRdM0HS/LGWWcUZZ9hVfZ+qbPQGZCumcTXOiN7Fyug= X-Endpoint-Received: by B4 Relay for Selvamani.Rajagopal@onsemi.com/20260531 with auth_id=803 X-Original-From: Selvamani Rajagopal Reply-To: Selvamani.Rajagopal@onsemi.com From: Selvamani Rajagopal Adding support for internal PHY of the integrated media access controller S2500. PLCA tx opportunity timer's default value is correct in this device, compared to NCN26000. Signed-off-by: Selvamani Rajagopal --- MAINTAINERS | 3 ++- drivers/net/phy/ncn26000.c | 38 +++++++++++++++++++++++++++++++++----- 2 files changed, 35 insertions(+), 6 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 63b71197d385..98334235c924 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19971,7 +19971,8 @@ S: Maintained F: arch/mips/boot/dts/ralink/omega2p.dts =20 ONSEMI ETHERNET PHY DRIVERS -M: Piergiorgio Beruto +M: Piergiorgio Beruto +M: Selva Rajagopal L: netdev@vger.kernel.org S: Supported W: http://www.onsemi.com diff --git a/drivers/net/phy/ncn26000.c b/drivers/net/phy/ncn26000.c index cabdd83c614f..2c8601c3f94a 100644 --- a/drivers/net/phy/ncn26000.c +++ b/drivers/net/phy/ncn26000.c @@ -2,7 +2,7 @@ /* * Driver for the onsemi 10BASE-T1S NCN26000 PHYs family. * - * Copyright 2022 onsemi + * Copyright 2026 onsemi */ #include #include @@ -14,6 +14,7 @@ =20 #include "mdio-open-alliance.h" =20 +#define PHY_ID_S2500 0x180FF411 #define PHY_ID_NCN26000 0x180FF5A1 =20 #define NCN26000_REG_IRQ_CTL 16 @@ -37,13 +38,18 @@ =20 static int ncn26000_config_init(struct phy_device *phydev) { + int ret =3D 0; + /* HW bug workaround: the default value of the PLCA TO_TIMER should be * 32, where the current version of NCN26000 reports 24. This will be * fixed in future PHY versions. For the time being, we force the * correct default here. */ - return phy_write_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_TOTMR, - TO_TMR_DEFAULT); + if (phy_id_compare_model(phydev->drv->phy_id, PHY_ID_NCN26000)) + ret =3D phy_write_mmd(phydev, MDIO_MMD_VEND2, + MDIO_OATC14_PLCA_TOTMR, + TO_TMR_DEFAULT); + return ret; } =20 static int ncn26000_config_aneg(struct phy_device *phydev) @@ -117,8 +123,8 @@ static irqreturn_t ncn26000_handle_interrupt(struct phy= _device *phydev) =20 static int ncn26000_config_intr(struct phy_device *phydev) { - int ret; u16 irqe; + int ret; =20 if (phydev->interrupts =3D=3D PHY_INTERRUPT_ENABLED) { // acknowledge IRQs @@ -141,6 +147,26 @@ static int ncn26000_config_intr(struct phy_device *phy= dev) } =20 static struct phy_driver ncn26000_driver[] =3D { + { + PHY_ID_MATCH_MODEL(PHY_ID_S2500), + .name =3D "S2500", + .features =3D PHY_BASIC_T1S_P2MP_FEATURES, + .config_init =3D ncn26000_config_init, + .config_intr =3D ncn26000_config_intr, + .config_aneg =3D ncn26000_config_aneg, + .read_status =3D ncn26000_read_status, + .handle_interrupt =3D ncn26000_handle_interrupt, + .set_plca_cfg =3D genphy_c45_plca_set_cfg, + .get_plca_cfg =3D genphy_c45_plca_get_cfg, + .get_plca_status =3D genphy_c45_plca_get_status, + .soft_reset =3D genphy_soft_reset, + .get_sqi =3D genphy_c45_oatc14_get_sqi, + .get_sqi_max =3D genphy_c45_oatc14_get_sqi_max, + .read_mmd =3D genphy_phy_read_mmd, + .write_mmd =3D genphy_phy_write_mmd, + .cable_test_get_status =3D genphy_c45_oatc14_cable_test_get_status, + .cable_test_start =3D genphy_c45_oatc14_cable_test_start, + }, { PHY_ID_MATCH_MODEL(PHY_ID_NCN26000), .name =3D "NCN26000", @@ -161,11 +187,13 @@ module_phy_driver(ncn26000_driver); =20 static const struct mdio_device_id __maybe_unused ncn26000_tbl[] =3D { { PHY_ID_MATCH_MODEL(PHY_ID_NCN26000) }, + { PHY_ID_MATCH_MODEL(PHY_ID_S2500) }, { } }; =20 MODULE_DEVICE_TABLE(mdio, ncn26000_tbl); =20 -MODULE_AUTHOR("Piergiorgio Beruto"); +MODULE_AUTHOR("Piergiorgio Beruto "); +MODULE_AUTHOR("Selva Rajagopal "); MODULE_DESCRIPTION("onsemi 10BASE-T1S PHY driver"); MODULE_LICENSE("Dual BSD/GPL"); --=20 2.43.0 From nobody Mon Jun 8 06:37:54 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0032230BB9B; Sat, 6 Jun 2026 05:42:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780724570; cv=none; b=nlmmkZw9HB8wACjy6f7YRRt6LvCnVm8M+YRjCdHer+w99nPnBaxfIJ+tPbBbu9Zoad1FdNIlF6NIjtDV5zpZ+1Rrg5CeEOnFtXND+bH7pafoxdB1rN9/U8GhyAfL3+Yqi24UsKx+ALwE4cqQLju4idHoEJyb9by424Zy2e2JhG8= ARC-Message-Signature: i=1; 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b=YvIZ7rjRLtoqFBDpqTWWohcdWJgdkwOLjwBXFWuoiHz/uPMCUpwMwaax+bQNfkb8S dYyKJjaGT8/q2cHaE9eMdFn/3k4x4KmrdTbSsaXjyeKKJWWE0Eeop8NFl/Z6XaFJDR 2FcRdXMu1Lnz/s6vPGJ4/li74WLgWFLiI1Damc57tRlBDS2WeyokWHz5N0bR1bt8nE 8W17R0h/s/cFOsuMCNVlgBuVito3wJdsBiggd8M+AlUBC3deX5OgAcyl6uVT5y8N6d 08ZJUxCKDgk4B/3022cmajdx68idaXnvVf2JQsNqaew/hv2p/n7JjaxRpzX0z3h1Gj njbn/qd+HT4cw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD75DCD8C85; Sat, 6 Jun 2026 05:42:49 +0000 (UTC) From: Selvamani Rajagopal via B4 Relay Date: Fri, 05 Jun 2026 22:42:42 -0700 Subject: [PATCH net-next v4 11/16] net: phy: ncn26000: Enable enhanced noise immunity Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260605-s2500-mac-phy-support-v4-11-de0fbc13c6d8@onsemi.com> References: <20260605-s2500-mac-phy-support-v4-0-de0fbc13c6d8@onsemi.com> In-Reply-To: <20260605-s2500-mac-phy-support-v4-0-de0fbc13c6d8@onsemi.com> To: Andrew Lunn , Piergiorgio Beruto , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Parthiban Veerasooran , Selva Rajagopal , Richard Cochran , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Simon Horman , Jonathan Corbet , Shuah Khan Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, Jerry Ray , Selvamani Rajagopal X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780724562; l=2396; i=Selvamani.Rajagopal@onsemi.com; s=20260531; h=from:subject:message-id; bh=0U1RzAHZSWzomZ4iVBpV8zjyjt3Pi1KvW4neKMCTNpc=; b=1oliSqsYP6VMqMDJ7KLkRxrP2fjGPoHIw/YJ2XwkDPeNajF3W1VPdq/B6Pv6tEQKzPh/YuQuU S1VEGIDbQY7DhqC52elqhmDqEIkjo91fRi/Muo3v2q9jbMqJ7iMplSZ X-Developer-Key: i=Selvamani.Rajagopal@onsemi.com; a=ed25519; pk=5QRdM0HS/LGWWcUZZ9hVfZ+qbPQGZCumcTXOiN7Fyug= X-Endpoint-Received: by B4 Relay for Selvamani.Rajagopal@onsemi.com/20260531 with auth_id=803 X-Original-From: Selvamani Rajagopal Reply-To: Selvamani.Rajagopal@onsemi.com From: Selvamani Rajagopal By setting ENI bit, noise immunity is improved and it is specifically meant for PLCA enabled nodes. Signed-off-by: Selvamani Rajagopal --- drivers/net/phy/ncn26000.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/drivers/net/phy/ncn26000.c b/drivers/net/phy/ncn26000.c index 2c8601c3f94a..c3a34b2c524d 100644 --- a/drivers/net/phy/ncn26000.c +++ b/drivers/net/phy/ncn26000.c @@ -36,6 +36,10 @@ =20 #define TO_TMR_DEFAULT 32 =20 +#define NCN26000_REG_PHYCFG1 0x8001 +#define NCN26000_PHYCFG1_ENI BIT(7) +#define NCN26000_PHYCFG1_ENI_MASK BIT(7) + static int ncn26000_config_init(struct phy_device *phydev) { int ret =3D 0; @@ -106,6 +110,24 @@ static int ncn26000_read_status(struct phy_device *phy= dev) return 0; } =20 +/* Intercept PLCA enable/disable request to + * set the proprietary, ENI mode accordingly + */ +static int ncn26000_c45_plca_set_cfg(struct phy_device *phydev, + const struct phy_plca_cfg *plca_cfg) +{ + int ret =3D genphy_c45_plca_set_cfg(phydev, plca_cfg); + u16 eni_cfg =3D 0; + + if (ret || plca_cfg->enabled < 0) + return ret; + + eni_cfg =3D (plca_cfg->enabled) ? NCN26000_PHYCFG1_ENI : 0; + return phy_modify_mmd(phydev, MDIO_MMD_VEND2, + NCN26000_REG_PHYCFG1, + NCN26000_PHYCFG1_ENI_MASK, eni_cfg); +} + static irqreturn_t ncn26000_handle_interrupt(struct phy_device *phydev) { int ret; @@ -156,7 +178,7 @@ static struct phy_driver ncn26000_driver[] =3D { .config_aneg =3D ncn26000_config_aneg, .read_status =3D ncn26000_read_status, .handle_interrupt =3D ncn26000_handle_interrupt, - .set_plca_cfg =3D genphy_c45_plca_set_cfg, + .set_plca_cfg =3D ncn26000_c45_plca_set_cfg, .get_plca_cfg =3D genphy_c45_plca_get_cfg, .get_plca_status =3D genphy_c45_plca_get_status, .soft_reset =3D genphy_soft_reset, @@ -177,7 +199,7 @@ static struct phy_driver ncn26000_driver[] =3D { .read_status =3D ncn26000_read_status, .handle_interrupt =3D ncn26000_handle_interrupt, .get_plca_cfg =3D genphy_c45_plca_get_cfg, - .set_plca_cfg =3D genphy_c45_plca_set_cfg, + .set_plca_cfg =3D ncn26000_c45_plca_set_cfg, .get_plca_status =3D genphy_c45_plca_get_status, .soft_reset =3D genphy_soft_reset, }, --=20 2.43.0 From nobody Mon Jun 8 06:37:54 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1079830C15E; Sat, 6 Jun 2026 05:42:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780724570; cv=none; b=aKny8QFi4JejKJGrlUW1pOG7jCh0sap9HkD3HH/beT9rRdljYzjdv4TabzIa3QVRdDWlaCoxcnGSVOAdOsg8mKhtVmynYdlOKmHi8grHwnj3lB/+CBm1U1MKWqBxDUWHIpGB4cnDCNhR4i1FmCD1DCGno6HaLvxZkMM4mMoTiJA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780724570; c=relaxed/simple; bh=a8UyF6IF3XwRksQoSWDs0MTcbLNGhYf33YAHeVV8QLQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MwFWSddulJQ8X352SqSsQUdBxtaVtE+pNI0cppZ4rxw7xtMLQxAu/193AZEDkpVVA69k5xTc/vqPMdffqNOiU9quwVjGKK4q1uEbN8V9JeW5po7ZdDzXq9HhU6/wRvHnqEQKPU87BUg00/SWkBlQp2JLyGi+7rdJX/GOXFmLqmk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=gIaqNitm; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="gIaqNitm" Received: by smtp.kernel.org (Postfix) with ESMTPS id E39A2C2BCF5; Sat, 6 Jun 2026 05:42:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1780724569; bh=a8UyF6IF3XwRksQoSWDs0MTcbLNGhYf33YAHeVV8QLQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=gIaqNitmAu/yY/HHnyueIY41D26oNkToLddYW06a7Ybg2Hqa7ii8BLv77LvXMYiXR cpKbgCoR44UbrV5clbMIW20kS5w6O+WGdDlwwm0N+9NXBPtc7A7HvLm8SmO50gGU72 RirDj4HIIEP7wFXGrNZnZMX2qG3+QUvDIdxEjqcbEhLlvuZF+c35joM3/Hb1dsM6We XlkTonB7O1LPHOg2FguBWGcNevBJjjM4G+aQiYzN08bU+ntXBzS6KxwPCMIosgQNcb RDTi16OGoWIiVPTPA7dLhnx8pWvdcCEl2TRkOnnihy6fddQDKvjSGcYz1hEYvTYWTZ 5mQeh8z627c+g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE4BDCD8C90; Sat, 6 Jun 2026 05:42:49 +0000 (UTC) From: Selvamani Rajagopal via B4 Relay Date: Fri, 05 Jun 2026 22:42:43 -0700 Subject: [PATCH net-next v4 12/16] net: phy: ncn26000: Support for loopback support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260605-s2500-mac-phy-support-v4-12-de0fbc13c6d8@onsemi.com> References: <20260605-s2500-mac-phy-support-v4-0-de0fbc13c6d8@onsemi.com> In-Reply-To: <20260605-s2500-mac-phy-support-v4-0-de0fbc13c6d8@onsemi.com> To: Andrew Lunn , Piergiorgio Beruto , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Parthiban Veerasooran , Selva Rajagopal , Richard Cochran , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Simon Horman , Jonathan Corbet , Shuah Khan Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, Jerry Ray , Selvamani Rajagopal X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780724562; l=886; i=Selvamani.Rajagopal@onsemi.com; s=20260531; h=from:subject:message-id; bh=6j9FApr9mdiEL4bEIZDwlR2AIaPGGvliDOcnuk/FhSQ=; b=rtNvJ5PfVSv8jTsb9GV2cu+Qtb2mF1ILOlEL2pfqnbKdFaLAM5m+RqUSMgxp+/Aqt5siWIYbN ZYWQn6EqCfCDxYxKiuYpyxiVJIkoLaG2mpwpZJbXu3DHRhpEFx8L+y4 X-Developer-Key: i=Selvamani.Rajagopal@onsemi.com; a=ed25519; pk=5QRdM0HS/LGWWcUZZ9hVfZ+qbPQGZCumcTXOiN7Fyug= X-Endpoint-Received: by B4 Relay for Selvamani.Rajagopal@onsemi.com/20260531 with auth_id=803 X-Original-From: Selvamani Rajagopal Reply-To: Selvamani.Rajagopal@onsemi.com From: Selvamani Rajagopal Adding loopback support for S2500 internal PHY to help running loopback test through ethtool Signed-off-by: Selvamani Rajagopal --- drivers/net/phy/ncn26000.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/phy/ncn26000.c b/drivers/net/phy/ncn26000.c index c3a34b2c524d..afafa81dc22b 100644 --- a/drivers/net/phy/ncn26000.c +++ b/drivers/net/phy/ncn26000.c @@ -178,6 +178,7 @@ static struct phy_driver ncn26000_driver[] =3D { .config_aneg =3D ncn26000_config_aneg, .read_status =3D ncn26000_read_status, .handle_interrupt =3D ncn26000_handle_interrupt, + .set_loopback =3D genphy_loopback_fixed_speed, .set_plca_cfg =3D ncn26000_c45_plca_set_cfg, .get_plca_cfg =3D genphy_c45_plca_get_cfg, .get_plca_status =3D genphy_c45_plca_get_status, --=20 2.43.0 From nobody Mon Jun 8 06:37:54 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2482430C353; Sat, 6 Jun 2026 05:42:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780724570; cv=none; b=JhT0fNt3RjtA+KsYhC4mV1kHpOGrtutLIMN/21OTC+UrcPoF0QtfEhOMcZy5tmxjAi0n6vkHaD2Xi1a+sObHsOJr7CRaJvb+/gpm4mPj2W9IalfI6D+kzX2y4XLtlKuxYxHD6TELGdw9JkmtbBPkQjPWacLtns5byZZqfmZQWds= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780724570; c=relaxed/simple; bh=+606bJSoTQP20bBtsbKVVaoQxsFK+qkfIB3L4zFiMsg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=jEN4mn/pF1CxqPS2hzUkoNXVz093NPagtUmN2w013+55QcmIXr9S/h38TROkP/v9KcItOGpSCkWsPdBDCAdAyfvyWk8QC5rgxShTkWNLY+BIs0FiH3qigL+meeVuyKlR7VPr1l0DrgXaByAnEd/jOEK6MPWB50e3sYI0IbURjI4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=J+HhCyx9; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="J+HhCyx9" Received: by smtp.kernel.org (Postfix) with ESMTPS id 06940C2BCC7; Sat, 6 Jun 2026 05:42:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1780724570; bh=+606bJSoTQP20bBtsbKVVaoQxsFK+qkfIB3L4zFiMsg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=J+HhCyx9w/x4MUtfR50IjHWzP86d3iYhhwkCoM/S3KA8RrGdl6oBN4AWFmF7psIUP XIzEJEWXyfSJ07x3zACFIFV71jqEgWk+yTCQvk2wOmFcqzeFFtgVD1vENA24nP/rer jRFphcja2J9uCSMFvsqK5XoTjuQ/LzyPPycSMGJwjp3zBgEKyMudjufyvbTxLdA40h 9JK3GqkTw412mSl0GKubU27RH23VV6oEZt+MH75wXibkyEU1jPxKH/pmeiNWyunRAY wuDEP3BCr3p9TJ2P9siSxhjYj7IfFbvmg79cl7UnHYUpZqDjciMl5nOAUbR77Y8i5j 7r6t+Nzkq9rNA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2E1ACD8C8E; Sat, 6 Jun 2026 05:42:49 +0000 (UTC) From: Selvamani Rajagopal via B4 Relay Date: Fri, 05 Jun 2026 22:42:44 -0700 Subject: [PATCH net-next v4 13/16] onsemi: s2500: Add driver support for TS2500 MAC-PHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260605-s2500-mac-phy-support-v4-13-de0fbc13c6d8@onsemi.com> References: <20260605-s2500-mac-phy-support-v4-0-de0fbc13c6d8@onsemi.com> In-Reply-To: <20260605-s2500-mac-phy-support-v4-0-de0fbc13c6d8@onsemi.com> To: Andrew Lunn , Piergiorgio Beruto , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Parthiban Veerasooran , Selva Rajagopal , Richard Cochran , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Simon Horman , Jonathan Corbet , Shuah Khan Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, Jerry Ray , Selvamani Rajagopal X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780724562; l=46929; i=Selvamani.Rajagopal@onsemi.com; s=20260531; h=from:subject:message-id; bh=hmJO+w/YOe5/UC8FeKavBGJe9oJaaSpucAf74pB7Fag=; b=aAbqL++2xRd3/RO3nS8M83C1dIilSlJDYYT1+Dx9wvtStw5EloZDf4EWI55zCDYSvvFtfpqoa vtHgZRGJ+s6CQT7z3Pc8EkPtaMBBwvVxuxs+sQbSN+tKx1fpBgG5Fej X-Developer-Key: i=Selvamani.Rajagopal@onsemi.com; a=ed25519; pk=5QRdM0HS/LGWWcUZZ9hVfZ+qbPQGZCumcTXOiN7Fyug= X-Endpoint-Received: by B4 Relay for Selvamani.Rajagopal@onsemi.com/20260531 with auth_id=803 X-Original-From: Selvamani Rajagopal Reply-To: Selvamani.Rajagopal@onsemi.com From: Selvamani Rajagopal Support for onsemi's S2500, 802.3 cg compliant Ethernet transceiver with integrated MAC-PHY. Works with Open Alliance TC6 framework. adjtime callback is implemented using adjfine. If time delta is too big, bigger than 1 second, using adjtime would take long to reduce the delta. In those cases, settime callback is used to reduce the delta. Once delta becomes less than a second, it uses adjfine to reduce the drift further. Signed-off-by: Selvamani Rajagopal --- MAINTAINERS | 7 + drivers/net/ethernet/oa_tc6/oa_tc6_std_def.h | 2 +- drivers/net/ethernet/onsemi/Kconfig | 21 + drivers/net/ethernet/onsemi/Makefile | 7 + drivers/net/ethernet/onsemi/s2500/Kconfig | 21 + drivers/net/ethernet/onsemi/s2500/Makefile | 7 + drivers/net/ethernet/onsemi/s2500/s2500_ethtool.c | 347 ++++++++++++ drivers/net/ethernet/onsemi/s2500/s2500_hw_def.h | 225 ++++++++ drivers/net/ethernet/onsemi/s2500/s2500_main.c | 632 ++++++++++++++++++= ++++ drivers/net/ethernet/onsemi/s2500/s2500_ptp.c | 233 ++++++++ 10 files changed, 1501 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 98334235c924..1a8ad30e0017 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19978,6 +19978,13 @@ S: Supported W: http://www.onsemi.com F: drivers/net/phy/ncn* =20 +ONSEMI S2500 10BASE-T1S MACPHY ETHERNET DRIVER +M: Selva Rajagopal +L: netdev@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/net/onnn,s2500.yaml +F: drivers/net/ethernet/onsemi/s2500/s2500_* + OP-TEE DRIVER M: Jens Wiklander L: op-tee@lists.trustedfirmware.org (moderated for non-subscribers) diff --git a/drivers/net/ethernet/oa_tc6/oa_tc6_std_def.h b/drivers/net/eth= ernet/oa_tc6/oa_tc6_std_def.h index 3a12b3228f30..d7780df07543 100644 --- a/drivers/net/ethernet/oa_tc6/oa_tc6_std_def.h +++ b/drivers/net/ethernet/oa_tc6/oa_tc6_std_def.h @@ -64,7 +64,7 @@ #define OA_TC6_PHY_STD_REG_ADDR_MASK 0x1F =20 /* Tx timestamp capture register A (high) */ -#define OA_TC6_REG_TTSCA_HIGH (0x1010) +#define OA_TC6_REG_TTSCA_HIGH (0x10) =20 /* Control command header */ #define OA_TC6_CTRL_HEADER_DATA_NOT_CTRL BIT(31) diff --git a/drivers/net/ethernet/onsemi/Kconfig b/drivers/net/ethernet/ons= emi/Kconfig new file mode 100644 index 000000000000..8dd3a3f074a2 --- /dev/null +++ b/drivers/net/ethernet/onsemi/Kconfig @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# onsemi network device configuration +# + +config NET_VENDOR_ONSEMI + bool "onsemi network devices" + help + If you have a network card belonging to this class, say Y. + + Note that the answer to this question doesn't directly affect the + kernel: saying N will just cause the configurator to skip all + the questions about onsemi ethernet devices. If you say Y, you + will be asked for your specific card in the following questions. + +if NET_VENDOR_ONSEMI + +source "drivers/net/ethernet/onsemi/s2500/Kconfig" + +endif # NET_VENDOR_ONSEMI + diff --git a/drivers/net/ethernet/onsemi/Makefile b/drivers/net/ethernet/on= semi/Makefile new file mode 100644 index 000000000000..f3d4eb154313 --- /dev/null +++ b/drivers/net/ethernet/onsemi/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Makefile for the onsemi network device drivers. +# + +obj-$(CONFIG_S2500_MACPHY) +=3D s2500/ + diff --git a/drivers/net/ethernet/onsemi/s2500/Kconfig b/drivers/net/ethern= et/onsemi/s2500/Kconfig new file mode 100644 index 000000000000..22b0afad7a21 --- /dev/null +++ b/drivers/net/ethernet/onsemi/s2500/Kconfig @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# onsemi S2500 Driver Support +# + +if NET_VENDOR_ONSEMI + +config S2500_MACPHY + tristate "S2500 support" + depends on SPI + select NCN26000_PHY + select OA_TC6 + help + Support for the onsemi TS2500 MACPHY Ethernet chip. + It works under the framework that conform to OPEN Alliance + 10BASE-T1x Serial Interface specification. + + To compile this driver as a module, choose M here. The module wi= ll be + called s2500. + +endif # NET_VENDOR_ONSEMI diff --git a/drivers/net/ethernet/onsemi/s2500/Makefile b/drivers/net/ether= net/onsemi/s2500/Makefile new file mode 100644 index 000000000000..61ec705cdf9f --- /dev/null +++ b/drivers/net/ethernet/onsemi/s2500/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Makefile for the onsemi network device drivers. +# +obj-$(CONFIG_S2500_MACPHY) :=3D s2500.o +s2500-objs :=3D s2500_main.o s2500_ethtool.o s2500_ptp.o + diff --git a/drivers/net/ethernet/onsemi/s2500/s2500_ethtool.c b/drivers/ne= t/ethernet/onsemi/s2500/s2500_ethtool.c new file mode 100644 index 000000000000..85bd8ea50dd8 --- /dev/null +++ b/drivers/net/ethernet/onsemi/s2500/s2500_ethtool.c @@ -0,0 +1,347 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2026 Semiconductor Components Industries, LLC ("onsemi"). + * onsemi's S2500 10BASE-T1S MAC-PHY driver + */ + +#include +#include + +#include "s2500_hw_def.h" + +#define S2500_NUM_REGS 38 +#define S2500_REGDUMP_LEN (sizeof(u32) * (S2500_NUM_REGS * 2)) + +#define S2500_NUM_MAC_STATS 21 +#define S2500_NUM_RMON_STATS 12 + +struct s2500_reg_map { + u16 reg; + u16 mms; +}; + +static const struct s2500_reg_map s2500_reg_map[S2500_NUM_REGS] =3D { + { S2500_REG_VS_ONIPVER, OA_TC6_PHY_C45_VS_PLCA_MMS4 }, + { S2500_REG_VS_TWEAKS1, OA_TC6_PHY_C45_VS_PLCA_MMS4 }, + { S2500_REG_VS_PLCAEXT, OA_TC6_PHY_C45_VS_PLCA_MMS4 }, + { S2500_REG_VS_PMATUNE0, OA_TC6_PHY_C45_VS_PLCA_MMS4 }, + { S2500_REG_VS_PMATUNE1, OA_TC6_PHY_C45_VS_PLCA_MMS4 }, + { S2500_REG_VS_T1SWUPTUNE, OA_TC6_PHY_C45_VS_PLCA_MMS4 }, + { S2500_REG_VS_HDD, OA_TC6_PHY_C45_VS_PLCA_MMS4 }, + { S2500_REG_VS_DCQ_TOID, OA_TC6_PHY_C45_VS_PLCA_MMS4 }, + { S2500_REG_VS_DCQ_SQI, OA_TC6_PHY_C45_VS_PLCA_MMS4 }, + { S2500_REG_VS_DCQ_SQI_PLUS, OA_TC6_PHY_C45_VS_PLCA_MMS4 }, + { S2500_REG_VS_HDD_TUNE1, OA_TC6_PHY_C45_VS_PLCA_MMS4 }, + { S2500_REG_VS_HDD_TUNE2, OA_TC6_PHY_C45_VS_PLCA_MMS4 }, + { S2500_REG_VS_HDD_TUNE3, OA_TC6_PHY_C45_VS_PLCA_MMS4 }, + { S2500_REG_VS_WS_STATUS_0, OA_TC6_PHY_C45_VS_PLCA_MMS4 }, + { S2500_REG_VS_WS_CTRL_0, OA_TC6_PHY_C45_VS_PLCA_MMS4 }, + { S2500_REG_VS_WS_STATUS_1, OA_TC6_PHY_C45_VS_PLCA_MMS4 }, + { S2500_REG_VS_WS_CTRL_1, OA_TC6_PHY_C45_VS_PLCA_MMS4 }, + { S2500_REG_VS_MIIMIRQE, OA_TC6_PHY_C45_VS_MMS12 }, + { S2500_REG_VS_MIIMIRQS, OA_TC6_PHY_C45_VS_MMS12 }, + { S2500_REG_VS_DIOCFG0, OA_TC6_PHY_C45_VS_MMS12 }, + { S2500_REG_VS_CHIPID, OA_TC6_PHY_C45_VS_MMS12 }, + { S2500_REG_VS_TWEAKS2, OA_TC6_PHY_C45_VS_MMS12 }, + { S2500_REG_VS_MACID0, OA_TC6_PHY_C45_VS_MMS12 }, + { S2500_REG_VS_MACID1, OA_TC6_PHY_C45_VS_MMS12 }, + { S2500_REG_VS_NVM_HEALTH, OA_TC6_PHY_C45_VS_MMS12 }, + { S2500_REG_VS_PTP_SEC, OA_TC6_PHY_C45_VS_MMS12 }, + { S2500_REG_VS_PTPNSEC, OA_TC6_PHY_C45_VS_MMS12 }, + { S2500_REG_VS_PTP_SETSEC, OA_TC6_PHY_C45_VS_MMS12 }, + { S2500_REG_VS_SETNSEC, OA_TC6_PHY_C45_VS_MMS12 }, + { S2500_REG_VS_PTP_ADJ, OA_TC6_PHY_C45_VS_MMS12 }, + { S2500_REG_VS_CMPCTL, OA_TC6_PHY_C45_VS_MMS12 }, + { S2500_REG_VS_CMPSEC, OA_TC6_PHY_C45_VS_MMS12 }, + { S2500_REG_VS_CMPNSEC, OA_TC6_PHY_C45_VS_MMS12 }, + { S2500_REG_VS_CMPPER, OA_TC6_PHY_C45_VS_MMS12 }, + { S2500_REG_VS_CAPCTL, OA_TC6_PHY_C45_VS_MMS12 }, + { S2500_REG_VS_CAPSEC, OA_TC6_PHY_C45_VS_MMS12 }, + { S2500_REG_VS_CAPNSEC, OA_TC6_PHY_C45_VS_MMS12 }, + { S2500_REG_VS_BCNCNT, OA_TC6_PHY_C45_VS_MMS12 }, +}; + +enum s2500_stat_idx { + S2500_MSTOCTECTSTX_IDX =3D 0, + S2500_MSTFRAMESTXOK_IDX, + S2500_MSTBCASTTXOK_IDX, + S2500_MSTMCASTTXOK_IDX, + S2500_MSTFRAMESTX64_IDX, + S2500_MSTFRAMESTX65_IDX, + S2500_MSTFRAMESTX128_IDX, + S2500_MSTFRAMESTX256_IDX, + S2500_MSTFRAMESTX512_IDX, + S2500_MSTFRAMESTX1024_IDX, + S2500_MSTTXUNDEFLOW_IDX, + S2500_MSTSINGLECOL_IDX, + S2500_MSTMULTICOL_IDX, + S2500_MSTEXCESSCOL_IDX, + S2500_MSTDEFERREDTX_IDX, + S2500_MSTCRSERR_IDX, + S2500_MSTOCTECTSRX_IDX, + S2500_MSTFRAMESRXOK_IDX, + S2500_MSTBCASTRXOK_IDX, + S2500_MSTMCASTRXOK_IDX, + S2500_MSTFRAMESRX64_IDX, + S2500_MSTFRAMESRX65_IDX, + S2500_MSTFRAMESRX128_IDX, + S2500_MSTFRAMESRX256_IDX, + S2500_MSTFRAMESRX512_IDX, + S2500_MSTFRAMESRX1024_IDX, + S2500_MSTRUNTSERR_IDX, + S2500_MSTRXTOOLONG_IDX, + S2500_MSTFCSERRS_IDX, + S2500_MSTSYMBOLERRS_IDX, + S2500_MSTALIGNERRS_IDX, + S2500_MSTRXOVERFLOW_IDX, + S2500_MSTRXDROPPED_IDX, +}; + +static const char s2500_mac_stat_strings[][ETH_GSTRING_LEN] =3D { + "tx_bytes", + "tx_frames", + "tx_broadcast_frames", + "tx_multicast_frames", + "tx_underflow_errors", + "tx_single_collisions", + "tx_multiple_collisions", + "tx_excessive_collisions", + "tx_deferred_frames", + "tx_carrier_sense_errors", + "rx_bytes", + "rx_frames", + "rx_broadcast_frames", + "rx_multicast_frames", + "rx_runts", + "rx_oversize_frames", + "rx_crc_errors", + "rx_symbol_errors", + "rx_alignment_errors", + "rx_busy_drops", + "rx_mismatch_drops", +}; + +static const u8 s2500_mac_stat_map[S2500_NUM_MAC_STATS] =3D { + S2500_MSTOCTECTSTX_IDX, + S2500_MSTFRAMESTXOK_IDX, + S2500_MSTBCASTTXOK_IDX, + S2500_MSTMCASTTXOK_IDX, + S2500_MSTTXUNDEFLOW_IDX, + S2500_MSTSINGLECOL_IDX, + S2500_MSTMULTICOL_IDX, + S2500_MSTEXCESSCOL_IDX, + S2500_MSTDEFERREDTX_IDX, + S2500_MSTCRSERR_IDX, + S2500_MSTOCTECTSRX_IDX, + S2500_MSTFRAMESRXOK_IDX, + S2500_MSTBCASTRXOK_IDX, + S2500_MSTMCASTRXOK_IDX, + S2500_MSTRUNTSERR_IDX, + S2500_MSTRXTOOLONG_IDX, + S2500_MSTFCSERRS_IDX, + S2500_MSTSYMBOLERRS_IDX, + S2500_MSTALIGNERRS_IDX, + S2500_MSTRXOVERFLOW_IDX, + S2500_MSTRXDROPPED_IDX, +}; + +static const u8 s2500_rmon_stat_map[S2500_NUM_RMON_STATS] =3D { + S2500_MSTFRAMESTX64_IDX, + S2500_MSTFRAMESTX65_IDX, + S2500_MSTFRAMESTX128_IDX, + S2500_MSTFRAMESTX256_IDX, + S2500_MSTFRAMESTX512_IDX, + S2500_MSTFRAMESTX1024_IDX, + S2500_MSTFRAMESRX64_IDX, + S2500_MSTFRAMESRX65_IDX, + S2500_MSTFRAMESRX128_IDX, + S2500_MSTFRAMESRX256_IDX, + S2500_MSTFRAMESRX512_IDX, + S2500_MSTFRAMESRX1024_IDX, +}; + +static const struct ethtool_rmon_hist_range s2500_rmon_hist_ranges[] =3D { + { 64, 64 }, + { 65, 127 }, + { 128, 255 }, + { 256, 511 }, + { 512, 1023 }, + { 1024, 2000 }, + { }, +}; + +#define S2500_MAC_STATS_LEN ARRAY_SIZE(s2500_mac_stat_strings) +static_assert(S2500_MAC_STATS_LEN =3D=3D S2500_NUM_MAC_STATS); +static_assert(ARRAY_SIZE(s2500_mac_stat_map) =3D=3D S2500_NUM_MAC_STATS); +static_assert(ARRAY_SIZE(s2500_rmon_stat_map) =3D=3D S2500_NUM_RMON_STATS); + +#define STAT_REG_OFFSET(x) ((S2500_REG_MAC_ST##x) - \ + S2500_REG_MAC_FIRST_STAT) + +static void s2500_update_stats(struct s2500_info *priv) +{ + u64 *data =3D priv->stats_data; + u32 *regs, *rptr; + int ret; + + regs =3D kmalloc_array(S2500_NUM_STAT_REGS, sizeof(u32), GFP_KERNEL); + if (!regs) + return; + + ret =3D oa_tc6_read_registers_mms(priv->tc6, S2500_REG_MAC_STOCTECTSTXL, + OA_TC6_PHY_C45_MAC_MMS1, regs, + S2500_NUM_STAT_REGS); + if (ret) + goto out; + + rptr =3D regs; + + /* TX bytes is a 64-bit register that spans over two 32-bit regs + * note: HW does auto-freeze when reading LSB and un-freeze on MSB + */ + *(data++) +=3D ((u64)*rptr) | (((u64)*(rptr + 1)) << 32); + + /* run until the next 64-bit register */ + for (rptr +=3D 2; (rptr - regs) < STAT_REG_OFFSET(OCTECTSRXL); ++rptr) + *(data++) +=3D *rptr; + + /* RX bytes is a 64-bit register that spans over two 32-bit regs + * note: HW does auto-freeze when reading LSB and un-freeze on MSB + */ + *(data++) +=3D ((u64)*rptr) | (((u64)*(rptr + 1)) << 32); + + for (rptr +=3D 2; (rptr - regs) < S2500_NUM_STAT_REGS; ++rptr) + *(data++) +=3D *rptr; +out: + kfree(regs); +} + +static void s2500_get_drvinfo(struct net_device *ndev, + struct ethtool_drvinfo *info) +{ + strscpy(info->driver, DRV_NAME, sizeof(info->driver)); + strscpy(info->bus_info, dev_name(&ndev->dev), + sizeof(info->bus_info)); +} + +static int s2500_get_sset_count(struct net_device *ndev, int sset) +{ + switch (sset) { + case ETH_SS_STATS: + return S2500_MAC_STATS_LEN; + default: + return -EOPNOTSUPP; + } +} + +static void s2500_get_strings(struct net_device *ndev, u32 stringset, + u8 *buf) +{ + switch (stringset) { + case ETH_SS_STATS: + memcpy(buf, s2500_mac_stat_strings, + S2500_MAC_STATS_LEN * ETH_GSTRING_LEN); + break; + } +} + +static void s2500_get_ethtool_stats(struct net_device *ndev, + struct ethtool_stats *stats, u64 *data) +{ + struct s2500_info *priv =3D netdev_priv(ndev); + int i; + + s2500_update_stats(priv); + for (i =3D 0; i < S2500_NUM_MAC_STATS; i++) + data[i] =3D priv->stats_data[s2500_mac_stat_map[i]]; +} + +static void s2500_get_rmon_stats(struct net_device *ndev, + struct ethtool_rmon_stats *rmon_stats, + const struct ethtool_rmon_hist_range **ranges) +{ + struct s2500_info *priv =3D netdev_priv(ndev); + int i; + + s2500_update_stats(priv); + + memset(rmon_stats, 0, sizeof(*rmon_stats)); + rmon_stats->src =3D ETHTOOL_MAC_STATS_SRC_AGGREGATE; + rmon_stats->undersize_pkts =3D priv->stats_data[S2500_MSTRUNTSERR_IDX]; + rmon_stats->oversize_pkts =3D priv->stats_data[S2500_MSTRXTOOLONG_IDX]; + rmon_stats->fragments =3D priv->stats_data[S2500_MSTFCSERRS_IDX]; + rmon_stats->jabbers =3D priv->stats_data[S2500_MSTALIGNERRS_IDX]; + + for (i =3D 0; i < 6; i++) + rmon_stats->hist_tx[i] =3D priv->stats_data[s2500_rmon_stat_map[i]]; + + for (i =3D 0; i < 6; i++) + rmon_stats->hist[i] =3D priv->stats_data[s2500_rmon_stat_map[i + 6]]; + + *ranges =3D s2500_rmon_hist_ranges; +} + +static int s2500_get_ts_info(struct net_device *ndev, + struct kernel_ethtool_ts_info *ts_info) +{ + struct s2500_info *priv =3D netdev_priv(ndev); + + return oa_tc6_get_ts_info(priv->tc6, ts_info); +} + +static int s2500_get_regs_len(struct net_device *dev) +{ + return S2500_REGDUMP_LEN; +} + +static void s2500_get_regs(struct net_device *ndev, + struct ethtool_regs *regs, void *p) +{ + struct s2500_info *priv =3D netdev_priv(ndev); + u32 *pbuff =3D (u32 *)p; + u16 reg, mms; + int ret =3D 0; + u32 val; + int i; + + regs->version =3D 0; + memset(p, 0, S2500_REGDUMP_LEN); + + if (!netif_running(ndev)) + return; + + for (i =3D 0; i < S2500_NUM_REGS; i++) { + val =3D 0; + reg =3D s2500_reg_map[i].reg; + mms =3D s2500_reg_map[i].mms; + ret =3D oa_tc6_read_register_mms(priv->tc6, reg, mms, &val); + if (ret) + continue; + *pbuff++ =3D cpu_to_be32(((u32)mms << 16) | reg); + *pbuff++ =3D cpu_to_be32(val); + } +} + +static void s2500_get_ts_stats(struct net_device *ndev, + struct ethtool_ts_stats *ts_stats) +{ + struct s2500_info *priv =3D netdev_priv(ndev); + + oa_tc6_get_ts_stats(priv->tc6, ts_stats); +} + +const struct ethtool_ops s2500_ethtool_ops =3D { + .get_drvinfo =3D s2500_get_drvinfo, + .get_link =3D ethtool_op_get_link, + .get_link_ksettings =3D phy_ethtool_get_link_ksettings, + .set_link_ksettings =3D phy_ethtool_set_link_ksettings, + .get_ts_stats =3D s2500_get_ts_stats, + .get_sset_count =3D s2500_get_sset_count, + .get_strings =3D s2500_get_strings, + .get_ethtool_stats =3D s2500_get_ethtool_stats, + .get_rmon_stats =3D s2500_get_rmon_stats, + .get_ts_info =3D s2500_get_ts_info, + .get_regs_len =3D s2500_get_regs_len, + .get_regs =3D s2500_get_regs, +}; + diff --git a/drivers/net/ethernet/onsemi/s2500/s2500_hw_def.h b/drivers/net= /ethernet/onsemi/s2500/s2500_hw_def.h new file mode 100644 index 000000000000..285fd87ccf92 --- /dev/null +++ b/drivers/net/ethernet/onsemi/s2500/s2500_hw_def.h @@ -0,0 +1,225 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright 2026 Semiconductor Components Industries, LLC ("onsemi"). + * onsemi's S2500 10BASE-T1S MAC-PHY driver + */ + +#ifndef S2500_HW_DEF_H +#define S2500_HW_DEF_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRV_NAME "s2500" + +#define S2500_N_MCAST_FILTERS 3 + +/* SPI OID and model register */ +#define S2500_REG_SPI_PHYID 0x1 + +#define S2500_SPI_PHYID_OUI_SHIFT 10 +#define S2500_SPI_PHYID_OUI_MASK GENMASK(31, S2500_SPI_PHYID_OUI_SHIFT) +#define S2500_SPI_PHYID_OUI_BYTE0_MASK GENMASK(21, 16) +#define S2500_SPI_PHYID_OUI_BYTE1_MASK GENMASK(15, 8) +#define S2500_SPI_PHYID_OUI_BYTE2_MASK GENMASK(7, 0) +/* SPI configuration register #0 */ +#define S2500_REG_SPI_CFG0 0x4 + +#define S2500_SPI_CFG0_SYNC_BIT BIT(15) +#define S2500_SPI_CFG0_TXCTHRESH_SHIFT 10 +#define S2500_SPI_CFG0_RXCTE_BIT BIT(8) +#define S2500_SPI_CFG0_FTSS_64_BIT BIT(6) +#define S2500_SPI_CFG0_CPS_SHIFT 0 + +#define S2500_TXCTHRESH_8 0x2 + +#define S2500_CPS_64 0x6 + +/* SPI status register #0 */ +#define S2500_REG_SPI_ST0 0x8 + +#define S2500_SPI_ST0_CDPE_BIT BIT(12) +#define S2500_SPI_ST0_TXFCSE_BIT BIT(11) +#define S2500_SPI_ST0_TTSCAC_BIT BIT(10) +#define S2500_SPI_ST0_TTSCAB_BIT BIT(9) +#define S2500_SPI_ST0_TTSCAA_BIT BIT(8) +#define S2500_SPI_ST0_RESETC_BIT BIT(6) +#define S2500_SPI_ST0_HDRE_BIT BIT(5) +#define S2500_SPI_ST0_LOFE_BIT BIT(4) +#define S2500_SPI_ST0_RXBOE_BIT BIT(3) +#define S2500_SPI_ST0_TXBUE_BIT BIT(2) +#define S2500_SPI_ST0_TXBOE_BIT BIT(1) +#define S2500_SPI_ST0_TXPE_BIT BIT(0) + +/* SPI IRQ enable register #0 (use the S2500_SPI_ST0_*_BIT constants) */ +#define S2500_REG_SPI_IRQM0 0xc + +/* SPI buffer status register */ +#define S2500_REG_SPI_BUFST 0xb + +#define S2500_REG_MAC_CTRL 0x0 + +#define S2500_MAC_CTRL_MCSF_BIT BIT(18) +#define S2500_MAC_CTRL_ADRF_BIT BIT(16) +#define S2500_MAC_CTRL_FCSA_BIT BIT(8) +#define S2500_MAC_CTRL_TXEN_BIT BIT(1) +#define S2500_MAC_CTRL_RXEN_BIT BIT(0) + +/* MAC address filter registers */ +#define S2500_REG_MAC_ADDRFILTL(n) (16 + 2 * (n)) +#define S2500_REG_MAC_ADDRFILTH(n) (17 + 2 * (n)) +#define S2500_REG_MAC_ADDRMASKL(n) (32 + 2 * (n)) +#define S2500_REG_MAC_ADDRMASKH(n) (33 + 2 * (n)) + +#define S2500_MAC_ADDRFILT_EN_BIT BIT(31) + +/* MAC statistic registers */ +#define S2500_REG_MAC_STOCTECTSTXL 48 +#define S2500_REG_MAC_STOCTECTSTXH 49 +#define S2500_REG_MAC_STFRAMESTXOK 50 +#define S2500_REG_MAC_STBCASTTXOK 51 +#define S2500_REG_MAC_STMCASTTXOK 52 +#define S2500_REG_MAC_STFRAMESTX64 53 +#define S2500_REG_MAC_STFRAMESTX65 54 +#define S2500_REG_MAC_STFRAMESTX128 55 +#define S2500_REG_MAC_STFRAMESTX256 56 +#define S2500_REG_MAC_STFRAMESTX512 57 +#define S2500_REG_MAC_STFRAMESTX1024 58 +#define S2500_REG_MAC_STTXUNDEFLOW 59 +#define S2500_REG_MAC_STSINGLECOL 60 +#define S2500_REG_MAC_STMULTICOL 61 +#define S2500_REG_MAC_STEXCESSCOL 62 +#define S2500_REG_MAC_STDEFERREDTX 63 +#define S2500_REG_MAC_STCRSERR 64 +#define S2500_REG_MAC_STOCTECTSRXL 65 +#define S2500_REG_MAC_STOCTECTSRXH 66 +#define S2500_REG_MAC_STFRAMESRXOK 67 +#define S2500_REG_MAC_STBCASTRXOK 68 +#define S2500_REG_MAC_STMCASTRXOK 69 +#define S2500_REG_MAC_STFRAMESRX64 70 +#define S2500_REG_MAC_STFRAMESRX65 71 +#define S2500_REG_MAC_STFRAMESRX128 72 +#define S2500_REG_MAC_STFRAMESRX256 73 +#define S2500_REG_MAC_STFRAMESRX512 74 +#define S2500_REG_MAC_STFRAMESRX1024 75 +#define S2500_REG_MAC_STRUNTSERR 76 +#define S2500_REG_MAC_STRXTOOLONG 77 +#define S2500_REG_MAC_STFCSERRS 78 +#define S2500_REG_MAC_STSYMBOLERRS 79 +#define S2500_REG_MAC_STALIGNERRS 80 +#define S2500_REG_MAC_STRXOVERFLOW 81 +#define S2500_REG_MAC_STRXDROPPED 82 + +/* First/last statistic register for sequential access */ +#define S2500_REG_MAC_FIRST_STAT S2500_REG_MAC_STOCTECTSTXL +#define S2500_REG_MAC_LAST_STAT S2500_REG_MAC_STRXDROPPED + +#define S2500_NUM_STAT_REGS \ + (S2500_REG_MAC_LAST_STAT - S2500_REG_MAC_FIRST_STAT + 1) +#define S2500_NUM_STAT_VARS (S2500_NUM_STAT_REGS - 2) + +/* Vendor specific MMS4 registers */ +#define S2500_REG_VS_ONIPVER 0x8000 +#define S2500_REG_VS_TWEAKS1 0x8001 +#define S2500_REG_VS_PLCAEXT 0x8002 +#define S2500_REG_VS_PMATUNE0 0x8003 +#define S2500_REG_VS_PMATUNE1 0x8004 +#define S2500_REG_VS_T1SWUPTUNE 0x8007 +#define S2500_REG_VS_HDD 0xCC01 +#define S2500_REG_VS_DCQ_TOID 0xCC02 +#define S2500_REG_VS_DCQ_SQI 0xCC03 +#define S2500_REG_VS_DCQ_SQI_PLUS 0xCC04 +#define S2500_REG_VS_HDD_TUNE1 0xCD00 +#define S2500_REG_VS_HDD_TUNE2 0xCD01 +#define S2500_REG_VS_HDD_TUNE3 0xCD02 +#define S2500_REG_VS_WS_STATUS_0 0xD000 +#define S2500_REG_VS_WS_CTRL_0 0xD001 +#define S2500_REG_VS_WS_STATUS_1 0xD100 +#define S2500_REG_VS_WS_CTRL_1 0xD101 + +/* Vendor specific MMS12 registers */ +#define S2500_REG_VS_MIIMIRQE 0x10 + +/* MIIM IRQ status register */ +#define S2500_REG_VS_MIIMIRQS 0x11 +#define MIIM_IRQ_STATUS_RSTS_SHIFT 15 +#define MIIM_IRQ_STATUS_RSTS BIT(MIIM_IRQ_STATUS_RSTS_SHIFT) + +#define S2500_REG_VS_DIOCFG0 0x12 + +#define S2500_REG_VS_CHIPID 0x1000 +#define S2500_REG_VS_TWEAKS2 0x1001 + +/* Permanent MAC address register */ +#define S2500_REG_VS_MACID0 0x1002 +#define S2500_VS_MACID0_BYTE4_MASK GENMASK(15, 8) +#define S2500_VS_MACID0_BYTE5_MASK GENMASK(7, 0) + +#define S2500_REG_VS_MACID1 0x1003 +#define S2500_VS_MACID1_BYTE3_MASK GENMASK(7, 0) +#define S2500_REG_VS_NVM_HEALTH 0x1005 + +/* PTP registers */ +#define S2500_REG_VS_PTP_SEC 0x1010 +#define S2500_REG_VS_PTP_SETSEC 0x1012 +#define S2500_REG_VS_PTP_ADJ 0x1014 +#define S2500_REG_VS_PTPNSEC 0x1011 +#define S2500_REG_VS_SETNSEC 0x1013 +#define S2500_REG_VS_CMPCTL 0x1015 +#define S2500_REG_VS_CMPSEC 0x1016 +#define S2500_REG_VS_CMPNSEC 0x1017 +#define S2500_REG_VS_CMPPER 0x1018 +#define S2500_REG_VS_CAPCTL 0x1019 +#define S2500_REG_VS_CAPSEC 0x101A +#define S2500_REG_VS_CAPNSEC 0x101B +#define S2500_REG_VS_BCNCNT 0x101C + +/* prototypes / forward declarations */ +extern const struct ethtool_ops s2500_ethtool_ops; + +struct s2500_info; + +struct s2500_info { + struct device *dev; + struct net_device *ndev; + + /* To have atomic set_rx_mode operation */ + spinlock_t lock; + + /* To have atomic operation when time is adjusted */ + struct mutex ptp_adj_lock; + struct task_struct *thread; + + /* global state variables */ + bool event_pending; + unsigned int ndev_flags; + bool rx_flags_upd; + + signed long poll_jiff; + + struct spi_device *spi; + + /* statistic counters variables */ + u64 stats_data[S2500_NUM_STAT_VARS]; + + /* PTP related variables */ + struct ptp_clock_info ptp_clock_info; + void *tc6; +}; + +int s2500_ptp_register(struct s2500_info *priv); + +#endif /* S2500_HW_DEF_H */ + diff --git a/drivers/net/ethernet/onsemi/s2500/s2500_main.c b/drivers/net/e= thernet/onsemi/s2500/s2500_main.c new file mode 100644 index 000000000000..7aa3267db39b --- /dev/null +++ b/drivers/net/ethernet/onsemi/s2500/s2500_main.c @@ -0,0 +1,632 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2026 Semiconductor Components Industries, LLC ("onsemi"). + * onsemi's S2500 10BASE-T1S MAC-PHY driver + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "s2500_hw_def.h" + +/* S2500 functions & definitions */ + +#define S2500_STATUS0_MASK (S2500_SPI_ST0_CDPE_BIT | \ + S2500_SPI_ST0_TXFCSE_BIT | \ + S2500_SPI_ST0_TTSCAC_BIT | \ + S2500_SPI_ST0_TTSCAB_BIT | \ + S2500_SPI_ST0_TTSCAA_BIT | \ + S2500_SPI_ST0_RESETC_BIT | \ + S2500_SPI_ST0_HDRE_BIT | \ + S2500_SPI_ST0_LOFE_BIT | \ + S2500_SPI_ST0_RXBOE_BIT | \ + S2500_SPI_ST0_TXBUE_BIT | \ + S2500_SPI_ST0_TXBOE_BIT | \ + S2500_SPI_ST0_TXPE_BIT) + +/* Initializes the net device MAC address by reading the UID stored + * into the device internal non-volatile memory. + */ +static int s2500_read_mac_from_nvmem(struct s2500_info *priv) +{ + u8 addr[ETH_ALEN]; + u32 mac1 =3D 0; + u32 mac0 =3D 0; + u32 val; + int ret; + + ret =3D oa_tc6_read_register_mms(priv->tc6, S2500_REG_VS_MACID1, + OA_TC6_PHY_C45_VS_MMS12, &mac1); + if (ret) + return ret; + + ret =3D oa_tc6_read_register_mms(priv->tc6, S2500_REG_VS_MACID0, + OA_TC6_PHY_C45_VS_MMS12, &mac0); + if (ret) + return ret; + + /* Pre-production parts may have 0 */ + if (mac0 =3D=3D 0 && mac1 =3D=3D 0) + return -ENXIO; + + ret =3D oa_tc6_read_register(priv->tc6, S2500_REG_SPI_PHYID, &val); + if (ret) + return ret; + + val =3D (val & S2500_SPI_PHYID_OUI_MASK) >> S2500_SPI_PHYID_OUI_SHIFT; + + /* Mapping for bits from PHY ID register to OUI as give below. + * - PHY-ID[10:17] provides OUI[16:23] + * - PHY-ID[18:25] provides OUI[8:15] + * - PHY-ID[26:31] provides OUI[2:7] + * + * Hardware presents OUI such a way that this requires not just + * byte level swap, bit level swap is needed as well. + */ + addr[0] =3D bitrev8(FIELD_GET(S2500_SPI_PHYID_OUI_BYTE0_MASK, val)); + addr[1] =3D bitrev8(FIELD_GET(S2500_SPI_PHYID_OUI_BYTE1_MASK, val)); + addr[2] =3D bitrev8(FIELD_GET(S2500_SPI_PHYID_OUI_BYTE2_MASK, val)); + + addr[3] =3D FIELD_GET(S2500_VS_MACID1_BYTE3_MASK, mac1); + addr[4] =3D FIELD_GET(S2500_VS_MACID0_BYTE4_MASK, mac0); + addr[5] =3D FIELD_GET(S2500_VS_MACID0_BYTE5_MASK, mac0); + + __dev_addr_set(priv->ndev, addr, ETH_ALEN); + priv->ndev->addr_assign_type =3D NET_ADDR_PERM; + return ret; +} + +/* Writes MAC address to macphy registers */ +static int s2500_set_mac_filter(struct net_device *ndev, const u8 *mac) +{ + struct s2500_info *priv =3D netdev_priv(ndev); + u32 val; + int ret; + + /* Set unicast address filter */ + ret =3D oa_tc6_write_register_mms(priv->tc6, S2500_REG_MAC_ADDRMASKL(0), + OA_TC6_PHY_C45_MAC_MMS1, 0xffffffff); + if (ret) + return ret; + + ret =3D oa_tc6_write_register_mms(priv->tc6, S2500_REG_MAC_ADDRMASKH(0), + OA_TC6_PHY_C45_MAC_MMS1, 0xffff); + if (ret) + return ret; + + val =3D get_unaligned_be32(&mac[2]); + + ret =3D oa_tc6_write_register_mms(priv->tc6, S2500_REG_MAC_ADDRFILTL(0), + OA_TC6_PHY_C45_MAC_MMS1, val); + if (ret) + return ret; + + val =3D S2500_MAC_ADDRFILT_EN_BIT | get_unaligned_be16(mac); + + return oa_tc6_write_register_mms(priv->tc6, S2500_REG_MAC_ADDRFILTH(0), + OA_TC6_PHY_C45_MAC_MMS1, val); +} + +static int s2500_mac_ctrl_modify_bits(struct s2500_info *priv, + u32 in_bits, bool clr) +{ + u32 reg =3D S2500_REG_MAC_CTRL; + u32 rval =3D 0; + int ret; + + ret =3D oa_tc6_read_register_mms(priv->tc6, reg, + OA_TC6_PHY_C45_MAC_MMS1, &rval); + if (!ret) { + u32 wval =3D 0; + + if (clr) + wval =3D rval & ~in_bits; + else + wval =3D rval | in_bits; + if (rval !=3D wval) + ret =3D oa_tc6_write_register_mms(priv->tc6, reg, + OA_TC6_PHY_C45_MAC_MMS1, wval); + } + return ret; +} + +static int s2500_init(struct s2500_info *priv) +{ + u32 val; + int ret; + + /* Configure the SPI protocol + 64 bit timestamp */ + val =3D S2500_SPI_CFG0_SYNC_BIT | S2500_SPI_CFG0_RXCTE_BIT | + (S2500_TXCTHRESH_8 << S2500_SPI_CFG0_TXCTHRESH_SHIFT) | + (S2500_CPS_64 << S2500_SPI_CFG0_CPS_SHIFT) | + S2500_SPI_CFG0_FTSS_64_BIT; + + ret =3D oa_tc6_write_register(priv->tc6, S2500_REG_SPI_CFG0, val); + if (ret) + return ret; + + val =3D (u32)~(S2500_SPI_ST0_RESETC_BIT | + S2500_SPI_ST0_HDRE_BIT | S2500_SPI_ST0_LOFE_BIT | + S2500_SPI_ST0_RXBOE_BIT | S2500_SPI_ST0_TXBOE_BIT | + S2500_SPI_ST0_TXPE_BIT); + + ret =3D oa_tc6_write_register(priv->tc6, S2500_REG_SPI_IRQM0, val); + if (ret) + return ret; + + /* Read the initial value of TX credits */ + ret =3D oa_tc6_read_register(priv->tc6, S2500_REG_SPI_BUFST, &val); + if (ret) + return ret; + + /* Program the source MAC address into the device */ + ret =3D s2500_set_mac_filter(priv->ndev, priv->ndev->dev_addr); + + val =3D S2500_MAC_CTRL_ADRF_BIT | S2500_MAC_CTRL_FCSA_BIT; + + return s2500_mac_ctrl_modify_bits(priv, val, false); +} + +static void s2500_shutdown(struct s2500_info *priv) +{ + u32 val =3D S2500_MAC_CTRL_TXEN_BIT | S2500_MAC_CTRL_RXEN_BIT; + struct net_device *ndev =3D priv->ndev; + + netif_stop_queue(ndev); + phy_stop(ndev->phydev); + + s2500_mac_ctrl_modify_bits(priv, val, true); +} + +static int s2500_set_promiscuous_mode(struct s2500_info *priv, + unsigned int rx_flags) +{ + u32 val =3D S2500_MAC_CTRL_ADRF_BIT; + bool clr =3D false; + + if (rx_flags & IFF_PROMISC) + clr =3D true; + return s2500_mac_ctrl_modify_bits(priv, val, clr); +} + +static int s2500_set_multicast_mode(struct s2500_info *priv, + unsigned int rx_flags) +{ + int i, ret =3D 0; + u32 val; + + if ((rx_flags & IFF_ALLMULTI) || + (netdev_mc_count(priv->ndev) > S2500_N_MCAST_FILTERS)) { + /* Disable multicast filter */ + ret =3D s2500_mac_ctrl_modify_bits(priv, + S2500_MAC_CTRL_MCSF_BIT, + true); + if (ret) + return ret; + + /* Accept all multicasts */ + ret =3D oa_tc6_write_register_mms(priv->tc6, S2500_REG_MAC_ADDRMASKL(1), + OA_TC6_PHY_C45_MAC_MMS1, 0); + if (ret) + return ret; + + ret =3D oa_tc6_write_register_mms(priv->tc6, S2500_REG_MAC_ADDRMASKH(1), + OA_TC6_PHY_C45_MAC_MMS1, 0x100); + if (ret) + return ret; + + ret =3D oa_tc6_write_register_mms(priv->tc6, S2500_REG_MAC_ADDRFILTL(1), + OA_TC6_PHY_C45_MAC_MMS1, 0); + if (ret) + return ret; + + val =3D S2500_MAC_ADDRFILT_EN_BIT | 0x00000100; + ret =3D oa_tc6_write_register_mms(priv->tc6, S2500_REG_MAC_ADDRFILTH(1), + OA_TC6_PHY_C45_MAC_MMS1, val); + } else if (netdev_mc_count(priv->ndev) =3D=3D 0) { + /* Enable multicast filter */ + ret =3D s2500_mac_ctrl_modify_bits(priv, + S2500_MAC_CTRL_MCSF_BIT, + false); + if (ret) + return ret; + + /* Disable filters */ + for (i =3D 1; i <=3D S2500_N_MCAST_FILTERS; i++) { + ret =3D oa_tc6_write_register_mms(priv->tc6, + S2500_REG_MAC_ADDRFILTH(i), + OA_TC6_PHY_C45_MAC_MMS1, 0); + if (ret) + return ret; + } + } else { + struct netdev_hw_addr *ha; + u32 addrh, addrl; + + /* Disable multicast filter */ + ret =3D s2500_mac_ctrl_modify_bits(priv, + S2500_MAC_CTRL_MCSF_BIT, + true); + if (ret) + return ret; + + /* Disable filters */ + for (i =3D 1; i <=3D S2500_N_MCAST_FILTERS; i++) { + ret =3D oa_tc6_write_register_mms(priv->tc6, + S2500_REG_MAC_ADDRFILTH(i), + OA_TC6_PHY_C45_MAC_MMS1, 0); + if (ret) + return ret; + } + + i =3D 1; + netdev_for_each_mc_addr(ha, priv->ndev) { + if (i > S2500_N_MCAST_FILTERS) + break; + + addrh =3D S2500_MAC_ADDRFILT_EN_BIT | + get_unaligned_be16(ha->addr); + addrl =3D get_unaligned_be32(&ha->addr[2]); + + ret =3D oa_tc6_write_register_mms(priv->tc6, + S2500_REG_MAC_ADDRFILTH(i), + OA_TC6_PHY_C45_MAC_MMS1, addrh); + if (ret) + return ret; + + ret =3D oa_tc6_write_register_mms(priv->tc6, + S2500_REG_MAC_ADDRFILTL(i), + OA_TC6_PHY_C45_MAC_MMS1, addrl); + if (ret) + return ret; + + ret =3D oa_tc6_write_register_mms(priv->tc6, + S2500_REG_MAC_ADDRMASKL(i), + OA_TC6_PHY_C45_MAC_MMS1, 0xffffffff); + if (ret) + return ret; + + ret =3D oa_tc6_write_register_mms(priv->tc6, + S2500_REG_MAC_ADDRMASKH(i), + OA_TC6_PHY_C45_MAC_MMS1, 0xffff); + if (ret) + return ret; + i++; + } + } + return ret; +} + +/* Deferred function for applying RX mode flags in non-atomic context */ +static int s2500_rx_mode_update(struct s2500_info *priv) +{ + unsigned int rx_flags; + unsigned long flags; + int ret; + + spin_lock_irqsave(&priv->lock, flags); + + rx_flags =3D priv->ndev_flags; + priv->rx_flags_upd =3D false; + + spin_unlock_irqrestore(&priv->lock, flags); + + ret =3D s2500_set_promiscuous_mode(priv, rx_flags); + if (ret) + goto out; + + ret =3D s2500_set_multicast_mode(priv, rx_flags); +out: + return ret; +} + +static void s2500_set_rx_mode(struct net_device *ndev) +{ + struct s2500_info *priv =3D netdev_priv(ndev); + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + + priv->rx_flags_upd =3D true; + priv->ndev_flags =3D ndev->flags; + + spin_unlock_irqrestore(&priv->lock, flags); + + if (priv->thread) + wake_up_process(priv->thread); +} + +static int s2500_set_mac_address(struct net_device *ndev, void *p) +{ + struct sockaddr *addr =3D p; + + if (!is_valid_ether_addr(addr->sa_data)) + return -EADDRNOTAVAIL; + + eth_hw_addr_set(ndev, addr->sa_data); + return s2500_set_mac_filter(ndev, addr->sa_data); +} + +static netdev_tx_t s2500_start_xmit(struct sk_buff *skb, + struct net_device *ndev) +{ + struct s2500_info *priv =3D netdev_priv(ndev); + + return oa_tc6_start_xmit(priv->tc6, skb); +} + +static int s2500_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) +{ + struct s2500_info *priv =3D netdev_priv(ndev); + + return oa_tc6_ioctl(priv->tc6, rq, cmd); +} + +static void s2500_process_events(struct s2500_info *priv) +{ + u32 val; + int ret; + + if (!priv->event_pending) + return; + + priv->event_pending =3D false; + + ret =3D oa_tc6_read_register(priv->tc6, S2500_REG_SPI_ST0, &val); + if (ret) { + dev_err(&priv->spi->dev, "Error reading ST0 register"); + return; + } +} + +static int s2500_thread_fun(void *data) +{ + struct s2500_info *priv =3D data; + bool update_rx_mode =3D false; + unsigned long flags; + signed long tout; + int ret =3D 0; + + tout =3D priv->poll_jiff; + + do { + if (update_rx_mode) { + ret =3D s2500_rx_mode_update(priv); + if (unlikely(ret)) { + dev_err(&priv->spi->dev, "Failed to set new RX mode"); + break; + } + } + + if (tout =3D=3D 0) { + tout =3D priv->poll_jiff; + + /* Force checking the status register */ + priv->event_pending =3D true; + } + + s2500_process_events(priv); + + spin_lock_irqsave(&priv->lock, flags); + __set_current_state(TASK_INTERRUPTIBLE); + + update_rx_mode =3D priv->rx_flags_upd; + ret =3D update_rx_mode; + + spin_unlock_irqrestore(&priv->lock, flags); + + if (!ret) + tout =3D schedule_timeout(tout); + else + set_current_state(TASK_RUNNING); + } while (!kthread_should_stop()); + return 0; +} + +static int s2500_open(struct net_device *ndev) +{ + struct s2500_info *priv =3D netdev_priv(ndev); + int ret =3D 0; + u32 val; + + dev_dbg(&ndev->dev, "%s", "s2500_open"); + phy_start(priv->ndev->phydev); + + priv->thread =3D kthread_run(s2500_thread_fun, priv, DRV_NAME "/%s:%d", + dev_name(&priv->spi->dev), + spi_get_chipselect(priv->spi, 0)); + + if (IS_ERR(priv->thread)) { + ret =3D PTR_ERR(priv->thread); + } else { + val =3D S2500_MAC_CTRL_TXEN_BIT | S2500_MAC_CTRL_RXEN_BIT; + ret =3D s2500_mac_ctrl_modify_bits(priv, val, false); + + netif_start_queue(priv->ndev); + } + return ret; +} + +static int s2500_stop(struct net_device *ndev) +{ + struct s2500_info *priv =3D netdev_priv(ndev); + + dev_dbg(&ndev->dev, "%s", "s2500_stop"); + + s2500_shutdown(priv); + + kthread_stop(priv->thread); + priv->thread =3D NULL; + + return 0; +} + +static int s2500_hwtstamp_get(struct net_device *ndev, + struct kernel_hwtstamp_config *k_cfg) +{ + struct s2500_info *priv =3D netdev_priv(ndev); + + oa_tc6_hwtstamp_get(priv->tc6, k_cfg); + return 0; +} + +static int s2500_hwtstamp_set(struct net_device *ndev, + struct kernel_hwtstamp_config *cfg, + struct netlink_ext_ack *extack) +{ + struct s2500_info *priv =3D netdev_priv(ndev); + + return oa_tc6_hwtstamp_set(priv->tc6, cfg); +} + +static const struct net_device_ops s2500_netdev_ops =3D { + .ndo_open =3D s2500_open, + .ndo_stop =3D s2500_stop, + .ndo_start_xmit =3D s2500_start_xmit, + .ndo_set_mac_address =3D s2500_set_mac_address, + .ndo_set_rx_mode =3D s2500_set_rx_mode, + .ndo_eth_ioctl =3D s2500_ioctl, + .ndo_hwtstamp_get =3D s2500_hwtstamp_get, + .ndo_hwtstamp_set =3D s2500_hwtstamp_set, +}; + +static int s2500_probe(struct spi_device *spi) +{ + struct device *dev =3D &spi->dev; + struct net_device *ndev; + struct s2500_info *priv; + u32 val; + int ret; + + if (spi->irq < 0) + return -ENODEV; + + ndev =3D devm_alloc_etherdev(dev, sizeof(struct s2500_info)); + if (!ndev) + return -ENOMEM; + + priv =3D netdev_priv(ndev); + priv->ndev =3D ndev; + priv->spi =3D spi; + priv->dev =3D dev; + + SET_NETDEV_DEV(ndev, dev); + + spin_lock_init(&priv->lock); + mutex_init(&priv->ptp_adj_lock); + ndev->irq =3D spi->irq; + + spi->dev.platform_data =3D priv; + spi_set_drvdata(spi, priv); + + ndev->netdev_ops =3D &s2500_netdev_ops; + ndev->ethtool_ops =3D &s2500_ethtool_ops; + ndev->if_port =3D IF_PORT_10BASET; + ndev->priv_flags |=3D IFF_UNICAST_FLT; + ndev->hw_features =3D NETIF_F_RXALL; + + priv->poll_jiff =3D HZ * 5; /* Poll interval */ + + priv->tc6 =3D oa_tc6_init(spi, ndev); + if (!priv->tc6) { + dev_err(&spi->dev, "OA TC6 init failed"); + return -ENODEV; + } + oa_tc6_set_vend1_mms(priv->tc6, OA_TC6_PHY_C45_VS_MMS12); + + /* Clear RSTS, if set */ + oa_tc6_read_register_mms(priv->tc6, S2500_REG_VS_MIIMIRQS, + OA_TC6_PHY_C45_VS_MMS12, &val); + val &=3D MIIM_IRQ_STATUS_RSTS; + if (val !=3D 0) + oa_tc6_write_register_mms(priv->tc6, S2500_REG_VS_MIIMIRQS, + OA_TC6_PHY_C45_VS_MMS12, + MIIM_IRQ_STATUS_RSTS); + + /* Acknowledge all IRQ status bits */ + ret =3D oa_tc6_read_register(priv->tc6, S2500_REG_SPI_ST0, &val); + if (!ret) { + u32 mask =3D S2500_STATUS0_MASK; + + val &=3D mask; + oa_tc6_write_register(priv->tc6, S2500_REG_SPI_ST0, val); + } + + ret =3D device_get_ethdev_address(priv->dev, ndev); + if (ret) + ret =3D s2500_read_mac_from_nvmem(priv); + + if (ret) { + eth_hw_addr_random(ndev); + dev_warn(&spi->dev, "Using random MAC address %pM", ndev->dev_addr); + } + + ret =3D s2500_init(priv); + if (unlikely(ret)) { + dev_err(&spi->dev, "failed to s2500_init the device"); + goto err_reg_read; + } + + /* Configure PTP if the model supports it */ + ret =3D s2500_ptp_register(priv); + if (unlikely(ret)) + goto err_reg_read; + + ret =3D register_netdev(ndev); + if (ret) { + dev_err(&spi->dev, "failed to register the S2500 device\n"); + ret =3D -ENODEV; + + goto err_reg_read; + } + return 0; + +err_reg_read: + dev_err(&spi->dev, "could not initialize macphy"); + return ret; +} + +static void s2500_remove(struct spi_device *spi) +{ + struct s2500_info *priv =3D spi->dev.platform_data; + + dev_dbg(&priv->ndev->dev, "%s", "s2500_remove"); + + oa_tc6_ptp_unregister(priv->tc6); + unregister_netdev(priv->ndev); + oa_tc6_exit(priv->tc6); +} + +static const struct of_device_id s2500_of_match[] =3D { + { .compatible =3D "onnn,s2500" }, + {} +}; + +static const struct spi_device_id s2500_ids[] =3D { + { "s2500" }, + {} +}; + +MODULE_DEVICE_TABLE(spi, s2500_ids); + +static struct spi_driver s2500_driver =3D { + .driver =3D { + .name =3D DRV_NAME, + .of_match_table =3D s2500_of_match, + }, + .probe =3D s2500_probe, + .remove =3D s2500_remove, + .id_table =3D s2500_ids, +}; + +module_spi_driver(s2500_driver); + +MODULE_AUTHOR("Piergiorgio Beruto "); +MODULE_AUTHOR("Selva Rajagopal "); +MODULE_DESCRIPTION("onsemi MACPHY ethernet driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/net/ethernet/onsemi/s2500/s2500_ptp.c b/drivers/net/et= hernet/onsemi/s2500/s2500_ptp.c new file mode 100644 index 000000000000..fd6617c7ac79 --- /dev/null +++ b/drivers/net/ethernet/onsemi/s2500/s2500_ptp.c @@ -0,0 +1,233 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2026 Semiconductor Components Industries, LLC ("onsemi"). + * onsemi's S2500 10BASE-T1S MAC-PHY driver + */ + +#include "s2500_hw_def.h" + +static int s2500_ptp_get_time64(struct ptp_clock_info *ptp, + struct timespec64 *ts, + struct ptp_system_timestamp *ptp_sts) +{ + struct s2500_info *priv =3D container_of(ptp, struct s2500_info, + ptp_clock_info); + u32 data[2]; + int ret; + + ptp_read_system_prets(ptp_sts); + ret =3D oa_tc6_read_registers_mms(priv->tc6, S2500_REG_VS_PTP_SEC, + OA_TC6_PHY_C45_VS_MMS12, &data[0], 2); + ptp_read_system_postts(ptp_sts); + + if (!ret) { + ts->tv_sec =3D data[0]; + ts->tv_nsec =3D data[1]; + } + + return ret; +} + +static int s2500_ptp_set_time64(struct ptp_clock_info *ptp, + const struct timespec64 *ts) +{ + struct s2500_info *priv =3D container_of(ptp, struct s2500_info, + ptp_clock_info); + u32 data[2]; + + if (ts->tv_sec >=3D (1ULL << 32)) + return -ERANGE; + + data[0] =3D (u32)ts->tv_sec; + data[1] =3D ts->tv_nsec | BIT(31); /* bit 31 =3D execute set command */ + + return oa_tc6_write_registers_mms(priv->tc6, S2500_REG_VS_PTP_SETSEC, + OA_TC6_PHY_C45_VS_MMS12, &data[0], 2); +} + +static int s2500_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) +{ + struct s2500_info *priv =3D container_of(ptp, struct s2500_info, + ptp_clock_info); + u32 sign_bit =3D 0; + long adj; + u32 val; + u64 ppm; + + if (scaled_ppm < 0) { + /* split sign / mod */ + sign_bit =3D 1U << 31; + scaled_ppm =3D ~scaled_ppm + 1; + } + + /** + * Convert unsigned scaled_ppm to atto-seconds per clock cycles. + * The scaled_ppm format is Qx.16 --> 1 lsb =3D 1/65536 ppm. + * The clock period of the S2500 is 8ns (125 MHz), so 1 lsb of + * adj register LSB is 1 atto-sec / 8ns =3D 0.000125 ppm. + * Represented in Qx.16 format, this is 0.000125 * 2^16 =3D 8(.192) + * To convert scaled_ppm into a register value we need to divide + * it by the LSB value, hence adj =3D (scaled_ppm * 1000) / 8192 to + * minimize the precision loss due to the integer arithmetic. + * That further reduces to (scaled_ppm * 125) / 1024. + */ + ppm =3D (u64)scaled_ppm * 125; + do_div(ppm, 1024); + adj =3D (long)ppm; + + /* check overflow */ + if (adj >=3D (1L << 28)) + return -ERANGE; + + val =3D (u32)adj | sign_bit; + return oa_tc6_write_register_mms(priv->tc6, S2500_REG_VS_PTP_ADJ, + OA_TC6_PHY_C45_VS_MMS12, val); +} + +static int s2500_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) +{ + struct s2500_info *priv =3D container_of(ptp, struct s2500_info, + ptp_clock_info); + struct ptp_system_timestamp sts; + struct timespec64 target; + unsigned int period_ms; + struct timespec64 now; + int max_iters =3D 3; + s64 scaled_ppm; + s64 remaining; + s64 target_ns; + int ret =3D 0; + s64 now_ns; + s64 num; + s64 den; + + if (!ptp) + return -EINVAL; + + /* Nothing to do */ + if (delta =3D=3D 0) + return 0; + + if (mutex_lock_interruptible(&priv->ptp_adj_lock)) + return -EINTR; + + /* Try to slew the clock using adjfine for better accuracy. For large + * adjustments fall back to setting time directly. + */ + remaining =3D delta; + + while (remaining !=3D 0 && max_iters--) { + s64 abs_delta =3D remaining > 0 ? remaining : -remaining; + + /* If the adjustment is very large, more than 1 second, + * use settime to avoid very long slewing periods or + * excessive frequency offsets. + */ + if (abs_delta > 1000000000LL) { + memset(&sts, 0, sizeof(sts)); + ret =3D ptp->gettimex64(ptp, &now, &sts); + if (!ret) { + struct timespec64 delta_ts; + + if (remaining >=3D 0) { + delta_ts =3D ns_to_timespec64(remaining); + target =3D timespec64_add(now, delta_ts); + } else { + delta_ts =3D ns_to_timespec64(-remaining); + target =3D timespec64_sub(now, delta_ts); + } + } + + if (target.tv_sec < 0 || target.tv_sec >=3D (1ULL << 32)) + ret =3D -ERANGE; + else + ret =3D ptp->settime64(ptp, &target); + + remaining =3D 0; + break; + } + + /* Choose a slewing period depending on magnitude */ + if (abs_delta <=3D 1000000LL) /* <=3D 1ms */ + period_ms =3D 1000; /* 1 s */ + else if (abs_delta <=3D 100000000LL) /* <=3D 100ms */ + period_ms =3D 10000; /* 10 s */ + else + period_ms =3D 60000; /* 60 s */ + + /* compute current time and fixed target for this iteration */ + memset(&sts, 0, sizeof(sts)); + ret =3D ptp->gettimex64(ptp, &now, &sts); + if (ret) + break; + + if (remaining >=3D 0) + target =3D timespec64_add(now, ns_to_timespec64(remaining)); + else + target =3D timespec64_sub(now, ns_to_timespec64(-remaining)); + + /* Compute scaled_ppm (Qx.16). scaled_ppm =3D ppm * 2^16 + * ppm =3D (delta_seconds / period_seconds) * 1e6 + * =3D> scaled_ppm =3D delta_ns * 65536 / (period_ms * 1000) + */ + num =3D remaining * 65536LL; + den =3D (s64)period_ms * 1000LL; + + /* Integer division rounds toward zero; keep sign in numerator */ + scaled_ppm =3D div_s64(num, den); + + /* Apply frequency adjustment */ + ret =3D ptp->adjfine(ptp, (long)scaled_ppm); + if (ret) + break; + + /* Sleep for the slew period (interruptible). If interrupted, clear + * the adjfine and return with -EINTR. + */ + if (msleep_interruptible(period_ms)) { + /* Clear adjfine */ + ptp->adjfine(ptp, 0); + ret =3D -EINTR; + break; + } + + /* Clear adjfine and measure remaining offset */ + ptp->adjfine(ptp, 0); + + memset(&sts, 0, sizeof(sts)); + ret =3D ptp->gettimex64(ptp, &now, &sts); + if (ret) + break; + + /* remaining =3D target - now (in ns) */ + target_ns =3D timespec64_to_ns(&target); + now_ns =3D timespec64_to_ns(&now); + remaining =3D target_ns - now_ns; + + /* If remaining is small (< 1us), finish */ + if (remaining > -1000 && remaining < 1000) + remaining =3D 0; + } + + mutex_unlock(&priv->ptp_adj_lock); + return ret; +} + +int s2500_ptp_register(struct s2500_info *priv) +{ + struct ptp_clock_info *info =3D &priv->ptp_clock_info; + int ret; + + info->max_adj =3D 100000000; + info->owner =3D THIS_MODULE; + info->adjfine =3D s2500_ptp_adjfine; + info->gettimex64 =3D s2500_ptp_get_time64; + info->settime64 =3D s2500_ptp_set_time64; + info->adjtime =3D s2500_ptp_adjtime; + + ret =3D oa_tc6_ptp_register(priv->tc6, info); + if (ret) + dev_err(&priv->spi->dev, "PTP registration failed"); + return ret; +} + --=20 2.43.0 From nobody Mon Jun 8 06:37:54 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3B6BD30D416; Sat, 6 Jun 2026 05:42:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780724570; cv=none; b=qZkSfSMY0GlI8Vnj2ThDm/37lbiLquw7ThXZJECC1TV+GE/yC3yB3nk6U1VsGnf1e0o10WKv20sN2WPbgM3txGCYKAiSS+MehDbDKbma0GT0CBbnRZAkYJKrVK1YahbNJp7Y1C4sDYBXexBB17qnSowyTk1u1SfBmxqOUjKROvg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780724570; c=relaxed/simple; bh=QG9/aUQq3lNYNSRpDS+oE4FGDJ/aRe862w851zW6Btg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=G7KZOizGz/YDkpkg43acIes21PHO2QnuQLiBgBjqUVAQFtxh/YWjMTkZ6JGi4KuXRN7U1sb7UY+YpL/CKjo3eCHs3AMpi5/c9+8t96wgr+FSyYgjolMq+n92Syq8ekl1xjK3dczopnMleUV7tJUL4b1EHWansv4oegjyVz6lkgE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=k4ps/SEc; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="k4ps/SEc" Received: by smtp.kernel.org (Postfix) with ESMTPS id 192AFC2BCC4; Sat, 6 Jun 2026 05:42:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1780724570; bh=QG9/aUQq3lNYNSRpDS+oE4FGDJ/aRe862w851zW6Btg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=k4ps/SEcFKfWZEfXb6GFo8obkV4WlrsG6q3A+tQRdabPaKzIkrblJNhuwDnGZXAG+ pvBczhT1aSL3yKqhk4aGe2Dx+IHeEp/DU9vdiMqdkKEXG0sx3ktJv1ixOnJzPB8RSd SZdpl6EmawYUNzK3AQZJyF1jMsqImz/iahZMQyR1W+H/tzvP7hzzjhfJdNoTOgd/oe /vNWpTliB036A07HsDFAbA2dtlcAk6VOyVm4Y3ww6DJZABwNCSKb23w0FBjhc9r4De oHSMbFjoPFGJ6IjnXaUWPtcvyfxKrYkLaz+Cctpejt1Ov48cOSs9HvAL71mgIgqfJ2 8hgAy0gQVu3qQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 11B01CD8C92; Sat, 6 Jun 2026 05:42:50 +0000 (UTC) From: Selvamani Rajagopal via B4 Relay Date: Fri, 05 Jun 2026 22:42:45 -0700 Subject: [PATCH net-next v4 14/16] onsemi: s2500: Added selftest support to onsemi's S2500 driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260605-s2500-mac-phy-support-v4-14-de0fbc13c6d8@onsemi.com> References: <20260605-s2500-mac-phy-support-v4-0-de0fbc13c6d8@onsemi.com> In-Reply-To: <20260605-s2500-mac-phy-support-v4-0-de0fbc13c6d8@onsemi.com> To: Andrew Lunn , Piergiorgio Beruto , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Parthiban Veerasooran , Selva Rajagopal , Richard Cochran , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Simon Horman , Jonathan Corbet , Shuah Khan Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, Jerry Ray , Selvamani Rajagopal X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780724562; l=1929; i=Selvamani.Rajagopal@onsemi.com; s=20260531; h=from:subject:message-id; bh=pwrT8nQjZ1Mftaz3kKIXboZB0R35Ne+b9zhE7hrK+JA=; b=Vo5hs0XFfqz/FTSZZqZjSzJBiKaoXnTGTWT12jwxtBzdMhCw7nwlRfdpeiSUHg+/QfUeAOy5E IAvRL59AlO7C2ha+bowftIcAja0L+O31YpDSc3/XZvBj5+GTztRnJmq X-Developer-Key: i=Selvamani.Rajagopal@onsemi.com; a=ed25519; pk=5QRdM0HS/LGWWcUZZ9hVfZ+qbPQGZCumcTXOiN7Fyug= X-Endpoint-Received: by B4 Relay for Selvamani.Rajagopal@onsemi.com/20260531 with auth_id=803 X-Original-From: Selvamani Rajagopal Reply-To: Selvamani.Rajagopal@onsemi.com From: Selvamani Rajagopal Split the selftest support into a separate patch for the ease of review. Signed-off-by: Selvamani Rajagopal --- drivers/net/ethernet/onsemi/s2500/Kconfig | 1 + drivers/net/ethernet/onsemi/s2500/s2500_ethtool.c | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/drivers/net/ethernet/onsemi/s2500/Kconfig b/drivers/net/ethern= et/onsemi/s2500/Kconfig index 22b0afad7a21..822398eb4760 100644 --- a/drivers/net/ethernet/onsemi/s2500/Kconfig +++ b/drivers/net/ethernet/onsemi/s2500/Kconfig @@ -8,6 +8,7 @@ if NET_VENDOR_ONSEMI config S2500_MACPHY tristate "S2500 support" depends on SPI + imply NET_SELFTESTS select NCN26000_PHY select OA_TC6 help diff --git a/drivers/net/ethernet/onsemi/s2500/s2500_ethtool.c b/drivers/ne= t/ethernet/onsemi/s2500/s2500_ethtool.c index 85bd8ea50dd8..334fac71ddea 100644 --- a/drivers/net/ethernet/onsemi/s2500/s2500_ethtool.c +++ b/drivers/net/ethernet/onsemi/s2500/s2500_ethtool.c @@ -5,6 +5,7 @@ */ =20 #include +#include #include =20 #include "s2500_hw_def.h" @@ -229,6 +230,8 @@ static int s2500_get_sset_count(struct net_device *ndev= , int sset) switch (sset) { case ETH_SS_STATS: return S2500_MAC_STATS_LEN; + case ETH_SS_TEST: + return net_selftest_get_count(); default: return -EOPNOTSUPP; } @@ -242,6 +245,9 @@ static void s2500_get_strings(struct net_device *ndev, = u32 stringset, memcpy(buf, s2500_mac_stat_strings, S2500_MAC_STATS_LEN * ETH_GSTRING_LEN); break; + case ETH_SS_TEST: + net_selftest_get_strings(buf); + break; } } =20 @@ -343,5 +349,6 @@ const struct ethtool_ops s2500_ethtool_ops =3D { .get_ts_info =3D s2500_get_ts_info, .get_regs_len =3D s2500_get_regs_len, .get_regs =3D s2500_get_regs, + .self_test =3D net_selftest, }; =20 --=20 2.43.0 From nobody Mon Jun 8 06:37:54 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F77630EF82; Sat, 6 Jun 2026 05:42:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780724570; cv=none; b=bPyhyH5vVBf1FXBoCrPBYl6dE8oapQWbFLPipQJ0ZtfD6BDhJrbr8oDWCqax8rDTy3IyHy06+4f2yKT97CWCF6Rpet+4X5yVfCsbsuZsokZhzMp84416BJAfDuET9+mFMMwZMTXcDZ4HzhCuuPa9vUweRBy8TFkZkD/A0Iud3xI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780724570; c=relaxed/simple; bh=heABrdCbeBYoZYV9Q+tn/OM7kZ998Emxjxc9jLrmfUA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=U8EldadaofMlL6ggpeXwITubUnNoDKtecTA6/COTzpOa1chEJ8S4O9MoKCWi8hqprVQ5eVe06J3jSVu1DiZuFp3h+XSiBllEJyYvXgxVkfnTgG4rZBi+mSOsx3RZNwKLj72fq+W4sBUdFrEd2yTa5PGRFzi1xQFMyolG/SWuCIY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qI+VARfj; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qI+VARfj" Received: by smtp.kernel.org (Postfix) with ESMTPS id 2F83EC2BCB0; Sat, 6 Jun 2026 05:42:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1780724570; bh=heABrdCbeBYoZYV9Q+tn/OM7kZ998Emxjxc9jLrmfUA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=qI+VARfji0b1kZI72S5x3kAIMcGjq5wxVZX6oBJjCPTKuCbmdy5/gUAYD2l7zXk7O wuX7NUBtHnlhVVuVIRrdSUw4ThvdW7H0Jwt/LIoHz72pvmksaR8/VYb/0W647pqtn6 hK1lW2wzOmQ795xh/XGA7ljzF3Ty95FRVo/eAclU2IAYzdF3V60m3IALXw9zgKMdva nJG3G34PB+fvfXcDQ9msLiyRZwS4Lw9q4mJNmFmKBzM/3jYsgd1yoT8aJ2DBhFirXy pC8RpcTyRt7/mOdRyqX59MD+trYTLAlgg2u9bf2FfIgnVGhXDDf2RwKX401f0YYLme V3EOG60aFx6cQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23B11CD8C85; Sat, 6 Jun 2026 05:42:50 +0000 (UTC) From: Selvamani Rajagopal via B4 Relay Date: Fri, 05 Jun 2026 22:42:46 -0700 Subject: [PATCH net-next v4 15/16] dt-bindings: net: add onsemi's S2500 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260605-s2500-mac-phy-support-v4-15-de0fbc13c6d8@onsemi.com> References: <20260605-s2500-mac-phy-support-v4-0-de0fbc13c6d8@onsemi.com> In-Reply-To: <20260605-s2500-mac-phy-support-v4-0-de0fbc13c6d8@onsemi.com> To: Andrew Lunn , Piergiorgio Beruto , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Parthiban Veerasooran , Selva Rajagopal , Richard Cochran , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Simon Horman , Jonathan Corbet , Shuah Khan Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, Jerry Ray , Selvamani Rajagopal X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780724562; l=2795; i=Selvamani.Rajagopal@onsemi.com; s=20260531; h=from:subject:message-id; bh=HUXIze6RdB6ERxDfpaDuHws8RvRgXJ4TnBjjVkgB2pc=; b=aDrRaIi0388pStuo00JchezrNyo+dUok5/9yDCvmHd8t+I/CLsVWxLoD8eykZxPWt76fJrJCb B0p7gJWjcqJAefgMFEU+hs7Ibl1+aGhEfUIMm8+27ltYmUh4U5EIEwB X-Developer-Key: i=Selvamani.Rajagopal@onsemi.com; a=ed25519; pk=5QRdM0HS/LGWWcUZZ9hVfZ+qbPQGZCumcTXOiN7Fyug= X-Endpoint-Received: by B4 Relay for Selvamani.Rajagopal@onsemi.com/20260531 with auth_id=803 X-Original-From: Selvamani Rajagopal Reply-To: Selvamani.Rajagopal@onsemi.com From: Selvamani Rajagopal Add YAML device tree binding for the onsemi S2500 IEEE 802.3cg compliant Ethernet transceiver device. We use IRQF_TRIGGER_FALLING, though OPEN Alliance 10BASE-T1x Serial Interface specification calls for IRQF_TRIGGER_LOW. This is to match IRQF_TRIGGER_FALLING used by OA TC6 framework code. This bug fix requires changes to the stable branch. At that time, this will be changed to IRQF_TRIGGER_LOW. Signed-off-by: Selvamani Rajagopal --- .../devicetree/bindings/net/onnn,s2500.yaml | 67 ++++++++++++++++++= ++++ 1 file changed, 67 insertions(+) diff --git a/Documentation/devicetree/bindings/net/onnn,s2500.yaml b/Docume= ntation/devicetree/bindings/net/onnn,s2500.yaml new file mode 100644 index 000000000000..11edf10508d9 --- /dev/null +++ b/Documentation/devicetree/bindings/net/onnn,s2500.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/onnn,s2500.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: onsemi S2500 10BASE-T1S MACPHY Ethernet Controllers + +maintainers: + - Piergiorgio Beruto + - Selva Rajagopal + +description: + The S2500 combines a Media Access Controller (MAC) and an + Ethernet PHY to enable 10BASE=E2=80=91T1S networks. The Ethernet Media A= ccess + Controller (MAC) module implements a 10 Mbps half duplex Ethernet MAC, + compatible with the IEEE 802.3 standard and a 10BASE-T1S physical layer + transceiver integrated into the S2500. The communication between + the host and the MAC-PHY is specified in the OPEN Alliance 10BASE-T1x + MACPHY Serial Interface (TC6). + +allOf: + - $ref: /schemas/net/ethernet-controller.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + const: onnn,s2500 + + reg: + maxItems: 1 + + interrupts: + description: + Interrupt from MAC-PHY asserted in the event of Receive Chunks + Available, Transmit Chunk Credits Available and Extended Status + Event. + maxItems: 1 + + spi-max-frequency: + maximum: 25000000 + +required: + - compatible + - reg + - interrupts + - spi-max-frequency + +unevaluatedProperties: false + +examples: + - | + #include + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethernet@0 { + compatible =3D "onnn,s2500"; + reg =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <ð0_pins>; + interrupt-parent =3D <&gpio>; + interrupts =3D <25 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency =3D <15000000>; + }; + }; --=20 2.43.0 From nobody Mon Jun 8 06:37:54 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B3D830F95F; Sat, 6 Jun 2026 05:42:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780724570; cv=none; b=ucWJsuaeMCuEdCXDBJyTvxGpdOTEwGeWpTn8Resyv+Eilq+TYx85XaA5GvvW19POydV2aLS972S3Lt0g/D2FG3EmrzqJR/TsLvPuL89wjt5c/mdmOQcKC79cwoK2zXxm0+OuZAhq3O5CrBVOmzgj3/9CRBTmqGaUitfTgt9iqlw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780724570; c=relaxed/simple; bh=LwObKbMYH5trZ9xLMT05dZHy//hBzE5Yhld+T95HsCU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MMTttzEvS/bVz+o/PNAuMA2xgloBPSPIJWKquEGOItVodhuVD4qVjiNXf89uFLxHOwWEm3S6TzDMhn9QG5VmjQbOODM1u9jlbsGHOnLYN+At9X69BOscUUyw7FZG26BAyI3ispnMRkVIuQE48FN7adWLHC807euV4rcqH49CPzU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=p53DixIh; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="p53DixIh" Received: by smtp.kernel.org (Postfix) with ESMTPS id 3AF4BC2BCFC; Sat, 6 Jun 2026 05:42:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1780724570; bh=LwObKbMYH5trZ9xLMT05dZHy//hBzE5Yhld+T95HsCU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=p53DixIhEszCg6onyjTt0EzJ/lU/vnhSiUhDxpyYl0oAXq6qJa9APftdf56Aesh4n GgyovOcrU34yMeQBfL5jIbpo3WPFuYMhsNDUls4CeJpRKATJ1EyLCIQoxUczszkH3t 1gQ3Eyq2E92w1qj6UH27zoHnOF+/IyNSiZ3/PYRRPYhB+LQ6hJ0aaZYV+bHqse4c8C tjGYUa6IqNQgL/U6qIVnmBDejJDLbNgIyZudtbi8CcZBjP33p1X5uiWtdIzpco3X7g ekLMJ/Zl/LBnmT8S/3XT2XpAZlX+Du9CiSi7BURJXQm4IwpH/dcB+G3YgD7jT7BcMH jihxbiJrwSHnQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 342A7CD8C93; Sat, 6 Jun 2026 05:42:50 +0000 (UTC) From: Selvamani Rajagopal via B4 Relay Date: Fri, 05 Jun 2026 22:42:47 -0700 Subject: [PATCH net-next v4 16/16] Documentation: networking: Add timestamp related APIs to OA TC6 framework Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260605-s2500-mac-phy-support-v4-16-de0fbc13c6d8@onsemi.com> References: <20260605-s2500-mac-phy-support-v4-0-de0fbc13c6d8@onsemi.com> In-Reply-To: <20260605-s2500-mac-phy-support-v4-0-de0fbc13c6d8@onsemi.com> To: Andrew Lunn , Piergiorgio Beruto , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Parthiban Veerasooran , Selva Rajagopal , Richard Cochran , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Simon Horman , Jonathan Corbet , Shuah Khan Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, Jerry Ray , Selvamani Rajagopal X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780724562; l=4814; i=Selvamani.Rajagopal@onsemi.com; s=20260531; h=from:subject:message-id; bh=qMIzLX0eC5ihmFdaKnhKOPCk6N1TEOL8NPk1LNjEmH4=; b=K/RVcj2az8TbAlcs1pGNk3cydG43TjXs/KRPyZsvcKVB3OaD4G9k8JQhjkhDTT5aAmn8cLobV zxHaDTIL7c0D3+u/dd3GjUT4UkNsmV0Hi2iBU3pP3IYSv9MncQfKNMF X-Developer-Key: i=Selvamani.Rajagopal@onsemi.com; a=ed25519; pk=5QRdM0HS/LGWWcUZZ9hVfZ+qbPQGZCumcTXOiN7Fyug= X-Endpoint-Received: by B4 Relay for Selvamani.Rajagopal@onsemi.com/20260531 with auth_id=803 X-Original-From: Selvamani Rajagopal Reply-To: Selvamani.Rajagopal@onsemi.com From: Selvamani Rajagopal Added new APIs to support hardware timestamp feature as defined in OPEN Alliance 10BASE-T1x MAC-PHY serial interface specification. Signed-off-by: Selvamani Rajagopal --- Documentation/networking/oa-tc6-framework.rst | 76 +++++++++++++++++++++++= ++++ 1 file changed, 76 insertions(+) diff --git a/Documentation/networking/oa-tc6-framework.rst b/Documentation/= networking/oa-tc6-framework.rst index fe2aabde923a..694d9485b1c5 100644 --- a/Documentation/networking/oa-tc6-framework.rst +++ b/Documentation/networking/oa-tc6-framework.rst @@ -153,6 +153,10 @@ OPEN Alliance TC6 Framework - Forwards the received Ethernet frame from 10Base-T1x MAC-PHY to n/w subsystem. =20 +- If supported by the hardware and enabled, updates hardware timestamp + in skb, when indicated by one of the three timestamp capture registers + through TSC fields of the header. + Data Transaction ~~~~~~~~~~~~~~~~ =20 @@ -495,3 +499,75 @@ the MAC-PHY. Zero align receive frame feature can be enabled to align all receive ether= net frames data to start at the beginning of any receive data chunk payload wi= th a start word offset (SWO) of zero. + +.. c:function:: int oa_tc6_ptp_register(struct oa_tc6 *tc6, \ + struct ptp_clock_info *info); + +Registers the PTP hardware clock related functions with the kernel. +This API simply registers. Initialization of the fields in the +ptp_clock_info structure are left to the vendor as programming hardware +timer is expected to be vendor dependent. The fields max_adj, owner, +and all the functions for the clock operations, like adjfine, gettimex64, +settime64, adjtime are expected to be initialized in the structure before +calling the registering the hardware clock. + +.. c:function:: void oa_tc6_ptp_unregister(struct oa_tc6 *tc6); + +Unregisters the PTP hardware clock related callbacks. + +.. c:function:: int oa_tc6_ioctl(struct oa_tc6 *tc6, struct ifreq *rq, \ + int cmd); + +ioctl interface to handle hardware timestamp and PHY related commands. + +.. c:function:: int oa_tc6_get_ts_info(struct oa_tc6 *tc6, \ + struct kernel_ethtool_ts_info *info= ); + +Provides timestamp related settings that are supported to ethtool. + +.. c:function:: void oa_tc6_hwtstamp_get(struct oa_tc6 *tc6, \ + struct kernel_hwtstamp_config *cf= g); + +Returns hardware timestamp configuration. Part of net_device_ops callbacks. + +.. c:function:: void oa_tc6_get_ts_stats(struct oa_tc6 *tc6, \ + struct ethtool_ts_stats *ts_stats= ); + +Provides hardware timestamp related traffic statistics for ethtool. + +.. c:function:: int oa_tc6_hwtstamp_set(struct oa_tc6 *tc6, \ + struct kernel_hwtstamp_config *cf= g); + +Helper to set hardware timestamp configuration. Part of net_device_ops +callbacks. + +.. c:function:: void oa_tc6_set_vend1_mms(struct oa_tc6 *tc6, int mms); + +Helper to map MDIO_MMD_VEND1 command to vendor specific Memory Map Select +(MMS) value. This function offers flexibility for vendors that may have +used any MMS value between 10 and 15 as allowed by the specification. +MDIO_MMD_VEND2 is already mapped to MMS4 in the OA TC6 frame work code. + +.. c:function:: int oa_tc6_write_registers_mms(struct oa_tc6 *tc6, \ + u16 address, u16 mms, \ + u32 value[], u8 length); +Writing multiple consecutive registers starting from @address for the +given @mms memory map selector in the MAC-PHY. Maximum of 128 consecutive +registers can be written starting at @address. + +.. c:function:: int oa_tc6_write_register_mms(struct oa_tc6 *tc6, \ + u16 address, u16 mms, \ + u32 value); +Write a single register addressed by @address and @mms in the MAC-PHY. + +.. c:function:: int oa_tc6_read_registers_mms(struct oa_tc6 *tc6, \ + u16 address, u16 mms, \ + u32 value[], u8 length); +Reading multiple consecutive registers starting from @address for the +given @mms memory map selector value, in the MAC-PHY. Maximum of 128 +consecutive registers can be read starting at @address. + +.. c:function:: int oa_tc6_read_register_mms(struct oa_tc6 *tc6, \ + u16 address, u16 mms, \ + u32 *value); +Read a single register addressed by @address and @mms in the MAC-PHY. --=20 2.43.0