From nobody Mon Jun 8 05:26:57 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 051E6346A11; Fri, 5 Jun 2026 13:14:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780665285; cv=none; b=lLpKxwxyiK55niEODBO6ZmWnmZFPc1mBeP6LbKNIEGH9IT5ikz4LuwL1RII6c/uB4bBUApGYkK0fgSZnhb8NmjQeQ6iKesgBpjov8SuQfjLbAfjTPOZfyk/kNVnK2WfJhoRXhsM9vuB4x4NtREap/9xGRPR6wAkx5Hw1MxVPbSI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780665285; c=relaxed/simple; bh=l4eCm8AIWkDUoE3WTsV7Zxme0lc2GyFF0+eYcS0+My8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GPJrr/VsiQxIfAGbMk8lXsh4RekDMABx4ybapmgDY2lUmPPbTp1oSKFzvg1gZFBmjEkr219QJMmw9vqX2+jDCxz+RmeDwI/qVt2GLixjFDvBywfdHlMv24h5To4UGojVaDBvEsh0aaWerGxIJatuBuHFOcLRKIZockCJ+CqDn1M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=s5mS2nEf; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="s5mS2nEf" Received: by smtp.kernel.org (Postfix) with ESMTPS id C7994C4AF09; Fri, 5 Jun 2026 13:14:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1780665284; bh=l4eCm8AIWkDUoE3WTsV7Zxme0lc2GyFF0+eYcS0+My8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=s5mS2nEfOBlkx4J3RDvaXUfGZPebNDzwJtzyun/uf6Q7ZIYiI3bTSc9enz76Qt5S+ pamXgaxTe9lkCf/tomi/pjU6Wgz4XNKTiZqPzs67cohHl5bur1J392Z9vOCb0gSeTG 1pWAq4M++H3qFhR5TPs2rf20xNi9UlKxhg8j1Cj5+18KlJwB4B63a5FbPY2bHMl97p jWssh5GDyjupaczgJJP+1iLT57ve23dYEt9hYv4pYs4U9kSJldoZOOVGkDa+4jm0at Lz6WHJM20GbAezeUKH4sQo8L9N97xYTpZbC9h9LggTUw2quotVIoXjxbpVQyjUsmxh lkZDCDvlwPMnw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B220BCD6E79; Fri, 5 Jun 2026 13:14:44 +0000 (UTC) From: David Heidelberg via B4 Relay Date: Fri, 05 Jun 2026 15:14:39 +0200 Subject: [PATCH v7 1/8] media: qcom: camss: csiphy: Introduce PHY configuration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260605-qcom-cphy-v7-1-426c37e9008f@ixit.cz> References: <20260605-qcom-cphy-v7-0-426c37e9008f@ixit.cz> In-Reply-To: <20260605-qcom-cphy-v7-0-426c37e9008f@ixit.cz> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Luca Weiss , Petr Hodina , "Dr. Git" , Cory Keitz , Loic Poulain Cc: Frank Li , Konrad Dybcio , Kieran Bingham , Sakari Ailus , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2428; i=david@ixit.cz; h=from:subject:message-id; bh=X7AOYJ4niyGHoBf3ode1cySyXfbTbBCjzlnLn/fppe8=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBqIsvCpu23xb+dSDehsmAwNCCye+poRgbnQOPcd 6HygHQq2AyJAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCaiLLwgAKCRBgAj/E00kg cj1FEADGAFYTnBOK/L90yh7uUSeCg/culB5FYvWKvrfqnqn5SM9ItCYKX1j9Zkw95EP74s8G091 5QfxrSuwSwjW0TfcP2roJasvQhLLtV1G3ryQUN+EjZB2g0xEKyeGai+s75T/NairKkKwJgRIsdO wgWAUqEwVK4omfo5/bGmNQRUGceIPKUrXUmNnzQXnzXGwH7TQHwJ3cS8SEa47P13o1tgFTs/lSK qXEqhL1rDejKpDSCGtx/0/22ltpoKTE8RRMO6KhRbe+hZUYv5tNb+9rhQA5XaFd97mjXiNB/Kz3 G5bpZgvLv/dMIzwzTJ8BMml9YkY4bJTv63CzSe4MML0oDFxNQk/blDgRpXxFQtCrvvTcwKRU8BR KPsSnJBG/BzGVbAR4hkzPFGJuRnfsSissJuzZq9JOSWTSOfkATg/ge0B/jWzUOw6574Jp+pO/A4 tQP9JVyHx0ywKMlpM3wKtq1y3UWtIHIsZBecBcMYrMhni196ijlICrXcEXGV9XuOIyGuLTD8iXP PDSwZiv40mKqKWA5W49z3Vsps/uQ6VG+Qo7Z94JQCcfYAo8Y6ce/UNa0Z0KSogoqsJNL8N832QD zFKgrUtb0cA4hVvML33pmnsszFQJq0r5skSkE5NWm5cLIdQo92WArCE3iKry85cvTq1/8XOYJKI fNqYWdYCSinnZMw== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg Read PHY configuration from the device-tree bus-type and save it into the csiphy structure for later use. For C-PHY, skip clock line configuration, as there is none. Acked-by: Cory Keitz Reviewed-by: Bryan O'Donoghue Reviewed-by: Frank Li Signed-off-by: David Heidelberg --- drivers/media/platform/qcom/camss/camss-csiphy.h | 2 ++ drivers/media/platform/qcom/camss/camss.c | 8 ++++++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.h b/drivers/med= ia/platform/qcom/camss/camss-csiphy.h index 9d9657b82f748..2ebb307be18ba 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy.h +++ b/drivers/media/platform/qcom/camss/camss-csiphy.h @@ -25,21 +25,23 @@ =20 struct csiphy_lane { u8 pos; u8 pol; }; =20 /** * struct csiphy_lanes_cfg - CSIPHY lanes configuration + * @phy_cfg: interface selection (C-PHY or D-PHY) * @num_data: number of data lanes * @data: data lanes configuration * @clk: clock lane configuration (only for D-PHY) */ struct csiphy_lanes_cfg { + enum v4l2_mbus_type phy_cfg; int num_data; struct csiphy_lane *data; struct csiphy_lane clk; }; =20 struct csiphy_csi2_cfg { struct csiphy_lanes_cfg lane_cfg; }; diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index 2123f6388e3d7..072c428e25166 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -4761,19 +4761,23 @@ static int camss_parse_endpoint_node(struct device = *dev, if (vep.bus_type !=3D V4L2_MBUS_CSI2_DPHY) { dev_err(dev, "Unsupported bus type %d\n", vep.bus_type); return -EINVAL; } =20 csd->interface.csiphy_id =3D vep.base.port; =20 mipi_csi2 =3D &vep.bus.mipi_csi2; - lncfg->clk.pos =3D mipi_csi2->clock_lane; - lncfg->clk.pol =3D mipi_csi2->lane_polarities[0]; lncfg->num_data =3D mipi_csi2->num_data_lanes; + lncfg->phy_cfg =3D vep.bus_type; + + if (lncfg->phy_cfg !=3D V4L2_MBUS_CSI2_CPHY) { + lncfg->clk.pos =3D mipi_csi2->clock_lane; + lncfg->clk.pol =3D mipi_csi2->lane_polarities[0]; + } =20 lncfg->data =3D devm_kcalloc(dev, lncfg->num_data, sizeof(*lncfg->data), GFP_KERNEL); if (!lncfg->data) return -ENOMEM; =20 for (i =3D 0; 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Fri, 5 Jun 2026 13:14:44 +0000 (UTC) From: David Heidelberg via B4 Relay Date: Fri, 05 Jun 2026 15:14:40 +0200 Subject: [PATCH v7 2/8] media: qcom: camss: csiphy-3ph: Use odd bits for configuring C-PHY lanes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260605-qcom-cphy-v7-2-426c37e9008f@ixit.cz> References: <20260605-qcom-cphy-v7-0-426c37e9008f@ixit.cz> In-Reply-To: <20260605-qcom-cphy-v7-0-426c37e9008f@ixit.cz> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Luca Weiss , Petr Hodina , "Dr. Git" , Cory Keitz , Loic Poulain Cc: Frank Li , Konrad Dybcio , Kieran Bingham , Sakari Ailus , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg So far, only D-PHY mode was supported, which uses even bits when enabling or masking lanes. For C-PHY configuration, the hardware instead requires using the odd bits. Since there can be unrecognized configuration allow returning failure. Acked-by: Cory Keitz Reviewed-by: Bryan O'Donoghue Reviewed-by: Bryan O'Donoghue Signed-off-by: David Heidelberg --- .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 39 +++++++++++++++++-= ---- 1 file changed, 31 insertions(+), 8 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/dri= vers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index dac8d2ecf7995..fa24fc9706748 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -9,16 +9,17 @@ */ =20 #include "camss.h" #include "camss-csiphy.h" =20 #include #include #include +#include =20 #define CSIPHY_3PH_LNn_CFG1(n) (0x000 + 0x100 * (n)) #define CSIPHY_3PH_LNn_CFG1_SWI_REC_DLY_PRG (BIT(7) | BIT(6)) #define CSIPHY_3PH_LNn_CFG2(n) (0x004 + 0x100 * (n)) #define CSIPHY_3PH_LNn_CFG2_LP_REC_EN_INT BIT(3) #define CSIPHY_3PH_LNn_CFG3(n) (0x008 + 0x100 * (n)) #define CSIPHY_3PH_LNn_CFG4(n) (0x00c + 0x100 * (n)) #define CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS 0xa4 @@ -1108,23 +1109,32 @@ static void csiphy_gen2_config_lanes(struct csiphy_= device *csiphy, writel_relaxed(val, csiphy->base + r->reg_addr); if (r->delay_us) udelay(r->delay_us); } } =20 static u8 csiphy_get_lane_mask(struct csiphy_lanes_cfg *lane_cfg) { - u8 lane_mask; - int i; + u8 lane_mask =3D 0; + u8 offset =3D 0; =20 - lane_mask =3D CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE; + switch (lane_cfg->phy_cfg) { + case V4L2_MBUS_CSI2_CPHY: + offset =3D 1; + break; + case V4L2_MBUS_CSI2_DPHY: + lane_mask =3D CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE; + break; + default: + break; + } =20 - for (i =3D 0; i < lane_cfg->num_data; i++) - lane_mask |=3D 1 << lane_cfg->data[i].pos; + for (int i =3D 0; i < lane_cfg->num_data; i++) + lane_mask |=3D BIT(lane_cfg->data[i].pos + offset); =20 return lane_mask; } =20 static bool csiphy_is_gen2(u32 version) { bool ret =3D false; =20 @@ -1155,19 +1165,32 @@ static void csiphy_lanes_enable(struct csiphy_devic= e *csiphy, struct csiphy_lanes_cfg *c =3D &cfg->csi2->lane_cfg; struct csiphy_device_regs *regs =3D csiphy->regs; u8 settle_cnt; u8 val; int i; =20 settle_cnt =3D csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260605-qcom-cphy-v7-3-426c37e9008f@ixit.cz> References: <20260605-qcom-cphy-v7-0-426c37e9008f@ixit.cz> In-Reply-To: <20260605-qcom-cphy-v7-0-426c37e9008f@ixit.cz> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Luca Weiss , Petr Hodina , "Dr. Git" , Cory Keitz , Loic Poulain Cc: Frank Li , Konrad Dybcio , Kieran Bingham , Sakari Ailus , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=3748; i=david@ixit.cz; h=from:subject:message-id; bh=w/BmjNZrtM9iVXxgRAPn/+3YAOZus8HvqEheY9VGpkA=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBqIsvC720GloCvKSrUdWoJHW9yH5S8fZZx8ZZUW eiwBk+VUtaJAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCaiLLwgAKCRBgAj/E00kg cgzPD/90mTBjxORQUjdW/yQkbGV3rbvndX6tqDlR6RRh4H4iOTG9R7A5m5JPoy5Po1J1YurpTDg Ios035YiB8640A8THnMWYrHVHzmdGn2CbnoA8DK5ZC7yIvKcfLfnyOae4eMPm/lkRRI8Bv6tuM0 1guJLlISwtMy8KC4viw3NSecDGrdOw181wa/OyHzw/v64QwHFzJKtb83dt+qykGjibd3A80fmaS hNWOM4/iUyJXLQkDh/s/aVc7gRIbamZQIIi69+7p66UkOULUpRXvaFyszgHibppxSPiiiuAWkHT EqyzX+JlM4Z9C2nqCHenIi+/DuZjChCvbZ7KXllW9PR13vtfmJbADT2DjMwklLeKFZwTF+d7p+u BVcKPZPaBogYZE41ZbJumOsdMFj3JNoOv6PuM7Tezf2dZMALqGKJxAPakuOkXXWj7/+N/pqFkBY EeT5A2uxfYIiIi5GS+iXuHWnBf3wi1aArr1EhlE+t3V5g1wJr5GNWWTtKnH2DLgp2/D3A0/yAfu S1E20v/R1aTWPBedrrrLJX4/aX6kxSCWlFdVBDXV3c9FYxq6agWRULCQ9a/zkUntKQIVLuGTL9/ 9ArttGJPCRCd6KeUMHQhaD/HCgQHx1QMagliP8f+MZWoAPoXHTLVT8w+/uqYyLB8jvFGgSmYCnW aPMKR/UFQ1UgDBg== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg Inherit C-PHY information from CSIPHY, so we can configure CSID properly. CSI2_RX_CFG0_PHY_TYPE_SEL must be set to 1, when C-PHY mode is used. Reviewed-by: Bryan O'Donoghue Acked-by: Cory Keitz Signed-off-by: David Heidelberg --- drivers/media/platform/qcom/camss/camss-csid-gen2.c | 1 + drivers/media/platform/qcom/camss/camss-csid.c | 5 +++++ drivers/media/platform/qcom/camss/camss-csid.h | 6 ++++++ 3 files changed, 12 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen2.c b/drivers/= media/platform/qcom/camss/camss-csid-gen2.c index eadcb2f7e3aaa..a5b406cc8ead3 100644 --- a/drivers/media/platform/qcom/camss/camss-csid-gen2.c +++ b/drivers/media/platform/qcom/camss/camss-csid-gen2.c @@ -178,16 +178,17 @@ static void __csid_configure_rx(struct csid_device *c= sid, int val; =20 if (!lane_cnt) lane_cnt =3D 4; =20 val =3D (lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES; val |=3D phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL; val |=3D phy->csiphy_id << CSI2_RX_CFG0_PHY_NUM_SEL; + val |=3D csid->phy.phy_sel << CSI2_RX_CFG0_PHY_TYPE_SEL; writel_relaxed(val, csid->base + CSID_CSI2_RX_CFG0); =20 val =3D 1 << CSI2_RX_CFG1_PACKET_ECC_CORRECTION_EN; if (vc > 3) val |=3D 1 << CSI2_RX_CFG1_VC_MODE; val |=3D 1 << CSI2_RX_CFG1_MISR_EN; writel_relaxed(val, csid->base + CSID_CSI2_RX_CFG1); } diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media= /platform/qcom/camss/camss-csid.c index 48459b46a981b..bcc34ac9dd212 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.c +++ b/drivers/media/platform/qcom/camss/camss-csid.c @@ -1286,16 +1286,21 @@ static int csid_link_setup(struct media_entity *ent= ity, /* do no allow a link from CSIPHY to CSID */ if (!csiphy->cfg.csi2) return -EPERM; =20 csid->phy.csiphy_id =3D csiphy->id; =20 lane_cfg =3D &csiphy->cfg.csi2->lane_cfg; csid->phy.lane_cnt =3D lane_cfg->num_data; + if (lane_cfg->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY) + csid->phy.phy_sel =3D CSID_PHY_SEL_CPHY; + else + csid->phy.phy_sel =3D CSID_PHY_SEL_DPHY; + csid->phy.lane_assign =3D csid_get_lane_assign(lane_cfg, lane_cfg->num_= data); csid->tpg_linked =3D false; } } /* Decide which virtual channels to enable based on which source pads are= enabled */ if (local->flags & MEDIA_PAD_FL_SOURCE) { struct v4l2_subdev *sd =3D media_entity_to_v4l2_subdev(entity); struct csid_device *csid =3D v4l2_get_subdevdata(sd); diff --git a/drivers/media/platform/qcom/camss/camss-csid.h b/drivers/media= /platform/qcom/camss/camss-csid.h index 5296b10f6bac8..e65590b0df69f 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.h +++ b/drivers/media/platform/qcom/camss/camss-csid.h @@ -39,16 +39,21 @@ enum csid_testgen_mode { CSID_PAYLOAD_MODE_USER_SPECIFIED =3D 6, CSID_PAYLOAD_MODE_NUM_SUPPORTED_GEN1 =3D 6, /* excluding disabled */ CSID_PAYLOAD_MODE_COMPLEX_PATTERN =3D 7, CSID_PAYLOAD_MODE_COLOR_BOX =3D 8, CSID_PAYLOAD_MODE_COLOR_BARS =3D 9, CSID_PAYLOAD_MODE_NUM_SUPPORTED_GEN2 =3D 9, /* excluding disabled */ }; =20 +enum csid_phy_sel { + CSID_PHY_SEL_DPHY =3D 0, + CSID_PHY_SEL_CPHY =3D 1 +}; + struct csid_format_info { u32 code; u8 data_type; u8 decode_format; u8 bpp; u8 spp; /* bus samples per pixel */ }; =20 @@ -65,16 +70,17 @@ struct csid_testgen_config { }; =20 struct csid_phy_config { u8 csiphy_id; u8 lane_cnt; u32 lane_assign; u32 en_vc; u8 need_vc_update; + enum csid_phy_sel phy_sel; }; =20 struct csid_device; =20 struct csid_hw_ops { /* * configure_stream - Configures and starts CSID input stream * @csid: CSID device --=20 2.53.0 From nobody Mon Jun 8 05:26:57 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3344B3B14C7; Fri, 5 Jun 2026 13:14:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780665285; cv=none; b=GwSWG7reFwj1lgVBFPf2Wk/RtYHOy349n6ZC9i056Wimt4wE5CdPlSuhPtmkLPxGQymkjxnsQBPDepr1t15ouSVxXgybBTYD7Z3CXWoj/CJlIRR4ChPGOERq5n1Vav3K/DxzJh6a5eS643wVSie7mfHg76qjEEYn0xKikAiK+iM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780665285; c=relaxed/simple; bh=VikAopXonkwBc0/7WJEzwivJGuf0Jcu9EJcpBRPLbCQ=; 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Fri, 5 Jun 2026 13:14:45 +0000 (UTC) From: David Heidelberg via B4 Relay Date: Fri, 05 Jun 2026 15:14:42 +0200 Subject: [PATCH v7 4/8] media: qcom: camss: Initialize lanes after lane configuration is available Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260605-qcom-cphy-v7-4-426c37e9008f@ixit.cz> References: <20260605-qcom-cphy-v7-0-426c37e9008f@ixit.cz> In-Reply-To: <20260605-qcom-cphy-v7-0-426c37e9008f@ixit.cz> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Luca Weiss , Petr Hodina , "Dr. Git" , Cory Keitz , Loic Poulain Cc: Frank Li , Konrad Dybcio , Kieran Bingham , Sakari Ailus , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=6060; i=david@ixit.cz; h=from:subject:message-id; bh=DuKX1oNfR8y3OMNQXdywJD7AgjuKHAViX5JlE8vDsfY=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBqIsvCgCJC3yL9/K5cZeg/SiUsk+Z6+amT/A89e B3eoqBiReiJAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCaiLLwgAKCRBgAj/E00kg cljmD/9j5rAl6uqQbG0Uk9dv/YJZMUsRUYoXcFEkVmixARShoie+URorkdRIY4T0GqFKDry0qgR Vt70IIh5tzBGs2BRcQZzTS89sv4JLMODKKJWhIsXKh5TzGR2WyAlhpvcnopgaVm3RetrOtidL3I k3A7cUr1UUgG28YDyNVM+KLDqzE0EyUf3rW6RboK9tQPfVWi1W8DKd6+Fn7IrGfeUcEBi7ZHTMW w7ek4R8uTV6ezm4agIU2eUCHH4LHTcWc39UtWRvnaQ0Hiwc9jFpLqhcXBUCD/B5wocJ6K1tbjkM elcumWpuViKpd16ThNR0cMbTkacz7/cb2liafmNaFGEw7zgh9YhztV7YtKzblkBlOK/jo+blMKS wRXWi4zxE04Ba1vabgt1nca1DtdrDC6zRsTv607Xgwajrr13WL4aW71XY320Sip+08U6QLKwswn SjdW+N3wBgTxtf881yrunNpQfBmqECZzgEgielmDkZrq3RXunrYm0HwyRzjmC0SV2/Bay+svOUa HLAgEfACbAkFSUZ3QdoGL1WmGuimcDLLoy5VIZtkDoMv/wQ3ttPD7cg5ZChPp6iUYE8sClhaNsv QIOtr8oq03GHkQOVkGNAY6+v/ytoIhFK8DDLUr/v7/+dpa4f1gAxDvtq7bCAq/STBSrtqDHA7CT MBppX68jitgydzQ== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg The lanes must not be initialized before the driver has access to the lane configuration, as it depends on whether D-PHY or C-PHY mode is in use. Move the lane initialization to csiphy_lanes_enable which is called when the configuration structures are available. Co-developed-by: Petr Hodina Signed-off-by: Petr Hodina Reviewed-by: Bryan O'Donoghue Acked-by: Cory Keitz Reviewed-by: Frank Li Signed-off-by: David Heidelberg --- .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 131 +++++++++++++++--= ---- 1 file changed, 93 insertions(+), 38 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/dri= vers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index fa24fc9706748..c76b9c352ea02 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -1163,16 +1163,108 @@ static void csiphy_lanes_enable(struct csiphy_devi= ce *csiphy, s64 link_freq, u8 lane_mask) { struct csiphy_lanes_cfg *c =3D &cfg->csi2->lane_cfg; struct csiphy_device_regs *regs =3D csiphy->regs; u8 settle_cnt; u8 val; int i; =20 + switch (csiphy->camss->res->version) { + case CAMSS_845: + if (c->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY) { + regs->lane_regs =3D NULL; + regs->lane_array_size =3D 0; + } else { + regs->lane_regs =3D &lane_regs_sdm845[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sdm845); + } + break; + case CAMSS_2290: + case CAMSS_6150: + if (c->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY) { + regs->lane_regs =3D NULL; + regs->lane_array_size =3D 0; + } else { + regs->lane_regs =3D &lane_regs_qcm2290[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_qcm2290); + } + break; + case CAMSS_6350: + if (c->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY) { + regs->lane_regs =3D NULL; + regs->lane_array_size =3D 0; + } else { + regs->lane_regs =3D &lane_regs_sm6350[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm6350); + } + break; + case CAMSS_7280: + case CAMSS_8250: + if (c->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY) { + regs->lane_regs =3D NULL; + regs->lane_array_size =3D 0; + } else { + regs->lane_regs =3D &lane_regs_sm8250[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm8250); + } + break; + case CAMSS_8280XP: + if (c->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY) { + regs->lane_regs =3D NULL; + regs->lane_array_size =3D 0; + } else { + regs->lane_regs =3D &lane_regs_sc8280xp[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sc8280xp); + } + break; + case CAMSS_X1E80100: + if (c->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY) { + regs->lane_regs =3D NULL; + regs->lane_array_size =3D 0; + } else { + regs->lane_regs =3D &lane_regs_x1e80100[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_x1e80100); + } + break; + case CAMSS_8550: + if (c->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY) { + regs->lane_regs =3D NULL; + regs->lane_array_size =3D 0; + } else { + regs->lane_regs =3D &lane_regs_sm8550[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm8550); + } + break; + case CAMSS_8650: + if (c->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY) { + regs->lane_regs =3D NULL; + regs->lane_array_size =3D 0; + } else { + regs->lane_regs =3D &lane_regs_sm8650[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm8650); + } + break; + case CAMSS_8300: + case CAMSS_8775P: + if (c->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY) { + regs->lane_regs =3D NULL; + regs->lane_array_size =3D 0; + } else { + regs->lane_regs =3D &lane_regs_sa8775p[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sa8775p); + } + break; + default: + break; + } + + if (!regs->lane_regs && c->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY) + WARN_ONCE(1, "Missing lane_regs definition for C-PHY!\n"); + settle_cnt =3D csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate); =20 val =3D 0; =20 switch (c->phy_cfg) { case V4L2_MBUS_CSI2_CPHY: for (i =3D 0; i < c->num_data; i++) val |=3D BIT((c->data[i].pos * 2) + 1); @@ -1231,63 +1323,26 @@ static int csiphy_init(struct csiphy_device *csiphy) struct device *dev =3D csiphy->camss->dev; struct csiphy_device_regs *regs; =20 regs =3D devm_kmalloc(dev, sizeof(*regs), GFP_KERNEL); if (!regs) return -ENOMEM; =20 csiphy->regs =3D regs; - regs->offset =3D 0x800; regs->common_status_offset =3D 0xb0; =20 switch (csiphy->camss->res->version) { - case CAMSS_845: - regs->lane_regs =3D &lane_regs_sdm845[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sdm845); - break; - case CAMSS_2290: - case CAMSS_6150: - regs->lane_regs =3D &lane_regs_qcm2290[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_qcm2290); - break; - case CAMSS_6350: - regs->lane_regs =3D &lane_regs_sm6350[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm6350); - break; - case CAMSS_7280: - case CAMSS_8250: - regs->lane_regs =3D &lane_regs_sm8250[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm8250); - break; - case CAMSS_8280XP: - regs->lane_regs =3D &lane_regs_sc8280xp[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sc8280xp); - break; case CAMSS_X1E80100: - regs->lane_regs =3D &lane_regs_x1e80100[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_x1e80100); - regs->offset =3D 0x1000; - break; case CAMSS_8550: - regs->lane_regs =3D &lane_regs_sm8550[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm8550); - regs->offset =3D 0x1000; - break; case CAMSS_8650: - regs->lane_regs =3D &lane_regs_sm8650[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm8650); 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b=K5oESsTx4dvHW/xkRfRKvWre+cHYehrSFskr2a6UWIZETlyaMNAMM/FY3Dhp5JhEW iRMzwC9Mxb7eQ9IdEzvjVRvyzANWu3WzNh3D2pxcmFXcZcSjR38MSgow6Xbi6omvSp 0C71lp8KUpj4X6ucY4RfWZke7PMc+cvkjw5piKJdH9PoRhBx2RXjTNDXCkt4xfoN9w 6wvbrWDTM/ZGYrY8UqTC7Z5uzSyIsAHVVwxvX89vkK9OaJADJVtYJSptHnCjQC00iq asierIoM848pbM6x0a83Mo3YLByMg+sWN4mOnM8NGTHjfLUsbSMMU6GWmeCu6TrC/N PpyL8PHyQ3vUw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19B99CD6E79; Fri, 5 Jun 2026 13:14:45 +0000 (UTC) From: David Heidelberg via B4 Relay Date: Fri, 05 Jun 2026 15:14:43 +0200 Subject: [PATCH v7 5/8] media: qcom: camss: csiphy-3ph: Add Gen2 v1.1 MIPI CSI-2 C-PHY init Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260605-qcom-cphy-v7-5-426c37e9008f@ixit.cz> References: <20260605-qcom-cphy-v7-0-426c37e9008f@ixit.cz> In-Reply-To: <20260605-qcom-cphy-v7-0-426c37e9008f@ixit.cz> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Luca Weiss , Petr Hodina , "Dr. Git" , Cory Keitz , Loic Poulain Cc: Frank Li , Konrad Dybcio , Kieran Bingham , Sakari Ailus , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=8232; i=david@ixit.cz; h=from:subject:message-id; bh=NeGmnBkhZ68soS2dAMTGfqfmfG9QUzfl7mYceAqvo/k=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBqIsvC3naZSok2E8DGgSqGaK23MiBOh/2dsLphu YdQMqKBq/OJAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCaiLLwgAKCRBgAj/E00kg cgTCEAC9pF7IgU87ZqphDq4x2a0wGL3VRiB/XVrkdIGZZXGkOEWcVV3eDPBtKuyBtL82zHnJ4mh HkuIdVWn/PSaokFiMly2y6dZ0odN/tyuJzJXFasB2O8O3WBt6oBLZAiGgjKSVZN0XoPymHZ55A0 bmRWOVwoqwGUxhWkphKC6yZqqVL/aaTDa94HhLoUa3K6/2c0W1QVEeeBP/Jpw46jsUipSlJrutB gAu/85Z8FeHZW2vVKGxuPhUxiX8KGPcmPAkK8oc+vhpE6Fw8v9bpNu1YaohW5w7X0UdPgmQabbw 3p9RxmBm3rNAYTRGl40iTMEyW7sSpbiHOYTvl0mDciIFKMjATPQbaAN1NbC7Op3TXM6J+ZNYwTF Xd6ohKLLFmQ46oUUERgW+Bd2FBd4J/d1Y1gUDxq5eClsDGdgf20BwmUCun9IoC+nN7A8fFuYrP8 IVgCs+LRUXFuaw3IYUhkWnGDafXgxFVzS6ORVLXdAvUEtiKzZZs49Yg2G17d58V/nCZ1wL56DJM Q86ongHLlzSM/Rv3rTe3AOY556AHW9WJPBRIoz8y2HVjsvpAGFLNfLH1hO8IzN0ctousBSrMhTo DpsywL4YJyoWDOBr2TsLk+u0KIDjRxL+5jl1gNavQ3widvzD5KkVaxOPogyUZZu63iNY/DvMzU5 hNUw9qlb07I6UHg== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg Add a PHY configuration sequence for the sdm845 which uses a Qualcomm Gen 2 version 1.1 CSI-2 PHY. The PHY can be configured as two phase or three phase in C-PHY or D-PHY mode. This configuration supports three-phase C-PHY mode. Acked-by: Cory Keitz Signed-off-by: David Heidelberg --- .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 78 ++++++++++++++++++= +++- 1 file changed, 76 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/dri= vers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index c76b9c352ea02..d9136e422f45f 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -45,16 +45,23 @@ =20 #define CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(offset, n) ((offset) + 0x4 * (n)) #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE BIT(7) #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B BIT(0) #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID BIT(1) #define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(offset, common_status_offset, n)= \ ((offset) + (common_status_offset) + 0x4 * (n)) =20 +#define CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(n) \ + (0x0100 + ((n) * 0x4)) +#define CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(n) \ + (0x0300 + ((n) * 0x4)) +#define CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(n) \ + (0x0500 + ((n) * 0x4)) + #define CSIPHY_DEFAULT_PARAMS 0 #define CSIPHY_LANE_ENABLE 1 #define CSIPHY_SETTLE_CNT_LOWER_BYTE 2 #define CSIPHY_SETTLE_CNT_HIGHER_BYTE 3 #define CSIPHY_DNP_PARAMS 4 #define CSIPHY_2PH_REGS 5 #define CSIPHY_3PH_REGS 6 #define CSIPHY_SKEW_CAL 7 @@ -141,16 +148,17 @@ csiphy_lane_regs lane_regs_sa8775p[] =3D { {0x0460, 0xFD, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0464, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x065C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0660, 0xFD, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, }; =20 /* GEN2 1.0 2PH */ +/* 5 entries: clock + 4 lanes */ static const struct csiphy_lane_regs lane_regs_sdm845[] =3D { {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS}, @@ -215,16 +223,82 @@ csiphy_lane_regs lane_regs_sdm845[] =3D { {0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, {0x060C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0660, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, }; =20 +/* GEN2 1.0 3PH */ +/* 3 entries: 3 lanes (C-PHY) */ +static const struct +csiphy_lane_regs lane_regs_sdm845_3ph[] =3D { + {CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(23), 0x43, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(26), 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(27), 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(1), 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(3), 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_B= YTE}, + {CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(2), 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_= BYTE}, + {CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(5), 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(20), 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(6), 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(7), 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(8), 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(9), 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(10), 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(11), 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(17), 0x12, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(24), 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(51), 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(25), 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(55), 0x51, 0x00, CSIPHY_DEFAULT_PARAMS}, + + {CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(23), 0x43, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(26), 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(27), 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(1), 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(3), 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_B= YTE}, + {CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(2), 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_= BYTE}, + {CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(5), 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(20), 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(6), 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(7), 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(8), 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(9), 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(10), 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(11), 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(17), 0x12, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(24), 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(51), 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(25), 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(55), 0x51, 0x00, CSIPHY_DEFAULT_PARAMS}, + + {CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(23), 0x43, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(26), 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(27), 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(1), 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(3), 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_B= YTE}, + {CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(2), 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_= BYTE}, + {CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(5), 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(20), 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(6), 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(7), 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(8), 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(9), 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(10), 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(11), 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(17), 0x12, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(24), 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(51), 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(25), 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(55), 0x51, 0x00, CSIPHY_DEFAULT_PARAMS}, + +}; + /* GEN2 1.1 2PH */ static const struct csiphy_lane_regs lane_regs_sc8280xp[] =3D { {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0034, 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(Postfix) with ESMTP id 31C50CD6E7C; Fri, 5 Jun 2026 13:14:45 +0000 (UTC) From: David Heidelberg via B4 Relay Date: Fri, 05 Jun 2026 15:14:44 +0200 Subject: [PATCH v7 6/8] media: qcom: camss: csiphy-3ph: Update Gen2 v1.1 MIPI CSI-2 C-PHY init Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260605-qcom-cphy-v7-6-426c37e9008f@ixit.cz> References: <20260605-qcom-cphy-v7-0-426c37e9008f@ixit.cz> In-Reply-To: <20260605-qcom-cphy-v7-0-426c37e9008f@ixit.cz> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Luca Weiss , Petr Hodina , "Dr. Git" , Cory Keitz , Loic Poulain Cc: Frank Li , Konrad Dybcio , Kieran Bingham , Sakari Ailus , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=6215; i=david@ixit.cz; h=from:subject:message-id; bh=SXjFB04JrDA9iR06sMcig8Xokkk2vPb6Ou/ppZyqNBE=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBqIsvCKHVDZ5ehtMjQq6XbMEgL9vKAFBnVP01m4 yCh79EchmCJAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCaiLLwgAKCRBgAj/E00kg ciKzEACZgO8102EBmN0SrgoQUO4wpe5XrZqgzLgj/wFcYsnBc4VFQ59ysmfLo4iRTjeAunCbIbY 1jA4FfgsUOgVfNnx242PMDar9YJ3p4pQkY0NCRjmSM4vXAEvmjZG4Kht4GZLnQqQIrc/5ld9Yx9 9W+V3lQtgWf5LiO66rp7y2hj0dg7KTdk+nnW6CZpkTjnA0/mtuNki8ppLwfysbLqYSxxIkEfLlR nXLf/u6ssCiHoNiFS7ycTRLf7iO7iHVpdfzpYDUK3fJnOCGLkfGK7I2gdtR2LAVPlApRz8Wepfc US1VeQNw6YeDA2vqZB6+39S1YzcmgY7GRWh8v+seAsG9vjkGEtE4EiEIH7TjM/0QBxOoXxrBzNc lAS5oLYW/UK7tHDpn0DR42AZ37KED+vHMW4r9ZF0GC+Lt5ZBDof6XiUkJ+51EyWlgaaoRnntI+v KT0m7qIdMvWYFw0VAg1s0P7dk5m4KRdfmfZM0jr/rKfgDHLrZRXSfsH9oCMmtBtu4PeecmQPh2d 8YNLQYwMR8ZWT9DFLkJJQRA3bqXv7NKb/H/wMzauaPXBgnkaBbeBSaG+4U/U3G+iKQgWYuwmRdW rpRJAdmi2xMgcI++wUyqQUvKcwxsXjVavB5oGIDdnQaTbKWltr5Modnnb3rouY9Srn5FXx/FOQ7 CVcJqUs666QTIKw== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg These values should improve C-PHY behaviour. Should match most recent Qualcomm code. Acked-by: Cory Keitz Suggested-by: Konrad Dybcio Signed-off-by: David Heidelberg --- .../media/platform/qcom/camss/camss-csiphy-3ph-1-0.c | 19 +++++++++------= ---- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/dri= vers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index d9136e422f45f..feafe8cc45e02 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -227,19 +227,19 @@ csiphy_lane_regs lane_regs_sdm845[] =3D { {0x0660, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, }; =20 /* GEN2 1.0 3PH */ /* 3 entries: 3 lanes (C-PHY) */ static const struct csiphy_lane_regs lane_regs_sdm845_3ph[] =3D { - {CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(23), 0x43, 0x00, CSIPHY_DEFAULT_PARAMS}, - {CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(26), 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS}, - {CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(27), 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(23), 0x63, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(26), 0xac, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(27), 0xa5, 0x00, CSIPHY_DEFAULT_PARAMS}, {CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(1), 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, {CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(3), 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_B= YTE}, {CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(2), 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_= BYTE}, {CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(5), 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, {CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(20), 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(6), 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, {CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(7), 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, {CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(8), 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -247,19 +247,19 @@ csiphy_lane_regs lane_regs_sdm845_3ph[] =3D { {CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(10), 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(11), 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(17), 0x12, 0x00, CSIPHY_DEFAULT_PARAMS}, {CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(24), 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, {CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(51), 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, {CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(25), 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(55), 0x51, 0x00, CSIPHY_DEFAULT_PARAMS}, =20 - {CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(23), 0x43, 0x00, CSIPHY_DEFAULT_PARAMS}, - {CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(26), 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS}, - {CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(27), 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(23), 0x63, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(26), 0xac, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(27), 0xa5, 0x00, CSIPHY_DEFAULT_PARAMS}, {CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(1), 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, {CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(3), 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_B= YTE}, {CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(2), 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_= BYTE}, {CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(5), 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, {CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(20), 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(6), 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, {CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(7), 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, {CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(8), 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -267,36 +267,35 @@ csiphy_lane_regs lane_regs_sdm845_3ph[] =3D { {CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(10), 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(11), 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(17), 0x12, 0x00, CSIPHY_DEFAULT_PARAMS}, {CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(24), 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, {CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(51), 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, {CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(25), 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(55), 0x51, 0x00, CSIPHY_DEFAULT_PARAMS}, =20 - {CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(23), 0x43, 0x00, CSIPHY_DEFAULT_PARAMS}, - {CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(26), 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS}, - {CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(27), 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(23), 0x63, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(26), 0xac, 0x00, CSIPHY_DEFAULT_PARAMS}, + {CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(27), 0xa5, 0x00, CSIPHY_DEFAULT_PARAMS}, {CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(1), 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, {CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(3), 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_B= YTE}, {CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(2), 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_= BYTE}, {CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(5), 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, {CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(20), 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(6), 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, {CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(7), 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, {CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(8), 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, {CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(9), 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, {CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(10), 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(11), 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(17), 0x12, 0x00, CSIPHY_DEFAULT_PARAMS}, {CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(24), 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, {CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(51), 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, {CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(25), 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(55), 0x51, 0x00, CSIPHY_DEFAULT_PARAMS}, - }; =20 /* GEN2 1.1 2PH */ static const struct csiphy_lane_regs lane_regs_sc8280xp[] =3D { {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, --=20 2.53.0 From nobody Mon Jun 8 05:26:57 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C23A3EBF0C; Fri, 5 Jun 2026 13:14:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780665285; cv=none; b=FW74ClCvS3pu2DdPodm1sjIYCeFnofmRfLR8E9YiFErXKVtHHbyou2GqR9hYmVnvc3NU5ZMfVufm8Ty5X+KlaFAW1ToLXKl5svFUSYa0319dw9M/r+3q7LeAIZwiZshCzmDOHMa+Ijx4NE1IU/miulXYYs+tBASDbuEdDcrSxZc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780665285; c=relaxed/simple; bh=mIBpzoLsYYpzL9RT4TD3QA5kH0+SeiIoOs0i0v91v6k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hAZhGIAWWVCIyGnaapYtJwfn0OWSiyBWQrt+ZbokBZCh+RAjK2hwqrePOtmv783hpUBNcPWZjwGPDVltuo3gUlo4/G5gfq4Z1krsL85VlTOySTMtjArxa4qYO7ZllVg4MXXV5USdN/Ar7Or5wC7jfmWdbfcYx5/ZvyKguiCxY7o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=htrVUw75; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="htrVUw75" Received: by smtp.kernel.org (Postfix) with ESMTPS id 4F910C2BCF5; Fri, 5 Jun 2026 13:14:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1780665285; bh=mIBpzoLsYYpzL9RT4TD3QA5kH0+SeiIoOs0i0v91v6k=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=htrVUw75GL9u7Wv7F4ALh/1pw+TO8IY8ioUeyyuZwaX/AQ4LIFkJzjAaud1SxvcJ9 46/1CplsUMMpNPCL3phvrd7XPRUOtGkndzWjzdCDqdPmxqvKAGpcWvvuQqo87dex/4 TjOiHXa/t2Xq+erxWDQhH1i3ObJS1+FA8BVRabY6wggEUx/xd+UVDPtWnyG+gEsi1D tlMoTP70I7yrWg/9xndvKDm3ibOaZiZJI3L5vpwczohp7ttsfF1adJKHIgzmw92pcG wzbpcfZFpZOgTkRS2Q5oqVmMF6vqQbPK/UVKI077fj6Lfev59F4I5aRQhB9cAdMZCN WN3R1D2rGX3vw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48050CD8C81; Fri, 5 Jun 2026 13:14:45 +0000 (UTC) From: David Heidelberg via B4 Relay Date: Fri, 05 Jun 2026 15:14:45 +0200 Subject: [PATCH v7 7/8] media: qcom: camss: Account for C-PHY when calculating link frequency Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260605-qcom-cphy-v7-7-426c37e9008f@ixit.cz> References: <20260605-qcom-cphy-v7-0-426c37e9008f@ixit.cz> In-Reply-To: <20260605-qcom-cphy-v7-0-426c37e9008f@ixit.cz> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Luca Weiss , Petr Hodina , "Dr. Git" , Cory Keitz , Loic Poulain Cc: Frank Li , Konrad Dybcio , Kieran Bingham , Sakari Ailus , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=7531; i=david@ixit.cz; h=from:subject:message-id; bh=dMZP7gPqJE1k13DCIY0n4Cw62GBidlljoZhlTRnWYUw=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBqIsvCe9fI2Z2m7WNMuoJBBkcFloUwf1AEaJzYq ZEr2aImPSiJAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCaiLLwgAKCRBgAj/E00kg cjCwD/4j7P/BftQ0KhLdHfbG8D4aUp1Ssy0zS97Gscsel36ST3lcMNCnqfowCLuvgb2M1alciin RKWFc231DNE6YGPB5o1AKk1xtsW0pF1l0oi0gYa6NzQafojcgFJH1SOKRYkPExiIVHLFuNSgeZi iDRMes08mX9TruP36DjqJZRafjhFDCKa4H9HVXn/GSwq+cJAXJGEKoo0/Z3g3E/Qk65Z2FKlA0L GefQVgc0JLJM4EXoIrZyJGk0EfMNNmfUjSpxorgfI245h6IyEt32ULiYExfzHcG1lgn1dcCufVm 9gBOI86aOT59Dk20XBkXAzGiBcrFX6iSZLngGvI8t5C4+2rgznbR4Us4FjZJITnlz5di7V8jNnf eQ6FHlX1SV62d5U2Fq7h+0Pxkf4365dDDZxkoBWE36YfCl/JMZoy6AEmo/qhZv3m9UEsQZW1gxC B0dqazBJs3MVLowDqiUBXX3yXw2Po8wbsUt344hJin8KwA4BwGUtrxTkAAFuh7LRQRSRTB/uE6c gHJZbFgDLDKO6nXwwZlPBojI1/FBZTDHrR0I4WbTDJYhlqk9pG2Ee7oLZMqB9iqEeXJE7SJU8sH 8CbC7fYfzBUCZodbdmKZLsre9+0p0Kx0EqjrUCTE+oWg9BpGeOw6WTOH5+HXcpu6pAB7g+gBP7T xQhxaKBpRnGtzsg== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg Ensure that the link frequency divider correctly accounts for C-PHY operation. The divider differs between D-PHY and C-PHY, as described in the MIPI CSI-2 specification. For more details, see: https://docs.kernel.org/driver-api/media/tx-rx.html#pixel-rate Suggested-by: Sakari Ailus Acked-by: Cory Keitz Tested-by: Cory Keitz Reviewed-by: Bryan O'Donoghue Link: https://docs.kernel.org/driver-api/media/tx-rx.html#pixel-rate Signed-off-by: David Heidelberg --- drivers/media/platform/qcom/camss/camss-csid.c | 7 +++++-- drivers/media/platform/qcom/camss/camss-csiphy.c | 6 ++---- drivers/media/platform/qcom/camss/camss.c | 18 +++++++++++++++--- drivers/media/platform/qcom/camss/camss.h | 2 +- 4 files changed, 23 insertions(+), 10 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media= /platform/qcom/camss/camss-csid.c index bcc34ac9dd212..7415e811082da 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.c +++ b/drivers/media/platform/qcom/camss/camss-csid.c @@ -534,25 +534,28 @@ const struct csid_format_info *csid_get_fmt_entry(con= st struct csid_format_info =20 /* * csid_set_clock_rates - Calculate and set clock rates on CSID module * @csiphy: CSID device */ static int csid_set_clock_rates(struct csid_device *csid) { struct device *dev =3D csid->camss->dev; + struct csiphy_device *csiphy =3D &csid->camss->csiphy[csid->phy.csiphy_id= ]; + struct csiphy_lanes_cfg *lane_cfg =3D &csiphy->cfg.csi2->lane_cfg; const struct csid_format_info *fmt; + s64 link_freq; int i, j; int ret; =20 fmt =3D csid_get_fmt_entry(csid->res->formats->formats, csid->res->format= s->nformats, csid->fmt[MSM_CSIPHY_PAD_SINK].code); - link_freq =3D camss_get_link_freq(&csid->subdev.entity, fmt->bpp, - csid->phy.lane_cnt); + + link_freq =3D camss_get_link_freq(&csid->subdev.entity, fmt->bpp, lane_cf= g); if (link_freq < 0) link_freq =3D 0; =20 for (i =3D 0; i < csid->nclocks; i++) { struct camss_clock *clock =3D &csid->clock[i]; =20 if (!strcmp(clock->name, "csi0") || !strcmp(clock->name, "csi1") || diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.c b/drivers/med= ia/platform/qcom/camss/camss-csiphy.c index 539ac4888b608..f9b1ed79e15de 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy.c @@ -138,19 +138,18 @@ static int csiphy_set_clock_rates(struct csiphy_devic= e *csiphy) { struct device *dev =3D csiphy->camss->dev; s64 link_freq; int i, j; int ret; =20 u8 bpp =3D csiphy_get_bpp(csiphy->res->formats->formats, csiphy->res->for= mats->nformats, csiphy->fmt[MSM_CSIPHY_PAD_SINK].code); - u8 num_lanes =3D csiphy->cfg.csi2->lane_cfg.num_data; =20 - link_freq =3D camss_get_link_freq(&csiphy->subdev.entity, bpp, num_lanes); + link_freq =3D camss_get_link_freq(&csiphy->subdev.entity, bpp, &csiphy->c= fg.csi2->lane_cfg); if (link_freq < 0) link_freq =3D 0; =20 for (i =3D 0; i < csiphy->nclocks; i++) { struct camss_clock *clock =3D &csiphy->clock[i]; =20 if (csiphy->rate_set[i]) { u64 min_rate =3D link_freq / 4; @@ -264,20 +263,19 @@ static int csiphy_set_power(struct v4l2_subdev *sd, i= nt on) */ static int csiphy_stream_on(struct csiphy_device *csiphy) { struct csiphy_config *cfg =3D &csiphy->cfg; s64 link_freq; u8 lane_mask =3D csiphy->res->hw_ops->get_lane_mask(&cfg->csi2->lane_cfg); u8 bpp =3D csiphy_get_bpp(csiphy->res->formats->formats, csiphy->res->for= mats->nformats, csiphy->fmt[MSM_CSIPHY_PAD_SINK].code); - u8 num_lanes =3D csiphy->cfg.csi2->lane_cfg.num_data; u8 val; =20 - link_freq =3D camss_get_link_freq(&csiphy->subdev.entity, bpp, num_lanes); + link_freq =3D camss_get_link_freq(&csiphy->subdev.entity, bpp, &csiphy->c= fg.csi2->lane_cfg); =20 if (link_freq < 0) { dev_err(csiphy->camss->dev, "Cannot get CSI2 transmitter's link frequency\n"); return -EINVAL; } =20 if (csiphy->base_clk_mux) { diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index 072c428e25166..db4e14a84a95f 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -27,16 +27,24 @@ #include #include =20 #include "camss.h" =20 #define CAMSS_CLOCK_MARGIN_NUMERATOR 105 #define CAMSS_CLOCK_MARGIN_DENOMINATOR 100 =20 +/* + * C-PHY encodes data by 16/7 ~ 2.28 bits/symbol + * D-PHY doesn't encode data, thus 16/16 =3D 1 b/s + */ +#define CAMSS_COMMON_PHY_DIVIDENT 16 +#define CAMSS_CPHY_DIVISOR 7 +#define CAMSS_DPHY_DIVISOR 16 + static const struct parent_dev_ops vfe_parent_dev_ops; =20 static const struct camss_subdev_resources csiphy_res_8x16[] =3D { /* CSIPHY0 */ { .regulators =3D {}, .clock =3D { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer" }, .clock_rate =3D { { 0 }, @@ -4618,30 +4626,34 @@ struct media_pad *camss_find_sensor_pad(struct medi= a_entity *entity) return pad; } } =20 /** * camss_get_link_freq - Get link frequency from sensor * @entity: Media entity in the current pipeline * @bpp: Number of bits per pixel for the current format - * @lanes: Number of lanes in the link to the sensor + * @lane_cfg: CSI2 lane configuration * * Return link frequency on success or a negative error code otherwise */ s64 camss_get_link_freq(struct media_entity *entity, unsigned int bpp, - unsigned int lanes) + struct csiphy_lanes_cfg *lane_cfg) { struct media_pad *sensor_pad; + u8 num_lanes =3D lane_cfg->num_data; + bool cphy =3D lane_cfg->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY; + unsigned int div =3D num_lanes * 2 * (cphy ? CAMSS_CPHY_DIVISOR : + CAMSS_DPHY_DIVISOR); =20 sensor_pad =3D camss_find_sensor_pad(entity); if (!sensor_pad) return -ENODEV; =20 - return v4l2_get_link_freq(sensor_pad, bpp, 2 * lanes); + return v4l2_get_link_freq(sensor_pad, CAMSS_COMMON_PHY_DIVIDENT * bpp, di= v); } =20 /* * camss_get_pixel_clock - Get pixel clock rate from sensor * @entity: Media entity in the current pipeline * @pixel_clock: Received pixel clock value * * Return 0 on success or a negative error code otherwise diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/plat= form/qcom/camss/camss.h index 93d691c8ac63b..d65a9b62f7e66 100644 --- a/drivers/media/platform/qcom/camss/camss.h +++ b/drivers/media/platform/qcom/camss/camss.h @@ -164,17 +164,17 @@ struct parent_dev_ops { }; =20 void camss_add_clock_margin(u64 *rate); int camss_enable_clocks(int nclocks, struct camss_clock *clock, struct device *dev); void camss_disable_clocks(int nclocks, struct camss_clock *clock); struct media_pad *camss_find_sensor_pad(struct media_entity *entity); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260605-qcom-cphy-v7-8-426c37e9008f@ixit.cz> References: <20260605-qcom-cphy-v7-0-426c37e9008f@ixit.cz> In-Reply-To: <20260605-qcom-cphy-v7-0-426c37e9008f@ixit.cz> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Luca Weiss , Petr Hodina , "Dr. Git" , Cory Keitz , Loic Poulain Cc: Frank Li , Konrad Dybcio , Kieran Bingham , Sakari Ailus , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1392; i=david@ixit.cz; h=from:subject:message-id; bh=yfuNEpBnQgvYmUSkvI5U4j/G6UateQzCMCBG6SxmfO0=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBqIsvCGPCeA6Vs/cZWC74UxxwO3XMTA73Yifj1y nb6TtTIXdqJAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCaiLLwgAKCRBgAj/E00kg cvDwD/9N0SLyhXrNDXxcob+1QDH1XlDJH/a9IgDU+RMX/2YzGvIj5sE8A/LrCVcQjRW4xv+yVmU xhBOqmZRyWEqVJb8JYS3wto2Hjg3x88u5z5Xn7v0bI5J1fS4/pCFnQLlgEmWdm0ObtjDWmt83lH RZ7RebCn0YSnhvZwflkWGM5syyA2wBJkl3Mear/zJcXDg7MLysiXNxG62S+tENla3NldYYtook3 Dwf41MF56Qqo/jPwESXhHqgfLsKjFGlhayui9Gbp5LDrfbph4BBna9pKZ3wsU3FZVoH3IkG7hhS 7d2EWCMg2nihfN+6Zuxbog0KajAoKupv6QGXeilQuTlAB8Wu78CSXmI3IMxYOm6yz8uRJqfVtWv fn7VifJEjATmL0epGJS4Hat8Ev4NY3vGH/uzuJSO0Bd1GK6FgR0FqCNgZQJi8btNH1N1139HA/H xU0HtFCJrBlB8VZS/6KTQf+ot14T8c9aE6gIAj5yxy7+PmyQ/uoni4/wlxo8LMdsVHujyTZD8Fq +Yibhb+0GWuSWJf++z2pdKkIVNCCrAMp/7w/sut95OOkDarfuIXhnv3pVbw7GQ5rlJWt/CG/FSO XojozBjaDbxwI3h8qI5W7NUqULsmu2Acg1i/aQ4QSPFpnf87+UDxj1GfmxES41+1O9MfH6VllEM jHoOngc8lFjLKkA== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg After all the changes done we can now safely enable C-PHY for a SoC where it's available. Acked-by: Cory Keitz Reviewed-by: Bryan O'Donoghue Reviewed-by: Frank Li Signed-off-by: David Heidelberg --- drivers/media/platform/qcom/camss/camss.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index db4e14a84a95f..555c53343a1e9 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -4761,21 +4761,21 @@ static int camss_parse_endpoint_node(struct device = *dev, struct v4l2_fwnode_endpoint vep =3D { { 0 } }; unsigned int i; int ret; =20 ret =3D v4l2_fwnode_endpoint_parse(ep, &vep); if (ret) return ret; =20 - /* - * Most SoCs support both D-PHY and C-PHY standards, but currently only - * D-PHY is supported in the driver. - */ - if (vep.bus_type !=3D V4L2_MBUS_CSI2_DPHY) { + switch (vep.bus_type) { + case V4L2_MBUS_CSI2_CPHY: + case V4L2_MBUS_CSI2_DPHY: + break; + default: dev_err(dev, "Unsupported bus type %d\n", vep.bus_type); return -EINVAL; } =20 csd->interface.csiphy_id =3D vep.base.port; =20 mipi_csi2 =3D &vep.bus.mipi_csi2; lncfg->num_data =3D mipi_csi2->num_data_lanes; --=20 2.53.0