From nobody Mon Jun 8 06:36:24 2026 Received: from mail-pj1-f74.google.com (mail-pj1-f74.google.com [209.85.216.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A179A37E2E5 for ; Thu, 4 Jun 2026 18:21:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.74 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780597285; cv=none; b=c0tdWE2t/rqlNrxLlj4l2cl9SUxyKsizfWBuJY7xMiH6bRJuLEclgV/DGbl6807XaTK+FTicRwsuURIViNU+tUeN4W5EpJQEBJqUlMaeIwg23w6NXj1UCmb6PWHO+a//mACd7YozuJrqlvY+0blGLa8PQPBjfpBXuUgB5mraiuM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780597285; c=relaxed/simple; bh=Es1v8sdHF6j+zSSIs3uGcU7RSkCWnEMk56BnyfML4Gk=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=Q7nG/S3dvZlGyTpcxYPFzvyQVXoI9s1wnN6JXq3+2koCdvZ/PzSB0MxU3+q+YIGGIH8ZCQ4KijWR+KJh7i8m3zZBuj6vO/su40M+HlCVa/tsjDfHdZrSxywR5Wp3SsY3/WMUB+YMvJ9R/hCY0e58A9pR2iNLDYbQLav1JypS2ig= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--praan.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=NqHP4AWN; arc=none smtp.client-ip=209.85.216.74 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--praan.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="NqHP4AWN" Received: by mail-pj1-f74.google.com with SMTP id 98e67ed59e1d1-36d99333358so1056743a91.3 for ; Thu, 04 Jun 2026 11:21:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20251104; t=1780597283; x=1781202083; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=6xpzlsU/13g3vBsNTBir2ktpGFm/ePGN+o4IZaBkeOg=; b=NqHP4AWNiCHSIrz9wJ6yztw1lnsu5UZd0Us7yHI1b29/m+ci7MSHCTatBjlZcbn3RR +ZO2vkb7PMp/DGWTw2YjUZZ1fEyVGSygGaWG+WKWOpBTNtpSaYN/WaPc/3cWzC1OPS3O R9SyJ9zFKEb5G1D+77hifU160kSZb675TC5g1nNfz7zCtgQosD5N1S/JX+4hfIniWpRB 7r5FiTWynvPjPzSGEHaqWlkj1hmQsumJ0tfudlq3hlO9+5Q+u/T8ZUqbw88/wkW8NLaV HVNqvXHGPDhIvWW2h3/R/EOws60pVwm99mZwML6IFIn1t3v0Hui+WwDeLkmTVhJT7OaJ mTiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1780597283; x=1781202083; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=6xpzlsU/13g3vBsNTBir2ktpGFm/ePGN+o4IZaBkeOg=; b=i/PbfVAw12gvD8PQ/7lMkrsxYwqXDUV9ph47qtIkpKrfX/nM4eB1jnJ3lgy2cSbu8o 12jTZdkphOBl7CzjAx+1Df0+N6CTo1ADUc7A3UNmbK7Vtly0jmB4YSNXMRr19+rNqblX Xpry03aexnzBaPepzXT12yaMfnkrsne2kJrMShZuwb5M4fXZG3DeEaB3ftT1zkS4lRB8 A2L4FpvMjp9anGEu7IdDF76C1FqAxvsNE53vo5i/K6ruE67fFcqhlwKLInZH/1C9MTxa NvKDz8cUjvLkvteD4t7Bok26IZ0jbg7UdAudeTB37zWTg6XROgm8YKVmg/GreUsfu1Rk igug== X-Forwarded-Encrypted: i=1; AFNElJ9Ap+Uls8cu13hNDkrh67QEjht4tnbvbNX3bhCmkOgxhO743A/DVYDt1jaDLbokdC/dlOFk8aZ8G9TshL8=@vger.kernel.org X-Gm-Message-State: AOJu0YznC/ioQ/XljDzj/ygl7H6YbMR8D/YCohg5EY/OwMwsgjeh7r2r S9FhI28kjN/nwv+KwZHAaMELhpXNURMq4k1LNPFZ9r8kDzGA+X9UqbG2u9JCAvSWVceRnW6rJ6L cIA== X-Received: from pjbmd5.prod.google.com ([2002:a17:90b:23c5:b0:36a:f1b9:c389]) (user=praan job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:4b87:b0:368:b01c:85a0 with SMTP id 98e67ed59e1d1-370f0b54dc0mr99930a91.14.1780597282715; Thu, 04 Jun 2026 11:21:22 -0700 (PDT) Date: Thu, 4 Jun 2026 18:21:13 +0000 In-Reply-To: <20260604182116.3179005-1-praan@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260604182116.3179005-1-praan@google.com> X-Mailer: git-send-email 2.54.0.1032.g2f8565e1d1-goog Message-ID: <20260604182116.3179005-2-praan@google.com> Subject: [PATCH v8 1/4] PCI/ATS: Ensure pci_ats_supported() is PF-aware for VFs From: Pranjal Shrivastava To: iommu@lists.linux.dev, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Joerg Roedel , Will Deacon , Robin Murphy , Baolu Lu , Jason Gunthorpe , Kevin Tian , Bjorn Helgaas , Samiullah Khawaja , Pranjal Shrivastava , Nicolin Chen Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update pci_ats_supported() to additionally check the associated PF's status when called on a VF. This ensures that PF-level quirks and untrusted status are correctly propagated to VFs, providing a robust support check that aligns with the kernel's PF-centric ATS configuration model and is immune to the timing of VF-specific fixups. Reviewed-by: Jason Gunthorpe Reviewed-by: Samiullah Khawaja Reviewed-by: Nicolin Chen Reviewed-by: Lu Baolu Reviewed-by: Kevin Tian Signed-off-by: Pranjal Shrivastava --- drivers/pci/ats.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/pci/ats.c b/drivers/pci/ats.c index 96efa00d9743..679a3c3c1d54 100644 --- a/drivers/pci/ats.c +++ b/drivers/pci/ats.c @@ -40,10 +40,13 @@ void pci_ats_init(struct pci_dev *dev) */ bool pci_ats_supported(struct pci_dev *dev) { - if (!dev->ats_cap) + if (!dev->ats_cap || dev->untrusted) return false; =20 - return (dev->untrusted =3D=3D 0); + if (dev->is_virtfn) + return pci_ats_supported(pci_physfn(dev)); + + return true; } EXPORT_SYMBOL_GPL(pci_ats_supported); =20 --=20 2.54.0.1032.g2f8565e1d1-goog From nobody Mon Jun 8 06:36:24 2026 Received: from mail-pl1-f201.google.com (mail-pl1-f201.google.com [209.85.214.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4AE863A2544 for ; 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Thu, 04 Jun 2026 11:21:24 -0700 (PDT) Date: Thu, 4 Jun 2026 18:21:14 +0000 In-Reply-To: <20260604182116.3179005-1-praan@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260604182116.3179005-1-praan@google.com> X-Mailer: git-send-email 2.54.0.1032.g2f8565e1d1-goog Message-ID: <20260604182116.3179005-3-praan@google.com> Subject: [PATCH v8 2/4] PCI/ATS: Validate STU for VFs in pci_prepare_ats() From: Pranjal Shrivastava To: iommu@lists.linux.dev, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Joerg Roedel , Will Deacon , Robin Murphy , Baolu Lu , Jason Gunthorpe , Kevin Tian , Bjorn Helgaas , Samiullah Khawaja , Pranjal Shrivastava , Nicolin Chen Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" While every PCI Function that implements ATS has an independent ATS Extended Capability structure with a Read/Write Smallest Translation Unit (STU) field, the kernel manages SR-IOV ATS by requiring the IOMMU driver to configure the STU on the Physical Function (PF) before any any Virtual Functions (VFs) are created. Currently, pci_prepare_ats() bails out early for VFs, assuming that the PF has already been correctly prepared. However, this creates a potential mismatch if a VF is subsequently prepared with a different page shift. Update pci_prepare_ats() to validate that the requested page shift (ps) matches the STU already configured in the associated PF. This ensures early detection of incompatible configurations and maintains the kernel's policy of consistent STU sizing across all functions associated with a given SMMU. Reviewed-by: Jason Gunthorpe Reviewed-by: Samiullah Khawaja Reviewed-by: Nicolin Chen Reviewed-by: Lu Baolu Reviewed-by: Kevin Tian Signed-off-by: Pranjal Shrivastava --- drivers/pci/ats.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/pci/ats.c b/drivers/pci/ats.c index 679a3c3c1d54..9cb23780093d 100644 --- a/drivers/pci/ats.c +++ b/drivers/pci/ats.c @@ -73,8 +73,12 @@ int pci_prepare_ats(struct pci_dev *dev, int ps) if (ps < PCI_ATS_MIN_STU) return -EINVAL; =20 - if (dev->is_virtfn) + if (dev->is_virtfn) { + if (pci_physfn(dev)->ats_stu !=3D ps) + return -EINVAL; + return 0; + } =20 dev->ats_stu =3D ps; ctrl =3D PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU); --=20 2.54.0.1032.g2f8565e1d1-goog From nobody Mon Jun 8 06:36:24 2026 Received: from mail-pj1-f74.google.com (mail-pj1-f74.google.com [209.85.216.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 28EED3B9949 for ; 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Thu, 04 Jun 2026 11:21:27 -0700 (PDT) Date: Thu, 4 Jun 2026 18:21:15 +0000 In-Reply-To: <20260604182116.3179005-1-praan@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260604182116.3179005-1-praan@google.com> X-Mailer: git-send-email 2.54.0.1032.g2f8565e1d1-goog Message-ID: <20260604182116.3179005-4-praan@google.com> Subject: [PATCH v8 3/4] iommu/arm-smmu-v3: Standardize ATS enablement failure reporting From: Pranjal Shrivastava To: iommu@lists.linux.dev, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Joerg Roedel , Will Deacon , Robin Murphy , Baolu Lu , Jason Gunthorpe , Kevin Tian , Bjorn Helgaas , Samiullah Khawaja , Pranjal Shrivastava Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update arm_smmu_enable_ats() to wrap the pci_enable_ats() call in WARN_ON(). Since probe-time checks now preclude configuration errors any failure during hardware enablement is considered a kernel bug. Reviewed-by: Kevin Tian Signed-off-by: Pranjal Shrivastava Reviewed-by: Nicolin Chen Reviewed-by: Samiullah Khawaja --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index a10affb483a4..0494c68daa19 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2956,7 +2956,12 @@ static void arm_smmu_enable_ats(struct arm_smmu_mast= er *master) * ATC invalidation of PASID 0 causes the entire ATC to be flushed. */ arm_smmu_atc_inv_master(master, IOMMU_NO_PASID); - if (pci_enable_ats(pdev, stu)) + + /* + * Since pci_prepare_ats() has already verified the HW capability + * and programmed the STE, pci_enable_ats() should not fail here. + */ + if (WARN_ON(pci_enable_ats(pdev, stu))) dev_err(master->dev, "Failed to enable ATS (STU %zu)\n", stu); } =20 --=20 2.54.0.1032.g2f8565e1d1-goog From nobody Mon Jun 8 06:36:24 2026 Received: from mail-pj1-f73.google.com (mail-pj1-f73.google.com [209.85.216.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3FA113BBA09 for ; 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Thu, 04 Jun 2026 11:21:29 -0700 (PDT) Date: Thu, 4 Jun 2026 18:21:16 +0000 In-Reply-To: <20260604182116.3179005-1-praan@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260604182116.3179005-1-praan@google.com> X-Mailer: git-send-email 2.54.0.1032.g2f8565e1d1-goog Message-ID: <20260604182116.3179005-5-praan@google.com> Subject: [PATCH v8 4/4] iommu/vt-d: Fail probe on ATS configuration failure From: Pranjal Shrivastava To: iommu@lists.linux.dev, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Joerg Roedel , Will Deacon , Robin Murphy , Baolu Lu , Jason Gunthorpe , Kevin Tian , Bjorn Helgaas , Samiullah Khawaja , Pranjal Shrivastava Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update the Intel VT-d driver to handle ATS configuration and enablement more strictly. Specifically, update the device probe to fail if pci_prepare_ats() returns an error. This ensures that any ATS-capable master reaching the attach phase is guaranteed to have a valid config. Additionally, update iommu_enable_pci_ats() to WARN() if pci_enable_ats fails. Since earlier checks in the probe phase preclude config-related failures, any failure during hardware enablement is considered a kernel bug. Reviewed-by: Lu Baolu Reviewed-by: Kevin Tian Signed-off-by: Pranjal Shrivastava Reviewed-by: Samiullah Khawaja --- drivers/iommu/intel/iommu.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 849d06dfe1ae..f39451323553 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -876,8 +876,14 @@ static void iommu_enable_pci_ats(struct device_domain_= info *info) if (!pci_ats_page_aligned(pdev)) return; =20 - if (!pci_enable_ats(pdev, VTD_PAGE_SHIFT)) - info->ats_enabled =3D 1; + /* + * pci_enable_ats() should not fail here because earlier checks + * have already verified support and configuration. + */ + if (WARN_ON(pci_enable_ats(pdev, VTD_PAGE_SHIFT))) + return; + + info->ats_enabled =3D 1; } =20 static void iommu_disable_pci_ats(struct device_domain_info *info) @@ -3292,7 +3298,10 @@ static struct iommu_device *intel_iommu_probe_device= (struct device *dev) =20 dev_iommu_priv_set(dev, info); if (pdev && pci_ats_supported(pdev)) { - pci_prepare_ats(pdev, VTD_PAGE_SHIFT); + ret =3D pci_prepare_ats(pdev, VTD_PAGE_SHIFT); + if (ret) + goto free; + ret =3D device_rbtree_insert(iommu, info); if (ret) goto free; --=20 2.54.0.1032.g2f8565e1d1-goog