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Thu, 04 Jun 2026 08:18:59 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: Biju Das , Brian Masney , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH 1/3] clk: renesas: r9a08g046: Add clock and reset entries for GE3D Date: Thu, 4 Jun 2026 16:18:49 +0100 Message-ID: <20260604151855.307772-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260604151855.307772-1-biju.das.jz@bp.renesas.com> References: <20260604151855.307772-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add clock and reset entries for GE3D. Signed-off-by: Biju Das --- This patch depend upon [1] [1] https://lore.kernel.org/all/20260603065731.93243-3-biju.das.jz@bp.renes= as.com/ --- drivers/clk/renesas/r9a08g046-cpg.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/clk/renesas/r9a08g046-cpg.c b/drivers/clk/renesas/r9a0= 8g046-cpg.c index 272922b76e1e..edc83a4104b2 100644 --- a/drivers/clk/renesas/r9a08g046-cpg.c +++ b/drivers/clk/renesas/r9a08g046-cpg.c @@ -18,12 +18,14 @@ #define G3L_CPG_PL2_DDIV (0x204) #define G3L_CPG_PL3_DDIV (0x208) #define G3L_CPG_SDHI_DDIV (0x218) +#define G3L_CPG_GE3D_DDIV (0x224) #define G3L_CPG_CA55CORE_DDIV (0x234) #define G3L_CPG_RSCI_DDIV (0x238) #define G3L_CPG_RSPI_DDIV (0x23c) #define G3L_CPG_SDHI_DSEL (0x244) #define G3L_CLKDIVSTATUS (0x280) #define G3L_CLKSELSTATUS (0x284) +#define G3L_CPG_GE3D_SSEL (0x40c) #define G3L_CPG_ETH_SSEL (0x410) #define G3L_CPG_RSCI_SSEL (0x414) #define G3L_CPG_RSPI_SSEL (0x418) @@ -36,6 +38,7 @@ #define G3L_DIV_SDHI0 DDIV_PACK(G3L_CPG_SDHI_DDIV, 0, 2) #define G3L_DIV_SDHI1 DDIV_PACK(G3L_CPG_SDHI_DDIV, 4, 2) #define G3L_DIV_SDHI2 DDIV_PACK(G3L_CPG_SDHI_DDIV, 8, 2) +#define G3L_DIV_GE3D DDIV_PACK(G3L_CPG_GE3D_DDIV, 0, 3) #define G3L_DIV_CA55_CORE0 DDIV_PACK(G3L_CPG_CA55CORE_DDIV, 0, 3) #define G3L_DIV_CA55_CORE1 DDIV_PACK(G3L_CPG_CA55CORE_DDIV, 4, 3) #define G3L_DIV_CA55_CORE2 DDIV_PACK(G3L_CPG_CA55CORE_DDIV, 8, 3) @@ -74,6 +77,7 @@ #define G3L_SEL_SDHI0_STS SEL_PLL_PACK(G3L_CLKSELSTATUS, 16, 1) #define G3L_SEL_SDHI1_STS SEL_PLL_PACK(G3L_CLKSELSTATUS, 17, 1) #define G3L_SEL_SDHI2_STS SEL_PLL_PACK(G3L_CLKSELSTATUS, 18, 1) +#define G3L_DIV_GE3D_STS DDIV_PACK(G3L_CLKDIVSTATUS, 27, 1) =20 /* RZ/G3L Specific clocks select. */ #define G3L_SEL_SDHI0 SEL_PLL_PACK(G3L_CPG_SDHI_DSEL, 0, 2) @@ -89,6 +93,7 @@ #define G3L_SEL_ETH1_RM SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 10, 1) #define G3L_SEL_ETH1_CLK_TX_I SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 11, 1) #define G3L_SEL_ETH1_CLK_RX_I SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 12, 1) +#define G3L_SEL_GE3D SEL_PLL_PACK(G3L_CPG_GE3D_SSEL, 0, 2) #define G3L_SEL_RSCI0 SEL_PLL_PACK(G3L_CPG_RSCI_SSEL, 0, 2) #define G3L_SEL_RSCI1 SEL_PLL_PACK(G3L_CPG_RSCI_SSEL, 2, 2) #define G3L_SEL_RSCI2 SEL_PLL_PACK(G3L_CPG_RSCI_SSEL, 4, 2) @@ -119,6 +124,8 @@ enum clk_ids { CLK_PLL2_DIV7, CLK_PLL3, CLK_PLL3_DIV2, + CLK_PLL3_DIV2_2, + CLK_PLL3_DIV3, CLK_PLL6, CLK_PLL6_DIV10, CLK_SEL_ETH0_TX, @@ -127,6 +134,7 @@ enum clk_ids { CLK_SEL_ETH1_TX, CLK_SEL_ETH1_RX, CLK_SEL_ETH1_RM, + CLK_SEL_GE3D, CLK_SEL_RSCI0, CLK_SEL_RSCI1, CLK_SEL_RSCI2, @@ -219,6 +227,7 @@ static const char * const sel_eth0_rm[] =3D { ".pll6_di= v10", "eth0_rxc_rx_clk" }; static const char * const sel_eth1_tx[] =3D { ".div_eth1_tr", "eth1_txc_tx= _clk" }; static const char * const sel_eth1_rx[] =3D { ".div_eth1_tr", "eth1_rxc_rx= _clk" }; static const char * const sel_eth1_rm[] =3D { ".pll6_div10", "eth1_rxc_rx_= clk" }; +static const char * const sel_ge3d[] =3D { ".pll1_div2", ".pll3_div3", ".p= ll6", ".pll3_div2_2" }; static const char * const sel_rsci_rspi[] =3D { ".pll2_div5", ".pll2_div6"= , ".pll2_div7", ".pll2_div2_4" }; static const char * const sel_sdhi[] =3D { ".pll2_div2", ".pll1_div2", ".= pll6", ".pll2_div6" }; static const char * const sel_eth0_clk_tx_i[] =3D { ".sel_eth0_tx", ".div_= eth0_rm" }; @@ -251,6 +260,8 @@ static const struct cpg_core_clk r9a08g046_core_clks[] = __initconst =3D { DEF_FIXED(".pll2_div6", CLK_PLL2_DIV6, CLK_PLL2, 1, 6), DEF_FIXED(".pll2_div7", CLK_PLL2_DIV7, CLK_PLL2, 1, 7), DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), + DEF_FIXED(".pll3_div2_2", CLK_PLL3_DIV2_2, CLK_PLL3_DIV2, 1, 2), + DEF_FIXED(".pll3_div3", CLK_PLL3_DIV3, CLK_PLL3, 1, 3), DEF_FIXED(".pll6_div10", CLK_PLL6_DIV10, CLK_PLL6, 1, 10), DEF_SD_MUX(".sel_sdhi0", CLK_SEL_SDHI0, G3L_SEL_SDHI0, G3L_SEL_SDHI0_STS,= sel_sdhi, mtable_sd, 0, NULL), @@ -258,6 +269,7 @@ static const struct cpg_core_clk r9a08g046_core_clks[] = __initconst =3D { mtable_sd, 0, NULL), DEF_SD_MUX(".sel_sdhi2", CLK_SEL_SDHI2, G3L_SEL_SDHI2, G3L_SEL_SDHI2_STS,= sel_sdhi, mtable_sd, 0, NULL), + DEF_MUX(".sel_ge3d", CLK_SEL_GE3D, G3L_SEL_GE3D, sel_ge3d), DEF_MUX(".sel_rsci0", CLK_SEL_RSCI0, G3L_SEL_RSCI0, sel_rsci_rspi), DEF_MUX(".sel_rsci1", CLK_SEL_RSCI1, G3L_SEL_RSCI1, sel_rsci_rspi), DEF_MUX(".sel_rsci2", CLK_SEL_RSCI2, G3L_SEL_RSCI2, sel_rsci_rspi), @@ -332,6 +344,8 @@ static const struct cpg_core_clk r9a08g046_core_clks[] = __initconst =3D { DEF_FIXED("ETHRM1", R9A08G046_CLK_ETHRM1, CLK_SEL_ETH1_RM, 1, 1), DEF_FIXED("ETHTX12", R9A08G046_CLK_ETHTX12, CLK_SEL_ETH1_TX, 1, 1), DEF_FIXED("ETHRX12", R9A08G046_CLK_ETHRX12, CLK_SEL_ETH1_RX, 1, 1), + DEF_G3S_DIV("G", R9A08G046_CLK_G, CLK_SEL_GE3D, G3L_DIV_GE3D, G3L_DIV_GE3= D_STS, + dtable_1_32, 0, 0, 0, NULL), DEF_FIXED("OSCCLK", R9A08G046_OSCCLK, CLK_EXTAL, 1, 1), }; =20 @@ -380,6 +394,12 @@ static const struct rzg2l_mod_clk r9a08g046_mod_clks[]= =3D { MSTOP(BUS_PERI_COM, BIT(11))), DEF_MOD("sdhi2_iaclkm", R9A08G046_SDHI2_IACLKM, R9A08G046_CLK_P1, 0x554,= 14, MSTOP(BUS_PERI_COM, BIT(11))), + DEF_MOD("ge3d_clk", R9A08G046_GE3D_CLK, R9A08G046_CLK_G, 0x558, 0, + MSTOP(BUS_PERI_VIDEO, BIT(12))), + DEF_MOD("ge3d_axi_clk", R9A08G046_GE3D_AXI_CLK, R9A08G046_CLK_P1, 0x558,= 1, + MSTOP(BUS_PERI_VIDEO, BIT(12))), + DEF_MOD("ge3d_ace_clk", R9A08G046_GE3D_ACE_CLK, R9A08G046_CLK_P1, 0x558,= 2, + MSTOP(BUS_PERI_VIDEO, BIT(12))), DEF_MOD("ssi0_pclk2", R9A08G046_SSI0_PCLK2, R9A08G046_CLK_P0, 0x570, 0, MSTOP(BUS_MCPU1, BIT(10))), DEF_MOD("ssi0_pclk_sfr", R9A08G046_SSI0_PCLK_SFR, R9A08G046_CLK_P0, 0x570= , 1, @@ -504,6 +524,9 @@ static const struct rzg2l_reset r9a08g046_resets[] =3D { DEF_RST(R9A08G046_SDHI1_IXRSTAXIS, 0x854, 6), DEF_RST(R9A08G046_SDHI2_IXRSTAXIM, 0x854, 7), DEF_RST(R9A08G046_SDHI2_IXRSTAXIS, 0x854, 8), + DEF_RST(R9A08G046_GE3D_RESETN, 0x858, 0), + DEF_RST(R9A08G046_GE3D_AXI_RESETN, 0x858, 1), + DEF_RST(R9A08G046_GE3D_ACE_RESETN, 0x858, 2), DEF_RST(R9A08G046_SSI0_RST_M2_REG, 0x870, 0), DEF_RST(R9A08G046_SSI1_RST_M2_REG, 0x870, 1), DEF_RST(R9A08G046_SSI2_RST_M2_REG, 0x870, 2), --=20 2.43.0 From nobody Mon Jun 8 08:36:47 2026 Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 39F1D32E6B4 for ; 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Thu, 04 Jun 2026 08:19:00 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a700:7301:1615:3574:e0c0:837d]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-490bc3b5b82sm82776805e9.1.2026.06.04.08.18.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jun 2026 08:19:00 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH 2/3] arm64: dts: renesas: r9a08g046: Add Mali-G31 GPU node Date: Thu, 4 Jun 2026 16:18:50 +0100 Message-ID: <20260604151855.307772-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260604151855.307772-1-biju.das.jz@bp.renesas.com> References: <20260604151855.307772-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add the Mali-G31 GPU node to the SoC DTSI. Signed-off-by: Biju Das --- This patch depend upon [1] [1] https://lore.kernel.org/all/20260603065731.93243-16-biju.das.jz@bp.rene= sas.com/ --- arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 126 +++++++++++++++++++++ 1 file changed, 126 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/d= ts/renesas/r9a08g046.dtsi index ce42c945fdf4..0c1cb22aada0 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi @@ -64,6 +64,110 @@ opp-1200000000 { }; }; =20 + gpu_opp_table: opp-table-1 { + compatible =3D "operating-points-v2"; + + opp-600000000 { + opp-hz =3D /bits/ 64 <600000000>; + opp-microvolt =3D <1000000>; + }; + + opp-533330000 { + opp-hz =3D /bits/ 64 <533330000>; + opp-microvolt =3D <1000000>; + }; + + opp-500000000 { + opp-hz =3D /bits/ 64 <500000000>; + opp-microvolt =3D <1000000>; + }; + + opp-400000000 { + opp-hz =3D /bits/ 64 <400000000>; + opp-microvolt =3D <1000000>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + opp-microvolt =3D <1000000>; + }; + + opp-266667000 { + opp-hz =3D /bits/ 64 <266667000>; + opp-microvolt =3D <1000000>; + }; + + opp-250000000 { + opp-hz =3D /bits/ 64 <250000000>; + opp-microvolt =3D <1000000>; + }; + + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>; + opp-microvolt =3D <1000000>; + }; + + opp-150000000 { + opp-hz =3D /bits/ 64 <150000000>; + opp-microvolt =3D <1000000>; + }; + + opp-133333000 { + opp-hz =3D /bits/ 64 <133333000>; + opp-microvolt =3D <1000000>; + }; + + opp-125000000 { + opp-hz =3D /bits/ 64 <125000000>; + opp-microvolt =3D <1000000>; + }; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>; + opp-microvolt =3D <1000000>; + }; + + opp-75000000 { + opp-hz =3D /bits/ 64 <75000000>; + opp-microvolt =3D <1000000>; + }; + + opp-66667000 { + opp-hz =3D /bits/ 64 <66667000>; + opp-microvolt =3D <1000000>; + }; + + opp-62500000 { + opp-hz =3D /bits/ 64 <62500000>; + opp-microvolt =3D <1000000>; + }; + + opp-50000000 { + opp-hz =3D /bits/ 64 <50000000>; + opp-microvolt =3D <1000000>; + }; + + opp-18750000 { + opp-hz =3D /bits/ 64 <18750000>; + opp-microvolt =3D <1000000>; + }; + + opp-16667000 { + opp-hz =3D /bits/ 64 <16667000>; + opp-microvolt =3D <1000000>; + }; + + opp-15625000 { + opp-hz =3D /bits/ 64 <15625000>; + opp-microvolt =3D <1000000>; + }; + + opp-12500000 { + opp-hz =3D /bits/ 64 <12500000>; + opp-microvolt =3D <1000000>; + }; + }; + cpus { #address-cells =3D <1>; #size-cells =3D <0>; @@ -592,6 +696,28 @@ ssi3: ssi@100e4c00 { status =3D "disabled"; }; =20 + gpu: gpu@108b0000 { + compatible =3D "renesas,r9a08g046-mali", + "arm,mali-bifrost"; + reg =3D <0x0 0x108b0000 0x0 0x10000>; + interrupts =3D , + , + , + ; + interrupt-names =3D "job", "mmu", "gpu", "event"; + clocks =3D <&cpg CPG_MOD R9A08G046_GE3D_CLK>, + <&cpg CPG_MOD R9A08G046_GE3D_AXI_CLK>, + <&cpg CPG_MOD R9A08G046_GE3D_ACE_CLK>; + clock-names =3D "gpu", "bus", "bus_ace"; + power-domains =3D <&cpg>; + resets =3D <&cpg R9A08G046_GE3D_RESETN>, + <&cpg R9A08G046_GE3D_AXI_RESETN>, + <&cpg R9A08G046_GE3D_ACE_RESETN>; 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charset="utf-8" From: Biju Das Enable the Mali-G31 (GPU) node on the RZ/G3L SMARC SoM board. Signed-off-by: Biju Das --- This patch depend upon [1] and [2] [1] https://lore.kernel.org/all/20260603065731.93243-17-biju.das.jz@bp.rene= sas.com/ [2] https://lore.kernel.org/all/20260603065731.93243-18-biju.das.jz@bp.rene= sas.com/ --- arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi b/arch/arm64/= boot/dts/renesas/rzg3l-smarc-som.dtsi index 3d5e6b8489a9..fd2aa064f9a4 100644 --- a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi @@ -51,6 +51,15 @@ memory@48000000 { reg =3D <0x0 0x48000000 0x0 0x78000000>; }; =20 + reg_1p0v: regulator-1p0v { + compatible =3D "regulator-fixed"; + regulator-name =3D "fixed-1.0V"; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1000000>; + regulator-boot-on; + regulator-always-on; + }; + reg_1p8v: regulator-1p8v { compatible =3D "regulator-fixed"; regulator-name =3D "fixed-1.8V"; @@ -119,6 +128,11 @@ &extal_clk { clock-frequency =3D <24000000>; }; =20 +&gpu { + status =3D "okay"; + mali-supply =3D <®_1p0v>; +}; + &i2c0 { pinctrl-0 =3D <&i2c0_pins>; pinctrl-names =3D "default"; --=20 2.43.0