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svCmDH57ft77gkRiY5erI2strXPPEumn0LorgUjlBKAax9I4EgN9Umg3c3noqHlNa2Jz5/NeG yThH961JY8XdrSYLBs7xmmH3PacYDj725SY3l1rbq95lVbk0ILHWFbCgWeQ5gZuXoPeGD//yt Sm9AoLu5OxkhILseH0QxGnXoQ9qrfgcenipXGvXxLME+bQJ1hV8/F5le4ZruNk33bXGoQvGsm zi5H90/8+Uub0s1hi8kurh14ehGXviP72chIclwQkdRSzx0CStTph3rGslcz615V855hVOoke REn6gZNWPLFVr3S0Mrv+bZGNfwx+6WVvBGHADV8hgqxjBKoO98c0PznsVEXeMfk99pZTlT9RX vxf23zfIAANAQivPNzYCRq1y4PhPyItYt2L/l9zOiOBm3HPRGf+pl4eq7NaVkh4b3GSEVzBYG dPlC692CD7xf0cYyGvoVgmwlnCpH9bnVoLjQc2ygYs+etKDheu1EOCG+7x9Qdl8VDtGy9YjUH dS7db6gI/VhDdqMR6AoZLg5HUbfQ5BGLhIWy2a2RLoxftgik0cPy/JSsYzKgRXhN83isVEh9O 0fE3Iz50NxWnsHpg+ziCIH0DwYlzx3aQxEY+SqIA4dmPt3ILJEaIDZozUdFo4rpDjOeh9fHj2 e8b70udRJZweHFjVnn7tcvNiq0riJfzJa5UvBOuDj4qkr8beYGOM5BogiYqloNJJ2jWhEvVnx 7znrbtVXx/uaaVNU9EXt8zVCdceBGmhWIGlkvDhHDMP4QePR2e52YEvxG5z8MygL4LjqiJ5bv T3kZHVwwY= Content-Type: text/plain; charset="utf-8" The Realtek interrupt controller has two important registers that are used by the driver in several places - GIMR: global interrupt mask register - IRR: Interrupt routing registers The usage of these registers is very inconsistent. GIMR is addressed directly while IRR has a helper that needs a macro as an input. Harmonize this by providing consistent helpers that improve code readability. The callers of these helpers use classic lock/unlock functions and sometimes use the wrong locking helper. E.g. irqsave variants are used in mask/unmask although not needed. Adapt and fix the surrounding call locations. Signed-off-by: Markus Stockhausen --- drivers/irqchip/irq-realtek-rtl.c | 64 +++++++++++++++---------------- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/drivers/irqchip/irq-realtek-rtl.c b/drivers/irqchip/irq-realte= k-rtl.c index 942c1f8c363d..4e2996eb671e 100644 --- a/drivers/irqchip/irq-realtek-rtl.c +++ b/drivers/irqchip/irq-realtek-rtl.c @@ -37,10 +37,29 @@ static void __iomem *realtek_ictl_base; #define IRR_OFFSET(idx) (4 * (3 - (idx * 4) / 32)) #define IRR_SHIFT(idx) ((idx * 4) % 32) =20 -static void write_irr(void __iomem *irr0, int idx, u32 value) +static inline void enable_gimr(unsigned int hw_irq) { - unsigned int offset =3D IRR_OFFSET(idx); - unsigned int shift =3D IRR_SHIFT(idx); + u32 gimr; + + gimr =3D readl(REG(RTL_ICTL_GIMR)); + gimr |=3D BIT(hw_irq); + writel(gimr, REG(RTL_ICTL_GIMR)); +} + +static inline void disable_gimr(unsigned int hw_irq) +{ + u32 gimr; + + gimr =3D readl(REG(RTL_ICTL_GIMR)); + gimr &=3D ~BIT(hw_irq); + writel(gimr, REG(RTL_ICTL_GIMR)); +} + +static void write_irr(int hw_irq, u32 value) +{ + void __iomem *irr0 =3D REG(RTL_ICTL_IRR0); + unsigned int offset =3D IRR_OFFSET(hw_irq); + unsigned int shift =3D IRR_SHIFT(hw_irq); u32 irr; =20 irr =3D readl(irr0 + offset) & ~(0xf << shift); @@ -50,30 +69,14 @@ static void write_irr(void __iomem *irr0, int idx, u32 = value) =20 static void realtek_ictl_unmask_irq(struct irq_data *i) { - unsigned long flags; - u32 value; - - raw_spin_lock_irqsave(&irq_lock, flags); - - value =3D readl(REG(RTL_ICTL_GIMR)); - value |=3D BIT(i->hwirq); - writel(value, REG(RTL_ICTL_GIMR)); - - raw_spin_unlock_irqrestore(&irq_lock, flags); + guard(raw_spinlock)(&irq_lock); + enable_gimr(i->hwirq); } =20 static void realtek_ictl_mask_irq(struct irq_data *i) { - unsigned long flags; - u32 value; - - raw_spin_lock_irqsave(&irq_lock, flags); - - value =3D readl(REG(RTL_ICTL_GIMR)); - value &=3D ~BIT(i->hwirq); - writel(value, REG(RTL_ICTL_GIMR)); - - raw_spin_unlock_irqrestore(&irq_lock, flags); + guard(raw_spinlock)(&irq_lock); + disable_gimr(i->hwirq); } =20 static struct irq_chip realtek_ictl_irq =3D { @@ -84,13 +87,10 @@ static struct irq_chip realtek_ictl_irq =3D { =20 static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_= t hw) { - unsigned long flags; - irq_set_chip_and_handler(irq, &realtek_ictl_irq, handle_level_irq); =20 - raw_spin_lock_irqsave(&irq_lock, flags); - write_irr(REG(RTL_ICTL_IRR0), hw, 1); - raw_spin_unlock_irqrestore(&irq_lock, flags); + guard(raw_spinlock_irqsave)(&irq_lock); + write_irr(hw, 1); =20 return 0; } @@ -127,7 +127,6 @@ static int __init realtek_rtl_of_init(struct device_nod= e *node, struct device_no { struct of_phandle_args oirq; struct irq_domain *domain; - unsigned int soc_irq; int parent_irq; =20 realtek_ictl_base =3D of_iomap(node, 0); @@ -135,9 +134,10 @@ static int __init realtek_rtl_of_init(struct device_no= de *node, struct device_no return -ENXIO; =20 /* Disable all cascaded interrupts and clear routing */ - writel(0, REG(RTL_ICTL_GIMR)); - for (soc_irq =3D 0; soc_irq < RTL_ICTL_NUM_INPUTS; soc_irq++) - write_irr(REG(RTL_ICTL_IRR0), soc_irq, 0); + for (unsigned int soc_irq =3D 0; soc_irq < RTL_ICTL_NUM_INPUTS; soc_irq++= ) { + disable_gimr(soc_irq); + write_irr(soc_irq, 0); + } =20 if (WARN_ON(!of_irq_count(node))) { /* --=20 2.54.0 From nobody Mon Jun 8 08:36:18 2026 Received: from mout.gmx.net (mout.gmx.net [212.227.17.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 62AB7374739 for ; Thu, 4 Jun 2026 13:06:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=212.227.17.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780578403; cv=none; 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hM4HqhbIN1PcA3ZXr63cfo2DOF8cIhnpKRBdi1LFEQ0Ac6L8lWq3dcxLoI4y7E39a5ruVkES+ RKVbx8k+bKTSO6PwyCNY4sMHV3dlxGi0MdBY2elFPev15XzfNE9GY9dGKefgajixkyMU1K1a0 Jt6rF7pK0TH47AY1EwW0KPx9L8xAi/a5oqDWiooxWlLKBHLdSfOckzvUb9mVOcd7qg3zyA== Content-Type: text/plain; charset="utf-8" The Realtek interrupt driver currently supports only single core systems. So the higher end devices like RTL839x and RTL930x with dual VPEs must be driven with NR_CPU=3D1. Enhance the driver to support multicore (dual VPE) systems. For this: - Extend the register map for multiple cores - Search for multiple CPU cores in the devicetree - Improve the register helpers to support multiple cores - Add an affinity setter - Enhance the IRQ handler for multiple cores Signed-off-by: Markus Stockhausen --- drivers/irqchip/irq-realtek-rtl.c | 92 ++++++++++++++++++++++--------- 1 file changed, 67 insertions(+), 25 deletions(-) diff --git a/drivers/irqchip/irq-realtek-rtl.c b/drivers/irqchip/irq-realte= k-rtl.c index 4e2996eb671e..eb7842932c9d 100644 --- a/drivers/irqchip/irq-realtek-rtl.c +++ b/drivers/irqchip/irq-realtek-rtl.c @@ -23,10 +23,11 @@ =20 #define RTL_ICTL_NUM_INPUTS 32 =20 -#define REG(x) (realtek_ictl_base + x) +#define REG(cpu, x) (realtek_ictl_base[cpu] + x) =20 static DEFINE_RAW_SPINLOCK(irq_lock); -static void __iomem *realtek_ictl_base; +static void __iomem *realtek_ictl_base[NR_CPUS]; +static cpumask_t realtek_ictl_cpu_configurable; =20 /* * IRR0-IRR3 store 4 bits per interrupt, but Realtek uses inverted numberi= ng, @@ -37,27 +38,27 @@ static void __iomem *realtek_ictl_base; #define IRR_OFFSET(idx) (4 * (3 - (idx * 4) / 32)) #define IRR_SHIFT(idx) ((idx * 4) % 32) =20 -static inline void enable_gimr(unsigned int hw_irq) +static inline void enable_gimr(unsigned int cpu, unsigned int hw_irq) { u32 gimr; =20 - gimr =3D readl(REG(RTL_ICTL_GIMR)); + gimr =3D readl(REG(cpu, RTL_ICTL_GIMR)); gimr |=3D BIT(hw_irq); - writel(gimr, REG(RTL_ICTL_GIMR)); + writel(gimr, REG(cpu, RTL_ICTL_GIMR)); } =20 -static inline void disable_gimr(unsigned int hw_irq) +static inline void disable_gimr(unsigned int cpu, unsigned int hw_irq) { u32 gimr; =20 - gimr =3D readl(REG(RTL_ICTL_GIMR)); + gimr =3D readl(REG(cpu, RTL_ICTL_GIMR)); gimr &=3D ~BIT(hw_irq); - writel(gimr, REG(RTL_ICTL_GIMR)); + writel(gimr, REG(cpu, RTL_ICTL_GIMR)); } =20 -static void write_irr(int hw_irq, u32 value) +static void write_irr(unsigned int cpu, int hw_irq, u32 value) { - void __iomem *irr0 =3D REG(RTL_ICTL_IRR0); + void __iomem *irr0 =3D REG(cpu, RTL_ICTL_IRR0); unsigned int offset =3D IRR_OFFSET(hw_irq); unsigned int shift =3D IRR_SHIFT(hw_irq); u32 irr; @@ -69,28 +70,61 @@ static void write_irr(int hw_irq, u32 value) =20 static void realtek_ictl_unmask_irq(struct irq_data *i) { + unsigned int cpu; + guard(raw_spinlock)(&irq_lock); - enable_gimr(i->hwirq); + for_each_cpu(cpu, irq_data_get_effective_affinity_mask(i)) + enable_gimr(cpu, i->hwirq); } =20 static void realtek_ictl_mask_irq(struct irq_data *i) { + unsigned int cpu; + guard(raw_spinlock)(&irq_lock); - disable_gimr(i->hwirq); + for_each_cpu(cpu, &realtek_ictl_cpu_configurable) + disable_gimr(cpu, i->hwirq); +} + +static int realtek_ictl_irq_affinity(struct irq_data *i, const struct cpum= ask *dest, bool force) +{ + cpumask_t cpu_configure, cpu_disable, cpu_enable; + unsigned int cpu; + + cpumask_and(&cpu_configure, cpu_present_mask, &realtek_ictl_cpu_configura= ble); + cpumask_and(&cpu_enable, &cpu_configure, dest); + cpumask_andnot(&cpu_disable, &cpu_configure, dest); + + scoped_guard(raw_spinlock, &irq_lock) { + for_each_cpu(cpu, &cpu_disable) + disable_gimr(cpu, i->hwirq); + for_each_cpu(cpu, &cpu_enable) { + if (!irqd_irq_masked(i)) + enable_gimr(cpu, i->hwirq); + } + } + + irq_data_update_effective_affinity(i, &cpu_enable); + + return IRQ_SET_MASK_OK; } =20 static struct irq_chip realtek_ictl_irq =3D { - .name =3D "realtek-rtl-intc", - .irq_mask =3D realtek_ictl_mask_irq, - .irq_unmask =3D realtek_ictl_unmask_irq, + .name =3D "realtek-rtl-intc", + .irq_mask =3D realtek_ictl_mask_irq, + .irq_unmask =3D realtek_ictl_unmask_irq, + .irq_set_affinity =3D realtek_ictl_irq_affinity, }; =20 static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_= t hw) { + unsigned int cpu; + irq_set_chip_and_handler(irq, &realtek_ictl_irq, handle_level_irq); =20 guard(raw_spinlock_irqsave)(&irq_lock); - write_irr(hw, 1); + for_each_cpu(cpu, &realtek_ictl_cpu_configurable) + write_irr(cpu, hw, 1); =20 return 0; } @@ -103,12 +137,13 @@ static const struct irq_domain_ops irq_domain_ops =3D= { static void realtek_irq_dispatch(struct irq_desc *desc) { struct irq_chip *chip =3D irq_desc_get_chip(desc); + unsigned int cpu =3D smp_processor_id(); struct irq_domain *domain; unsigned long pending; unsigned int soc_int; =20 chained_irq_enter(chip, desc); - pending =3D readl(REG(RTL_ICTL_GIMR)) & readl(REG(RTL_ICTL_GISR)); + pending =3D readl(REG(cpu, RTL_ICTL_GIMR)) & readl(REG(cpu, RTL_ICTL_GISR= )); =20 if (unlikely(!pending)) { spurious_interrupt(); @@ -129,16 +164,23 @@ static int __init realtek_rtl_of_init(struct device_n= ode *node, struct device_no struct irq_domain *domain; int parent_irq; =20 - realtek_ictl_base =3D of_iomap(node, 0); - if (!realtek_ictl_base) - return -ENXIO; - - /* Disable all cascaded interrupts and clear routing */ - for (unsigned int soc_irq =3D 0; soc_irq < RTL_ICTL_NUM_INPUTS; soc_irq++= ) { - disable_gimr(soc_irq); - write_irr(soc_irq, 0); + cpumask_clear(&realtek_ictl_cpu_configurable); + + for (unsigned int cpu =3D 0; cpu < NR_CPUS; cpu++) { + realtek_ictl_base[cpu] =3D of_iomap(node, cpu); + if (realtek_ictl_base[cpu]) { + cpumask_set_cpu(cpu, &realtek_ictl_cpu_configurable); + /* Disable all cascaded interrupts and clear routing */ + for (unsigned int soc_irq =3D 0; soc_irq < RTL_ICTL_NUM_INPUTS; soc_irq= ++) { + disable_gimr(cpu, soc_irq); + write_irr(cpu, soc_irq, 0); + } + } } =20 + if (cpumask_empty(&realtek_ictl_cpu_configurable)) + return -ENXIO; + if (WARN_ON(!of_irq_count(node))) { /* * If DT contains no parent interrupts, assume MIPS CPU IRQ 2 --=20 2.54.0