From nobody Mon Jun 8 09:49:26 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D36CD425CE1; Thu, 4 Jun 2026 11:45:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780573529; cv=none; b=Z2nkp2jg8lEWJcwb1jlY8r2DAyp242iEEChFIX3KrCtxFNCBagsgpr+ZHzEsIydjoFJeWd9G4Z/enJNgspNGbqhJwCwrOLu7/KG/asbpD7/Bn9IugFfcSzi5+94KLHqK56jODBY0FuGVcEeO0xMNHyZErekipdKYb9Dpb/l5WMg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780573529; c=relaxed/simple; bh=vebusa1eZmDb3cD4rm8P2Yx27GhxkEHXrT/cIyaVmwk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Ro5hhH6fzt0zH7lHdFdb86JiAel6957tS0S6chjxzZ5EBSzXsvKlYa+Ha1eXQXw96VThRsP6MUqwhsVljT0ef9dBVyXuztC/q8794wTkxp9q9+XaUE8kYrFzRSlZEv2QJhGtMVr9MlJPHJ8cFSisAGwZL7vEMplnPIC3+xl0zac= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=Wh2ceaXS; arc=none smtp.client-ip=220.197.31.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="Wh2ceaXS" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=YM /9VqWu3m7TrPwzFB5YPC2jCH/xULVDjTWw9xL6Ghk=; b=Wh2ceaXSLV+HfK+/Rt YocLHgKG93qEPocEWv1sI5MAMOjuKSSVtleOlAHL0HMo5jG3qam+ed6BkiV90N+W /rQDD9NsGIYblZrDu/0EhDZIwrpoGS66YvXjMKv6pJB0nN2dbE00OFGtR4hJRrhJ W0M5mXY5H/tDbbSaLHucdyoxM= Received: from localhost.localdomain (unknown []) by gzsmtp1 (Coremail) with SMTP id PCgvCgA320NHZSFqPEN8AQ--.47837S3; Thu, 04 Jun 2026 19:45:12 +0800 (CST) From: hginjgerx@163.com To: huangjunxian6@hisilicon.com, hginjgerx@qq.com Cc: Chengchang Tang , Jason Gunthorpe , Leon Romanovsky , linux-rdma@vger.kernel.org (open list:HISILICON ROCE DRIVER), linux-kernel@vger.kernel.org (open list) Subject: [PATCH for-next 1/3] RDMA/hns: Fix hung task when drain qp failed. Date: Thu, 4 Jun 2026 19:45:08 +0800 Message-Id: <20260604114510.2955010-2-hginjgerx@163.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20260604114510.2955010-1-hginjgerx@163.com> References: <20260604114510.2955010-1-hginjgerx@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: PCgvCgA320NHZSFqPEN8AQ--.47837S3 X-Coremail-Antispam: 1Uf129KBjvJXoW7CryxuF45ArW8trW5WFW8Xrb_yoW8Cr4fpF 4Yka45KFWDGFnF9a1xJr4a9w1ftaykG3ykWrZ7Ka43trnxCa1Fqr18t34UtFWrJrZ5J3W2 vr90grsruFyIvaUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07ji3kZUUUUU= X-CM-SenderInfo: hkjl0yhjhu5qqrwthudrp/xtbC5AhOIWohZUhmDAAA3P Content-Type: text/plain; charset="utf-8" From: Chengchang Tang The flush CQE is executed asynchronously. If the drain QP has already triggered the flush CQE, but a HW error occurs during this process, the driver is unable to detect the flush failure. In this case, the drain QP thread will wait for the completion signal indefinitely by using wait_for_completion(), leading to a hung task exception warning. Replace wait_for_completion() with wait_for_completion_timeout() to avoid indefinite waiting. Fixes: 354e7a6d448b ("RDMA/hns: Support drain SQ and RQ") Signed-off-by: Chengchang Tang Signed-off-by: Junxian Huang --- drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniban= d/hw/hns/hns_roce_hw_v2.c index 4afd7d6ae3ca..fe3c658d8c08 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c @@ -914,6 +914,7 @@ static void handle_drain_completion(struct ib_cq *ibcq, struct hns_roce_drain_cqe *drain, struct hns_roce_dev *hr_dev) { +#define DRAIN_QP_TMO (HZ * 30) #define TIMEOUT (HZ / 10) struct hns_roce_cq *hr_cq =3D to_hr_cq(ibcq); unsigned long flags; @@ -958,8 +959,10 @@ static void handle_drain_completion(struct ib_cq *ibcq, ibcq->comp_handler(ibcq, ibcq->cq_context); =20 waiting_done: - if (ibcq->comp_handler) - wait_for_completion(&drain->done); + if (ibcq->comp_handler) { + if (!wait_for_completion_timeout(&drain->done, DRAIN_QP_TMO)) + ibdev_err_ratelimited(&hr_dev->ib_dev, "Drain qp timeout!\n"); + } } =20 static void hns_roce_v2_drain_rq(struct ib_qp *ibqp) --=20 2.33.0 From nobody Mon Jun 8 09:49:26 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 19E48426D16; Thu, 4 Jun 2026 11:45:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780573536; cv=none; b=nULr839S66Cex0SoOhqQ3gcV+yTc7zKnwxJkvr9CXnHz6BTo0U7wjvhlrItasbaVUm8WRBsZ+ZDCVFselTUiM/HlorctBeqyz7hy90kg1ITF5uuwMLefeUWrqk+ApQJ4rigjjzzrz9X0CYHOIi0kLbjxk+sz+dsjVGWq1Lp5Z4s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780573536; c=relaxed/simple; bh=Y2EG4aOxO040LBpGxzCAh1VuYkFd1xkARY/Fvs7+ZWc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Q86kj+pTHAelZj9IEH3zLNq2a0pzrk+8MYhaZy1T/JSq6cMbZ+scp27Z7diFQgf7KMvgK7BzwxsKf02RxVFYxwDWKh/Z0M/EjWA9tCxyLqjFfpZn/eaSUBFBo867pSmxME5VhjyYPa7EO/OEcd+DH8DDneq7oqDjFqTFUZkbVWw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=M1jNZ3kk; arc=none smtp.client-ip=220.197.31.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="M1jNZ3kk" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=A7 ZV5UyuVvyiqz1npEjK5bSRrlubam+AGqOWOLPx6yY=; b=M1jNZ3kkcVHCkh1p2I UOy/bU+qw5Es2fJ55NxvR8wuM5UOvYnG+oyD58GEZ9xIA/A5U2mWoH1oBO//oKoO fLoH3MF8LnCtGk12daYNzulsZCcfgVajNVFVyLJ/8FLZD0Ed8PXFWDVkPnfKS2y8 h2kmqmNUBOq7OMoqm2S41yyaE= Received: from localhost.localdomain (unknown []) by gzsmtp1 (Coremail) with SMTP id PCgvCgA320NHZSFqPEN8AQ--.47837S4; Thu, 04 Jun 2026 19:45:13 +0800 (CST) From: hginjgerx@163.com To: huangjunxian6@hisilicon.com, hginjgerx@qq.com Cc: Chengchang Tang , Jason Gunthorpe , Leon Romanovsky , linux-rdma@vger.kernel.org (open list:HISILICON ROCE DRIVER), linux-kernel@vger.kernel.org (open list) Subject: [PATCH for-next 2/3] RDMA/hns: Fix missing CQE when UD QP use different SL Date: Thu, 4 Jun 2026 19:45:09 +0800 Message-Id: <20260604114510.2955010-3-hginjgerx@163.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20260604114510.2955010-1-hginjgerx@163.com> References: <20260604114510.2955010-1-hginjgerx@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: PCgvCgA320NHZSFqPEN8AQ--.47837S4 X-Coremail-Antispam: 1Uf129KBjvJXoWxCry3ArWDuF45Cw4kCw1xXwb_yoW5Ary7pF W5AasIkrW5G3Wj9a129a17Zr9xtasrKw1DGFyvkasI9F1aka98KF1vyryUJFykJrykGr13 Xr45Jrnxua4xuF7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07jEHqcUUUUU= X-CM-SenderInfo: hkjl0yhjhu5qqrwthudrp/xtbC-wlOIWohZUmflgAA33 Content-Type: text/plain; charset="utf-8" From: Chengchang Tang Due to the HW issue, CQE may be dropped if UD QP use multiple SLs. Fixes: 926a01dc000d ("RDMA/hns: Add QP operations support for hip08 SoC") Signed-off-by: Chengchang Tang Signed-off-by: Junxian Huang --- drivers/infiniband/hw/hns/hns_roce_device.h | 1 + drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 15 ++++++++++----- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/infiniband/hw/hns/hns_roce_device.h b/drivers/infiniba= nd/hw/hns/hns_roce_device.h index eb7b1865e4c7..686610642c0a 100644 --- a/drivers/infiniband/hw/hns/hns_roce_device.h +++ b/drivers/infiniband/hw/hns/hns_roce_device.h @@ -654,6 +654,7 @@ struct hns_roce_qp { u8 priority; spinlock_t flush_lock; struct hns_roce_dip *dip; + bool ud_sl_set; }; =20 struct hns_roce_ib_iboe { diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniban= d/hw/hns/hns_roce_hw_v2.c index fe3c658d8c08..6dd56a85d890 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c @@ -431,7 +431,8 @@ static int set_ud_opcode(struct hns_roce_v2_ud_send_wqe= *ud_sq_wqe, return 0; } =20 -static int fill_ud_av(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, +static int fill_ud_av(struct hns_roce_qp *qp, + struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, struct hns_roce_ah *ah) { struct ib_device *ib_dev =3D ah->ibah.device; @@ -441,7 +442,12 @@ static int fill_ud_av(struct hns_roce_v2_ud_send_wqe *= ud_sq_wqe, hr_reg_write(ud_sq_wqe, UD_SEND_WQE_HOPLIMIT, ah->av.hop_limit); hr_reg_write(ud_sq_wqe, UD_SEND_WQE_TCLASS, ah->av.tclass); hr_reg_write(ud_sq_wqe, UD_SEND_WQE_FLOW_LABEL, ah->av.flowlabel); - hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SL, ah->av.sl); + if (!qp->ud_sl_set) { + qp->sl =3D ah->av.sl; + qp->ud_sl_set =3D true; + } + + hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SL, qp->sl); =20 ud_sq_wqe->sgid_index =3D ah->av.gid_index; =20 @@ -491,12 +497,10 @@ static inline int set_ud_wqe(struct hns_roce_qp *qp, qp->qkey : ud_wr(wr)->remote_qkey); hr_reg_write(ud_sq_wqe, UD_SEND_WQE_DQPN, ud_wr(wr)->remote_qpn); =20 - ret =3D fill_ud_av(ud_sq_wqe, ah); + ret =3D fill_ud_av(qp, ud_sq_wqe, ah); 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charset="utf-8" From: Chengchang Tang Add debugfs interface to set SL for GSI QP. The interface validates that SL value does not exceed MAX_SERVICE_LEVEL. The GSI QP uses the configured SL instead of the SL from AH when posting UD SQ WQE. Signed-off-by: Chengchang Tang Signed-off-by: Junxian Huang --- drivers/infiniband/hw/hns/hns_roce_debugfs.c | 30 ++++++++++++++++++++ drivers/infiniband/hw/hns/hns_roce_debugfs.h | 1 + drivers/infiniband/hw/hns/hns_roce_device.h | 1 + drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 5 ++-- 4 files changed, 35 insertions(+), 2 deletions(-) diff --git a/drivers/infiniband/hw/hns/hns_roce_debugfs.c b/drivers/infinib= and/hw/hns/hns_roce_debugfs.c index 05630f7c9155..2f9410fdd0d7 100644 --- a/drivers/infiniband/hw/hns/hns_roce_debugfs.c +++ b/drivers/infiniband/hw/hns/hns_roce_debugfs.c @@ -339,6 +339,29 @@ static void create_cc_param_debugfs(struct hns_roce_de= v *hr_dev, } } =20 +static int gsi_sl_debugfs_read(struct seq_file *seq, void *data) +{ + struct hns_roce_dev *hr_dev =3D data; + + seq_printf(seq, "%u\n", hr_dev->gsi_sl); + return 0; +} + +static ssize_t gsi_sl_debugfs_write(char *buf, size_t count, void *data) +{ + struct hns_roce_dev *hr_dev =3D data; + u32 val; + + if (kstrtou32(buf, 0, &val)) + return -EINVAL; + + if (val > MAX_SERVICE_LEVEL) + return -EINVAL; + + hr_dev->gsi_sl =3D val; + return count; +} + /* debugfs for device */ void hns_roce_register_debugfs(struct hns_roce_dev *hr_dev) { @@ -349,6 +372,13 @@ void hns_roce_register_debugfs(struct hns_roce_dev *hr= _dev) =20 create_sw_stat_debugfs(hr_dev, dbgfs->root); create_cc_param_debugfs(hr_dev, dbgfs->root); + + dbgfs->gsi_sl_seqfile.read =3D gsi_sl_debugfs_read; + dbgfs->gsi_sl_seqfile.write =3D gsi_sl_debugfs_write; + dbgfs->gsi_sl_seqfile.data =3D hr_dev; + debugfs_create_file("gsi_sl", 0600, dbgfs->root, + &dbgfs->gsi_sl_seqfile, + &hns_debugfs_seqfile_fops); } =20 void hns_roce_unregister_debugfs(struct hns_roce_dev *hr_dev) diff --git a/drivers/infiniband/hw/hns/hns_roce_debugfs.h b/drivers/infinib= and/hw/hns/hns_roce_debugfs.h index 116b1e8b6677..f04683900022 100644 --- a/drivers/infiniband/hw/hns/hns_roce_debugfs.h +++ b/drivers/infiniband/hw/hns/hns_roce_debugfs.h @@ -47,6 +47,7 @@ struct hns_roce_dev_debugfs { struct dentry *root; struct hns_sw_stat_debugfs sw_stat_root; struct hns_cc_param_debugfs cc_param_root[CONG_TYPE_MAX_NUM]; + struct hns_debugfs_seqfile gsi_sl_seqfile; }; =20 struct hns_roce_dev; diff --git a/drivers/infiniband/hw/hns/hns_roce_device.h b/drivers/infiniba= nd/hw/hns/hns_roce_device.h index 686610642c0a..8a5a116efd9e 100644 --- a/drivers/infiniband/hw/hns/hns_roce_device.h +++ b/drivers/infiniband/hw/hns/hns_roce_device.h @@ -1048,6 +1048,7 @@ struct hns_roce_dev { struct hns_roce_dev_debugfs dbgfs; atomic64_t *dfx_cnt; struct hns_roce_scc_param *scc_param; + u8 gsi_sl; }; =20 enum hns_roce_trace_type { diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniban= d/hw/hns/hns_roce_hw_v2.c index 6dd56a85d890..8d6444f44553 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c @@ -442,8 +442,9 @@ static int fill_ud_av(struct hns_roce_qp *qp, hr_reg_write(ud_sq_wqe, UD_SEND_WQE_HOPLIMIT, ah->av.hop_limit); hr_reg_write(ud_sq_wqe, UD_SEND_WQE_TCLASS, ah->av.tclass); hr_reg_write(ud_sq_wqe, UD_SEND_WQE_FLOW_LABEL, ah->av.flowlabel); - if (!qp->ud_sl_set) { - qp->sl =3D ah->av.sl; + if (!qp->ud_sl_set || qp->ibqp.qp_type =3D=3D IB_QPT_GSI) { + qp->sl =3D qp->ibqp.qp_type =3D=3D IB_QPT_GSI ? + hr_dev->gsi_sl : ah->av.sl; qp->ud_sl_set =3D true; } =20 --=20 2.33.0