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Thu, 4 Jun 2026 04:45:29 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , Shay Drory , Or Har-Toov , Edward Srouji , Simon Horman , Maher Sanalla , Parav Pandit , Kees Cook , Moshe Shemesh , Patrisious Haddad , , , , Gal Pressman Subject: [PATCH net-next 01/15] net/mlx5: E-Switch, skip uplink IB rep load for SD secondary devices Date: Thu, 4 Jun 2026 14:44:41 +0300 Message-ID: <20260604114455.434711-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260604114455.434711-1-tariqt@nvidia.com> References: <20260604114455.434711-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B1:EE_|PH7PR12MB7425:EE_ X-MS-Office365-Filtering-Correlation-Id: 42358554-5aea-4d5d-d298-08dec22ed2af X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|376014|1800799024|7416014|82310400026|11063799006|56012099006|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: LEzDfpJm27t/iiOHwoFNIV1Gm34bmrp5zqninbgqJC3Nmom7JqIl1Ax7B4J1HpSj93yesAvXBPQTibH4nO0YKXY6Rg7BuJ1kSNzBBuIsDtMcn6KfStKvqrqHhkyWMigeVarBqDIxbT4hWpGc6ST4QL94fqxM2gT97e40fKwzHp6q+5q9dc5+gMnd/LdxWPfmI/t81AzUa+/w5eZTG2MY53jdfY1YgMLvgGi6rqs8cd4yUR6Kd8NeFv0EaTWjqbjPRnZmWMLR62S1dEG8ym6479SNaEb8a8QRr9aMo00HwVVD5UbMR/g0z2lUbktF4bEvAsiCjWrHEuGgbGxoaNbeXL5iZTi5U82eMGx5WtFWhOJAuLuvoD/lanjN0Y7IALIB6vlnR03tHqZI6yDaF3KDMK6ygblGxOAKGtBVmrHU7JEPaldeDUOo8mKkA6MpBg4EzJ+PAqFHAoescWHHW8vfSrUPGw8XSpLuUfQxpEaNBpMb6ee9n92JZYYKlnenGtprM0TF5PGtypt/5lcTv+WpD8R4m5t+PL/tV4V8KKbJpmSAoSuPlCHBU79xwqL0MoQFaNj7j7Ajv1kj50iMBciIpOc2eq7YI0EwOFtc1O/wWZpnpZEPkiMY4049RECXryCyPH4w53n5B1WSz8N+k691StkJ6huwukJkoEjmJUStW25wZkGC+XVxd9Rrj+vBW+kpuaZq/mKOiOzCYuVl7lBu7Oe68Tpddx30UAKo/M0jh78= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(376014)(1800799024)(7416014)(82310400026)(11063799006)(56012099006)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: QxWNex0J95XWE6go/GkqHOR07NE+vsKWg/ihbzWOJE+fHU1bMmQdqySmY8rpt/0G+33FIuTr/nZButlqjLxS7MxkR+pRl1YX/w6/kPCLRxjHpOIjcEfL7BY9IF/KsPTl+KuQwk/sE+KVGiU2lRYkEtdm9L/qvoHqTCR5exP9GCiWdAyzP6gOydGV1ykxByr0UEgdv8wTm/wC3gRxUDABNbIXBZTDQjaN7086Hpy3hDM5o98FYKnS7833mtPbZgGjYRIJj9bl2dBVyuPB3n7VMzppLSVsriuqs7yWUOdcaHDGcNgx10FDY+2yiuBsJSuBWpBaBQBOCMrPrOBEj1bVugVb05aZwzFTHXiTa8cnhHQQfuzrilNl50oBI8bX1I63ZivNlIf8xfmohlZRvUDR2FxijqTsM5yuu6RkYodciNiHIEXUQzPTM1KR+9JrZcre X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jun 2026 11:45:49.1081 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 42358554-5aea-4d5d-d298-08dec22ed2af X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7425 Content-Type: text/plain; charset="utf-8" From: Shay Drory SD secondary devices share the primary's uplink and do not have their own uplink representor. When reloading IB reps on secondary devices, skip the uplink and only load VF/SF vport IB reps. Signed-off-by: Shay Drory Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/eswitch_offloads.c | 25 ++++++++++++++++--- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/d= rivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index 830fc910a080..12805e80ce57 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -3643,11 +3643,19 @@ int mlx5_eswitch_reload_ib_reps(struct mlx5_eswitch= *esw) if (atomic_read(&rep->rep_data[REP_ETH].state) !=3D REP_LOADED) return 0; =20 - ret =3D __esw_offloads_load_rep(esw, rep, REP_IB, NULL); - if (ret) - return ret; + /* SD secondary devices share the primary's uplink and do not + * have their own uplink representor. Only load VF/SF vports. + */ + if (mlx5_sd_is_primary(esw->dev)) { + ret =3D __esw_offloads_load_rep(esw, rep, REP_IB, NULL); + if (ret) + return ret; + } =20 mlx5_esw_for_each_rep(esw, i, rep) { + if (!mlx5_sd_is_primary(esw->dev) && + rep->vport =3D=3D MLX5_VPORT_UPLINK) + continue; if (atomic_read(&rep->rep_data[REP_ETH].state) =3D=3D REP_LOADED) __esw_offloads_load_rep(esw, rep, REP_IB, NULL); } @@ -4586,14 +4594,23 @@ mlx5_eswitch_register_vport_reps_blocked(struct mlx= 5_eswitch *esw, =20 static void mlx5_eswitch_reload_reps_blocked(struct mlx5_eswitch *esw) { + struct mlx5_eswitch_rep *uplink; struct mlx5_vport *vport; + bool newly_loaded; unsigned long i; =20 if (esw->mode !=3D MLX5_ESWITCH_OFFLOADS) return; =20 - if (mlx5_esw_offloads_rep_load(esw, MLX5_VPORT_UPLINK)) + uplink =3D mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK); + if (__esw_offloads_load_rep(esw, uplink, REP_ETH, &newly_loaded)) + return; + if (mlx5_sd_is_primary(esw->dev) && + __esw_offloads_load_rep(esw, uplink, REP_IB, NULL)) { + if (newly_loaded) + __esw_offloads_unload_rep(esw, uplink, REP_ETH); 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Thu, 4 Jun 2026 04:45:35 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , Shay Drory , Or Har-Toov , Edward Srouji , Simon Horman , Maher Sanalla , Parav Pandit , Kees Cook , Moshe Shemesh , Patrisious Haddad , , , , Gal Pressman Subject: [PATCH net-next 02/15] net/mlx5: devcom, expose locked variant of send_event Date: Thu, 4 Jun 2026 14:44:42 +0300 Message-ID: <20260604114455.434711-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260604114455.434711-1-tariqt@nvidia.com> References: <20260604114455.434711-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A3:EE_|CY8PR12MB7491:EE_ X-MS-Office365-Filtering-Correlation-Id: f4e4fab3-fed6-4b21-5aec-08dec22ed376 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|7416014|376014|1800799024|22082099003|18002099003|6133799003|11063799006|56012099006; X-Microsoft-Antispam-Message-Info: 0uiydLsDRzHyi16ym7U+jH3XuCqN7e1MMHFh/tLGjn3FbYFR7EK1ulU40z2V0GUrPWC1iOLI5UzcQO3ce6LGvmya9k5q342+EAUai1BpivBAgYo8ARIDWC86WT0Rr6hkJJKCf5fXL0PLj7zMNplLf8v9R5vttSQ9GUq2EUdY98J/bgIL4vgoq1DMCrdiBJVtOztQiRlLlYAp2iSB79VaCuGo6HhijDwhJpJaZfrGT+Rt6YAd3tPM3c2+msk+gTAMrwsefb2kGYAO8ROsx2QRvz6NsqP45yQ0IZy6+vZ82SzoOVtifhCfmfYc+NfvEU3BdXNxjG64ysCq9xnKzEcMXlbsRfsQDeDyvPIJqP09TO/haRm9VEQWv0E2BFCF9nE8/Frj7HVDRCKqYSz2+YsjdMUIJ8+M9usDSDHMAzXbV/txjYdRfp2wWBmC9G9ztomF81IlmHTY6wIG02YFT3MNWIo7waVx6UlZrEYvcsCXlGMZ+F0zfszda67av59fTOUKZEmBcss9LIXB1c8OAE4bMUaUM0Ijak1EtzMkZeNRt9/nI668CfS1yWesjDMR3VsKerGrWrpJ4ivFAKkQeBV2raGo3i+ArqOH6UyWkL6X1YhTdvzDB/OQMAZ9xRK4fo/uElUMt+iP0fp378ZNayyUJwvRRiob4uom7j6pyjlR5sUQSTu8tVTUJFcpZTDojbZc+0uydJHXbFJ0uaBu+IKFv2v3EoF3Xs1rsQY/23/Auo4= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(82310400026)(7416014)(376014)(1800799024)(22082099003)(18002099003)(6133799003)(11063799006)(56012099006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: zHCnFwzuc3e+Ehg52ACt5NIVCCRFgqtXcnTObTNx3hJi2GoWVFyi5qptI3s/9AbmCMceB645RkUazo1PoNQmNmQAob4hd5IZuyY/i4O/Cq6rQNkrgwcy5No1ISK6hZJjvRrmICM1G2BVR+aaLzwitQ7VILfEDDS/1MFYEiE5IXRTxZCfqQLWDseLFHE0He/J+xON4DZ6HIPdJig5NMOyCXRJsMeo5hlEswZBQsCp2CKdeWb5w7JXL4Hhd00hrmXFJLIF+isGq0qse/QGkRIeqPMfvUwt8Hyj2dS66ThiBVsN6sMLwWNkEqhMT16k+GDMea94Rg0Wjy4JVB6WGK2fP05yTlLNpcXTewmsnD2evp3crf7bdjbZzzvZDasf3pL4SuflR4utEp6mIeFSkmWX57PEhH0e9tuDCKY1d8r5R1cNUeAMSVlFWBcpksTQiNdz X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jun 2026 11:45:50.3335 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f4e4fab3-fed6-4b21-5aec-08dec22ed376 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A3.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7491 Content-Type: text/plain; charset="utf-8" From: Shay Drory Factor mlx5_devcom_send_event() into two functions: - mlx5_devcom_locked_send_event(): performs the dispatch (and rollback) with comp->sem already held by the caller. - mlx5_devcom_send_event(): unchanged wrapper that takes comp->sem, calls the locked variant, and releases it. This lets callers bracket multiple event broadcasts under a single held write lock, eliminating the gap between consecutive dispatches where peer state could change. Will be used by a downstream patch. Signed-off-by: Shay Drory Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/lib/devcom.c | 29 ++++++++++++++----- .../ethernet/mellanox/mlx5/core/lib/devcom.h | 3 ++ 2 files changed, 25 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.c b/drivers= /net/ethernet/mellanox/mlx5/core/lib/devcom.c index d40c53193ea8..96b4f06d6184 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.c @@ -287,9 +287,9 @@ int mlx5_devcom_comp_get_size(struct mlx5_devcom_comp_d= ev *devcom) return kref_read(&comp->ref); } =20 -int mlx5_devcom_send_event(struct mlx5_devcom_comp_dev *devcom, - int event, int rollback_event, - void *event_data) +int mlx5_devcom_locked_send_event(struct mlx5_devcom_comp_dev *devcom, + int event, int rollback_event, + void *event_data) { struct mlx5_devcom_comp_dev *pos; struct mlx5_devcom_comp *comp; @@ -299,8 +299,8 @@ int mlx5_devcom_send_event(struct mlx5_devcom_comp_dev = *devcom, if (!devcom) return -ENODEV; =20 + lockdep_assert_held_write(&devcom->comp->sem); comp =3D devcom->comp; - down_write(&comp->sem); list_for_each_entry(pos, &comp->comp_dev_list_head, list) { data =3D rcu_dereference_protected(pos->data, lockdep_is_held(&comp->sem= )); =20 @@ -311,12 +311,11 @@ int mlx5_devcom_send_event(struct mlx5_devcom_comp_de= v *devcom, } } =20 - up_write(&comp->sem); return 0; =20 rollback: if (list_entry_is_head(pos, &comp->comp_dev_list_head, list)) - goto out; + return err; pos =3D list_prev_entry(pos, list); list_for_each_entry_from_reverse(pos, &comp->comp_dev_list_head, list) { data =3D rcu_dereference_protected(pos->data, lockdep_is_held(&comp->sem= )); @@ -324,7 +323,23 @@ int mlx5_devcom_send_event(struct mlx5_devcom_comp_dev= *devcom, if (pos !=3D devcom && data) comp->handler(rollback_event, data, event_data); } -out: + return err; +} + +int mlx5_devcom_send_event(struct mlx5_devcom_comp_dev *devcom, + int event, int rollback_event, + void *event_data) +{ + struct mlx5_devcom_comp *comp; + int err; + + if (!devcom) + return -ENODEV; + + comp =3D devcom->comp; + down_write(&comp->sem); + err =3D mlx5_devcom_locked_send_event(devcom, event, rollback_event, + event_data); up_write(&comp->sem); return err; } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.h b/drivers= /net/ethernet/mellanox/mlx5/core/lib/devcom.h index 316052a85ca5..d5c60c03e55c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.h @@ -46,6 +46,9 @@ mlx5_devcom_register_component(struct mlx5_devcom_dev *de= vc, void *data); void mlx5_devcom_unregister_component(struct mlx5_devcom_comp_dev *devcom); =20 +int mlx5_devcom_locked_send_event(struct mlx5_devcom_comp_dev *devcom, + int event, int rollback_event, + void *event_data); int mlx5_devcom_send_event(struct mlx5_devcom_comp_dev *devcom, int event, int rollback_event, void *event_data); --=20 2.44.0 From nobody Mon Jun 8 09:48:39 2026 Received: from SN4PR0501CU005.outbound.protection.outlook.com (mail-southcentralusazon11011066.outbound.protection.outlook.com [40.93.194.66]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 133E6428830; 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , Shay Drory , Or Har-Toov , Edward Srouji , Simon Horman , Maher Sanalla , Parav Pandit , Kees Cook , Moshe Shemesh , Patrisious Haddad , , , , Gal Pressman Subject: [PATCH net-next 03/15] net/mlx5: devcom, add DEVCOM_CANT_FAIL for non-rollback events Date: Thu, 4 Jun 2026 14:44:43 +0300 Message-ID: <20260604114455.434711-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260604114455.434711-1-tariqt@nvidia.com> References: <20260604114455.434711-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A0:EE_|CY3PR12MB9702:EE_ X-MS-Office365-Filtering-Correlation-Id: 83c396f5-7a05-4886-8d00-08dec22ed9e9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|36860700016|376014|1800799024|82310400026|6133799003|18002099003|22082099003|11063799006|56012099006; X-Microsoft-Antispam-Message-Info: oD5vsTYIq1VPvv0adXMVbZpo7Q9DlXEbJVbHxBX1ZYb2djBdFcctecd38AbhNnaOxhXkW+CCRQFFKD7lxEb9IC9qWxC8gpaIXfs0ZzNQdr0LF+l3DaGSQMoBm5HLiiFbmsvodrUNiFSI0mw/dvee1NSaJcptC1vxJDxVfJXsMzlQQ9+8e90YJdbjWZCREOdPDpjeWuTjBBO/BSzW/G21C0cPLP6ZxGsjibezzhTaw3bOvgEUGYEL8x9WWU3xVjDf3Zm50xcPVge1QiTsVvpNi0q1Htr50G7pYuLDuxsd5Mm2Ue2peMcMsHZdttxqVpQ80q1/2TrXSu7zKOnJ6n2iAaX/xmLTeQvfJ5dSKle622LAC7+JOZIONA+T6CN7xSz9nhKwVtb1Pii8bo2qIRJG+OElTIl0T22INfqm7FLCKEsDRqMLcX7Hl/hrWpMnKClePLauTU2Jl+7YEINC1JAn3tDpUm5XtK71TbfYo5fAHAYrms3FsEhrmXCTr2nN2SlyUHMa3ICAXGokjPdsMdEO5tfIpdCVhS6HA0NVCB5PuPpZziYGJz2czQlQeR9gT6xNw8xEnLAxrEpyyZBPOmvIAAMAUDQA+aXz2aOpaI63ZxAEj8qcwqSrf90l+YbkDlB5S4/zL1pXHjOI0m8O0S8vyHVfCEpuKiIgEUYyovCUmZ9+n7M+Eng2O4ePRGDYPktHPWylLDJMcjk1R7A+hx2yHvqzsC3CVpytEwmhv18eykU= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(36860700016)(376014)(1800799024)(82310400026)(6133799003)(18002099003)(22082099003)(11063799006)(56012099006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: PXRnQoO5Qz8QsWbw0wl8fNGaOLXHimyAK6EjFcrN4cEY33ck1p9QPfPz92MAMtBvOmU1ytIMJX8O69P1i2kNwgMwAhzvnNfEpYXcI4ytYIE5pCiVHUY91PPxsNJ/q4DKzxBxUjLtT6EtbaP9iYTmiJcuP+yULmClV5It+0LOKN/Xca4uAfUAoDY920TN/aUYqkdv8w43tGxQF1ghxVmCxbtcOU8utZqfmXKl6+3pgNSdm9eMtOBARIYRFEAw9i51EkHBealunvcPKthvyK2HiE6legJkwVMB2BEbtP0AFVtJZ8q0ClW+UntFGaQ2RaH9EgrVGoaA3mEOqLmeX4DpICk5VCWEQDI0DIfrSPuY8qBafWcjrlj5AX6aKo2+WCenokT+uqlwbrbPdPs2XQKaQQV5cdvrQ75NYdgrbmTlZw5R53OdgJE+uHLC+p6yTGWr X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jun 2026 11:46:01.1564 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 83c396f5-7a05-4886-8d00-08dec22ed9e9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A0.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY3PR12MB9702 Content-Type: text/plain; charset="utf-8" From: Shay Drory Some devcom events are not expected to fail. Rather than attempting a rollback that may not be meaningful, allow callers to pass DEVCOM_CANT_FAIL as the rollback_event to indicate that the event handler should not fail. If it does, emit a warning and stop propagating to further peers, but skip the rollback path. Signed-off-by: Shay Drory Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.c | 7 ++++++- drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.h | 2 ++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.c b/drivers= /net/ethernet/mellanox/mlx5/core/lib/devcom.c index 96b4f06d6184..64f92427602d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.c @@ -306,8 +306,13 @@ int mlx5_devcom_locked_send_event(struct mlx5_devcom_c= omp_dev *devcom, =20 if (pos !=3D devcom && data) { err =3D comp->handler(event, data, event_data); - if (err) + if (err && rollback_event !=3D DEVCOM_CANT_FAIL) { goto rollback; + } else if (err && rollback_event =3D=3D DEVCOM_CANT_FAIL) { + WARN_ONCE(1, "devcom component %d event %d failed: %d\n", + comp->id, event, err); + return err; + } } } =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.h b/drivers= /net/ethernet/mellanox/mlx5/core/lib/devcom.h index d5c60c03e55c..7a704fafdbd3 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.h @@ -46,6 +46,8 @@ mlx5_devcom_register_component(struct mlx5_devcom_dev *de= vc, void *data); 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , Shay Drory , Or Har-Toov , Edward Srouji , Simon Horman , Maher Sanalla , Parav Pandit , Kees Cook , Moshe Shemesh , Patrisious Haddad , , , , Gal Pressman Subject: [PATCH net-next 04/15] net/mlx5: SD, make primary/secondary role determination more robust Date: Thu, 4 Jun 2026 14:44:44 +0300 Message-ID: <20260604114455.434711-5-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260604114455.434711-1-tariqt@nvidia.com> References: <20260604114455.434711-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A2:EE_|MW4PR12MB6998:EE_ X-MS-Office365-Filtering-Correlation-Id: a6b3e7fe-c907-486f-2cf4-08dec22edc22 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|7416014|376014|1800799024|36860700016|18002099003|22082099003|56012099006|5023799004|11063799006; X-Microsoft-Antispam-Message-Info: VuekgTifV38ze24U1wcKUsX2mYYOgpxzJaYMUdwsCAHvqFNrEbuWxFvnZLn/eq4QZg80wXzKMiRq2O6V+a2Gh84OVC3vgKIKh6pljvUxl3cX5Zlf4DQxRW/IeSEbEqPNOQdDLEdYJ/oogQEkqNhMeUU/lmHpA3Nrmx7pcq72lbMHWsH5xKwIz2uohX849akRrcsDyZ/CwrgPXixw9o1ZoZubzaQ3IHC37IXydWSew4g7qTPrQUHPJy32OA+owFAePeN7oMD8CNfWkID4fE4gen+aHkWgSmxYPExt1ULaghN4vgcSu/S2Oty5NR4pNuqFDB5b/Lz8uPcMOp8MAn3rHogacqfq94YSbJJqwbUjSpAA17cetiUIimBiSGHse6E/Zi4atJTFqiOQlmzWmuTSO54tePZ4aRmVhfricrVR5u8ipHAVFzx1AmP0Y65nGAEJkH+vTBRCOSXaB/y9rUeMHBamyNpXktaNGG9F094/EeIDbNYSHdfFN3TvwJS/bedrP+NECvMOL3IYXBwCdOt/pBriqxKXml5OK+th+0b8z1Z/6TMCqokQNHfP7ahvP4cmCKtT2r0LPOWRy2ebOGpUjF8LK87P14g5Imd6P6jpOY/yozuTUuRJryVNsRHY2VPeZVSZBcqVDH5pv3UPkjec3UNcMZ7jPqnVFaDrMHWaHgiOBvlkTkw8IEmdOcWXeKpud9oRc30mnyPLIxxYaEYct0/F5rJfx483Z/tnn9rcYcw= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(7416014)(376014)(1800799024)(36860700016)(18002099003)(22082099003)(56012099006)(5023799004)(11063799006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ubMy+NQYOW3sXNC5g144K6IkGn0O/+Jsi/ekD0J+PJIfE/6j4s0CeqmJyn3BYjkcCONlawWEshlgjM6c9yw0EvTUngAj7wqGVt26VHS5YQ4QEFMTS5gz0zojnpJSFtoE/Xd+3Psuy8IBn+YCUJeoSUU3dPBbNfqzk6sYvS1gSGeMK7VlIiqTcxofXOtdfgzw4uPps+bHmkPrVRXKsSSis4k10PmIevlzmkuYq14dagVS/scgh5a8h3Poi5d4BqK5b1TqBQp0yRxBDZ7wiPSdunhV67HemA60ZptVhnkoa2CvcnI3PRETulBS7J8ViWt6w0jQrqdT0SgcxBCs9jtr+MwzTgpopyWBMYeEiBUyGgV9q4+glLwPALMQaxOc1f2MzVUYFu6XHcPm+HMBQLquE4nbLsF7lKrXYkMxenFNuhmlSX7FWcbernPBVYdgETu5 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jun 2026 11:46:04.8811 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a6b3e7fe-c907-486f-2cf4-08dec22edc22 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A2.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6998 Content-Type: text/plain; charset="utf-8" From: Shay Drory Refactor SD group registration to use devcom event-driven role determination to ensure SD is marked as ready only after roles are fully assigned and the group state is consistent, making outside accessors, which will be added in downstream patches, safe to use without races. The devcom events: - SD_PRIMARY_SET event: each device compares bus numbers with peers to determine which should be primary - SD_SECONDARIES_SET event: secondaries register themselves with the elected primary device Signed-off-by: Shay Drory Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/lib/sd.c | 137 +++++++++++++----- 1 file changed, 102 insertions(+), 35 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c b/drivers/net= /ethernet/mellanox/mlx5/core/lib/sd.c index 25286ecd724e..41979bf6a615 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c @@ -26,6 +26,8 @@ struct mlx5_sd { struct { /* primary */ struct mlx5_core_dev *secondaries[MLX5_SD_MAX_GROUP_SZ - 1]; struct mlx5_flow_table *tx_ft; + /* Next index for secondary registration */ + u8 next_secondary_idx; }; struct { /* secondary */ struct mlx5_core_dev *primary_dev; @@ -374,62 +376,125 @@ static void sd_lag_cleanup(struct mlx5_core_dev *dev) mutex_unlock(&ldev->lock); } =20 +enum { + SD_PRIMARY_SET, + SD_SECONDARIES_SET, +}; + +static void sd_handle_primary_set(struct mlx5_core_dev *dev, + struct mlx5_core_dev *peer) +{ + struct mlx5_sd *peer_sd =3D mlx5_get_sd(peer); + struct mlx5_sd *sd =3D mlx5_get_sd(dev); + struct mlx5_core_dev *candidate; + struct mlx5_sd *candidate_sd; + + /* Peer is the device that being sent to all the other devices in the + * group. Hence, use peer to get the candidate device. + */ + candidate =3D peer_sd->primary ? peer : peer_sd->primary_dev; + + if (dev->pdev->bus->number >=3D candidate->pdev->bus->number) + return; + + candidate_sd =3D mlx5_get_sd(candidate); + + sd->primary =3D true; + candidate_sd->primary =3D false; + candidate_sd->primary_dev =3D dev; + peer_sd->primary =3D false; + peer_sd->primary_dev =3D dev; +} + +static void sd_handle_secondaries_set(struct mlx5_core_dev *dev, + struct mlx5_core_dev *peer) +{ + struct mlx5_sd *peer_sd =3D mlx5_get_sd(peer); + struct mlx5_sd *sd =3D mlx5_get_sd(dev); + u8 idx; + + /* Primary has nothing to register with itself. */ + if (sd->primary) + return; + + /* dev is a secondary device, peer is the primary device. + * Secondary registers itself with the primary. + */ + idx =3D peer_sd->next_secondary_idx++; + peer_sd->secondaries[idx] =3D dev; + sd->primary_dev =3D peer; +} + +static int mlx5_sd_devcom_event(int event, void *my_data, void *event_data) +{ + struct mlx5_core_dev *peer =3D event_data; + struct mlx5_core_dev *dev =3D my_data; + + switch (event) { + case SD_PRIMARY_SET: + sd_handle_primary_set(dev, peer); + break; + case SD_SECONDARIES_SET: + sd_handle_secondaries_set(dev, peer); + break; + } + + return 0; +} + static int sd_register(struct mlx5_core_dev *dev) { - struct mlx5_devcom_comp_dev *devcom, *pos; struct mlx5_devcom_match_attr attr =3D {}; - struct mlx5_core_dev *peer, *primary; - struct mlx5_sd *sd, *primary_sd; - int err, i; + struct mlx5_devcom_comp_dev *devcom; + struct mlx5_core_dev *primary; + struct mlx5_sd *sd; + int err; =20 sd =3D mlx5_get_sd(dev); attr.key.val =3D sd->group_id; attr.flags =3D MLX5_DEVCOM_MATCH_FLAGS_NS; attr.net =3D mlx5_core_net(dev); - devcom =3D mlx5_devcom_register_component(dev->priv.devc, MLX5_DEVCOM_SD_= GROUP, - &attr, NULL, dev); + devcom =3D mlx5_devcom_register_component(dev->priv.devc, + MLX5_DEVCOM_SD_GROUP, + &attr, mlx5_sd_devcom_event, + dev); if (!devcom) return -EINVAL; =20 sd->devcom =3D devcom; =20 - if (mlx5_devcom_comp_get_size(devcom) !=3D sd->host_buses) - return 0; - mlx5_devcom_comp_lock(devcom); - mlx5_devcom_comp_set_ready(devcom, true); - mlx5_devcom_comp_unlock(devcom); + if (mlx5_devcom_comp_get_size(devcom) !=3D sd->host_buses || + mlx5_devcom_comp_is_ready(devcom)) + goto out; =20 - if (!mlx5_devcom_for_each_peer_begin(devcom)) { - err =3D -ENODEV; + /* Send SD_PRIMARY_SET event with this device. + * All peers will receive this event and compare to this device. + * The one with lowest bus number will be marked as primary. + */ + sd->primary =3D true; + err =3D mlx5_devcom_locked_send_event(devcom, SD_PRIMARY_SET, + SD_PRIMARY_SET, dev); + if (err) goto err_devcom_unreg; - } - - primary =3D dev; - mlx5_devcom_for_each_peer_entry(devcom, peer, pos) - if (peer->pdev->bus->number < primary->pdev->bus->number) - primary =3D peer; =20 - primary_sd =3D mlx5_get_sd(primary); - primary_sd->primary =3D true; - i =3D 0; - /* loop the secondaries */ - mlx5_devcom_for_each_peer_entry(primary_sd->devcom, peer, pos) { - struct mlx5_sd *peer_sd =3D mlx5_get_sd(peer); - - primary_sd->secondaries[i++] =3D peer; - peer_sd->primary =3D false; - peer_sd->primary_dev =3D primary; - } + /* Broadcast SD_SECONDARIES_SET. Each non-sender peer's handler runs; + * the primary's handler returns early so only secondaries register. + */ + primary =3D sd->primary ? dev : sd->primary_dev; + if (!sd->primary) + sd_handle_secondaries_set(dev, primary); + mlx5_devcom_locked_send_event(devcom, SD_SECONDARIES_SET, + DEVCOM_CANT_FAIL, primary); =20 - mlx5_devcom_for_each_peer_end(devcom); + mlx5_devcom_comp_set_ready(devcom, true); +out: + mlx5_devcom_comp_unlock(devcom); return 0; =20 err_devcom_unreg: - mlx5_devcom_comp_lock(sd->devcom); - mlx5_devcom_comp_set_ready(sd->devcom, false); - mlx5_devcom_comp_unlock(sd->devcom); - mlx5_devcom_unregister_component(sd->devcom); + mlx5_devcom_comp_unlock(devcom); + mlx5_devcom_unregister_component(devcom); return err; } =20 @@ -672,6 +737,7 @@ int mlx5_sd_init(struct mlx5_core_dev *dev) peer_sd->primary_dev =3D NULL; } primary_sd->primary =3D false; + primary_sd->next_secondary_idx =3D 0; mlx5_devcom_comp_set_ready(sd->devcom, false); mlx5_devcom_comp_unlock(sd->devcom); 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , Shay Drory , Or Har-Toov , Edward Srouji , Simon Horman , Maher Sanalla , Parav Pandit , Kees Cook , Moshe Shemesh , Patrisious Haddad , , , , Gal Pressman Subject: [PATCH net-next 05/15] net/mlx5: SD, add L2 table silent mode query support Date: Thu, 4 Jun 2026 14:44:45 +0300 Message-ID: <20260604114455.434711-6-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260604114455.434711-1-tariqt@nvidia.com> References: <20260604114455.434711-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF0000449E:EE_|IA0PR12MB8424:EE_ X-MS-Office365-Filtering-Correlation-Id: 759b11f2-8d7a-4919-c5a9-08dec22edf4c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|7416014|376014|82310400026|1800799024|18002099003|22082099003|6133799003|11063799006|56012099006; X-Microsoft-Antispam-Message-Info: ZlmwNUzisUyq50mAM0Y2q7Q5v5SCFWnrGMq0qiYrVfIH562fc3Rz3qigHSDZu4vxC76sJni5ReO1dsjzRgcgjtuOPHMmnE8SFOg9hBoRU1hoMI1ppxZZYY0B+rvN9EXs32bVHKb5wc/0KOHCvM8zwwAco8wYlnF/5NRjyEKF6kFJvGYlijXN2ryfQs9OEvpb8fWo7haG2ERrhs1D7YlrhmITtgR+rWmPh8E285S8NvlOwSM3JnBlwG40+m6iCQoo3ejLjeErY8GCpa+ig5excvGf0hrfjZtr7LnNHL/6TEHT2Xjz2ODAvxRKgxObKIaTWm8DxMx+oXIzTRUEtvh8NzL6J6qjSBnEcCCoSDLIUc0HROKrlXYAwK+r/7fglPg2un8WjsuqLAOKkcS4WX0nBgvOxd09YlzRAp1haIar/WZmxPmE29WIR/DQirn6e1JO66TSaFhZiFHJ7TmunpPIxVsWQ34eMwVPTgFvE4gRwFCLTbcEA9htsUgU17YlAfkC0/bOVyZQkpUrRDDCwFp0OrfUI5qz2SRcweBIzcTBM+eDo8xOROzkw18zR2QNX6kepDblPjkDiM+SUnKXRvf1NWD4rSam5qhwVK9dmGc2lKXeX5gxsGdCVW96Fq3m6NKQngphfbOMH10AJPFpWUuAyUVXkuG7rFwOYC+L4vJXu33h5ExJ7C8Yv+EjFa/YQuz4ryRVX3ZpIWdocjUIcdZQ/lhMcGsF8wbuB39z3l6s6vw= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(7416014)(376014)(82310400026)(1800799024)(18002099003)(22082099003)(6133799003)(11063799006)(56012099006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: V0AneuDRo/Krdsr40aACGtGC7kaMLKl0rdztzDeALvmvrJWJOCgbXksjWFV5I2q6wp6Jf/Pcph6UhY32iQ8HqKK/KiDgTgVJFlvnD5LwQ2hh9+r+NAE4hcdp4Yse/Wgp81XZZ0UDqmRDnY78WuF18xTKEghESGM/xYD5fobbFOb0Ip1XQc1w0eJowUeZXdHa1FXa6YMeJji4wkvCZDWZUyrX3Y6nMMrAuOBXKcCX4Qsc3PfNDyvCwLNQiEexa7FuOJ+7cnAAvm3Wa2ZYjagDaxgLF9067OaRt/HsaAvnya4pRZxLSbpaExEeDd03+dPjXKDe4h0L6xtSj8w1jQ52nGl91FPssnjyqXL7sWQ+eSvLHmkDSVBlg8D7OwXGRtswN0UD47IoriM2DyytbCWKV+88unjqnvABkOwiR1DWvvJWs1OPKH3X01fDyEUewm5a X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jun 2026 11:46:10.1867 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 759b11f2-8d7a-4919-c5a9-08dec22edf4c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF0000449E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8424 Content-Type: text/plain; charset="utf-8" From: Shay Drory Add mlx5_fs_cmd_query_l2table_silent() to query the current silent mode state from firmware. This allows detecting if firmware has already put secondary devices into silent mode. During SD group registration, query the silent mode of each device. If a device is already in silent mode (set by firmware), record this in the fw_silents_secondaries flag and use it to help determine the primary/secondary roles. When fw_silents_secondaries is set, skip the driver-initiated silent mode set/unset operations since firmware manages this state. This handles configurations where firmware persistently silences secondary devices. Signed-off-by: Shay Drory Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/fs_cmd.c | 21 ++++ .../net/ethernet/mellanox/mlx5/core/fs_cmd.h | 2 + .../net/ethernet/mellanox/mlx5/core/lib/sd.c | 105 +++++++++++++++--- 3 files changed, 114 insertions(+), 14 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c b/drivers/net= /ethernet/mellanox/mlx5/core/fs_cmd.c index 1cd4cd898ec2..8af73393770c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c @@ -1217,3 +1217,24 @@ int mlx5_fs_cmd_set_tx_flow_table_root(struct mlx5_c= ore_dev *dev, u32 ft_id, boo =20 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); } + +int mlx5_fs_cmd_query_l2table_silent(struct mlx5_core_dev *dev, u8 *silent= _mode) +{ + u32 out[MLX5_ST_SZ_DW(query_l2_table_entry_out)] =3D {}; + u32 in[MLX5_ST_SZ_DW(query_l2_table_entry_in)] =3D {}; + int err; + + if (!MLX5_CAP_GEN(dev, silent_mode_query)) + return -EOPNOTSUPP; + + MLX5_SET(query_l2_table_entry_in, in, opcode, + MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY); + MLX5_SET(query_l2_table_entry_in, in, silent_mode_query, 1); + + err =3D mlx5_cmd_exec_inout(dev, query_l2_table_entry, in, out); + if (err) + return err; + + *silent_mode =3D MLX5_GET(query_l2_table_entry_out, out, silent_mode); + return 0; +} diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.h b/drivers/net= /ethernet/mellanox/mlx5/core/fs_cmd.h index 7eb7b3ffe3d8..60280ff7da50 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.h @@ -124,6 +124,8 @@ const struct mlx5_flow_cmds *mlx5_fs_cmd_get_fw_cmds(vo= id); =20 int mlx5_fs_cmd_set_l2table_entry_silent(struct mlx5_core_dev *dev, u8 sil= ent_mode); int mlx5_fs_cmd_set_tx_flow_table_root(struct mlx5_core_dev *dev, u32 ft_i= d, bool disconnect); +int mlx5_fs_cmd_query_l2table_silent(struct mlx5_core_dev *dev, + u8 *silent_mode); =20 static inline bool mlx5_fs_cmd_is_fw_term_table(struct mlx5_flow_table *ft) { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c b/drivers/net= /ethernet/mellanox/mlx5/core/lib/sd.c index 41979bf6a615..afad05a1e3fe 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c @@ -22,6 +22,7 @@ struct mlx5_sd { struct dentry *dfs; u8 state; bool primary; + bool fw_silents_secondaries; union { struct { /* primary */ struct mlx5_core_dev *secondaries[MLX5_SD_MAX_GROUP_SZ - 1]; @@ -167,7 +168,8 @@ static bool mlx5_sd_caps_supported(struct mlx5_core_dev= *dev, u8 host_buses) /* Disconnect secondaries from the network */ if (!MLX5_CAP_GEN(dev, eswitch_manager)) return false; - if (!MLX5_CAP_GEN(dev, silent_mode_set)) + if (!MLX5_CAP_GEN(dev, silent_mode_set) && + !MLX5_CAP_GEN(dev, silent_mode_query)) return false; =20 /* RX steering from primary to secondaries */ @@ -379,23 +381,77 @@ static void sd_lag_cleanup(struct mlx5_core_dev *dev) enum { SD_PRIMARY_SET, SD_SECONDARIES_SET, + SD_FW_SILENT_CHECK, }; =20 -static void sd_handle_primary_set(struct mlx5_core_dev *dev, - struct mlx5_core_dev *peer) +static int sd_handle_fw_silent_check(struct mlx5_core_dev *dev, + struct mlx5_core_dev *peer) +{ + struct mlx5_sd *peer_sd =3D mlx5_get_sd(peer); + struct mlx5_sd *sd =3D mlx5_get_sd(dev); + u8 dev_silent =3D 0, peer_silent =3D 0; + int err; + + if (peer_sd->fw_silents_secondaries) { + sd->fw_silents_secondaries =3D true; + return 0; + } + + err =3D mlx5_fs_cmd_query_l2table_silent(dev, &dev_silent); + if (err) { + sd_warn(dev, "Failed to query silent mode for dev: %d\n", err); + return err; + } + + err =3D mlx5_fs_cmd_query_l2table_silent(peer, &peer_silent); + if (err) { + sd_warn(dev, "Failed to query silent mode for peer: %d\n", err); + return err; + } + + if (dev_silent || peer_silent) { + sd->fw_silents_secondaries =3D true; + peer_sd->fw_silents_secondaries =3D true; + sd_info(dev, "FW indicates at least one device is silent\n"); + } + return 0; +} + +static int sd_handle_primary_set(struct mlx5_core_dev *dev, + struct mlx5_core_dev *peer) { struct mlx5_sd *peer_sd =3D mlx5_get_sd(peer); struct mlx5_sd *sd =3D mlx5_get_sd(dev); struct mlx5_core_dev *candidate; struct mlx5_sd *candidate_sd; + bool dev_should_be_primary; =20 /* Peer is the device that being sent to all the other devices in the * group. Hence, use peer to get the candidate device. */ candidate =3D peer_sd->primary ? peer : peer_sd->primary_dev; =20 - if (dev->pdev->bus->number >=3D candidate->pdev->bus->number) - return; + if (sd->fw_silents_secondaries) { + u8 candidate_silent =3D 0; + int err; + + err =3D mlx5_fs_cmd_query_l2table_silent(candidate, + &candidate_silent); + if (err) { + sd_warn(candidate, "Failed to query silent mode for dev: %d\n", + err); + return err; + } + /* Candidate is silent, dev should be primary */ + dev_should_be_primary =3D candidate_silent; + } else { + /* No FW silent mode, use bus number */ + dev_should_be_primary =3D + dev->pdev->bus->number < candidate->pdev->bus->number; + } + + if (!dev_should_be_primary) + return 0; =20 candidate_sd =3D mlx5_get_sd(candidate); =20 @@ -404,6 +460,7 @@ static void sd_handle_primary_set(struct mlx5_core_dev = *dev, candidate_sd->primary_dev =3D dev; peer_sd->primary =3D false; peer_sd->primary_dev =3D dev; + return 0; } =20 static void sd_handle_secondaries_set(struct mlx5_core_dev *dev, @@ -431,12 +488,13 @@ static int mlx5_sd_devcom_event(int event, void *my_d= ata, void *event_data) struct mlx5_core_dev *dev =3D my_data; =20 switch (event) { + case SD_FW_SILENT_CHECK: + return sd_handle_fw_silent_check(dev, peer); case SD_PRIMARY_SET: - sd_handle_primary_set(dev, peer); - break; + return sd_handle_primary_set(dev, peer); case SD_SECONDARIES_SET: sd_handle_secondaries_set(dev, peer); - break; + return 0; } =20 return 0; @@ -468,9 +526,21 @@ static int sd_register(struct mlx5_core_dev *dev) mlx5_devcom_comp_is_ready(devcom)) goto out; =20 + /* If silent mode query is supported, ask each device whether it is + * silent and propagate the result to the whole group. In each group + * only one device is not silent + */ + if (MLX5_CAP_GEN(dev, silent_mode_query)) { + err =3D mlx5_devcom_locked_send_event(devcom, SD_FW_SILENT_CHECK, + SD_FW_SILENT_CHECK, dev); + if (err) + goto err_devcom_unreg; + } + /* Send SD_PRIMARY_SET event with this device. * All peers will receive this event and compare to this device. - * The one with lowest bus number will be marked as primary. + * If fw_silents_secondaries is set, choose non-silent device. + * Otherwise use bus number. */ sd->primary =3D true; err =3D mlx5_devcom_locked_send_event(devcom, SD_PRIMARY_SET, @@ -586,9 +656,11 @@ static int sd_cmd_set_secondary(struct mlx5_core_dev *= secondary, struct mlx5_sd *sd =3D mlx5_get_sd(secondary); int err; =20 - err =3D mlx5_fs_cmd_set_l2table_entry_silent(secondary, 1); - if (err) - return err; + if (!primary_sd->fw_silents_secondaries) { + err =3D mlx5_fs_cmd_set_l2table_entry_silent(secondary, 1); + if (err) + return err; + } =20 err =3D sd_secondary_create_alias_ft(secondary, primary, primary_sd->tx_f= t, &sd->alias_obj_id, alias_key); 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , Shay Drory , Or Har-Toov , Edward Srouji , Simon Horman , Maher Sanalla , Parav Pandit , Kees Cook , Moshe Shemesh , Patrisious Haddad , , , , Gal Pressman Subject: [PATCH net-next 06/15] net/mlx5: SD, expend vport metadata for SD secondary devices Date: Thu, 4 Jun 2026 14:44:46 +0300 Message-ID: <20260604114455.434711-7-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260604114455.434711-1-tariqt@nvidia.com> References: <20260604114455.434711-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B1:EE_|CYXPR12MB9385:EE_ X-MS-Office365-Filtering-Correlation-Id: ea445f79-b522-4b51-8727-08dec22ee2f1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|7416014|376014|36860700016|18002099003|22082099003|11063799006|6133799003|56012099006; X-Microsoft-Antispam-Message-Info: mzqWgeNqoc/ktNQNT/RA1DIp6KLeQg5yhQfqMjQ4m1ZrLgMGVPQdK0zxEzfmOtpRwXHKoS/Mz5Q4IvNwwmWXvybrIpVkKTwhIqbvcx+lbqOif+cImya8LFR2QTh/YB5ma3QZtHHXSh1hNIQU6QRSWt4JF76KA2rJwNvrEmghVp6AyckA6oLkvEKGjPx9OCihLcYzQaYQG8X7ivbcK9X7s8GYwu1id0Zv1iuDnIb6opFkAEMkUVz6mQw/GYCCRzlrWvbGM79jzOkNsY/geb6ewG0OelLR42SH1/Y8VjF3CqS7nR+OU1sRT4EEYx4IppbFiVl1ioPMndsmp+LHg4K+ApThLbMpzkEkGwI3FImKJJea1qk8/MysomvU4O+p+rp9j0FioJ8Lu+4ZkNDPZZNqA0BUJ4USaS+6Bna+iZARReX8BtlE542NM7itpLoQIfP611w3yX0t3sXZgg+hBU9iPNxuc2u1SL8TLMZ/wRIAiPadFTm58lHPg+siuPH0NGEUzR1g0Jqa89k+FLyqFCxis+HThUCgUVUqMl5lSchKQmv1Lpjtl1hhZLRUPSnH6SirDl6jKlf8b4ejoXkSxdLuGd/yTKizR+fF11JacWCB8tRYnIUv4X0PIh955/D0ylWLToXfF82VVGYLQmERFSFMgBvp6jvosQrLKd9N2BsgFShegsP7xTJgsGN3LvgJ/dtmzyJYRW1J3pP6bQDJT3M3qQzHHnmNON/tzZgOvOt/6l0= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(7416014)(376014)(36860700016)(18002099003)(22082099003)(11063799006)(6133799003)(56012099006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: I+/4PB8zWY4FajWKyEzvDe6aF/4pVoGxzRQ2dc4G1NdsWMeMDeQ+MAUxi+f9gsvKYJ+KxXGp9ehIaUfZMuDW4IIiyIrKjyr2lmCkBQEZUHhr/fip+hLBIhHXEA61LUDKG/euqy87YDU9o3QrhYJVR4EDtlO2xVMRHvFhQMGKPnm65knJVoSGBaxNxr6cqcuuuEQ18O2ICWX+/PeBCsdwtJx0GF92BLLuQGIdzA0sfjhsmeEjGCdrZ1RJCUnt2C5dplX6NwaLKSVbnV1f9/zdA/nsKE59RU/cLLs6LxTZA61eEhicDH6ijYzUVbqR3SwduHEjPpH02EPZv+dbwKT4iRCGyekPdI01zmIjdkgPCwQLqMShhOl6yn39cz9AIV8vzJgJnw8Sx4m6wAhDOMZQhbqMJrzq2YI4m39aUFvlpzJ3BpRvP+Y331p1+uhAntNu X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jun 2026 11:46:16.3454 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ea445f79-b522-4b51-8727-08dec22ee2f1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYXPR12MB9385 Content-Type: text/plain; charset="utf-8" From: Shay Drory In Socket Direct configurations the primary and secondary PFs share the same native_port_num. The eswitch vport metadata encodes pf_num in its upper bits to distinguish vports across PFs. Without SD-awareness, both PFs generate identical metadata, causing FDB rules to steer traffic to the wrong representor. Add mlx5_sd_pf_num_get() which remaps the pf_num for SD devices. Use it so each PF in an SD group produces unique vport metadata. Signed-off-by: Shay Drory Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/eswitch_offloads.c | 6 +++--- .../net/ethernet/mellanox/mlx5/core/lib/sd.c | 21 +++++++++++++++++++ .../net/ethernet/mellanox/mlx5/core/lib/sd.h | 1 + 3 files changed, 25 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/d= rivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index 12805e80ce57..366531d8ef02 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -3472,12 +3472,12 @@ u32 mlx5_esw_match_metadata_alloc(struct mlx5_eswit= ch *esw) u32 vport_end_ida =3D (1 << ESW_VPORT_BITS) - 1; /* Reserve 0xf for internal port offload */ u32 max_pf_num =3D (1 << ESW_PFNUM_BITS) - 2; - u32 pf_num; + int pf_num; int id; =20 /* Only 4 bits of pf_num */ - pf_num =3D mlx5_get_dev_index(esw->dev); - if (pf_num > max_pf_num) + pf_num =3D mlx5_sd_pf_num_get(esw->dev); + if (pf_num < 0 || pf_num > max_pf_num) return 0; =20 /* Metadata is 4 bits of PFNUM and 12 bits of unique id */ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c b/drivers/net= /ethernet/mellanox/mlx5/core/lib/sd.c index afad05a1e3fe..8b1f3a25d80d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c @@ -85,6 +85,27 @@ bool mlx5_sd_is_primary(struct mlx5_core_dev *dev) return sd->primary; } =20 +int mlx5_sd_pf_num_get(struct mlx5_core_dev *dev) +{ + struct mlx5_sd *sd =3D mlx5_get_sd(dev); + int pf_num =3D mlx5_get_dev_index(dev); + struct mlx5_core_dev *pos; + int i; + + if (!sd) + return pf_num; + + mlx5_devcom_comp_assert_locked(sd->devcom); + if (!mlx5_devcom_comp_is_ready(sd->devcom)) + return -ENODEV; + + mlx5_sd_for_each_dev(i, mlx5_sd_get_primary(dev), pos) + if (pos =3D=3D dev) + break; + + return pf_num * sd->host_buses + i; +} + struct mlx5_core_dev * mlx5_sd_primary_get_peer(struct mlx5_core_dev *primary, int idx) { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.h b/drivers/net= /ethernet/mellanox/mlx5/core/lib/sd.h index 011702ff6f02..7a41adbcee71 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.h @@ -12,6 +12,7 @@ struct mlx5_sd; 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , Shay Drory , Or Har-Toov , Edward Srouji , Simon Horman , Maher Sanalla , Parav Pandit , Kees Cook , Moshe Shemesh , Patrisious Haddad , , , , Gal Pressman Subject: [PATCH net-next 07/15] net/mlx5: SD, support switchdev mode transition with shared FDB Date: Thu, 4 Jun 2026 14:44:47 +0300 Message-ID: <20260604114455.434711-8-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260604114455.434711-1-tariqt@nvidia.com> References: <20260604114455.434711-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF0000449E:EE_|MN0PR12MB5764:EE_ X-MS-Office365-Filtering-Correlation-Id: 52b74c99-196c-4560-8bac-08dec22ee4a0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|7416014|376014|82310400026|1800799024|22082099003|18002099003|56012099006|11063799006|6133799003; X-Microsoft-Antispam-Message-Info: fLHfvTKDDz1/bFv9hBf8gWZBkPkFD6qxEyBtomKGQ04YQx4/uvn7OQbcwm8BuQsds5955F/W0bbZPhIVohinrqkqoG8D0pRXx07lFNdimWe+FTzbge4x9hu1EvxiooO6zXkdkpOkFJt0VUUwSDOes2zn4oYr5OPrgugWtNC5xo6otQzeLH8e7bv0RFWO9BhyqZ8u3VIU+H6ZhpEEBW4to6+fKos1XrwTtMKvqntwMW5viWgCmdtS/ZbkLF33KfW1rx5ztYESX9BVxtRxAITwCxwYIochf8IYTiWHRfeMWRofF26KytQs2um4abqyR2hnitnIZuZT9Yo9Dz9u6uIgh72/JOHFo1XbJ+inQ8JZ5EpqKepmQgDuGoJJlUjdOf8yy9+L9kszCA2JuOYj/F9ddPl1QghfK1zQ18egP764EIAsyLULl905hDipTsX0GZVKFft0NTeiSP+xdpFwwmqS9KQzHG4bp3Fmnbh+Q/WO/tYOfL+IlJmdT7hIy3Xon3HnOGAqEqgJIO2v45wnOAToTo4IgOMeCEJOLMExar4qeIN8cqChgxkAVPCDuSxE+fRAg2uiI6M3UR44rBrFSx/ckXrJDdiph4WBbVfztNSAG3ezczjVtGhFqaTCglv5AXaV2rpta0nTxYjWGN+YIrrJ2auxzm8ZogNxNFspzrDQefC27/+9431iOojOBzgRMHSbO7DqLlnStYMWk6/7CppWsNyNFw5nesN/xi5U9jVxhMw= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(7416014)(376014)(82310400026)(1800799024)(22082099003)(18002099003)(56012099006)(11063799006)(6133799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: HEZ9j3Z4tE8LwG0Tp6tIR+XzkRFWmDPSaLbcA/dFtWMtZ3FvVBl4DDYovtQJQ3xWfQjjKTd9SgA4Rcrnzao5hHpTQmwUrr786wzhN5dA3FJbU6CZFASSW4HbfzQs9Gmtgm5iVq/LGqzh1NduwgAMz9e+RZvQUY9y+nAEY+uUfycKoSRcRFIzSpuT3XleV51efLNDCALaHX7YecvBKwxGEhqcuJypa7tAGR55ELvQUCASrFR/zG21Ads/29I/Wdke84emmZK17F55bXRtwTkFG0zyAPpj7+YWQ5j0BlTPaNwgme8c3LvTKbYIdY84v6e//UA2YoguSzuN+LkPrwjI529J2Qh0LV/zcsij5jMowHgR81pHCKHhdAbak460dxWMKNao9CT1YKpFDjxFsWLdSUmDtz08WSO8DX8SaysRCQbx2acG1V4aeO7A/ZF7z8ed X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jun 2026 11:46:19.1204 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 52b74c99-196c-4560-8bac-08dec22ee4a0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF0000449E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5764 Content-Type: text/plain; charset="utf-8" From: Shay Drory When the eswitch transitions, propagate the change to SD: secondaries get their TX flow table root reconfigured for the new mode, and when all group devices move to switchdev, the per-group shared FDB is activated. Shared FDB activation is best-effort - failure does not block the eswitch transition; the next transition retries. Note: the existing mlx5_get_sd() guard that blocks switchdev for SD devices is intentionally retained. It will be removed once all supporting patches are in place. Signed-off-by: Shay Drory Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/eswitch_offloads.c | 24 +++- .../net/ethernet/mellanox/mlx5/core/lib/sd.c | 133 +++++++++++++++++- .../net/ethernet/mellanox/mlx5/core/lib/sd.h | 7 + 3 files changed, 156 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/d= rivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index 366531d8ef02..1133267a53fb 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -46,6 +46,7 @@ #include "fs_core.h" #include "lib/mlx5.h" #include "lib/devcom.h" +#include "lib/sd.h" #include "lib/eq.h" #include "lib/fs_chains.h" #include "en_tc.h" @@ -3164,6 +3165,9 @@ static void esw_unset_master_egress_rule(struct mlx5_= core_dev *dev, vport =3D mlx5_eswitch_get_vport(dev->priv.eswitch, dev->priv.eswitch->manager_vport); =20 + if (!vport->egress.acl) + return; + esw_acl_egress_ofld_bounce_rule_destroy(vport, MLX5_CAP_GEN(slave_dev, vh= ca_id)); =20 if (xa_empty(&vport->egress.offloads.bounce_rules)) { @@ -3182,6 +3186,9 @@ int mlx5_eswitch_offloads_single_fdb_add_one(struct m= lx5_eswitch *master_esw, if (err) return err; =20 + if (!mlx5_sd_is_primary(slave_esw->dev)) + return 0; + err =3D esw_set_master_egress_rule(master_esw->dev, slave_esw->dev, max_slaves); if (err) @@ -3401,7 +3408,7 @@ void mlx5_esw_offloads_devcom_init(struct mlx5_eswitc= h *esw, return; =20 if ((MLX5_VPORT_MANAGER(esw->dev) || mlx5_core_is_ecpf_esw_manager(esw->d= ev)) && - !mlx5_lag_is_supported(esw->dev)) + (!mlx5_lag_is_supported(esw->dev) && !mlx5_get_sd(esw->dev))) return; =20 xa_init(&esw->paired); @@ -4219,11 +4226,6 @@ int mlx5_devlink_eswitch_mode_set(struct devlink *de= vlink, u16 mode, if (IS_ERR(esw)) return PTR_ERR(esw); =20 - if (mlx5_fw_reset_in_progress(esw->dev)) { - NL_SET_ERR_MSG_MOD(extack, "Can't change eswitch mode during firmware re= set"); - return -EBUSY; - } - if (esw_mode_from_devlink(mode, &mlx5_mode)) return -EINVAL; =20 @@ -4233,11 +4235,18 @@ int mlx5_devlink_eswitch_mode_set(struct devlink *d= evlink, u16 mode, return -EPERM; } =20 + if (mlx5_fw_reset_in_progress(esw->dev)) { + NL_SET_ERR_MSG_MOD(extack, + "Can't change eswitch mode during firmware reset"); + return -EBUSY; + } + /* Avoid try_lock, active/inactive mode change is not restricted */ if (mlx5_devlink_switchdev_active_mode_change(esw, mode)) return 0; =20 mlx5_lag_disable_change(esw->dev); + err =3D mlx5_esw_try_lock(esw); if (err < 0) { NL_SET_ERR_MSG_MOD(extack, "Can't change mode, E-Switch is busy"); @@ -4304,6 +4313,9 @@ int mlx5_devlink_eswitch_mode_set(struct devlink *dev= link, u16 mode, esw->eswitch_operation_in_progress =3D false; unlock: mlx5_esw_unlock(esw); + /* Shared FDB activation is creating LAG which is changing reps. */ + if (!err) + mlx5_sd_eswitch_mode_set(esw->dev, mlx5_mode); enable_lag: mlx5_lag_enable_change(esw->dev); return err; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c b/drivers/net= /ethernet/mellanox/mlx5/core/lib/sd.c index 8b1f3a25d80d..d2ed156ed1c6 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c @@ -5,6 +5,8 @@ #include "../lag/lag.h" #include "mlx5_core.h" #include "lib/mlx5.h" +#include "devlink.h" +#include "eswitch.h" #include "fs_cmd.h" #include #include @@ -33,6 +35,8 @@ struct mlx5_sd { struct { /* secondary */ struct mlx5_core_dev *primary_dev; u32 alias_obj_id; + /* TX flow table root in switchdev (silent) config */ + bool tx_root_silent; }; }; }; @@ -669,6 +673,29 @@ static void sd_secondary_destroy_alias_ft(struct mlx5_= core_dev *secondary) MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS); } =20 +static int mlx5_sd_secondary_conf_tx_root(struct mlx5_core_dev *secondary, + bool disconnect) +{ + struct mlx5_sd *sd =3D mlx5_get_sd(secondary); + int err; + + /* Idempotent: skip if TX root is already in the requested state. */ + if (sd->tx_root_silent =3D=3D disconnect) + return 0; + + if (disconnect) + err =3D mlx5_fs_cmd_set_tx_flow_table_root(secondary, 0, true); + else + err =3D mlx5_fs_cmd_set_tx_flow_table_root(secondary, + sd->alias_obj_id, + false); + if (err) + return err; + + sd->tx_root_silent =3D disconnect; + return 0; +} + static int sd_cmd_set_secondary(struct mlx5_core_dev *secondary, struct mlx5_core_dev *primary, u8 *alias_key) @@ -688,7 +715,8 @@ static int sd_cmd_set_secondary(struct mlx5_core_dev *s= econdary, if (err) goto err_unset_silent; =20 - err =3D mlx5_fs_cmd_set_tx_flow_table_root(secondary, sd->alias_obj_id, f= alse); + err =3D mlx5_fs_cmd_set_tx_flow_table_root(secondary, sd->alias_obj_id, + false); if (err) goto err_destroy_alias_ft; =20 @@ -707,7 +735,7 @@ static void sd_cmd_unset_secondary(struct mlx5_core_dev= *secondary) struct mlx5_sd *primary_sd; =20 primary_sd =3D mlx5_get_sd(mlx5_sd_get_primary(secondary)); - mlx5_fs_cmd_set_tx_flow_table_root(secondary, 0, true); + mlx5_sd_secondary_conf_tx_root(secondary, true); sd_secondary_destroy_alias_ft(secondary); if (!primary_sd->fw_silents_secondaries) mlx5_fs_cmd_set_l2table_entry_silent(secondary, 0); @@ -936,6 +964,107 @@ struct auxiliary_device *mlx5_sd_get_adev(struct mlx5= _core_dev *dev, return &primary_adev->adev; } =20 +#ifdef CONFIG_MLX5_ESWITCH +/* All SD members must have completed esw_offloads_enable (i.e., reached + * mlx5_esw_offloads_devcom_init) and become eswitch-peers of the primary. + * Until then, mlx5_eswitch_is_peer() returns false for the not-yet-paired + * member and shared_fdb_supported_filter would reject. When all PFs trans= ition + * in parallel, only the last one to finish satisfies this gate; the earli= er + * ones return 0 silently here. + */ +static bool mlx5_sd_all_paired(struct mlx5_core_dev *primary) +{ + struct mlx5_eswitch *primary_esw =3D primary->priv.eswitch; + struct mlx5_core_dev *pos; + int i; + + mlx5_sd_for_each_secondary(i, primary, pos) { + if (!mlx5_eswitch_is_peer(primary_esw, pos->priv.eswitch)) + return false; + } + return true; +} + +static void mlx5_sd_activate_shared_fdb(struct mlx5_core_dev *primary) +{ + struct mlx5_sd *sd =3D mlx5_get_sd(primary); + struct mlx5_lag *ldev; + struct lag_func *pf; + int err; + int i; + + if (!mlx5_sd_all_paired(primary)) + return; + + ldev =3D mlx5_lag_dev(primary); + if (!ldev) { + sd_warn(primary, "Shared FDB MUST have ldev\n"); + return; + } + + mutex_lock(&ldev->lock); + /* Check if SD FDB is already active for this group */ + mlx5_lag_for_each(i, 0, ldev, sd->group_id) { + pf =3D mlx5_lag_pf(ldev, i); + if (pf->sd_fdb_active) + goto unlock; + break; + } + + if (!mlx5_lag_shared_fdb_supported_filter(ldev, sd->group_id)) { + sd_warn(primary, "Shared FDB not supported\n"); + goto unlock; + } + + err =3D mlx5_lag_shared_fdb_create(ldev, NULL, 0, sd->group_id); + if (err) + sd_warn(primary, "Failed to create shared FDB: %d\n", err); + else + sd_info(primary, "Shared FDB created\n"); + +unlock: + mutex_unlock(&ldev->lock); +} + +void mlx5_sd_eswitch_mode_set(struct mlx5_core_dev *dev, u16 mlx5_mode) +{ + struct mlx5_core_dev *primary; + struct mlx5_sd *sd; + int err; + + sd =3D mlx5_get_sd(dev); + if (!sd || !mlx5_devcom_comp_is_ready(sd->devcom)) + return; + + mlx5_devcom_comp_lock(sd->devcom); + if (!mlx5_devcom_comp_is_ready(sd->devcom)) + goto unlock; + + primary =3D mlx5_sd_get_primary(dev); + + /* Secondary devices need TX root reconfiguration */ + if (dev !=3D primary) { + bool disconnect =3D (mlx5_mode =3D=3D MLX5_ESWITCH_OFFLOADS); + + err =3D mlx5_sd_secondary_conf_tx_root(dev, disconnect); + if (err) { + sd_warn(dev, "Failed to set TX root: %d\n", err); + goto unlock; + } + } + + /* Try to activate shared FDB when all devices are in switchdev. + * Shared FDB is optional - failure here doesn't fail the transition. + */ + if (mlx5_mode =3D=3D MLX5_ESWITCH_OFFLOADS) + mlx5_sd_activate_shared_fdb(primary); + +unlock: + mlx5_devcom_comp_unlock(sd->devcom); +} + +#endif /* CONFIG_MLX5_ESWITCH */ + void mlx5_sd_put_adev(struct auxiliary_device *actual_adev, struct auxiliary_device *adev) { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.h b/drivers/net= /ethernet/mellanox/mlx5/core/lib/sd.h index 7a41adbcee71..cb88bf34079a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.h @@ -45,6 +45,13 @@ mlx5_sd_get_devcom(struct mlx5_core_dev *dev) } #endif =20 +#ifdef CONFIG_MLX5_ESWITCH +void mlx5_sd_eswitch_mode_set(struct mlx5_core_dev *dev, u16 mlx5_mode); +#else +static inline void +mlx5_sd_eswitch_mode_set(struct mlx5_core_dev *dev, u16 mlx5_mode) { retur= n; } +#endif + #define mlx5_sd_for_each_dev_from_to(i, primary, ix_from, to, pos) \ for (i =3D ix_from; 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Thu, 4 Jun 2026 04:46:08 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , Shay Drory , Or Har-Toov , Edward Srouji , Simon Horman , Maher Sanalla , Parav Pandit , Kees Cook , Moshe Shemesh , Patrisious Haddad , , , , Gal Pressman Subject: [PATCH net-next 08/15] net/mlx5: E-Switch, notify SD on eswitch disable Date: Thu, 4 Jun 2026 14:44:48 +0300 Message-ID: <20260604114455.434711-9-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260604114455.434711-1-tariqt@nvidia.com> References: <20260604114455.434711-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A0:EE_|SA1PR12MB9246:EE_ X-MS-Office365-Filtering-Correlation-Id: 568a2f44-c46f-4c01-feb6-08dec22ee756 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|82310400026|36860700016|6133799003|22082099003|18002099003|56012099006|11063799006; X-Microsoft-Antispam-Message-Info: 9vwkTFvsK2UCfo4pAd7i54/8W7sSM5WNkN5lDx8lP57Hmh7xw/u9K0ZNiTf8GJr17RHfjIJqFM30q+Q3PP9Zto2hyX6D68JdxKkFg56JcmNkSTWDu4ILSYmW8jRZTapm3c57XoRkdRz/RXvXUR0tIrjCbyd0PDkEDjl4N+830GxsPr6SE3Rgtg8tLTp9CYJaeFzJi7Kg9HAaZGsvFMGU6WVIudGBq1TL5L8ywv/sLBT45si9WGHgTm3BNIeSWrYmHYrSBfsusZgdoK53rL8WrgYPY5d+VIff8mtkEavPjU7d0uIrb2pM+hz3Bb+H+zzYws6Q5ZqMLjKkp8F4H0o4uyY2P8e4aCaGm0p1tza7o1K/B2/gJ4YgmTeKBTHJ4YEFVqFmFwe7kPv5fLLhn6ozkZhA7jXNQlh0tHn0K3Q+sOxvtV55u7ec9uLkbF6inX7m7TxdwqfHzRQdlNBLFWYEFrfgVSX2y4utpUV0GVL2JGhg2/2WGojtrJH+J9ZRZCVXuWxPismr1/3xRvN0VpYDlZyNF799UcojOeUPuCHwnVUyP+5dypL8DB0jEx/XYUMBz1DIE8THd+E4SIahr1gEJ09pRNm/VkSjNJSDA/Yld3NOOX2vYkl6kslOBAgQUUb7GYlPnEnNwF2aYnS45RVzEyZkz70MfKvwrl9c3rlPI4OOcD84IYKk6BnzmPmPPgwNlbIwWfwYzJdmaF1ZUBAXLJODDzr30n6UfUlInCBQFrM= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(1800799024)(82310400026)(36860700016)(6133799003)(22082099003)(18002099003)(56012099006)(11063799006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: GyciSi0bsnbm+FHbTauTHeNafyssXmJxzWqfgXAL+L4yEzSynmoPa04SZ/R1PsQDKZxkS1C9YKH6eVDnxF6Bhf9A0/Z1yP5PG4M/dG2cTOtd4q8bcTzenq0ctpSCaeAl3g5qY1t6kh9dSlfW9caNWox4bmdQG6qF2DA0lG2NdmdRZq9HKmOcAFzSCPYP5m8gOpTmg7XHw0XM+qyICKJiF4xqQYn6o4g+aIGEG/huhXAlt19rRrdqwDeoN82/yzbydw2toZQH2GeZ6KXfoKOGlOSxC2A5Zw4irs5RdU4pt73azbSI4rYzGSJRZ4tyYSJl+QNeeWXWZ+tag/a2ZNuOl4TTD8N1jZTtz6OcyLFLtuWQ/1dBEl50Kdg9741mevgau4diXyWFBkVTTmgBnQ3v0MXv/7o1vlGpbCVTK2BgGW4TzaEchkghV65/vruXdBiA X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jun 2026 11:46:23.6836 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 568a2f44-c46f-4c01-feb6-08dec22ee756 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A0.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB9246 Content-Type: text/plain; charset="utf-8" From: Shay Drory When eswitch is disabled, notify the SD layer so it can clean up SD-specific resources such as the TX flow table root configuration on secondary devices. Signed-off-by: Shay Drory Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/eswitch.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.c index f8cfbf76dd6a..93d51f09b17f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c @@ -2072,6 +2072,7 @@ void mlx5_eswitch_disable(struct mlx5_eswitch *esw) mlx5_esw_reps_unblock(esw); =20 esw->mode =3D MLX5_ESWITCH_LEGACY; + mlx5_sd_eswitch_mode_set(esw->dev, MLX5_ESWITCH_LEGACY); mlx5_lag_enable_change(esw->dev); } =20 --=20 2.44.0 From nobody Mon Jun 8 09:48:39 2026 Received: from CH4PR04CU002.outbound.protection.outlook.com (mail-northcentralusazon11013045.outbound.protection.outlook.com [40.107.201.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A367C43CEE9; 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , Shay Drory , Or Har-Toov , Edward Srouji , Simon Horman , Maher Sanalla , Parav Pandit , Kees Cook , Moshe Shemesh , Patrisious Haddad , , , , Gal Pressman Subject: [PATCH net-next 09/15] net/mlx5: LAG, store demux resources per master lag_func Date: Thu, 4 Jun 2026 14:44:49 +0300 Message-ID: <20260604114455.434711-10-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260604114455.434711-1-tariqt@nvidia.com> References: <20260604114455.434711-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A0:EE_|LV8PR12MB9451:EE_ X-MS-Office365-Filtering-Correlation-Id: 9ee61e5a-0af2-4ce3-55d4-08dec22eea6e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|36860700016|1800799024|376014|82310400026|11063799006|3023799007|56012099006|6133799003|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: lg/OjLMkdoyv379ECc5EfeS2cEva/QiQqyshWjg5OkE48M6XzG7LddCs3N0Wnkkvs/Nn2VsF0oB8qwencrAi24ztwCxIrmfVztpUPTR7AuX7u6c5OoX8OIWC0SGmshf6Tjlva9TaDSlpyyatcyk9VERU4l2bx5hhwjaczl1VBZvuy3BdIth97FwOL3gN51roL8yr31gfy0NH4zFQddxMqqzvzBZMHOku8/DPehNZLz+c/f1Hol1YL7idBBUMm/8XhWThhIInw1RZA4+iQYeSOL3zXA/7rr4lDACp7JnD7I0AFpt8FOdJlnguQfmszVYi2av27+8OTw73E0IimBUqNBGhMYPcVxtwAZDR2Ll0kTp0fbKttpSErwlcoKqxipsE5uJ8pW4hAcs7gcCrl/rc3exMPS2Zu9nVHAW7+cSBGTp6QVQZTiNvOlaPi3iSkr1J+YPQiv5IxasV33dwdsaBkR4c690YLkcz3P30xTRI0NDVRNMvLYySatxgzbzwYjl2OTRa4GFEpuq0iPapTWR9IPm6xOKXzTbyEHV1blO1LQ1LZ1gucm5SjXYrFnwQD3YL/2irZt1lWCB7cnxzgMFo/Z8g6f9R96uaiWEGWTvKSrLPIa8w14nEO0xDt9KSzsCJBKfKsq25f6DfT7zoulcf22PWg/rnRBkwCUGDUS3ReMLY4CHkJ6Ub5jwO137VyWwO3U5zF3QQC9PSTg8FLh1k5g/jR9jp8/fPfUkdVWUp9M4= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(36860700016)(1800799024)(376014)(82310400026)(11063799006)(3023799007)(56012099006)(6133799003)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: hWGUjvY8wL6EHa2zHklZX1om79qVdiq9CwKw4GG8oODm+u+D1iXay6rUnXBQFQ39R+alY532u9qTXHzPl9IFCd9XMPXxgcEbXvRFftSP4teC+hNKNw4Nv9Yi51XT3RSssDkegrGNogAOTv6qd55x60hgR2DpIPbhNfewJA1ogFClvArvG2FDg/BNo4hGS26lcd71ltjmH+uqYODoKsLhhgxkaSJDtBi93bUMFuJwBhZh+G5MkLO/8s6vn/iVy213NKgJ86wxd1o6uw4AYEKUMTsVKImk7SLaRCyTz2vmClqjEwaZIgGOLs/HV3fGYydHSC6JVOjFl22kPe5FwoJgDL/YBo436wB2eS0yC3VVIa74N7H9wj3BbBeogYppEHPXLv35e/RSuIXxHZd/wsMWiCzWnb2KBj2c8FSZQL0nDfLBQEfozj/pbqmFNytSQtjf X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jun 2026 11:46:28.8667 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9ee61e5a-0af2-4ce3-55d4-08dec22eea6e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A0.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9451 Content-Type: text/plain; charset="utf-8" From: Shay Drory The lag demux resources (flow table, flow group, and rules xarray) are stored on the shared ldev. With Socket Direct, multiple SD groups each create their own demux FT/FG during their master's IB device initialization. Since they all write to the same ldev fields, the second group's init overwrites the first group's pointers, leaking the first group's FT/FG. During teardown, the cleanup uses the overwritten pointers, destroying the wrong group's resources and leaving leaked flow tables in the LAG namespace. These leaked tables can interfere with subsequently created demux tables. Move the demux resources from the shared ldev to per-master lag_func instances. Each master device now owns its own independent demux state. The rule_add and rule_del helpers look up the appropriate master's lag_func via the existing filter/group infrastructure. Signed-off-by: Shay Drory Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/lag/lag.c | 95 +++++++++++++------ .../net/ethernet/mellanox/mlx5/core/lag/lag.h | 7 +- 2 files changed, 68 insertions(+), 34 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/lag/lag.c index dd3f18f85466..e23c1e81b98f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c @@ -1590,7 +1590,7 @@ struct mlx5_devcom_comp_dev *mlx5_lag_get_devcom_comp= (struct mlx5_lag *ldev) =20 static int mlx5_lag_demux_ft_fg_init(struct mlx5_core_dev *dev, struct mlx5_flow_table_attr *ft_attr, - struct mlx5_lag *ldev) + struct lag_func *pf) { #ifdef CONFIG_MLX5_ESWITCH struct mlx5_flow_namespace *ns; @@ -1601,20 +1601,20 @@ static int mlx5_lag_demux_ft_fg_init(struct mlx5_co= re_dev *dev, if (!ns) return 0; =20 - ldev->lag_demux_ft =3D mlx5_create_flow_table(ns, ft_attr); - if (IS_ERR(ldev->lag_demux_ft)) - return PTR_ERR(ldev->lag_demux_ft); + pf->lag_demux_ft =3D mlx5_create_flow_table(ns, ft_attr); + if (IS_ERR(pf->lag_demux_ft)) + return PTR_ERR(pf->lag_demux_ft); =20 fg =3D mlx5_esw_lag_demux_fg_create(dev->priv.eswitch, - ldev->lag_demux_ft); + pf->lag_demux_ft); if (IS_ERR(fg)) { err =3D PTR_ERR(fg); - mlx5_destroy_flow_table(ldev->lag_demux_ft); - ldev->lag_demux_ft =3D NULL; + mlx5_destroy_flow_table(pf->lag_demux_ft); + pf->lag_demux_ft =3D NULL; return err; } =20 - ldev->lag_demux_fg =3D fg; + pf->lag_demux_fg =3D fg; return 0; #else return -EOPNOTSUPP; @@ -1623,7 +1623,7 @@ static int mlx5_lag_demux_ft_fg_init(struct mlx5_core= _dev *dev, =20 static int mlx5_lag_demux_fw_init(struct mlx5_core_dev *dev, struct mlx5_flow_table_attr *ft_attr, - struct mlx5_lag *ldev) + struct lag_func *pf) { struct mlx5_flow_namespace *ns; int err; @@ -1632,12 +1632,12 @@ static int mlx5_lag_demux_fw_init(struct mlx5_core_= dev *dev, if (!ns) return 0; =20 - ldev->lag_demux_fg =3D NULL; + pf->lag_demux_fg =3D NULL; ft_attr->max_fte =3D 1; - ldev->lag_demux_ft =3D mlx5_create_lag_demux_flow_table(ns, ft_attr); - if (IS_ERR(ldev->lag_demux_ft)) { - err =3D PTR_ERR(ldev->lag_demux_ft); - ldev->lag_demux_ft =3D NULL; + pf->lag_demux_ft =3D mlx5_create_lag_demux_flow_table(ns, ft_attr); + if (IS_ERR(pf->lag_demux_ft)) { + err =3D PTR_ERR(pf->lag_demux_ft); + pf->lag_demux_ft =3D NULL; return err; } =20 @@ -1648,6 +1648,7 @@ int mlx5_lag_demux_init(struct mlx5_core_dev *dev, struct mlx5_flow_table_attr *ft_attr) { struct mlx5_lag *ldev; + struct lag_func *pf; =20 if (!ft_attr) return -EINVAL; @@ -1656,12 +1657,16 @@ int mlx5_lag_demux_init(struct mlx5_core_dev *dev, if (!ldev) return -ENODEV; =20 - xa_init(&ldev->lag_demux_rules); + pf =3D mlx5_lag_pf_by_dev(ldev, dev); + if (!pf) + return -ENODEV; + + xa_init(&pf->lag_demux_rules); =20 if (mlx5_get_sd(dev)) - return mlx5_lag_demux_ft_fg_init(dev, ft_attr, ldev); + return mlx5_lag_demux_ft_fg_init(dev, ft_attr, pf); =20 - return mlx5_lag_demux_fw_init(dev, ft_attr, ldev); + return mlx5_lag_demux_fw_init(dev, ft_attr, pf); } EXPORT_SYMBOL(mlx5_lag_demux_init); =20 @@ -1670,40 +1675,63 @@ void mlx5_lag_demux_cleanup(struct mlx5_core_dev *d= ev) struct mlx5_flow_handle *rule; struct mlx5_lag *ldev; unsigned long vport_num; + struct lag_func *pf; =20 ldev =3D mlx5_lag_dev(dev); if (!ldev) return; =20 - xa_for_each(&ldev->lag_demux_rules, vport_num, rule) + pf =3D mlx5_lag_pf_by_dev(ldev, dev); + if (!pf) + return; + + xa_for_each(&pf->lag_demux_rules, vport_num, rule) mlx5_del_flow_rules(rule); - xa_destroy(&ldev->lag_demux_rules); + xa_destroy(&pf->lag_demux_rules); =20 - if (ldev->lag_demux_fg) - mlx5_destroy_flow_group(ldev->lag_demux_fg); - if (ldev->lag_demux_ft) - mlx5_destroy_flow_table(ldev->lag_demux_ft); - ldev->lag_demux_fg =3D NULL; - ldev->lag_demux_ft =3D NULL; + if (pf->lag_demux_fg) + mlx5_destroy_flow_group(pf->lag_demux_fg); + if (pf->lag_demux_ft) + mlx5_destroy_flow_table(pf->lag_demux_ft); + pf->lag_demux_fg =3D NULL; + pf->lag_demux_ft =3D NULL; } EXPORT_SYMBOL(mlx5_lag_demux_cleanup); =20 +static struct lag_func *mlx5_lag_dev_get_master_pf(struct mlx5_lag *ldev, + struct mlx5_core_dev *dev) +{ + u32 filter =3D mlx5_lag_get_filter(ldev, dev); + int idx; + + idx =3D mlx5_lag_get_dev_index_by_seq_filter(ldev, MLX5_LAG_P1, filter); + if (idx < 0) + return NULL; + + return mlx5_lag_pf(ldev, idx); +} + int mlx5_lag_demux_rule_add(struct mlx5_core_dev *vport_dev, u16 vport_num, int index) { struct mlx5_flow_handle *rule; + struct lag_func *master; struct mlx5_lag *ldev; int err; =20 ldev =3D mlx5_lag_dev(vport_dev); - if (!ldev || !ldev->lag_demux_fg) + if (!ldev) return 0; =20 - if (xa_load(&ldev->lag_demux_rules, index)) + master =3D mlx5_lag_dev_get_master_pf(ldev, vport_dev); + if (!master || !master->lag_demux_fg) + return 0; + + if (xa_load(&master->lag_demux_rules, index)) return 0; =20 rule =3D mlx5_esw_lag_demux_rule_create(vport_dev->priv.eswitch, - vport_num, ldev->lag_demux_ft); + vport_num, master->lag_demux_ft); if (IS_ERR(rule)) { err =3D PTR_ERR(rule); mlx5_core_warn(vport_dev, @@ -1712,7 +1740,7 @@ int mlx5_lag_demux_rule_add(struct mlx5_core_dev *vpo= rt_dev, u16 vport_num, return err; } =20 - err =3D xa_err(xa_store(&ldev->lag_demux_rules, index, rule, + err =3D xa_err(xa_store(&master->lag_demux_rules, index, rule, GFP_KERNEL)); if (err) { mlx5_del_flow_rules(rule); @@ -1728,13 +1756,18 @@ EXPORT_SYMBOL(mlx5_lag_demux_rule_add); void mlx5_lag_demux_rule_del(struct mlx5_core_dev *dev, int index) { struct mlx5_flow_handle *rule; + struct lag_func *master_pf; struct mlx5_lag *ldev; =20 ldev =3D mlx5_lag_dev(dev); - if (!ldev || !ldev->lag_demux_fg) + if (!ldev) + return; + + master_pf =3D mlx5_lag_dev_get_master_pf(ldev, dev); + if (!master_pf || !master_pf->lag_demux_fg) return; =20 - rule =3D xa_erase(&ldev->lag_demux_rules, index); + rule =3D xa_erase(&master_pf->lag_demux_rules, index); if (rule) mlx5_del_flow_rules(rule); } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/lag/lag.h index 0296f752bb4c..c689f1951cd8 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.h @@ -59,6 +59,10 @@ struct lag_func { struct mlx5_nb port_change_nb; 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , Shay Drory , Or Har-Toov , Edward Srouji , Simon Horman , Maher Sanalla , Parav Pandit , Kees Cook , Moshe Shemesh , Patrisious Haddad , , , , Gal Pressman Subject: [PATCH net-next 10/15] net/mlx5: LAG, disable both regular and SD LAG on lag_disable_change Date: Thu, 4 Jun 2026 14:44:50 +0300 Message-ID: <20260604114455.434711-11-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260604114455.434711-1-tariqt@nvidia.com> References: <20260604114455.434711-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A1:EE_|DS0PR12MB8564:EE_ X-MS-Office365-Filtering-Correlation-Id: f5f74df4-7c63-45e4-ed29-08dec22eedaf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|7416014|376014|82310400026|1800799024|22082099003|18002099003|56012099006|11063799006; X-Microsoft-Antispam-Message-Info: A8YdVkbkqFje9kgxFHJmdZ8fy/KLUejG9zUtsjmg51Idc0cDJ+0eGgT3wI6hRbQb4UE4jnMijncxl6U6n4kPT7lkCXjtKAqoPCk9z9JfggcrDgl008igQ+MVRp+eNAf/wFhGXW59HZu/rBchaXMhW4YD7VkVO8ZKkhhU77depG/DaspyEeYZzpiGbdnFExc0bcYc/vY55RpadsURuT9GgNLedrv8cxjvADurg4CMkjwt1MUAzRK6Xf5mhY0LmTszDpY2TrzZ7MuBGBIzmHPJk0T7pmoatwJadjBU7Lc52NAeRWhXql5YCQq3lZy9hPW3Ic+189nyNBvFd+pzJmaEktJnMn5ChofPOoBNkMrbvlNPLHtt0Mz22e39SuIcVdxkGChbcXxAmQy6lf5++wTjYCob8ESHxNV/zzpZomjt1NbgkSRX72FcMT4AesvN1OO+nNxStsEhXPrGmmpRZsXWVS86Rdrr9hPPmZjloTI1pmS7zhph0kxZf5fBFCYJpZsoEogyVYpmHE4PCyH9xJAYf9qXZ5DV2Ftahmt2sYLfYpmrZ1VGOFAPR/WeGqQk52QbdLIVLOr2BDv4Ayp+9P/RLHJrrHHC0MKg1BGKG6+zphvBmA0bXRylLt1V+02U9HV5JTz10njU9F9+NveNVkxh6QqEe+6Mf19w8n2aGABjQQS7AZhYSzxpQ7c5jE4/A6QA5nS2A9vjl3yzhWdIe/xnR5bFfQw/6ULiUn4AGhQjL60= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(7416014)(376014)(82310400026)(1800799024)(22082099003)(18002099003)(56012099006)(11063799006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: sKwMPvpRHXkPiSWoFZgfKXFDZEdXTxML0ZYlgQiQ9DBRL2ykRfZ5IReFbJEwiExyNjwA4B7LtOGWtvpwCF5aGG2hQbCqt2qDvK8jz4LWIw1G2GFNkMBfq/53svgFWW7o5C/lLF+K7nTZwzZKAcWl4N6l6IcYpsPz3vSzlpKp53WvIlNg8p/WxF3aY78rGSluhbc+AX17K9KRa2feYZz8gKqUcwtf97NkNsk/MgjQFgoI8xrFyXJX1D1ExhKVUjpermZpCeCgTzTrddz+dilUfVN+ekc6FRGZLk1YUNnrPC+npxgiqUltp4P3u8xMui5sRN4yrnGTmyMgFjxaTnXNPla/ZoRJrseI37IzfiV8vZmWgziEY+vGPGD2TVbYP16/XMRqf7qLbZPeI8pDDusscnfthL0tufp0fpMe/TvPVbjTAZc4Qmei3cu9KZ3KfObV X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jun 2026 11:46:34.3182 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f5f74df4-7c63-45e4-ed29-08dec22eedaf X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A1.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8564 Content-Type: text/plain; charset="utf-8" From: Shay Drory Extend mlx5_lag_disable_change() to properly disable both regular LAG and SD LAG when requested. Each LAG type uses its own devcom component for locking. Use mlx5_sd_get_devcom() helper to retrieve the SD devcom component, needed for proper locking when disabling SD LAG. Signed-off-by: Shay Drory Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/lag/lag.c | 25 +++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/lag/lag.c index e23c1e81b98f..b660253ffc6d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c @@ -2494,13 +2494,18 @@ EXPORT_SYMBOL(mlx5_lag_is_shared_fdb); =20 void mlx5_lag_disable_change(struct mlx5_core_dev *dev) { + struct mlx5_devcom_comp_dev *sd_devcom =3D mlx5_sd_get_devcom(dev); + struct mlx5_core_dev *primary; struct mlx5_lag *ldev; + struct lag_func *pf; + int i; =20 ldev =3D mlx5_lag_dev(dev); if (!ldev) return; =20 - mlx5_devcom_comp_lock(dev->priv.hca_devcom_comp); + primary =3D mlx5_sd_get_primary(dev) ?: dev; + mlx5_devcom_comp_lock(primary->priv.hca_devcom_comp); mutex_lock(&ldev->lock); =20 ldev->mode_changes_in_progress++; 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , Shay Drory , Or Har-Toov , Edward Srouji , Simon Horman , Maher Sanalla , Parav Pandit , Kees Cook , Moshe Shemesh , Patrisious Haddad , , , , Gal Pressman Subject: [PATCH net-next 11/15] net/mlx5: LAG, introduce software vport LAG implementation Date: Thu, 4 Jun 2026 14:44:51 +0300 Message-ID: <20260604114455.434711-12-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260604114455.434711-1-tariqt@nvidia.com> References: <20260604114455.434711-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A0:EE_|SN7PR12MB7132:EE_ X-MS-Office365-Filtering-Correlation-Id: 57b030a8-4319-43dd-39d1-08dec22ef153 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|1800799024|36860700016|22082099003|18002099003|56012099006|11063799006|3023799007; X-Microsoft-Antispam-Message-Info: fHkvam7239evYwkYImfo/5DTLvAL4yqq7L7k+COFhJ/VIfc5vp8O0kXx+Yd2UfsHYXzMHKKv1pkvbY9VktUMyJ2nw0frLU09IFVNedYfgcPdPgpG2vIfy+4Mio+COFGf0p7HhftbnUP85ZzYeZNYTltlBc6lbFZGHsyeUsdY0Bdfhx4KAKQPDlG4IUshEYQ+Dx7EJZMK5uHZAPjRDYBdWZrW/EEmERRkEokrOJDGhPhsOoMvMI35RlMGFQXVcpsalDrWica7wraEOE0z2jlc6Cul5gEQMnVo+blkvveBUCbZgdnf2RBwaEXTZwS0BSPOkryYxNQEozeOETQHsAZqyVhx7pofuy0QFCA9Z2WaOraFxjWl0nhee5Pe5JgCJq23CnJiM+KiPZSjOG/+uUJstJPZstE8rTW+zdUaqZG+3umGAYATmiZo+5k7idqUPfNohvceFEDodplBbaITsIAXiNHkddMFzWXsUyp9mlq/nM8LIv73qhLS5w+ROVVWJYbRhpls5F3M9187nLNFUQ10SJCTx0I7a2QC+6eJc65b4WEJ0xB0SN9etQPafE+07Y4W/d9BnlMutqrQFlvi9VytTnmNOKhBQ00P48fmtCF7cTLZiRNzXXR5heYQBOAfEz/KNsg8qlymIsD8BtY2VbnQDrw2y/NZBprfq2RX7pmE5Wew245rprXru6wn+FD+48vsn5qgRWr1EHOwIXyr6KCugFyuGyHrrRlL+aNb7Y0pV4U= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(82310400026)(1800799024)(36860700016)(22082099003)(18002099003)(56012099006)(11063799006)(3023799007);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 7nCLntQFWJPS01l4MpfUvtohs+1MbmzUAhTJ5vA/Q7AS5FmzIHhjR7YKpq2BzYkcNDOII8B5vTJdOXN6vQjpc9Pjt0wARgueeox3WNjrNqQWTSM7d6YnGL/uXg0YJwwJDEM8hyWQWPBJH61K+tTcrAvLnxYPuQ+kW1uhW1RlWG+xT4XOw/TDENWlXKKhJeixQn55TNS4P9unDIITJoTHLWEqJdeXiKFBiEbRJSZCk++ccyg4BU4OhF+SsK57UV68CpAdcfrOXmkvkfnsCVt2fk6X9ZTd2tlWF2yxfz0Q522eDQI9/Dg1KrkJ4tD0ZpEc9v6zF+y7NA//198oT7qtqgGg8p0qc0TqEBSJZsKkXUalqWHB2gkvDe9bUiU5lmZltDaFhHDsHZWXB9Cf9+DnWmOLSQVl7Ipt9nf9efpcpsk1esCR1FkNofpb08vYrkYl X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jun 2026 11:46:40.4376 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 57b030a8-4319-43dd-39d1-08dec22ef153 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A0.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7132 Content-Type: text/plain; charset="utf-8" From: Shay Drory SD LAG is a virtual LAG without hardware LAG support, so it cannot use the firmware vport LAG commands. Implement a software-based vport LAG using egress ACL bounce rules. Add esw_set_slave_egress_rule() to create an egress ACL rule on the slave's manager vport that bounces traffic to the master's manager vport. This achieves the same traffic steering as hardware vport LAG. Redirect mlx5_cmd_create_vport_lag() and mlx5_cmd_destroy_vport_lag() to the software implementation when operating in SD LAG mode. In addition, adjust lag_demux creation to check SD LAG mode as well. Signed-off-by: Shay Drory Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/eswitch.h | 4 + .../mellanox/mlx5/core/eswitch_offloads.c | 142 ++++++++++++++++++ .../net/ethernet/mellanox/mlx5/core/lag/lag.c | 49 +++++- .../net/ethernet/mellanox/mlx5/core/lag/lag.h | 14 ++ .../mellanox/mlx5/core/lag/shared_fdb.c | 74 ++++++++- 5 files changed, 280 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.h index 94a530d19828..a5f0774834fe 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h @@ -950,6 +950,10 @@ void esw_vport_change_handle_locked(struct mlx5_vport = *vport); =20 bool mlx5_esw_offloads_controller_valid(const struct mlx5_eswitch *esw, u3= 2 controller); =20 +int mlx5_eswitch_offloads_vport_lag_add_one(struct mlx5_eswitch *master_es= w, + struct mlx5_eswitch *slave_esw); +void mlx5_eswitch_offloads_vport_lag_del_one(struct mlx5_eswitch *master_e= sw, + struct mlx5_eswitch *slave_esw); int mlx5_eswitch_offloads_single_fdb_add_one(struct mlx5_eswitch *master_e= sw, struct mlx5_eswitch *slave_esw, int max_slaves); void mlx5_eswitch_offloads_single_fdb_del_one(struct mlx5_eswitch *master_= esw, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/d= rivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index 1133267a53fb..ad812fb1bb80 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -3041,6 +3041,136 @@ static int __esw_set_master_egress_rule(struct mlx5= _core_dev *master, return err; } =20 +static int esw_slave_egress_create_resources(struct mlx5_eswitch *esw, + struct mlx5_vport *vport) +{ + struct mlx5_flow_table_attr ft_attr =3D { + .max_fte =3D 1, .prio =3D 0, .level =3D 0, + }; + int inlen =3D MLX5_ST_SZ_BYTES(create_flow_group_in); + struct mlx5_flow_namespace *ns; + struct mlx5_flow_table *acl; + struct mlx5_flow_group *g; + u32 *flow_group_in; + int err =3D 0; + + if (vport->egress.acl) + return 0; + + xa_init_flags(&vport->egress.offloads.bounce_rules, XA_FLAGS_ALLOC); + ns =3D mlx5_get_flow_vport_namespace(esw->dev, + MLX5_FLOW_NAMESPACE_ESW_EGRESS, + vport->index); + if (!ns) + return -EINVAL; + + flow_group_in =3D kvzalloc(inlen, GFP_KERNEL); + if (!flow_group_in) + return -ENOMEM; + + if (vport->vport || mlx5_core_is_ecpf(esw->dev)) + ft_attr.flags =3D MLX5_FLOW_TABLE_OTHER_VPORT; + + acl =3D mlx5_create_vport_flow_table(ns, &ft_attr, vport->vport); + if (IS_ERR(acl)) { + err =3D PTR_ERR(acl); + goto out; + } + + g =3D mlx5_create_flow_group(acl, flow_group_in); + if (IS_ERR(g)) { + err =3D PTR_ERR(g); + goto err_table; + } + + vport->egress.acl =3D acl; + vport->egress.offloads.bounce_grp =3D g; + vport->egress.type =3D VPORT_EGRESS_ACL_TYPE_SHARED_FDB; + err =3D 0; + +err_table: + if (err && !IS_ERR_OR_NULL(acl)) { + mlx5_destroy_flow_table(acl); + vport->egress.acl =3D NULL; + } +out: + kvfree(flow_group_in); + return err; +} + +static void esw_slave_egress_destroy_resources(struct mlx5_vport *vport) +{ + if (!IS_ERR_OR_NULL(vport->egress.offloads.bounce_grp)) { + mlx5_destroy_flow_group(vport->egress.offloads.bounce_grp); + vport->egress.offloads.bounce_grp =3D NULL; + } + if (!IS_ERR_OR_NULL(vport->egress.acl)) { + esw_acl_egress_ofld_cleanup(vport); + xa_destroy(&vport->egress.offloads.bounce_rules); + } +} + +static int esw_set_slave_egress_rule(struct mlx5_core_dev *master, + struct mlx5_core_dev *slave) +{ + struct mlx5_eswitch *slave_esw =3D slave->priv.eswitch; + u16 master_vhca =3D MLX5_CAP_GEN(master, vhca_id); + struct mlx5_flow_destination dest =3D {}; + struct mlx5_flow_handle *bounce_rule; + struct mlx5_flow_act flow_act =3D {}; + struct mlx5_vport *slave_vport; + int err; + + slave_vport =3D mlx5_eswitch_get_vport(slave_esw, + slave_esw->manager_vport); + if (IS_ERR(slave_vport)) + return PTR_ERR(slave_vport); + + err =3D esw_slave_egress_create_resources(slave_esw, slave_vport); + if (err) + return err; + + flow_act.action =3D MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; + dest.type =3D MLX5_FLOW_DESTINATION_TYPE_VPORT; + dest.vport.num =3D master->priv.eswitch->manager_vport; + dest.vport.vhca_id =3D master_vhca; + dest.vport.flags =3D MLX5_FLOW_DEST_VPORT_VHCA_ID; + + bounce_rule =3D mlx5_add_flow_rules(slave_vport->egress.acl, NULL, + &flow_act, &dest, 1); + if (IS_ERR(bounce_rule)) { + err =3D PTR_ERR(bounce_rule); + goto err_rule; + } + err =3D xa_insert(&slave_vport->egress.offloads.bounce_rules, + master_vhca, bounce_rule, GFP_KERNEL); + if (err) + goto err_insert; + + return 0; +err_insert: + mlx5_del_flow_rules(bounce_rule); +err_rule: + esw_slave_egress_destroy_resources(slave_vport); + return err; +} + +static void esw_unset_slave_egress_rule(struct mlx5_core_dev *master, + struct mlx5_core_dev *slave) +{ + struct mlx5_eswitch *slave_esw =3D slave->priv.eswitch; + u16 master_vhca =3D MLX5_CAP_GEN(master, vhca_id); + struct mlx5_vport *slave_vport; + + slave_vport =3D mlx5_eswitch_get_vport(slave_esw, + slave_esw->manager_vport); + if (IS_ERR(slave_vport)) + return; + + esw_acl_egress_ofld_bounce_rule_destroy(slave_vport, master_vhca); + esw_slave_egress_destroy_resources(slave_vport); +} + static int esw_master_egress_create_resources(struct mlx5_eswitch *esw, struct mlx5_flow_namespace *egress_ns, struct mlx5_vport *vport, size_t count) @@ -3208,6 +3338,18 @@ void mlx5_eswitch_offloads_single_fdb_del_one(struct= mlx5_eswitch *master_esw, esw_unset_master_egress_rule(master_esw->dev, slave_esw->dev); } =20 +int mlx5_eswitch_offloads_vport_lag_add_one(struct mlx5_eswitch *master_es= w, + struct mlx5_eswitch *slave_esw) +{ + return esw_set_slave_egress_rule(master_esw->dev, slave_esw->dev); +} + +void mlx5_eswitch_offloads_vport_lag_del_one(struct mlx5_eswitch *master_e= sw, + struct mlx5_eswitch *slave_esw) +{ + esw_unset_slave_egress_rule(master_esw->dev, slave_esw->dev); +} + #define ESW_OFFLOADS_DEVCOM_PAIR (0) #define ESW_OFFLOADS_DEVCOM_UNPAIR (1) =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/lag/lag.c index b660253ffc6d..9566fbf59fdb 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c @@ -139,9 +139,44 @@ static int mlx5_cmd_modify_lag(struct mlx5_core_dev *d= ev, struct mlx5_lag *ldev, return mlx5_cmd_exec_in(dev, modify_lag, in); } =20 +static u32 mlx5_lag_dev_group_id(struct mlx5_core_dev *dev) +{ + struct mlx5_lag *ldev =3D mlx5_lag_dev(dev); + struct lag_func *pf; + int i; + + if (!ldev) + return 0; + + mlx5_lag_for_each(i, 0, ldev, MLX5_LAG_FILTER_ALL) { + pf =3D mlx5_lag_pf(ldev, i); + if (pf->dev =3D=3D dev) + return pf->sd_fdb_active ? pf->group_id : 0; + } + return 0; +} + +static int mlx5_lag_is_sw_lag(struct mlx5_core_dev *dev) +{ + return mlx5_lag_is_sd(dev); +} + int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev) { u32 in[MLX5_ST_SZ_DW(create_vport_lag_in)] =3D {}; + struct mlx5_lag *ldev =3D mlx5_lag_dev(dev); + int ret; + + if (mlx5_lag_is_sw_lag(dev)) { + if (!ldev) + return -ENODEV; + + mutex_lock(&ldev->lock); + ret =3D mlx5_lag_create_vport_lag(mlx5_lag_dev(dev), + mlx5_lag_dev_group_id(dev)); + mutex_unlock(&ldev->lock); + return ret; + } =20 MLX5_SET(create_vport_lag_in, in, opcode, MLX5_CMD_OP_CREATE_VPORT_LAG); =20 @@ -152,6 +187,18 @@ EXPORT_SYMBOL(mlx5_cmd_create_vport_lag); int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev) { u32 in[MLX5_ST_SZ_DW(destroy_vport_lag_in)] =3D {}; + struct mlx5_lag *ldev =3D mlx5_lag_dev(dev); + + if (mlx5_lag_is_sw_lag(dev)) { + if (!ldev) + return 0; + + mutex_lock(&ldev->lock); + mlx5_lag_destroy_vport_lag(mlx5_lag_dev(dev), + mlx5_lag_dev_group_id(dev)); + mutex_unlock(&ldev->lock); + return 0; + } =20 MLX5_SET(destroy_vport_lag_in, in, opcode, MLX5_CMD_OP_DESTROY_VPORT_LAG); =20 @@ -1663,7 +1710,7 @@ int mlx5_lag_demux_init(struct mlx5_core_dev *dev, =20 xa_init(&pf->lag_demux_rules); =20 - if (mlx5_get_sd(dev)) + if (mlx5_lag_is_sw_lag(dev)) return mlx5_lag_demux_ft_fg_init(dev, ft_attr, pf); =20 return mlx5_lag_demux_fw_init(dev, ft_attr, pf); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/lag/lag.h index c689f1951cd8..34350b0a7307 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.h @@ -175,6 +175,8 @@ int mlx5_lag_shared_fdb_create(struct mlx5_lag *ldev, enum mlx5_lag_mode mode, u32 group_id); void mlx5_lag_shared_fdb_destroy(struct mlx5_lag *ldev, u32 group_id); +int mlx5_lag_create_vport_lag(struct mlx5_lag *ldev, u32 group_id); +int mlx5_lag_destroy_vport_lag(struct mlx5_lag *ldev, u32 group_id); int mlx5_lag_create_single_fdb(struct mlx5_lag *ldev); void mlx5_lag_destroy_single_fdb(struct mlx5_lag *ldev); bool mlx5_lag_shared_fdb_supported(struct mlx5_lag *ldev); @@ -191,6 +193,18 @@ static inline int mlx5_lag_shared_fdb_create(struct ml= x5_lag *ldev, static inline void mlx5_lag_shared_fdb_destroy(struct mlx5_lag *ldev, u32 group_id) {} =20 +static inline int mlx5_lag_create_vport_lag(struct mlx5_lag *ldev, + u32 group_id) +{ + return -EOPNOTSUPP; +} + +static inline int mlx5_lag_destroy_vport_lag(struct mlx5_lag *ldev, + u32 group_id) +{ + return -EOPNOTSUPP; +} + static inline int mlx5_lag_create_single_fdb(struct mlx5_lag *ldev) { return -EOPNOTSUPP; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c b/dri= vers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c index 1371e14c4c13..8d4f2903a101 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/shared_fdb.c @@ -89,6 +89,76 @@ static int mlx5_lag_create_single_fdb_filter(struct mlx5= _lag *ldev, u32 filter) return err; } =20 +int mlx5_lag_create_vport_lag(struct mlx5_lag *ldev, u32 group_id) +{ + u32 filter =3D group_id ? group_id : MLX5_LAG_FILTER_ALL; + int master_idx =3D mlx5_lag_get_dev_index_by_seq_filter(ldev, MLX5_LAG_P1, + filter); + struct mlx5_eswitch *master_esw; + struct mlx5_core_dev *dev0; + int i, j; + int err; + + if (master_idx < 0) + return -EINVAL; + + dev0 =3D mlx5_lag_pf(ldev, master_idx)->dev; + master_esw =3D dev0->priv.eswitch; + + mlx5_lag_for_each(i, 0, ldev, filter) { + struct mlx5_eswitch *slave_esw; + + if (i =3D=3D master_idx) + continue; + + slave_esw =3D mlx5_lag_pf(ldev, i)->dev->priv.eswitch; + err =3D mlx5_eswitch_offloads_vport_lag_add_one(master_esw, + slave_esw); + if (err) + goto err; + } + + return 0; + +err: + mlx5_lag_for_each_reverse(j, i - 1, 0, ldev, filter) { + struct mlx5_eswitch *slave_esw; + + if (j =3D=3D master_idx) + continue; + slave_esw =3D mlx5_lag_pf(ldev, j)->dev->priv.eswitch; + mlx5_eswitch_offloads_vport_lag_del_one(master_esw, slave_esw); + } + return err; +} + +int mlx5_lag_destroy_vport_lag(struct mlx5_lag *ldev, u32 group_id) +{ + u32 filter =3D group_id ? group_id : MLX5_LAG_FILTER_ALL; + int master_idx =3D mlx5_lag_get_dev_index_by_seq_filter(ldev, MLX5_LAG_P1, + filter); + struct mlx5_eswitch *master_esw; + struct mlx5_core_dev *dev0; + int i; + + if (master_idx < 0) + return 0; + + dev0 =3D mlx5_lag_pf(ldev, master_idx)->dev; + master_esw =3D dev0->priv.eswitch; + + mlx5_lag_for_each(i, 0, ldev, filter) { + struct mlx5_core_dev *dev; + + if (i =3D=3D master_idx) + continue; + dev =3D mlx5_lag_pf(ldev, i)->dev; + mlx5_eswitch_offloads_vport_lag_del_one(master_esw, + dev->priv.eswitch); + } + return 0; +} + static void mlx5_lag_destroy_single_fdb_filter(struct mlx5_lag *ldev, u32 filter) { @@ -141,7 +211,7 @@ int mlx5_lag_shared_fdb_create(struct mlx5_lag *ldev, enum mlx5_lag_mode mode, u32 group_id) { - u32 filter =3D group_id ? group_id : MLX5_LAG_FILTER_PORTS; + u32 filter =3D group_id ? group_id : MLX5_LAG_FILTER_ALL; int idx =3D mlx5_lag_get_dev_index_by_seq_filter(ldev, MLX5_LAG_P1, filter); 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , Shay Drory , Or Har-Toov , Edward Srouji , Simon Horman , Maher Sanalla , Parav Pandit , Kees Cook , Moshe Shemesh , Patrisious Haddad , , , , Gal Pressman Subject: [PATCH net-next 12/15] net/mlx5: LAG, add MPESW over SD LAG support Date: Thu, 4 Jun 2026 14:44:52 +0300 Message-ID: <20260604114455.434711-13-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260604114455.434711-1-tariqt@nvidia.com> References: <20260604114455.434711-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF00000206:EE_|BL1PR12MB5801:EE_ X-MS-Office365-Filtering-Correlation-Id: 90d3410e-3244-4a08-e5bc-08dec22ef12b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|376014|7416014|1800799024|18002099003|22082099003|6133799003|56012099006|11063799006; X-Microsoft-Antispam-Message-Info: xg/ZTpDJ6M3Z0lHiD2f6EJuLKroPW56O3k9BquyC6DxmANLnIQWaU/IAORAlxBGo5+93y0Vak1ScSxcu0dr+vtouUWW5oiUXgAeqMiK3gb6HFvoH4jJ2PPHp1ccBpRMAzgpbuUnzi2uUehtcPMV58spOGYh/4TRRDRYReXcBet9DjToN8ZsSquLn+RsPoTqptKBp48zBOuoLKh/KgYeSo6tCeQbjwd81k8uhGBwgb1PXDj/VaotXCLPgIFDAbkVUeJmaLJXIQ0LTl+tmFBhpMuL8Zc6mlJZq7ONAkuj8KLrB1tvuxUeown2TCSPDLytDtQC8pA9NuJ2zI3SP2LX2kyE8xUF7YGKjMMeJFKlKT26ytkXFz0l496BTBRjNZYSLqywwBXV+SjD27sdaRwqGfsnpQx6zDKgPbomZ7SH+tyKUGzQq0eMhz/cw0/IkCHWlcT7A3T6o9B1WehOQvcTCJIij68cGputGkiV/2wmiws1DMCBoz1QptpPl7Nf0P74q+0AE8bOZI+Lgp4LpUhtUCqvfPBZWWbM30K5aA23d+lpDma+RnSWQWQbY++S8OqBsw+Bb6s4EPJvfxi+7u2w3mAk7R5VK3p2VdrNfY6u2+hDUx/eRwSD2jEnul01aMWNlNGKHcG+mCegyDhWGa+wl699NXGmcT17pcFz8AcRZyTQyyHcgRHaL6nsBvI2L31JTaaSZ2bZboIv4fkqhe8pb7b+LyvkF2+NsHl5d0FnmELg= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(82310400026)(376014)(7416014)(1800799024)(18002099003)(22082099003)(6133799003)(56012099006)(11063799006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: PndICmx78XGrhhw2OlAgUNj22TkRddRca03zdnnA+ig29wZGr8EEj+RjuEPxgayambJB9ThvTuBvd3pxdCBsShkB6DHeG1pp7VSrHtWSyagwrk1kCuQSJp05u3Gm0TpGMo9f8m4OJmOlAgjiSIHCsKf25RynssC/gs3+bgFxVqSiwzjqicx8xqzMbmKJkIqpwlB+CXcgifLB7bJKzyLq16OZiayVExfDJhN+E+/RB0oKnjUSH5khQyDofHuX1Ewt3lfoGwYHua2tRhUvlZ4DqrmdoJRUFfb8YthIetTHJal5hJ2HRu/BleWLYdzI3NbAZAJd946dhb5yaWxo3I7I3Z7GwObRId284NhCKfweIbqVLk4XiJnQQEyTkWHcBE+gc+hZC+SspQOjW+GSAGStQpKH17QqPhYTytS4vXhZalilGjlC+4b3v1mldHqEdgL3 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jun 2026 11:46:40.3391 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 90d3410e-3244-4a08-e5bc-08dec22ef12b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF00000206.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5801 Content-Type: text/plain; charset="utf-8" From: Shay Drory Enable MPESW LAG creation over SD LAG members, forming a composite LAG hierarchy. This allows bonding multiple SD groups together under a single MPESW configuration with shared FDB. When enabling composite MPESW, the individual SD LAG shared FDB configurations are temporarily torn down and recreated when the composite LAG is disabled. Signed-off-by: Shay Drory Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/lag/lag.c | 6 ++ .../net/ethernet/mellanox/mlx5/core/lag/lag.h | 8 ++ .../ethernet/mellanox/mlx5/core/lag/mpesw.c | 95 +++++++++++++++++-- .../ethernet/mellanox/mlx5/core/lag/mpesw.h | 4 + 4 files changed, 105 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/lag/lag.c index 9566fbf59fdb..25a9012e3014 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c @@ -2545,6 +2545,7 @@ void mlx5_lag_disable_change(struct mlx5_core_dev *de= v) struct mlx5_core_dev *primary; struct mlx5_lag *ldev; struct lag_func *pf; + bool mpesw; int i; =20 ldev =3D mlx5_lag_dev(dev); @@ -2553,6 +2554,9 @@ void mlx5_lag_disable_change(struct mlx5_core_dev *de= v) =20 primary =3D mlx5_sd_get_primary(dev) ?: dev; mlx5_devcom_comp_lock(primary->priv.hca_devcom_comp); + mpesw =3D ldev->mode =3D=3D MLX5_LAG_MODE_MPESW; + if (mpesw) + mlx5_mpesw_sd_devcoms_lock(ldev); mutex_lock(&ldev->lock); =20 ldev->mode_changes_in_progress++; @@ -2564,6 +2568,8 @@ void mlx5_lag_disable_change(struct mlx5_core_dev *de= v) } =20 mutex_unlock(&ldev->lock); + if (mpesw) + mlx5_mpesw_sd_devcoms_unlock(ldev); mlx5_devcom_comp_unlock(primary->priv.hca_devcom_comp); =20 if (!sd_devcom) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/lag/lag.h index 34350b0a7307..3a90d360d724 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.h @@ -157,6 +157,14 @@ __mlx5_lag_is_sd(struct mlx5_lag *ldev, struct mlx5_co= re_dev *dev) return pf && pf->group_id !=3D 0; } =20 +static inline bool +__mlx5_lag_dev_is_port(struct mlx5_lag *ldev, struct mlx5_core_dev *dev) +{ + struct lag_func *pf =3D mlx5_lag_pf_by_dev(ldev, dev); + + return pf && xa_get_mark(&ldev->pfs, pf->idx, MLX5_LAG_XA_MARK_PORT); +} + static inline bool __mlx5_lag_is_active(struct mlx5_lag *ldev) { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c b/drivers/= net/ethernet/mellanox/mlx5/core/lag/mpesw.c index 2cb44084e239..50bfb450c71e 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c @@ -15,7 +15,7 @@ static void mlx5_mpesw_metadata_cleanup(struct mlx5_lag *= ldev) u32 pf_metadata; int i; =20 - mlx5_ldev_for_each(i, 0, ldev) { + mlx5_lag_for_each(i, 0, ldev, MLX5_LAG_FILTER_ALL) { dev =3D mlx5_lag_pf(ldev, i)->dev; esw =3D dev->priv.eswitch; pf_metadata =3D ldev->lag_mpesw.pf_metadata[i]; @@ -36,7 +36,7 @@ static int mlx5_mpesw_metadata_set(struct mlx5_lag *ldev) u32 pf_metadata; int i, err; =20 - mlx5_ldev_for_each(i, 0, ldev) { + mlx5_lag_for_each(i, 0, ldev, MLX5_LAG_FILTER_ALL) { dev =3D mlx5_lag_pf(ldev, i)->dev; esw =3D dev->priv.eswitch; pf_metadata =3D mlx5_esw_match_metadata_alloc(esw); @@ -52,7 +52,7 @@ static int mlx5_mpesw_metadata_set(struct mlx5_lag *ldev) goto err_metadata; } =20 - mlx5_ldev_for_each(i, 0, ldev) { + mlx5_lag_for_each(i, 0, ldev, MLX5_LAG_FILTER_ALL) { dev =3D mlx5_lag_pf(ldev, i)->dev; mlx5_notifier_call_chain(dev->priv.events, MLX5_DEV_EVENT_MULTIPORT_ESW, (void *)0); @@ -65,6 +65,48 @@ static int mlx5_mpesw_metadata_set(struct mlx5_lag *ldev) return err; } =20 +static void mlx5_mpesw_restore_sd_fdb(struct mlx5_lag *ldev) +{ + struct lag_func *pf; + int err, i; + + mlx5_ldev_for_each(i, 0, ldev) { + pf =3D mlx5_lag_pf(ldev, i); + err =3D mlx5_lag_shared_fdb_create(ldev, NULL, 0, pf->group_id); + if (err) + mlx5_core_warn(pf->dev, + "Failed to restore SD shared FDB (%d)\n", + err); + } +} + +static int mlx5_mpesw_teardown_sd_fdb(struct mlx5_lag *ldev) +{ + struct lag_func *pf; + int i; + + mlx5_ldev_for_each(i, 0, ldev) { + pf =3D mlx5_lag_pf(ldev, i); + if (!pf->sd_fdb_active) + continue; + mlx5_lag_shared_fdb_destroy(ldev, pf->group_id); + } + return 0; +} + +static bool mlx5_lag_has_sd_group(struct mlx5_lag *ldev) +{ + struct lag_func *pf; + int i; + + mlx5_ldev_for_each(i, 0, ldev) { + pf =3D mlx5_lag_pf(ldev, i); + if (pf->group_id) + return true; + } + return false; +} + static int mlx5_lag_enable_mpesw(struct mlx5_lag *ldev) { int idx =3D mlx5_lag_get_dev_index_by_seq(ldev, MLX5_LAG_P1); @@ -92,10 +134,17 @@ static int mlx5_lag_enable_mpesw(struct mlx5_lag *ldev) if (err) return err; =20 + if (mlx5_lag_has_sd_group(ldev)) + mlx5_mpesw_teardown_sd_fdb(ldev); + err =3D mlx5_lag_shared_fdb_create(ldev, NULL, MLX5_LAG_MODE_MPESW, MLX5_LAG_FILTER_ALL); if (err) { - mlx5_core_warn(dev0, "Failed to create LAG in MPESW mode (%d)\n", err); + mlx5_core_warn(dev0, + "Failed to create LAG in MPESW mode (%d)\n", + err); + if (mlx5_lag_has_sd_group(ldev)) + mlx5_mpesw_restore_sd_fdb(ldev); mlx5_mpesw_metadata_cleanup(ldev); return err; } @@ -105,9 +154,36 @@ static int mlx5_lag_enable_mpesw(struct mlx5_lag *ldev) =20 void mlx5_lag_disable_mpesw(struct mlx5_lag *ldev) { - if (ldev->mode =3D=3D MLX5_LAG_MODE_MPESW) { - mlx5_mpesw_metadata_cleanup(ldev); - mlx5_lag_shared_fdb_destroy(ldev, MLX5_LAG_FILTER_ALL); + if (ldev->mode !=3D MLX5_LAG_MODE_MPESW) + return; + + mlx5_mpesw_metadata_cleanup(ldev); + mlx5_lag_shared_fdb_destroy(ldev, MLX5_LAG_FILTER_ALL); + if (mlx5_lag_has_sd_group(ldev)) + mlx5_mpesw_restore_sd_fdb(ldev); +} + +void mlx5_mpesw_sd_devcoms_lock(struct mlx5_lag *ldev) +{ + struct mlx5_devcom_comp_dev *sd_devcom; + int i; + + mlx5_ldev_for_each(i, 0, ldev) { + sd_devcom =3D mlx5_sd_get_devcom(mlx5_lag_pf(ldev, i)->dev); + if (sd_devcom) + mlx5_devcom_comp_lock(sd_devcom); + } +} + +void mlx5_mpesw_sd_devcoms_unlock(struct mlx5_lag *ldev) +{ + struct mlx5_devcom_comp_dev *sd_devcom; + int i; + + mlx5_ldev_for_each_reverse(i, MLX5_MAX_PORTS, 0, ldev) { + sd_devcom =3D mlx5_sd_get_devcom(mlx5_lag_pf(ldev, i)->dev); + if (sd_devcom) + mlx5_devcom_comp_unlock(sd_devcom); } } =20 @@ -122,6 +198,7 @@ static void mlx5_mpesw_work(struct work_struct *work) return; =20 mlx5_devcom_comp_lock(devcom); + mlx5_mpesw_sd_devcoms_lock(ldev); mutex_lock(&ldev->lock); if (ldev->mode_changes_in_progress) { mpesww->result =3D -EAGAIN; @@ -134,6 +211,7 @@ static void mlx5_mpesw_work(struct work_struct *work) mlx5_lag_disable_mpesw(ldev); unlock: mutex_unlock(&ldev->lock); + mlx5_mpesw_sd_devcoms_unlock(ldev); mlx5_devcom_comp_unlock(devcom); complete(&mpesww->comp); } @@ -199,7 +277,8 @@ bool mlx5_lag_is_mpesw(struct mlx5_core_dev *dev) { struct mlx5_lag *ldev =3D mlx5_lag_dev(dev); =20 - return ldev && ldev->mode =3D=3D MLX5_LAG_MODE_MPESW; + return ldev && ldev->mode =3D=3D MLX5_LAG_MODE_MPESW && + __mlx5_lag_dev_is_port(ldev, dev); } EXPORT_SYMBOL(mlx5_lag_is_mpesw); =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.h b/drivers/= net/ethernet/mellanox/mlx5/core/lag/mpesw.h index b767dbb4f457..5099723ba0f7 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.h @@ -33,8 +33,12 @@ void mlx5_lag_mpesw_disable(struct mlx5_core_dev *dev); int mlx5_lag_mpesw_enable(struct mlx5_core_dev *dev); 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , Shay Drory , Or Har-Toov , Edward Srouji , Simon Horman , Maher Sanalla , Parav Pandit , Kees Cook , Moshe Shemesh , Patrisious Haddad , , , , Gal Pressman Subject: [PATCH net-next 13/15] net/mlx5: E-Switch, defer rep load while SD LAG is not active Date: Thu, 4 Jun 2026 14:44:53 +0300 Message-ID: <20260604114455.434711-14-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260604114455.434711-1-tariqt@nvidia.com> References: <20260604114455.434711-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A2:EE_|SJ0PR12MB8616:EE_ X-MS-Office365-Filtering-Correlation-Id: bcbe4fbc-e535-4c96-f1f9-08dec22ef7d5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|376014|7416014|82310400026|1800799024|22082099003|18002099003|56012099006|11063799006; X-Microsoft-Antispam-Message-Info: jcC129pp1l9S1eAyGaHxsKNLpyiRKiyMMB/0LhmDcdX0l3tuYSFyFSL2z5ZLs+CycgwEFkQDP7hYVinItXdmlG2DQbRBqbMyXKb0H7KWslFJ9gthg8jnyR2l3vyiipwXfyYdpfFMIJewc5Em1tct7PE1e5ZisOjjEziRy+8TC7bZ9ddjVukCUs2ppFLOp2/mGzvjwfXg5Cm84/9XyCeSo5Uh5IhM3gNrmS+U9wQi54pN5Xfb1YK0ZY0Oa3t/wYzsu4UxPseulA5SBvMAcDZFg0ilkB11+DWnb78TrARZFxDvJ8rSc0UaV9N7gNRvFh5DgEua9QqLh6fnvJFzENz0AENlaNtDrg6mH/U2xJAyVW0FMgWiKpHDYYri6PA69krYpQ47EOlPXtV3Xcu6TFFPYuB2mB07as4eKMWKhhrt9cknwdRlIFY6xVJFdTaFBtMwvMZArTsv1v2QQ+hpLatytNmNsrnDKeEBeaO6D0recrr9f6XzlpZaQVC1m1iGJDbFnKPjCJ0k+e99K7jatjXmW3dicjU0iWcaO9k2jbsknursaVf9K6/OpPTdrBf8IsHXVNHLEgjc674umx1Iz53GARwUrmnNWqPPpk0ZISuL/hK9Px4kLmeqssXJcvHeqg6Ik1W8ITSwkseN/FFqa/4IRc+ozu8YEVEJc2jTGX4ezGazyExUlgm0oM5swlKjECYLGrAdAobrvN3ucnxnL9slVEIgb5S3gqZXZD7JMEQla0I= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(376014)(7416014)(82310400026)(1800799024)(22082099003)(18002099003)(56012099006)(11063799006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: xjdbpLOxFCDVsc+7LlDxJccCGTmorRRJYUG1aoIKQuBNmcAKDjJDW40QwUQS1OlTelXdOFWIrLclxjc3kjXVm89LFx8Jvw8QOVjB5f7YGLEOk6fOzULTiDhUNGDs4O45JELS5pAHr0hE7DOp+P4BNYAJMk2fjgzeW1CCa58+01dE5WfUEF4mwHavOXo2tYQQF1OnKtS7Py0MzHESfBuJqM082snGGJt+esGIkxL5HOq4folZOtHoeMHjDdwkbe+y/w54nrcqK/Z0gJjYO/pWKe3JPp4nCcDEIHlEXj0V2VUtmQ6agvA0Vy6nLTheMJH/aNnX4h5tUDXf8UyaUekdOmFpVVhz5FeMMNWgDkgmBHkRQUO1hIo/SVrzhKy4L9Mq4wvS/IDSGH5puDlRAlE4yoBYSKz45zdD5eTLIV3oCtf0Q4maEKo6nMg0Ob9u30/m X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jun 2026 11:46:51.3691 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bcbe4fbc-e535-4c96-f1f9-08dec22ef7d5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A2.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB8616 Content-Type: text/plain; charset="utf-8" From: Shay Drory On an SD device, vport representors are not functional until the SD group is combined and shared FDB is active. Skip both the initial load and the reload path in that window; reps are loaded as part of the SD LAG activation flow once it becomes active. Signed-off-by: Shay Drory Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/d= rivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index ad812fb1bb80..4d3f80bd6af0 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -2863,6 +2863,10 @@ static int mlx5_esw_offloads_rep_load(struct mlx5_es= witch *esw, u16 vport_num) int rep_type; int err; =20 + if (vport_num !=3D MLX5_VPORT_UPLINK && + mlx5_get_sd(esw->dev) && !mlx5_lag_is_active(esw->dev)) + return 0; + rep =3D mlx5_eswitch_get_rep(esw, vport_num); for (rep_type =3D 0; rep_type < NUM_REP_TYPES; rep_type++) { err =3D __esw_offloads_load_rep(esw, rep, rep_type, @@ -4766,6 +4770,9 @@ static void mlx5_eswitch_reload_reps_blocked(struct m= lx5_eswitch *esw) return; } =20 + if (mlx5_get_sd(esw->dev) && !mlx5_lag_is_active(esw->dev)) + return; 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Thu, 4 Jun 2026 04:46:41 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , Shay Drory , Or Har-Toov , Edward Srouji , Simon Horman , Maher Sanalla , Parav Pandit , Kees Cook , Moshe Shemesh , Patrisious Haddad , , , , Gal Pressman Subject: [PATCH net-next 14/15] net/mlx5: SD, defer vport metadata init until SD is ready Date: Thu, 4 Jun 2026 14:44:54 +0300 Message-ID: <20260604114455.434711-15-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260604114455.434711-1-tariqt@nvidia.com> References: <20260604114455.434711-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF0000449E:EE_|IA1PR12MB7760:EE_ X-MS-Office365-Filtering-Correlation-Id: 0fce6336-7d61-4f27-abea-08dec22efffa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|36860700016|1800799024|22082099003|18002099003|11063799006|56012099006; X-Microsoft-Antispam-Message-Info: fdnrZsZj9FlvbkkzBx0rxYBsyBiy7XRh8AKY57e3OIfih93aSaJIgI6jc7FY07nsq8OZiG6+Ibss1BgqKwOGgqarJWKq8gwr6HofCd6eYnv4iqQM+cnb4SEEm/mZLXzOX4PArgSb72PWEgYdIedcWs4kJR897VKhJSchzzMp27/gBGeH7L+SedwM5unyIkyFMxLS8OsbDxt/fhG0c15c9EZIKzsZ4CCL4uhw1IKu73GZxN6Q2/4XECOEcqn+ZIlW4tEi+eKBq32YC8KwTjH3vv672xO7608Uhd0LAynYRtO/wgE8feFBlDmOZ+Da4xGWiG9HJJovecZAfV/iC2gVV7JXv2er7cWHp460sGBJ1dOtI+XCRkOiWH6Jg5TaPk6J5uH78fEJ3D5hdC7cXsqelmjd7jwMeVVDdS04slEa1fNZJCJqqL2JL8OVIZgOzDy0sgad5MWBynjTJhW96Ul7P6kCWnvVTGKF6U7v53Aa9leDsV9+UGem4Ra5Q/SYAoH/hpr8yyw2g08Frz4cl++PT0lK1MGUokpWnfbeMoWqypBz87dkr5MQbUFl54CSMSx4IGsxpBYIUpkizMmK08wwocSFk80VLMvpKgorhxVFjrLdpLyyUk6b7XACsAR1zVRSZEeDl5SE+3LYVGAcBm6nEuwWeDqqOM6t+He4z2F0G1DjB6bX4KcMxE4VyKL+S4hRgRqa3KFMmS6meGxjOqP9YIOJDFXrJEDe4OZomoWqBBU= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(82310400026)(36860700016)(1800799024)(22082099003)(18002099003)(11063799006)(56012099006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: TPW+6nWueoN697A6URMxrZQOkVQciTnOG+WL/63oSIkkChJvIkKaXwju3VMN0wTfa5Q/j7ceRVtiRu2i+MTBdyYtvF9nUR9lE+avCa8UIjc7sxGq9wEHPkJmWbwDoTiConnEEDKe7V0K/5xJa3LLCqhNyumzM8seLVi6qkbUnU2fJIISLv6vU17yX/GgTNZ1+yVPlA3JZ2fAbcvqf9FTSENP4HoVZXzrAD5z7lP0oo1AHKR6FK0DDfpAJualSpI6nyBG/vVV9ViSc6jTKHjpO+KbfpfdH1AW8hRB6zm/6raNk2vgyKl1d5rGxRAMp2sA9W4ikxRdTHXyHgPeiM68fQHLaxsvOc9F5g94mWAqf781F0+RQR7eCXvdeCuzV1IinKgBea29/cRz9sGZcztJ+nJ5nEyHwiyeL6Z8KKOVH+Oekspfu2z7gtnsHx/y9D6b X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jun 2026 11:47:04.9943 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0fce6336-7d61-4f27-abea-08dec22efffa X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF0000449E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7760 Content-Type: text/plain; charset="utf-8" From: Shay Drory Allow SD devices to transition to switchdev before the SD group is fully up. Metadata allocation requires the SD group to be ready, so defer it from esw_offloads_enable() until SD shared-FDB activation. Add mlx5_esw_offloads_init_deferred_metadata() which allocates per-vport metadata and refreshes the manager ingress ACLs that were previously programmed with metadata=3D0. The helper is idempotent and can be called multiple times. Signed-off-by: Shay Drory Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/eswitch.h | 1 + .../mellanox/mlx5/core/eswitch_offloads.c | 46 ++++++++++++++++++- .../net/ethernet/mellanox/mlx5/core/lib/sd.c | 16 +++++++ 3 files changed, 62 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.h index a5f0774834fe..ecf6a28a1c08 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h @@ -440,6 +440,7 @@ struct mlx5_eswitch { =20 void esw_offloads_disable(struct mlx5_eswitch *esw); int esw_offloads_enable(struct mlx5_eswitch *esw); +int mlx5_esw_offloads_init_deferred_metadata(struct mlx5_eswitch *esw); void esw_offloads_cleanup(struct mlx5_eswitch *esw); int esw_offloads_init(struct mlx5_eswitch *esw); =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/d= rivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index 4d3f80bd6af0..503530b0acba 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -43,6 +43,7 @@ #include "esw/acl/ofld.h" #include "rdma.h" #include "en.h" +#include "en_rep.h" #include "fs_core.h" #include "lib/mlx5.h" #include "lib/devcom.h" @@ -3675,6 +3676,7 @@ static void esw_offloads_vport_metadata_cleanup(struc= t mlx5_eswitch *esw, =20 WARN_ON(vport->metadata !=3D vport->default_metadata); mlx5_esw_match_metadata_free(esw, vport->default_metadata); + vport->default_metadata =3D 0; } =20 static void esw_offloads_metadata_uninit(struct mlx5_eswitch *esw) @@ -3711,6 +3713,38 @@ static int esw_offloads_metadata_init(struct mlx5_es= witch *esw) return err; } =20 +/* Deferred metadata init for SD devices: allocate vport metadata + * Safe to call multiple times - subsequent calls are no-ops. + */ +int mlx5_esw_offloads_init_deferred_metadata(struct mlx5_eswitch *esw) +{ + struct mlx5_vport *manager; + int err; + + if (!mlx5_eswitch_vport_match_metadata_enabled(esw)) + return 0; + + manager =3D mlx5_eswitch_get_vport(esw, esw->manager_vport); + if (IS_ERR(manager)) + return PTR_ERR(manager); + + /* Sanity check: skip if metadata was already initialized */ + if (manager->default_metadata) + return 0; + + err =3D esw_offloads_metadata_init(esw); + if (err) + return err; + + /* Manager vport don't have a rep/netdev loaded but its ingress ACL + * was programmed with metadata=3D0 in esw_create_offloads_acl_tables() - + * refresh it explicitly. + */ + mlx5_esw_acl_ingress_vport_metadata_update(esw, esw->manager_vport, 0); + + return 0; +} + int esw_vport_create_offloads_acl_tables(struct mlx5_eswitch *esw, struct mlx5_vport *vport) @@ -4053,7 +4087,17 @@ int esw_offloads_enable(struct mlx5_eswitch *esw) if (err) goto err_roce; =20 - err =3D esw_offloads_metadata_init(esw); + /* SD devices defer metadata init until SD is ready and + * mlx5_sd_pf_num_get() can return the correct pf_num. + */ + if (!mlx5_get_sd(esw->dev)) { + err =3D esw_offloads_metadata_init(esw); + } else if (mlx5_eswitch_vport_match_metadata_enabled(esw)) { + struct mlx5_vport *uplink =3D + mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK); + + err =3D esw_offloads_vport_metadata_setup(esw, uplink); + } if (err) goto err_metadata; =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c b/drivers/net= /ethernet/mellanox/mlx5/core/lib/sd.c index d2ed156ed1c6..82ae8c3969fe 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c @@ -988,6 +988,7 @@ static bool mlx5_sd_all_paired(struct mlx5_core_dev *pr= imary) static void mlx5_sd_activate_shared_fdb(struct mlx5_core_dev *primary) { struct mlx5_sd *sd =3D mlx5_get_sd(primary); + struct mlx5_core_dev *pos; struct mlx5_lag *ldev; struct lag_func *pf; int err; @@ -1016,6 +1017,21 @@ static void mlx5_sd_activate_shared_fdb(struct mlx5_= core_dev *primary) goto unlock; } =20 + /* Initialize vport metadata for all group devices. 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , Shay Drory , Or Har-Toov , Edward Srouji , Simon Horman , Maher Sanalla , Parav Pandit , Kees Cook , Moshe Shemesh , Patrisious Haddad , , , , Gal Pressman Subject: [PATCH net-next 15/15] net/mlx5: SD, enable SD over ECPF and allow switchdev transition Date: Thu, 4 Jun 2026 14:44:55 +0300 Message-ID: <20260604114455.434711-16-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260604114455.434711-1-tariqt@nvidia.com> References: <20260604114455.434711-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF0000449E:EE_|SA3PR12MB9227:EE_ X-MS-Office365-Filtering-Correlation-Id: b760f387-fbe0-414d-ce0b-08dec22f017e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|376014|7416014|1800799024|18002099003|22082099003|56012099006|11063799006; X-Microsoft-Antispam-Message-Info: hnOuk+4siPXlVSHJPBqN+M8ePy7/Mo/ApW0pa4f9vcNmkhFkxOr9EIXWOCvq2VdBGWVHZ5I0FUrN7CVaF6k6KJmLqABmbrfmhesAlx/HkVTcRRUK9y/aCZH5bJ21tX9Maw0xFgPMPQTbvpfArhxiyUZNi7guTKsCm6I8pv/s1kLZWyaKPDYi1DkfAwK7ZexfPHoP2VLcoIjNsagytZY3nsd7+KtCwkzK5ALtZ4LUrGdZWRwNK83S6yYoTSafZMuN9dXMaomRYP2QsAh9G+ni/J9NAPYvGfGSvs7S0Lf9ghtL3Z4eNnIzg0pxkrdt/CPWcgc3SIKsgK3O4h2UWGw62Hfdq5jsEronWjnoYjeKDlPO1zvruDkbZoQWSE6ML5pRflR8kvNF05sawj6b/Kr+A5M1FsUrWBdmef1SS7fykqhPuDl/IF8EG9ogRDp4WJgErpVNUlGGO08qKfZo2ksXUWQwqilGcJBf3lDCtBlfVxG6Lv6Bl3cxYfbXh6zF8gQ1OUszJHjNiqb250m1EzHH2rSBl+xjHvoxYRMddPhaQU9bUEbhUI344j9zTmSbVfM92pKtJEj5z+empgtA36MjOV3tN7a//wGuQ1iQpYA+mgHhuwIo9iKDnheAtkfvq2uASvaNhLQ/wgZjMi6HMDfg38yVvJ/GyWOUfkS1nd+0lQuBDLzZDbhqFv2h+N8p1nEBbrDT2Q/nVETt+N+fAKwsIPPcvVfOzjod4LBcwrST4ZE= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(82310400026)(376014)(7416014)(1800799024)(18002099003)(22082099003)(56012099006)(11063799006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 1VMZEuKpX1VQbNzrGy8ZaZdq5JBZ1ym4+esPjoVOSi0igezdCy8AwA8wZz+YLh+XfpQlDGZ1c4d0CEneKz6lfsMNzIN3Cu1Nb+45NITW4/9ZKKLLQKxWkXZw8ixyyRnHKRBWAQug1ucJBnUDNhy6O+26rT3mbtGtJmMjBSHIgqndOvMEmCCgNe6le4nZTuXTtP4DFgnfdZyRkycV1mL+Ia+QRrWKOUzYZxE2gVOGDSbWvKqRPUZ0JVWb+KzjPiACQIUnbqiTsxVRHLJXHj+m2MzJkdAuP/RlR65EsUzXGygQ3/wOt43zn7sJNnt6TldKkGo6KhLgkVA0/Xzaa4y0uuuTH3lM5BX78RiAEwV/O5pGu72ANUqfnq5t4Ny5ukimViaQK4cINhPucmTuYrWqtLf7Tia/1ZvzitwLv8u9Fut5K9Rqrva0Q3svupuhydBJ X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jun 2026 11:47:07.5545 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b760f387-fbe0-414d-ce0b-08dec22f017e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF0000449E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB9227 Content-Type: text/plain; charset="utf-8" From: Shay Drory Remove the restriction blocking SD on embedded CPU PFs (ECPF), enabling SD functionality on BlueField DPUs. Remove the blocker preventing SD devices from transitioning to switchdev mode. The infrastructure added in earlier patches properly handles this case. Signed-off-by: Shay Drory Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/eswitch_offloads.c | 6 ------ drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c | 8 -------- 2 files changed, 14 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/d= rivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index 503530b0acba..e3911da555e9 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -4419,12 +4419,6 @@ int mlx5_devlink_eswitch_mode_set(struct devlink *de= vlink, u16 mode, if (esw_mode_from_devlink(mode, &mlx5_mode)) return -EINVAL; =20 - if (mlx5_mode =3D=3D MLX5_ESWITCH_OFFLOADS && mlx5_get_sd(esw->dev)) { - NL_SET_ERR_MSG_MOD(extack, - "Can't change E-Switch mode to switchdev when multi-PF netdev (Sock= et Direct) is configured."); - return -EPERM; - } - if (mlx5_fw_reset_in_progress(esw->dev)) { NL_SET_ERR_MSG_MOD(extack, "Can't change eswitch mode during firmware reset"); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c b/drivers/net= /ethernet/mellanox/mlx5/core/lib/sd.c index 82ae8c3969fe..a9cc5a6ab007 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c @@ -222,10 +222,6 @@ bool mlx5_sd_is_supported(struct mlx5_core_dev *dev) if (!mlx5_core_is_pf(dev)) return false; =20 - /* Block on embedded CPU PFs */ - if (mlx5_core_is_ecpf(dev)) - return false; - err =3D mlx5_query_nic_vport_sd_group(dev, &sd_group); if (err || !sd_group) return false; @@ -252,10 +248,6 @@ static int sd_init(struct mlx5_core_dev *dev) if (!mlx5_core_is_pf(dev)) return 0; =20 - /* Block on embedded CPU PFs */ - if (mlx5_core_is_ecpf(dev)) - return 0; - err =3D mlx5_query_nic_vport_sd_group(dev, &sd_group); if (err) return err; --=20 2.44.0