From nobody Mon Jun 8 09:49:33 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 77AE6403E96; Thu, 4 Jun 2026 11:19:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780571946; cv=none; b=Q7U3ycnPWxvLG/T92rqOFY34QA+91+V8hkKyQoooRbNwQVQu2UNoOCJNkVSaBfY2/rcibbLJfmcwN5I9mjqKxB21420/JBQinscdYANT3THQ4dTmFXMIkm52PM+02ZQHonKIPh9nhqfMRf4zL9DYezpiFlBK7+eQpCnxNNCpjbY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780571946; c=relaxed/simple; bh=u517BEwQRTLE01P0mJFfmff+0nMkj7k3ExoYJzgThMo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=VlZNrCZqSMcpxbF9e16qpttfW19FrU2u7uMTA2jce8soby4OZSkBY/9zWjCARDyRXc5Rtj5906hKviPNiQWigRYGbw42Ny4XWGGgTZP6jseW2aspDfQZoTId+z2Q55Y3cgNr4woo4q0Y8ZvRyXuUlGYKwgXYGC5nOQzQ7CVokkM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com; spf=pass smtp.mailfrom=realtek.com; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b=dWU7W28m; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realtek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b="dWU7W28m" X-SpamFilter-By: ArmorX SpamTrap 5.80 with qID 654BILTF0299932, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=realtek.com; s=dkim; t=1780571902; bh=kp3CXR9786IlCOU/M2dXnjgdAwiYVzueeangPNGEtds=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=dWU7W28mk3hUn247ZGwKCpLbiI0R+gXsdptVw+RDpZIpB91NYlTw3DwI2K6YpeOTs iKDeqoaAUKyC1ppRT3Zc7IcRrEo/iY5+JZUmZCQx687L3rX3OLdNEzMtkkluwaEGXX lSfKISLoxhKsOedBHFrJYOVaRQhQjJ/vSwLPanNydaqACENyAKKyo3AAjCWFMVxlMu JWIkQX1uTw/pSDnjwrVMuMkT0joSdH9NSkQIGoOy6wyzbRiAtvpra53/Nh5aoC92wd gNKawUSnOuKE85xhP6xCI7evl7OtNhmU7ohy1nurlC8pAAkc3hyBMFBmjQUBuOlV6I d+o20mUU25afQ== Received: from mail.realtek.com (rtkexhmbs02.realtek.com.tw[172.21.6.41]) by rtits2.realtek.com.tw (8.15.2/3.28/5.94) with ESMTPS id 654BILTF0299932 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 4 Jun 2026 19:18:21 +0800 Received: from RTKEXHMBS06.realtek.com.tw (10.21.1.56) by RTKEXHMBS02.realtek.com.tw (172.21.6.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Thu, 4 Jun 2026 19:18:21 +0800 Received: from RTKEXHMBS05.realtek.com.tw (10.21.1.55) by RTKEXHMBS06.realtek.com.tw (10.21.1.56) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Thu, 4 Jun 2026 19:18:21 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS05.realtek.com.tw (10.21.1.55) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Thu, 4 Jun 2026 19:18:21 +0800 From: Yu-Chun Lin To: , , , CC: , , , , , , , , Subject: [PATCH 1/3] dt-bindings: soc: realtek: Add Realtek DHC I/O level detector Date: Thu, 4 Jun 2026 19:18:18 +0800 Message-ID: <20260604111821.975624-2-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260604111821.975624-1-eleanor.lin@realtek.com> References: <20260604111821.975624-1-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Tzuyi Chang Add device tree binding documentation for the Realtek DHC I/O level detector. This hardware block is responsible for detecting the I/O signaling levels (e.g., 1.8V or 3.3V) of various interfaces (RGMII, SDIO, eMMC, etc.) and applying the corresponding pad configurations via pinctrl states. Signed-off-by: Tzuyi Chang Signed-off-by: Yu-Chun Lin --- .../realtek/realtek,rtd1625-io-detect.yaml | 77 +++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/realtek/realtek,r= td1625-io-detect.yaml diff --git a/Documentation/devicetree/bindings/soc/realtek/realtek,rtd1625-= io-detect.yaml b/Documentation/devicetree/bindings/soc/realtek/realtek,rtd1= 625-io-detect.yaml new file mode 100644 index 000000000000..badf27212dfd --- /dev/null +++ b/Documentation/devicetree/bindings/soc/realtek/realtek,rtd1625-io-dete= ct.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2026 Realtek Semiconductor Corporation +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/realtek/realtek,rtd1625-io-detect.y= aml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek DHC I/O Level Detector + +maintainers: + - Tzuyi Chang + +description: | + The Realtek DHC I/O Level Detector is a hardware block that detects I/O + signaling levels (such as 1.8V or 3.3V) to determine the correct pad + configurations for specific IP blocks. + +properties: + compatible: + const: realtek,rtd1625-io-detect + + pinctrl-names: + items: + - const: rgmii_1v8 + - const: rgmii_3v3 + - const: sdio_1v8 + - const: sdio_3v3 + - const: csi_1v8 + - const: csi_3v3 + - const: sd_1v8 + - const: sd_3v3 + - const: uart1_1v8 + - const: uart1_3v3 + - const: aio_1v8 + - const: aio_3v3 + - const: emmc_1v8 + - const: emmc_3v3 + + realtek,iso-pinctrl: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Pinctrl phandle containing I/O detection registers. + +required: + - compatible + - pinctrl-names + - realtek,iso-pinctrl + +additionalProperties: false + +examples: + - | + io-detect { + compatible =3D "realtek,rtd1625-io-detect"; + pinctrl-names =3D "rgmii_1v8", "rgmii_3v3", + "sdio_1v8", "sdio_3v3", + "csi_1v8", "csi_3v3", + "sd_1v8", "sd_3v3", + "uart1_1v8", "uart1_3v3", + "aio_1v8", "aio_3v3", + "emmc_1v8", "emmc_3v3"; + pinctrl-0 =3D <&rgmii_vsel_1v8_pins>; + pinctrl-1 =3D <&rgmii_vsel_3v3_pins>; + pinctrl-2 =3D <&sdio_vsel_1v8_pins>; + pinctrl-3 =3D <&sdio_vsel_3v3_pins>; + pinctrl-4 =3D <&csi_vsel_1v8_pins>; + pinctrl-5 =3D <&csi_vsel_3v3_pins>; + pinctrl-6 =3D <&sd_vsel_1v8_pins>; + pinctrl-7 =3D <&sd_vsel_3v3_pins>; + pinctrl-8 =3D <&uart1_vsel_1v8_pins>; + pinctrl-9 =3D <&uart1_vsel_3v3_pins>; + pinctrl-10 =3D <&aio_vsel_1v8_pins>; + pinctrl-11 =3D <&aio_vsel_3v3_pins>; + pinctrl-12 =3D <&emmc_vsel_1v8_pins>; + pinctrl-13 =3D <&emmc_vsel_3v3_pins>; + realtek,iso-pinctrl =3D <&iso_pinctrl>; + }; --=20 2.43.0 From nobody Mon Jun 8 09:49:33 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D295413230; 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Thu, 4 Jun 2026 19:18:22 +0800 Received: from RTKEXHMBS06.realtek.com.tw (10.21.1.56) by RTKEXHMBS04.realtek.com.tw (10.21.1.54) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Thu, 4 Jun 2026 19:18:22 +0800 Received: from RTKEXHMBS05.realtek.com.tw (10.21.1.55) by RTKEXHMBS06.realtek.com.tw (10.21.1.56) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Thu, 4 Jun 2026 19:18:21 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS05.realtek.com.tw (10.21.1.55) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Thu, 4 Jun 2026 19:18:21 +0800 From: Yu-Chun Lin To: , , , CC: , , , , , , , , Subject: [PATCH 2/3] soc: realtek: Add driver for DHC I/O level detector Date: Thu, 4 Jun 2026 19:18:19 +0800 Message-ID: <20260604111821.975624-3-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260604111821.975624-1-eleanor.lin@realtek.com> References: <20260604111821.975624-1-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Tzuyi Chang Add driver support for the Realtek DHC I/O level detector. The driver reads hardware registers to determine the current I/O voltage levels (e.g., 1.8V or 3.3V) for specific IP blocks. Based on the detection results, it selects and applies the appropriate pinctrl states to ensure the correct pad configurations are used. Signed-off-by: Tzuyi Chang Signed-off-by: Yu-Chun Lin --- MAINTAINERS | 1 + drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/realtek/Kconfig | 21 ++++ drivers/soc/realtek/Makefile | 2 + drivers/soc/realtek/rtd-io-detect.c | 152 ++++++++++++++++++++++++++++ 6 files changed, 178 insertions(+) create mode 100644 drivers/soc/realtek/Kconfig create mode 100644 drivers/soc/realtek/Makefile create mode 100644 drivers/soc/realtek/rtd-io-detect.c diff --git a/MAINTAINERS b/MAINTAINERS index 9ec290e38b44..6121eb4f904e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3379,6 +3379,7 @@ F: arch/arm/boot/dts/realtek/ F: arch/arm/mach-realtek/ F: arch/arm64/boot/dts/realtek/ F: drivers/pinctrl/realtek/ +F: drivers/soc/realtek/ =20 ARM/RISC-V/RENESAS ARCHITECTURE M: Geert Uytterhoeven diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index a2d65adffb80..d63b9d4dc042 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -20,6 +20,7 @@ source "drivers/soc/microchip/Kconfig" source "drivers/soc/nuvoton/Kconfig" source "drivers/soc/pxa/Kconfig" source "drivers/soc/qcom/Kconfig" +source "drivers/soc/realtek/Kconfig" source "drivers/soc/renesas/Kconfig" source "drivers/soc/rockchip/Kconfig" source "drivers/soc/samsung/Kconfig" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index c9e689080ceb..8678b1001183 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -26,6 +26,7 @@ obj-y +=3D nuvoton/ obj-y +=3D pxa/ obj-y +=3D amlogic/ obj-y +=3D qcom/ +obj-y +=3D realtek/ obj-y +=3D renesas/ obj-y +=3D rockchip/ obj-$(CONFIG_SOC_SAMSUNG) +=3D samsung/ diff --git a/drivers/soc/realtek/Kconfig b/drivers/soc/realtek/Kconfig new file mode 100644 index 000000000000..4c5796c7f9f7 --- /dev/null +++ b/drivers/soc/realtek/Kconfig @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Realtek SoC drivers +# +menu "Realtek SoC drivers" + depends on ARCH_REALTEK || COMPILE_TEST + +config RTD_IO_LEVEL_DETECT + tristate "Realtek DHC I/O Level Detector" + depends on PINCTRL_RTD + select MFD_SYSCON + default ARCH_REALTEK + help + Enable support for the Realtek DHC I/O level detector. + + This driver handles the auto-detection of I/O signaling levels + (such as 1.8V and 3.3V) and dynamically configures the pad states + for specific IP blocks. + +endmenu + diff --git a/drivers/soc/realtek/Makefile b/drivers/soc/realtek/Makefile new file mode 100644 index 000000000000..c307e5bdb52d --- /dev/null +++ b/drivers/soc/realtek/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_RTD_IO_LEVEL_DETECT) +=3D rtd-io-detect.o diff --git a/drivers/soc/realtek/rtd-io-detect.c b/drivers/soc/realtek/rtd-= io-detect.c new file mode 100644 index 000000000000..84ef8ea23cb5 --- /dev/null +++ b/drivers/soc/realtek/rtd-io-detect.c @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Realtek DHC I/O Level Detect driver + * + * Copyright (c) 2026 Realtek Semiconductor Corp. + */ + +#include +#include +#include +#include +#include +#include +#include + +struct rtd_io_detect_desc_info { + const char *name; + const char *state_1v8; + const char *state_3v3; + unsigned int reg_offset; + unsigned int en_offset; + unsigned int status_offset; +}; + +struct rtd_io_detect_descs { + const struct rtd_io_detect_desc_info *info; + int num_descs; +}; + +struct rtd_io_detect_data { + const struct rtd_io_detect_descs *descs; + struct regmap *base; + struct device *dev; +}; + +#define RTD_IO_DETECT_DESC(_name, _reg_off, _en_off, _st_off) \ + { \ + .name =3D #_name, \ + .state_1v8 =3D #_name "_1v8", \ + .state_3v3 =3D #_name "_3v3", \ + .reg_offset =3D _reg_off, \ + .en_offset =3D _en_off, \ + .status_offset =3D _st_off, \ + } + +static const struct rtd_io_detect_desc_info rtd1625_io_detect_desc[] =3D { + RTD_IO_DETECT_DESC(rgmii, 0x1a0, 8, 1), + RTD_IO_DETECT_DESC(sd, 0x1a0, 9, 2), + RTD_IO_DETECT_DESC(csi, 0x1a0, 10, 3), + RTD_IO_DETECT_DESC(sdio, 0x1a0, 11, 4), + RTD_IO_DETECT_DESC(uart1, 0x1a0, 12, 5), + RTD_IO_DETECT_DESC(aio, 0x1a0, 13, 6), + RTD_IO_DETECT_DESC(emmc, 0x1a0, 14, 7), +}; + +static const struct rtd_io_detect_descs rtd1625_io_detect_descs =3D { + .info =3D rtd1625_io_detect_desc, + .num_descs =3D ARRAY_SIZE(rtd1625_io_detect_desc), +}; + +static void detect_io_set(struct pinctrl *pinctrl, + const struct rtd_io_detect_desc_info *desc, + struct rtd_io_detect_data *data) +{ + struct pinctrl_state *state_1v8; + struct pinctrl_state *state_3v3; + unsigned int val; + int ret; + + state_1v8 =3D pinctrl_lookup_state(pinctrl, desc->state_1v8); + if (IS_ERR(state_1v8)) { + dev_err(data->dev, "Failed to lookup %s state: %ld\n", + desc->state_1v8, PTR_ERR(state_1v8)); + return; + } + + state_3v3 =3D pinctrl_lookup_state(pinctrl, desc->state_3v3); + if (IS_ERR(state_3v3)) { + dev_err(data->dev, "Failed to lookup %s state: %ld\n", + desc->state_3v3, PTR_ERR(state_3v3)); + return; + } + + regmap_update_bits(data->base, desc->reg_offset, + BIT(desc->en_offset), BIT(desc->en_offset)); + + regmap_read(data->base, desc->reg_offset, &val); + + ret =3D pinctrl_select_state(pinctrl, + (val & BIT(desc->status_offset)) ? state_3v3 : state_1v8); + if (ret) + dev_err(data->dev, "Failed to select pinctrl state\n"); +} + +static int rtd_io_detect_probe(struct platform_device *pdev) +{ + struct rtd_io_detect_data *data; + struct device *dev =3D &pdev->dev; + struct device_node *pinctrl_np; + struct pinctrl *pinctrl; + int i; + + data =3D devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + pinctrl_np =3D of_parse_phandle(dev->of_node, "realtek,iso-pinctrl", 0); + if (!pinctrl_np) { + dev_err(dev, "Failed to find ISO pinctrl node\n"); + return -ENODEV; + } + + data->base =3D device_node_to_regmap(pinctrl_np); + of_node_put(pinctrl_np); + + if (IS_ERR(data->base)) + return dev_err_probe(dev, PTR_ERR(data->base), "Failed to get regmap\n"); + + data->descs =3D device_get_match_data(dev); + if (!data->descs) + return -EINVAL; + + pinctrl =3D devm_pinctrl_get(dev); + if (IS_ERR(pinctrl)) + return dev_err_probe(dev, PTR_ERR(pinctrl), "Failed to get pinctrl\n"); + + data->dev =3D dev; + + for (i =3D 0; i < data->descs->num_descs; i++) + detect_io_set(pinctrl, &data->descs->info[i], data); + + return 0; +} + +static const struct of_device_id rtd_io_detect_of_matches[] =3D { + { .compatible =3D "realtek,rtd1625-io-detect", .data =3D &rtd1625_io_dete= ct_descs }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rtd_io_detect_of_matches); + +static struct platform_driver rtd_io_detect_driver =3D { + .driver =3D { + .name =3D "rtd_io_level_detect", + .of_match_table =3D rtd_io_detect_of_matches, + }, + .probe =3D rtd_io_detect_probe, +}; +module_platform_driver(rtd_io_detect_driver); + +MODULE_DESCRIPTION("Realtek DHC SoC I/O Level Detect driver"); +MODULE_LICENSE("GPL"); + --=20 2.43.0 From nobody Mon Jun 8 09:49:33 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 06F5E410D13; Thu, 4 Jun 2026 11:19:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780571948; cv=none; b=RbQl++N/wI0TrqeIEceBwOGtiy2gtQdL/6C14SejLynJ9SRqa+4mWbHAtOyTJArmtSgRROnFrUD1tbrdCCp7IcwgKKubQWRNSoQgloPjmrw4GbXU1erZOAqeCmLCflrZCzTJYHSeteUM12BtzXiXWF+5n76le21y/J9sPzWAWYo= ARC-Message-Signature: i=1; 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Thu, 4 Jun 2026 19:18:22 +0800 Received: from RTKEXHMBS05.realtek.com.tw (10.21.1.55) by RTKEXHMBS06.realtek.com.tw (10.21.1.56) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Thu, 4 Jun 2026 19:18:22 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS05.realtek.com.tw (10.21.1.55) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Thu, 4 Jun 2026 19:18:21 +0800 From: Yu-Chun Lin To: , , , CC: , , , , , , , , Subject: [PATCH 3/3] arm64: dts: realtek: Add I/O level detector Date: Thu, 4 Jun 2026 19:18:20 +0800 Message-ID: <20260604111821.975624-4-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260604111821.975624-1-eleanor.lin@realtek.com> References: <20260604111821.975624-1-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add io-level-detector node with pinctrl configurations for 1.8V/3.3V voltage selection on RGMII, SDIO, CSI, SD, UART1, AIO, and eMMC. Signed-off-by: Yu-Chun Lin --- This patch depends on this pinctrl node patch [1]. [1] https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git/commit/?id= =3D50d92732d10e --- arch/arm64/boot/dts/realtek/kent-pinctrl.dtsi | 108 ++++++++++++++++++ arch/arm64/boot/dts/realtek/kent.dtsi | 28 +++++ 2 files changed, 136 insertions(+) create mode 100644 arch/arm64/boot/dts/realtek/kent-pinctrl.dtsi diff --git a/arch/arm64/boot/dts/realtek/kent-pinctrl.dtsi b/arch/arm64/boo= t/dts/realtek/kent-pinctrl.dtsi new file mode 100644 index 000000000000..ec7e33034b96 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/kent-pinctrl.dtsi @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Copyright (c) 2022-2026 Realtek Semiconductor Corp. + */ + +&iso_pinctrl { + aio_vsel_1v8_pins: aio-vsel-1v8-pins { + pins =3D "gpio_98", "gpio_99", "gpio_100", "gpio_101", "gpio_102", "gpio= _103", + "gpio_104", "gpio_105", "gpio_106", "gpio_107", "gpio_108", "gpio= _109", + "gpio_110", "gpio_111", "gpio_112"; + power-source =3D <0>; + input-threshold-voltage-microvolt =3D <1800000>; + }; + + aio_vsel_3v3_pins: aio-vsel-3v3-pins { + pins =3D "gpio_98", "gpio_99", "gpio_100", "gpio_101", "gpio_102", "gpio= _103", + "gpio_104", "gpio_105", "gpio_106", "gpio_107", "gpio_108", "gpio= _109", + "gpio_110", "gpio_111", "gpio_112"; + power-source =3D <1>; + input-threshold-voltage-microvolt =3D <3300000>; + }; + + csi_vsel_1v8_pins: csi-vsel-1v8-pins { + pins =3D "csi_vdsel"; + function =3D "csi_1v8"; + }; + + csi_vsel_3v3_pins: csi-vsel-3v3-pins { + pins =3D "csi_vdsel"; + function =3D "csi_3v3"; + }; + + rgmii_vsel_1v8_pins: rgmii-vsel-1v8-pins { + pins =3D "rgmii_vdsel"; + function =3D "rgmii_1v8"; + }; + + rgmii_vsel_3v3_pins: rgmii-vsel-3v3-pins { + pins =3D "rgmii_vdsel"; + function =3D "rgmii_3v3"; + }; + + sdio_vsel_1v8_pins: sdio-vsel-1v8-pins { + pins =3D "gpio_45", "gpio_46", "gpio_47", "gpio_48", "gpio_49", "gpio_50= "; + power-source =3D <0>; + }; + + sdio_vsel_3v3_pins: sdio-vsel-3v3-pins { + pins =3D "gpio_45", "gpio_46", "gpio_47", "gpio_48", "gpio_49", "gpio_50= "; + power-source =3D <1>; + }; + + uart1_vsel_1v8_pins: uart1-vsel-1v8-pins { + pins =3D "gpio_8", "gpio_9", "gpio_10", "gpio_11"; + power-source =3D <0>; + input-threshold-voltage-microvolt =3D <1800000>; + }; + + uart1_vsel_3v3_pins: uart1-vsel-3v3-pins { + pins =3D "gpio_8", "gpio_9", "gpio_10", "gpio_11"; + power-source =3D <1>; + input-threshold-voltage-microvolt =3D <3300000>; + }; +}; + +&main2_pinctrl { + emmc_vsel_1v8_pins: emmc-vsel-1v8-pins { + pins =3D "emmc_rst_n", + "emmc_dd_sb", + "emmc_clk", + "emmc_cmd", + "emmc_data_0", + "emmc_data_1", + "emmc_data_2", + "emmc_data_3", + "emmc_data_4", + "emmc_data_5", + "emmc_data_6", + "emmc_data_7"; + power-source =3D <0>; + }; + + emmc_vsel_3v3_pins: emmc-vsel-3v3-pins { + pins =3D "emmc_rst_n", + "emmc_dd_sb", + "emmc_clk", + "emmc_cmd", + "emmc_data_0", + "emmc_data_1", + "emmc_data_2", + "emmc_data_3", + "emmc_data_4", + "emmc_data_5", + "emmc_data_6", + "emmc_data_7"; + power-source =3D <1>; + }; + + sd_vsel_1v8_pins: sd-vsel-1v8-pins { + pins =3D "gpio_40", "gpio_41", "hif_clk", "hif_data", "hif_en", "hif_rdy= "; + power-source =3D <0>; + }; + + sd_vsel_3v3_pins: sd-vsel-3v3-pins { + pins =3D "gpio_40", "gpio_41", "hif_clk", "hif_data", "hif_en", "hif_rdy= "; + power-source =3D <1>; + }; +}; diff --git a/arch/arm64/boot/dts/realtek/kent.dtsi b/arch/arm64/boot/dts/re= altek/kent.dtsi index 8d4293cd4c03..f18b975c3593 100644 --- a/arch/arm64/boot/dts/realtek/kent.dtsi +++ b/arch/arm64/boot/dts/realtek/kent.dtsi @@ -125,6 +125,32 @@ psci: psci { method =3D "smc"; }; =20 + io_level_detector: io-level-detector { + compatible =3D "realtek,rtd1625-io-detect"; + pinctrl-names =3D "rgmii_1v8", "rgmii_3v3", + "sdio_1v8", "sdio_3v3", + "csi_1v8", "csi_3v3", + "sd_1v8", "sd_3v3", + "uart1_1v8", "uart1_3v3", + "aio_1v8", "aio_3v3", + "emmc_1v8", "emmc_3v3"; + pinctrl-0 =3D <&rgmii_vsel_1v8_pins>; + pinctrl-1 =3D <&rgmii_vsel_3v3_pins>; + pinctrl-2 =3D <&sdio_vsel_1v8_pins>; + pinctrl-3 =3D <&sdio_vsel_3v3_pins>; + pinctrl-4 =3D <&csi_vsel_1v8_pins>; + pinctrl-5 =3D <&csi_vsel_3v3_pins>; + pinctrl-6 =3D <&sd_vsel_1v8_pins>; + pinctrl-7 =3D <&sd_vsel_3v3_pins>; + pinctrl-8 =3D <&uart1_vsel_1v8_pins>; + pinctrl-9 =3D <&uart1_vsel_3v3_pins>; + pinctrl-10 =3D <&aio_vsel_1v8_pins>; + pinctrl-11 =3D <&aio_vsel_3v3_pins>; + pinctrl-12 =3D <&emmc_vsel_1v8_pins>; + pinctrl-13 =3D <&emmc_vsel_3v3_pins>; + realtek,iso-pinctrl =3D <&iso_pinctrl>; + }; + soc@0 { compatible =3D "simple-bus"; ranges =3D <0x0 0x0 0x0 0x40000>, /* boot code */ @@ -184,3 +210,5 @@ gic: interrupt-controller@ff100000 { }; }; }; + +#include "kent-pinctrl.dtsi" --=20 2.43.0