From nobody Mon Jun 8 09:52:39 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BD1D0352C28; Thu, 4 Jun 2026 08:30:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780561821; cv=none; b=toCZ89kd6SpE+WmT95m5XFRyH9LaNDo42JXc3mHcMIPm6xpJbsnTmSRvnnwxK+0M/L8C2vh0asoJ6RzM3+dkTE0LZtzNbW6zgxtZVgtrsPKr64vgHL4QFwKEFKTjA/EKb75REa3gEDJMHxrJsL9OBdzEedrc9cXJR0QZ/TCY7OE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780561821; c=relaxed/simple; bh=EqUsJb5dmF8hJKkcZTRQyLGmvdg26mTAQ0mITdbTufg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PsfIyFKtMnQuN0pWrlhI3rRiM7o+MV0q5k3fzP33/ncPp4l7usJdzXR5jv6+Aj/dthxax7i+5r2tf1jRWkfa8JU6oI3dojWZB6cWoNOVL7sA/HFnMsognp5YDDBGT2lv4q4GVa2DWrcv6w+Eto4Gh9JOkOAPSu1zf4nsvs56X3g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=A5NPQlqq; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="A5NPQlqq" Received: by smtp.kernel.org (Postfix) with ESMTPS id 69E91C2BCC6; Thu, 4 Jun 2026 08:30:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1780561821; bh=EqUsJb5dmF8hJKkcZTRQyLGmvdg26mTAQ0mITdbTufg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=A5NPQlqqmtUoH8md30A7A3t4PqZPHYIliMi+XLiWx2E4Bhf7nttWDZxf477AY6Fyd 3IoJjK44SyhMeovFyRIioxvo1Ip264aHndt9mzDhP7xglI7p/p93PchHUaEFxmD7ph dZx1p3mnYgvNzJVo88Pz0kzp5jGnyHibR2fL2p1sfr79tq7cH228nZ8B+zIox3/V+l h3Os/wKbvplEIBj9O/l0kNdJjZxEehnaLbSg/csdmJ2iDPMtKMey/ND/YrP9989MTY 7auY64yK00CmYXWOQbUTaWqj9r+XFnQQB+Rw2o3C2j2fyd2M1UgbCV17woyR3rZNk8 3nABI9ZQ4gVmw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55411CD6E4A; Thu, 4 Jun 2026 08:30:21 +0000 (UTC) From: Cedric Jehasse via B4 Relay Date: Thu, 04 Jun 2026 10:30:14 +0200 Subject: [PATCH net-next 1/2] net: dsa: add support for dcb pcp app Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260604-net-next-mv88e6xxx-pcp-prio-v1-1-f9d10fe6cdc8@luminex.be> References: <20260604-net-next-mv88e6xxx-pcp-prio-v1-0-f9d10fe6cdc8@luminex.be> In-Reply-To: <20260604-net-next-mv88e6xxx-pcp-prio-v1-0-f9d10fe6cdc8@luminex.be> To: Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Russell King Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Luke Howard , Cedric Jehasse , Cedric Jehasse X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780561819; l=7081; i=cedric.jehasse@luminex.be; s=20260213; h=from:subject:message-id; bh=vAbt2oUZwh/Xl1VBsXEixbjizxp0CkUnxtZsJliOylM=; b=fRYhAMUUjGItSLgK1KBvFXTrF64mRPvaT/fHSgkT2XMW6s1snlpMsIo7J1q7Ion/DSLUt+pBH k2FIxzWGT9iASVhBQiI+cGU5+BGe5UlCvFmDY1GE0VdFzizo2cyskR+ X-Developer-Key: i=cedric.jehasse@luminex.be; a=ed25519; pk=DL2RaHc2bc7tTDTMJdugm42BtJk4Ip+7V41Gkj+Avjk= X-Endpoint-Received: by B4 Relay for cedric.jehasse@luminex.be/20260213 with auth_id=638 X-Original-From: Cedric Jehasse Reply-To: cedric.jehasse@luminex.be From: Cedric Jehasse Set/get of dscp-prio map is already supported by dsa. This adds support for set/get of pcp-prio map in a similar way. Signed-off-by: Cedric Jehasse --- include/net/dsa.h | 10 +++++ net/dsa/user.c | 126 ++++++++++++++++++++++++++++++++++++++++++++++++++= +--- 2 files changed, 129 insertions(+), 7 deletions(-) diff --git a/include/net/dsa.h b/include/net/dsa.h index 8b6d34e8a6f0..05428c555ccd 100644 --- a/include/net/dsa.h +++ b/include/net/dsa.h @@ -447,6 +447,11 @@ struct dsa_switch { */ u32 dscp_prio_mapping_is_global:1; =20 + /* Drivers that have global PCP mapping settings must set this to + * true to automatically apply the settings to all ports. + */ + u32 pcp_prio_mapping_is_global:1; + /* Listener for switch fabric events */ struct notifier_block nb; =20 @@ -970,6 +975,11 @@ struct dsa_switch_ops { u8 prio); int (*port_del_dscp_prio)(struct dsa_switch *ds, int port, u8 dscp, u8 prio); + int (*port_get_pcp_prio)(struct dsa_switch *ds, int port, u8 pcp); + int (*port_add_pcp_prio)(struct dsa_switch *ds, int port, u8 pcp, + u8 prio); + int (*port_del_pcp_prio)(struct dsa_switch *ds, int port, u8 pcp, + u8 prio); int (*port_set_apptrust)(struct dsa_switch *ds, int port, const u8 *sel, int nsel); int (*port_get_apptrust)(struct dsa_switch *ds, int port, u8 *sel, diff --git a/net/dsa/user.c b/net/dsa/user.c index c4bd6fe90b45..aa6d030968b9 100644 --- a/net/dsa/user.c +++ b/net/dsa/user.c @@ -2238,11 +2238,11 @@ dsa_user_dcbnl_set_default_prio(struct net_device *= dev, struct dcb_app *app) return 0; } =20 -/* Update the DSCP prio entries on all user ports of the switch in case - * the switch supports global DSCP prio instead of per port DSCP prios. +/* Update the APP entries on all user ports of the switch in case + * the switch supports global prio settings instead of per port prios. */ -static int dsa_user_dcbnl_ieee_global_dscp_setdel(struct net_device *dev, - struct dcb_app *app, bool del) +static int dsa_user_dcbnl_ieee_global_setdel(struct net_device *dev, + struct dcb_app *app, bool del) { int (*setdel)(struct net_device *dev, struct dcb_app *app); struct dsa_port *dp =3D dsa_user_to_port(dev); @@ -2284,7 +2284,7 @@ static int dsa_user_dcbnl_ieee_global_dscp_setdel(str= uct net_device *dev, =20 restore_err =3D setdel(user, app); if (restore_err) - netdev_err(user, "Failed to restore DSCP prio entry configuration\n"); + netdev_err(user, "Failed to restore APP entry configuration\n"); } =20 return err; @@ -2324,7 +2324,7 @@ dsa_user_dcbnl_add_dscp_prio(struct net_device *dev, = struct dcb_app *app) if (!ds->dscp_prio_mapping_is_global) return 0; =20 - err =3D dsa_user_dcbnl_ieee_global_dscp_setdel(dev, app, false); + err =3D dsa_user_dcbnl_ieee_global_setdel(dev, app, false); if (err) { if (ds->ops->port_del_dscp_prio) ds->ops->port_del_dscp_prio(ds, port, dscp, new_prio); @@ -2335,6 +2335,54 @@ dsa_user_dcbnl_add_dscp_prio(struct net_device *dev,= struct dcb_app *app) return 0; } =20 +static int __maybe_unused +dsa_user_dcbnl_add_pcp_prio(struct net_device *dev, struct dcb_app *app) +{ + struct dsa_port *dp =3D dsa_user_to_port(dev); + struct dsa_switch *ds =3D dp->ds; + unsigned long mask, new_prio; + int err, port =3D dp->index; + u8 pcp =3D app->protocol; + + if (!ds->ops->port_add_pcp_prio) + return -EOPNOTSUPP; + + if (app->priority >=3D IEEE_8021QAZ_MAX_TCS) + return -EINVAL; + + if (pcp >=3D 16) { + netdev_err(dev, "PCP APP entry with protocol value %u is invalid\n", + pcp); + return -EINVAL; + } + + err =3D dcb_ieee_setapp(dev, app); + if (err) + return err; + + mask =3D dcb_ieee_getapp_mask(dev, app); + new_prio =3D __fls(mask); + + err =3D ds->ops->port_add_pcp_prio(ds, port, pcp, new_prio); + if (err) { + dcb_ieee_delapp(dev, app); + return err; + } + + if (!ds->pcp_prio_mapping_is_global) + return 0; + + err =3D dsa_user_dcbnl_ieee_global_setdel(dev, app, false); + if (err) { + if (ds->ops->port_del_pcp_prio) + ds->ops->port_del_pcp_prio(ds, port, pcp, new_prio); + dcb_ieee_delapp(dev, app); + return err; + } + + return 0; +} + static int __maybe_unused dsa_user_dcbnl_ieee_setapp(struct net_device *de= v, struct dcb_app *app) { @@ -2349,6 +2397,8 @@ static int __maybe_unused dsa_user_dcbnl_ieee_setapp(= struct net_device *dev, break; case IEEE_8021QAZ_APP_SEL_DSCP: return dsa_user_dcbnl_add_dscp_prio(dev, app); + case DCB_APP_SEL_PCP: + return dsa_user_dcbnl_add_pcp_prio(dev, app); default: return -EOPNOTSUPP; } @@ -2405,7 +2455,7 @@ dsa_user_dcbnl_del_dscp_prio(struct net_device *dev, = struct dcb_app *app) if (!ds->dscp_prio_mapping_is_global) return 0; =20 - err =3D dsa_user_dcbnl_ieee_global_dscp_setdel(dev, app, true); + err =3D dsa_user_dcbnl_ieee_global_setdel(dev, app, true); if (err) { if (ds->ops->port_add_dscp_prio) ds->ops->port_add_dscp_prio(ds, port, dscp, @@ -2417,6 +2467,42 @@ dsa_user_dcbnl_del_dscp_prio(struct net_device *dev,= struct dcb_app *app) return 0; } =20 +static int __maybe_unused +dsa_user_dcbnl_del_pcp_prio(struct net_device *dev, struct dcb_app *app) +{ + struct dsa_port *dp =3D dsa_user_to_port(dev); + struct dsa_switch *ds =3D dp->ds; + int err, port =3D dp->index; + u8 pcp =3D app->protocol; + + if (!ds->ops->port_del_pcp_prio) + return -EOPNOTSUPP; + + err =3D dcb_ieee_delapp(dev, app); + if (err) + return err; + + err =3D ds->ops->port_del_pcp_prio(ds, port, pcp, app->priority); + if (err) { + dcb_ieee_setapp(dev, app); + return err; + } + + if (!ds->pcp_prio_mapping_is_global) + return 0; + + err =3D dsa_user_dcbnl_ieee_global_setdel(dev, app, true); + if (err) { + if (ds->ops->port_add_pcp_prio) + ds->ops->port_add_pcp_prio(ds, port, pcp, + app->priority); + dcb_ieee_setapp(dev, app); + return err; + } + + return 0; +} + static int __maybe_unused dsa_user_dcbnl_ieee_delapp(struct net_device *de= v, struct dcb_app *app) { @@ -2431,6 +2517,8 @@ static int __maybe_unused dsa_user_dcbnl_ieee_delapp(= struct net_device *dev, break; case IEEE_8021QAZ_APP_SEL_DSCP: return dsa_user_dcbnl_del_dscp_prio(dev, app); + case DCB_APP_SEL_PCP: + return dsa_user_dcbnl_del_pcp_prio(dev, app); default: return -EOPNOTSUPP; } @@ -2486,6 +2574,30 @@ static int dsa_user_dcbnl_init(struct net_device *de= v) } } =20 + if (ds->ops->port_get_pcp_prio) { + int protocol; + + for (protocol =3D 0; protocol < 16; protocol++) { + struct dcb_app app =3D { + .selector =3D DCB_APP_SEL_PCP, + .protocol =3D protocol, + }; + int prio; + + prio =3D ds->ops->port_get_pcp_prio(ds, port, protocol); + if (prio =3D=3D -EOPNOTSUPP) + continue; + if (prio < 0) + return prio; + + app.priority =3D prio; + + err =3D dcb_ieee_setapp(dev, &app); + if (err) + return err; + } + } + return 0; } =20 --=20 2.43.0 From nobody Mon Jun 8 09:52:39 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C889B39183E; Thu, 4 Jun 2026 08:30:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780561821; cv=none; b=OE7WWpGkM0xhBHgPEJyXbUvdNu8Qu2StPMpJvEK+GUixqv+kqzMNH4tn2xeRxuIYFShSlUN7Fw+Kw6ghouxsLOLoKD+XrX0QuolyGoEN6fUFMVOJwomwcC5gIUW4hWK+p+7PjqUpRM0goGapDyj6xewlENLtJzcpeW9pOJJAYrk= ARC-Message-Signature: i=1; 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b=ZPziAXRLanlMHArBfh1soX16QAK/KsVRqRALH29sGfMUmFdU/oqrZLGe/sl+pYy7s 3cJsU9bgz/7oaueAGrE7qWGL2WPn6vocrYcKKyRCoIjTEQ7Wu4sRwCtK7Pcr1y8pzj MynfxpxKOiRVSbsN0JnT2M7EnCIY3jmqi82WYlZyQ9YTFfrV7T54SFJ0rD8kxR2yFM sJ/VrPuX2SeGJZFC6rTAZ2KwJeGF7ExLsnqnnebjyHxMTWmLWFGpfkuCzX+fPxvucD tLonCwgD+WYoR0P/xpb33MtCVU+Dya+zvwe17gEozCMJMTEwFgAwspbI6NKlzYL8Ka TjwXICzdS50jQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66227CD6E6B; Thu, 4 Jun 2026 08:30:21 +0000 (UTC) From: Cedric Jehasse via B4 Relay Date: Thu, 04 Jun 2026 10:30:15 +0200 Subject: [PATCH net-next 2/2] net: dsa: mv88e6xxx: add support for dcb pcp app Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260604-net-next-mv88e6xxx-pcp-prio-v1-2-f9d10fe6cdc8@luminex.be> References: <20260604-net-next-mv88e6xxx-pcp-prio-v1-0-f9d10fe6cdc8@luminex.be> In-Reply-To: <20260604-net-next-mv88e6xxx-pcp-prio-v1-0-f9d10fe6cdc8@luminex.be> To: Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Russell King Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Luke Howard , Cedric Jehasse , Cedric Jehasse X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780561819; l=23190; i=cedric.jehasse@luminex.be; s=20260213; h=from:subject:message-id; bh=vbq/xR+1aOCJGVhsg0S57sI1gN3M56tEOWeAmq/+PXE=; b=WEZ6Ra5o/OBIiNAFfp2GHUVRQ2Ep4OTq2KnvwVW39N5ssn/h+O//g1EnV9OM00OKX1bCLipX7 sY66cle5IE2ABXkgt0iaN/iinD+qDPPIcrwLVv6uPJnbvTe8bg217WU X-Developer-Key: i=cedric.jehasse@luminex.be; a=ed25519; pk=DL2RaHc2bc7tTDTMJdugm42BtJk4Ip+7V41Gkj+Avjk= X-Endpoint-Received: by B4 Relay for cedric.jehasse@luminex.be/20260213 with auth_id=638 X-Original-From: Cedric Jehasse Reply-To: cedric.jehasse@luminex.be From: Cedric Jehasse Implement the DSA pcp_prio hooks to support the dcb pcp app. In the Marvell switches this is done by configuring the IEEE PRI Mapping table. There are different hardware implementations of this table depending on the switch: * a global table * the 6390 has one table per port * the 6393 has one table for DEI=3D0, and another table for DEI=3D1 per port Example command: dcb app replace dev p1 pcp-prio 7nd:3 Signed-off-by: Cedric Jehasse --- drivers/net/dsa/mv88e6xxx/Makefile | 1 + drivers/net/dsa/mv88e6xxx/chip.c | 36 ++++++ drivers/net/dsa/mv88e6xxx/chip.h | 17 +++ drivers/net/dsa/mv88e6xxx/dcb.c | 229 +++++++++++++++++++++++++++++++++= ++++ drivers/net/dsa/mv88e6xxx/dcb.h | 21 ++++ drivers/net/dsa/mv88e6xxx/port.c | 28 ++++- drivers/net/dsa/mv88e6xxx/port.h | 8 ++ 7 files changed, 338 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/mv88e6xxx/Makefile b/drivers/net/dsa/mv88e6xxx= /Makefile index b0b08c6f159c..6eb9be4d934a 100644 --- a/drivers/net/dsa/mv88e6xxx/Makefile +++ b/drivers/net/dsa/mv88e6xxx/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_NET_DSA_MV88E6XXX) +=3D mv88e6xxx.o mv88e6xxx-objs :=3D chip.o +mv88e6xxx-objs +=3D dcb.o mv88e6xxx-objs +=3D devlink.o mv88e6xxx-objs +=3D global1.o mv88e6xxx-objs +=3D global1_atu.o diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/c= hip.c index 5bbf5e69de9a..e12b84e42a93 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -35,6 +35,7 @@ #include =20 #include "chip.h" +#include "dcb.h" #include "devlink.h" #include "global1.h" #include "global2.h" @@ -4258,6 +4259,7 @@ static const struct mv88e6xxx_ops mv88e6085_ops =3D { .stu_loadpurge =3D mv88e6352_g1_stu_loadpurge, .phylink_get_caps =3D mv88e6185_phylink_get_caps, .set_max_frame_size =3D mv88e6185_g1_set_max_frame_size, + .dcb_ops =3D &mv88e6352_dcb_ops, }; =20 static const struct mv88e6xxx_ops mv88e6095_ops =3D { @@ -4290,6 +4292,7 @@ static const struct mv88e6xxx_ops mv88e6095_ops =3D { .phylink_get_caps =3D mv88e6095_phylink_get_caps, .pcs_ops =3D &mv88e6185_pcs_ops, .set_max_frame_size =3D mv88e6185_g1_set_max_frame_size, + .dcb_ops =3D &mv88e6352_dcb_ops, }; =20 static const struct mv88e6xxx_ops mv88e6097_ops =3D { @@ -4337,6 +4340,7 @@ static const struct mv88e6xxx_ops mv88e6097_ops =3D { .stu_getnext =3D mv88e6352_g1_stu_getnext, .stu_loadpurge =3D mv88e6352_g1_stu_loadpurge, .set_max_frame_size =3D mv88e6185_g1_set_max_frame_size, + .dcb_ops =3D &mv88e6352_dcb_ops, }; =20 static const struct mv88e6xxx_ops mv88e6123_ops =3D { @@ -4378,6 +4382,7 @@ static const struct mv88e6xxx_ops mv88e6123_ops =3D { .stu_loadpurge =3D mv88e6352_g1_stu_loadpurge, .phylink_get_caps =3D mv88e6185_phylink_get_caps, .set_max_frame_size =3D mv88e6185_g1_set_max_frame_size, + .dcb_ops =3D &mv88e6352_dcb_ops, }; =20 static const struct mv88e6xxx_ops mv88e6131_ops =3D { @@ -4418,6 +4423,7 @@ static const struct mv88e6xxx_ops mv88e6131_ops =3D { .vtu_getnext =3D mv88e6185_g1_vtu_getnext, .vtu_loadpurge =3D mv88e6185_g1_vtu_loadpurge, .phylink_get_caps =3D mv88e6185_phylink_get_caps, + .dcb_ops =3D &mv88e6352_dcb_ops, }; =20 static const struct mv88e6xxx_ops mv88e6141_ops =3D { @@ -4481,6 +4487,7 @@ static const struct mv88e6xxx_ops mv88e6141_ops =3D { .serdes_get_regs =3D mv88e6390_serdes_get_regs, .phylink_get_caps =3D mv88e6341_phylink_get_caps, .pcs_ops =3D &mv88e6390_pcs_ops, + .dcb_ops =3D &mv88e6352_dcb_ops, }; =20 static const struct mv88e6xxx_ops mv88e6161_ops =3D { @@ -4529,6 +4536,7 @@ static const struct mv88e6xxx_ops mv88e6161_ops =3D { .ptp_ops =3D &mv88e6165_ptp_ops, .phylink_get_caps =3D mv88e6185_phylink_get_caps, .set_max_frame_size =3D mv88e6185_g1_set_max_frame_size, + .dcb_ops =3D &mv88e6352_dcb_ops, }; =20 static const struct mv88e6xxx_ops mv88e6165_ops =3D { @@ -4566,6 +4574,7 @@ static const struct mv88e6xxx_ops mv88e6165_ops =3D { .avb_ops =3D &mv88e6165_avb_ops, .ptp_ops =3D &mv88e6165_ptp_ops, .phylink_get_caps =3D mv88e6185_phylink_get_caps, + .dcb_ops =3D &mv88e6352_dcb_ops, }; =20 static const struct mv88e6xxx_ops mv88e6171_ops =3D { @@ -4612,6 +4621,7 @@ static const struct mv88e6xxx_ops mv88e6171_ops =3D { .stu_getnext =3D mv88e6352_g1_stu_getnext, .stu_loadpurge =3D mv88e6352_g1_stu_loadpurge, .phylink_get_caps =3D mv88e6351_phylink_get_caps, + .dcb_ops =3D &mv88e6352_dcb_ops, }; =20 static const struct mv88e6xxx_ops mv88e6172_ops =3D { @@ -4669,6 +4679,7 @@ static const struct mv88e6xxx_ops mv88e6172_ops =3D { .gpio_ops =3D &mv88e6352_gpio_ops, .phylink_get_caps =3D mv88e6352_phylink_get_caps, .pcs_ops =3D &mv88e6352_pcs_ops, + .dcb_ops =3D &mv88e6352_dcb_ops, }; =20 static const struct mv88e6xxx_ops mv88e6175_ops =3D { @@ -4715,6 +4726,7 @@ static const struct mv88e6xxx_ops mv88e6175_ops =3D { .stu_getnext =3D mv88e6352_g1_stu_getnext, .stu_loadpurge =3D mv88e6352_g1_stu_loadpurge, .phylink_get_caps =3D mv88e6351_phylink_get_caps, + .dcb_ops =3D &mv88e6352_dcb_ops, }; =20 static const struct mv88e6xxx_ops mv88e6176_ops =3D { @@ -4773,6 +4785,7 @@ static const struct mv88e6xxx_ops mv88e6176_ops =3D { .gpio_ops =3D &mv88e6352_gpio_ops, .phylink_get_caps =3D mv88e6352_phylink_get_caps, .pcs_ops =3D &mv88e6352_pcs_ops, + .dcb_ops =3D &mv88e6352_dcb_ops, }; =20 static const struct mv88e6xxx_ops mv88e6185_ops =3D { @@ -4811,6 +4824,7 @@ static const struct mv88e6xxx_ops mv88e6185_ops =3D { .phylink_get_caps =3D mv88e6185_phylink_get_caps, .pcs_ops =3D &mv88e6185_pcs_ops, .set_max_frame_size =3D mv88e6185_g1_set_max_frame_size, + .dcb_ops =3D &mv88e6352_dcb_ops, }; =20 static const struct mv88e6xxx_ops mv88e6190_ops =3D { @@ -4830,6 +4844,7 @@ static const struct mv88e6xxx_ops mv88e6190_ops =3D { .port_set_speed_duplex =3D mv88e6390_port_set_speed_duplex, .port_max_speed_mode =3D mv88e6390_port_max_speed_mode, .port_tag_remap =3D mv88e6390_port_tag_remap, + .dcb_ops =3D &mv88e6390_dcb_ops, .port_set_policy =3D mv88e6352_port_set_policy, .port_set_frame_mode =3D mv88e6351_port_set_frame_mode, .port_set_ucast_flood =3D mv88e6352_port_set_ucast_flood, @@ -4931,6 +4946,7 @@ static const struct mv88e6xxx_ops mv88e6190x_ops =3D { .gpio_ops =3D &mv88e6352_gpio_ops, .phylink_get_caps =3D mv88e6390x_phylink_get_caps, .pcs_ops =3D &mv88e6390_pcs_ops, + .dcb_ops =3D &mv88e6390_dcb_ops, }; =20 static const struct mv88e6xxx_ops mv88e6191_ops =3D { @@ -4990,6 +5006,7 @@ static const struct mv88e6xxx_ops mv88e6191_ops =3D { .ptp_ops =3D &mv88e6352_ptp_ops, .phylink_get_caps =3D mv88e6390_phylink_get_caps, .pcs_ops =3D &mv88e6390_pcs_ops, + .dcb_ops =3D &mv88e6390_dcb_ops, }; =20 static const struct mv88e6xxx_ops mv88e6240_ops =3D { @@ -5051,6 +5068,7 @@ static const struct mv88e6xxx_ops mv88e6240_ops =3D { .ptp_ops =3D &mv88e6352_ptp_ops, .phylink_get_caps =3D mv88e6352_phylink_get_caps, .pcs_ops =3D &mv88e6352_pcs_ops, + .dcb_ops =3D &mv88e6352_dcb_ops, }; =20 static const struct mv88e6xxx_ops mv88e6250_ops =3D { @@ -5096,6 +5114,7 @@ static const struct mv88e6xxx_ops mv88e6250_ops =3D { .ptp_ops =3D &mv88e6352_ptp_ops, .phylink_get_caps =3D mv88e6250_phylink_get_caps, .set_max_frame_size =3D mv88e6185_g1_set_max_frame_size, + .dcb_ops =3D &mv88e6352_dcb_ops, }; =20 static const struct mv88e6xxx_ops mv88e6290_ops =3D { @@ -5158,6 +5177,7 @@ static const struct mv88e6xxx_ops mv88e6290_ops =3D { .phylink_get_caps =3D mv88e6390_phylink_get_caps, .pcs_ops =3D &mv88e6390_pcs_ops, .tcam_ops =3D &mv88e6390_tcam_ops, + .dcb_ops =3D &mv88e6390_dcb_ops, }; =20 static const struct mv88e6xxx_ops mv88e6320_ops =3D { @@ -5211,6 +5231,7 @@ static const struct mv88e6xxx_ops mv88e6320_ops =3D { .avb_ops =3D &mv88e6352_avb_ops, .ptp_ops =3D &mv88e6352_ptp_ops, .phylink_get_caps =3D mv88e632x_phylink_get_caps, + .dcb_ops =3D &mv88e6352_dcb_ops, }; =20 static const struct mv88e6xxx_ops mv88e6321_ops =3D { @@ -5263,6 +5284,7 @@ static const struct mv88e6xxx_ops mv88e6321_ops =3D { .avb_ops =3D &mv88e6352_avb_ops, .ptp_ops =3D &mv88e6352_ptp_ops, .phylink_get_caps =3D mv88e632x_phylink_get_caps, + .dcb_ops =3D &mv88e6352_dcb_ops, }; =20 static const struct mv88e6xxx_ops mv88e6341_ops =3D { @@ -5329,6 +5351,7 @@ static const struct mv88e6xxx_ops mv88e6341_ops =3D { .serdes_get_regs =3D mv88e6390_serdes_get_regs, .phylink_get_caps =3D mv88e6341_phylink_get_caps, .pcs_ops =3D &mv88e6390_pcs_ops, + .dcb_ops =3D &mv88e6352_dcb_ops, }; =20 static const struct mv88e6xxx_ops mv88e6350_ops =3D { @@ -5375,6 +5398,7 @@ static const struct mv88e6xxx_ops mv88e6350_ops =3D { .stu_getnext =3D mv88e6352_g1_stu_getnext, .stu_loadpurge =3D mv88e6352_g1_stu_loadpurge, .phylink_get_caps =3D mv88e6351_phylink_get_caps, + .dcb_ops =3D &mv88e6352_dcb_ops, }; =20 static const struct mv88e6xxx_ops mv88e6351_ops =3D { @@ -5423,6 +5447,7 @@ static const struct mv88e6xxx_ops mv88e6351_ops =3D { .avb_ops =3D &mv88e6352_avb_ops, .ptp_ops =3D &mv88e6352_ptp_ops, .phylink_get_caps =3D mv88e6351_phylink_get_caps, + .dcb_ops =3D &mv88e6352_dcb_ops, }; =20 static const struct mv88e6xxx_ops mv88e6352_ops =3D { @@ -5487,6 +5512,7 @@ static const struct mv88e6xxx_ops mv88e6352_ops =3D { .serdes_get_regs =3D mv88e6352_serdes_get_regs, .phylink_get_caps =3D mv88e6352_phylink_get_caps, .pcs_ops =3D &mv88e6352_pcs_ops, + .dcb_ops =3D &mv88e6352_dcb_ops, }; =20 static const struct mv88e6xxx_ops mv88e6390_ops =3D { @@ -5553,6 +5579,7 @@ static const struct mv88e6xxx_ops mv88e6390_ops =3D { .phylink_get_caps =3D mv88e6390_phylink_get_caps, .pcs_ops =3D &mv88e6390_pcs_ops, .tcam_ops =3D &mv88e6390_tcam_ops, + .dcb_ops =3D &mv88e6390_dcb_ops, }; =20 static const struct mv88e6xxx_ops mv88e6390x_ops =3D { @@ -5618,6 +5645,7 @@ static const struct mv88e6xxx_ops mv88e6390x_ops =3D { .ptp_ops =3D &mv88e6390_ptp_ops, .phylink_get_caps =3D mv88e6390x_phylink_get_caps, .pcs_ops =3D &mv88e6390_pcs_ops, + .dcb_ops =3D &mv88e6390_dcb_ops, }; =20 static const struct mv88e6xxx_ops mv88e6393x_ops =3D { @@ -5684,6 +5712,7 @@ static const struct mv88e6xxx_ops mv88e6393x_ops =3D { .phylink_get_caps =3D mv88e6393x_phylink_get_caps, .pcs_ops =3D &mv88e6393x_pcs_ops, .tcam_ops =3D &mv88e6393_tcam_ops, + .dcb_ops =3D &mv88e6393x_dcb_ops, }; =20 static const struct mv88e6xxx_qav_info mv88e6352_qav_info =3D { @@ -7385,6 +7414,9 @@ static const struct dsa_switch_ops mv88e6xxx_switch_o= ps =3D { .port_hwtstamp_get =3D mv88e6xxx_port_hwtstamp_get, .port_txtstamp =3D mv88e6xxx_port_txtstamp, .port_rxtstamp =3D mv88e6xxx_port_rxtstamp, + .port_get_pcp_prio =3D mv88e6xxx_port_get_pcp_prio, + .port_add_pcp_prio =3D mv88e6xxx_port_add_pcp_prio, + .port_del_pcp_prio =3D mv88e6xxx_port_del_pcp_prio, .port_setup_tc =3D mv88e6xxx_port_setup_tc, .cls_flower_add =3D mv88e6xxx_cls_flower_add, .cls_flower_del =3D mv88e6xxx_cls_flower_del, @@ -7402,6 +7434,7 @@ static const struct dsa_switch_ops mv88e6xxx_switch_o= ps =3D { =20 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) { + const struct mv88e6xxx_dcb_ops *dcb_ops =3D chip->info->ops->dcb_ops; struct device *dev =3D chip->dev; struct dsa_switch *ds; =20 @@ -7418,6 +7451,9 @@ static int mv88e6xxx_register_switch(struct mv88e6xxx= _chip *chip) ds->ageing_time_min =3D chip->info->age_time_coeff; ds->ageing_time_max =3D chip->info->age_time_coeff * U8_MAX; =20 + ds->pcp_prio_mapping_is_global =3D dcb_ops && + dcb_ops->global_get_pcp_prio; + /* Some chips support up to 32, but that requires enabling the * 5-bit port mode, which we do not support. 640k^W16 ought to * be enough for anyone. diff --git a/drivers/net/dsa/mv88e6xxx/chip.h b/drivers/net/dsa/mv88e6xxx/c= hip.h index e563cfe8ab2a..1aa77b643924 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.h +++ b/drivers/net/dsa/mv88e6xxx/chip.h @@ -211,6 +211,7 @@ struct mv88e6xxx_stu_entry { }; =20 struct mv88e6xxx_bus_ops; +struct mv88e6xxx_dcb_ops; struct mv88e6xxx_irq_ops; struct mv88e6xxx_gpio_ops; struct mv88e6xxx_avb_ops; @@ -728,6 +729,9 @@ struct mv88e6xxx_ops { =20 /* Ternary Content Addressable Memory operations */ const struct mv88e6xxx_tcam_ops *tcam_ops; + + /* Data Center Bridging operations */ + const struct mv88e6xxx_dcb_ops *dcb_ops; }; =20 struct mv88e6xxx_irq_ops { @@ -779,6 +783,19 @@ struct mv88e6xxx_avb_ops { u16 data); }; =20 +struct mv88e6xxx_dcb_ops { + /* Get/set the chip's global PCP to queue priority mapping */ + int (*global_get_pcp_prio)(struct mv88e6xxx_chip *chip, u8 pcp); + int (*global_set_pcp_prio)(struct mv88e6xxx_chip *chip, u8 pcp, + u8 prio); + + /* Get/set a port's PCP to queue priority mapping */ + int (*port_get_pcp_prio)(struct mv88e6xxx_chip *chip, int port, + u8 pcp); + int (*port_set_pcp_prio)(struct mv88e6xxx_chip *chip, int port, + u8 pcp, u8 prio); +}; + struct mv88e6xxx_ptp_ops { u64 (*clock_read)(struct cyclecounter *cc); int (*ptp_enable)(struct ptp_clock_info *ptp, diff --git a/drivers/net/dsa/mv88e6xxx/dcb.c b/drivers/net/dsa/mv88e6xxx/dc= b.c new file mode 100644 index 000000000000..0a3099cdf388 --- /dev/null +++ b/drivers/net/dsa/mv88e6xxx/dcb.c @@ -0,0 +1,229 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright (c) 2026 Luminex Network Intelligence + +#include "chip.h" +#include "dcb.h" +#include "global1.h" +#include "port.h" + +static int mv88e6352_get_pcp_prio(struct mv88e6xxx_chip *chip, u8 pcp) +{ + u16 val; + int err; + + /* These devices have no mapping table for frames with DEI bit set */ + if (pcp >=3D 8) + return -EOPNOTSUPP; + + err =3D mv88e6xxx_g1_read(chip, MV88E6XXX_G1_IEEE_PRI, &val); + if (err) + return err; + + return (val >> (pcp * 2)) & 3; +} + +static int mv88e6352_set_pcp_prio(struct mv88e6xxx_chip *chip, u8 pcp, u8 = prio) +{ + u16 val; + int err; + + /* These devices have no mapping table for frames with DEI bit set */ + if (pcp >=3D 8) + return -EOPNOTSUPP; + + if (prio >=3D 4) + return -EINVAL; + + err =3D mv88e6xxx_g1_read(chip, MV88E6XXX_G1_IEEE_PRI, &val); + if (err) + return err; + + val &=3D ~(3 << (pcp * 2)); + val |=3D prio << (pcp * 2); + + return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, val); +} + +static int mv88e639x_port_ieeepmt_pcp_entry(u8 pcp, bool has_dei, + u16 *table, u8 *ptr) +{ + if (pcp >=3D 16) + return -EINVAL; + + /* not all devices have a table for mapping with DEI bit set */ + if (pcp >=3D 8 && !has_dei) + return -EOPNOTSUPP; + + *table =3D pcp >=3D 8 ? + MV88E6393X_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP_DEI : + MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP; + *ptr =3D pcp & 7; + + return 0; +} + +static int mv88e639x_port_get_pcp_prio(struct mv88e6xxx_chip *chip, int po= rt, + u8 pcp, bool has_dei) +{ + u16 val, table; + u8 ptr; + int err; + + err =3D mv88e639x_port_ieeepmt_pcp_entry(pcp, has_dei, &table, &ptr); + if (err) + return err; + + err =3D mv88e6xxx_port_ieeepmt_read(chip, port, table, ptr, &val); + if (err) + return err; + + if (val & MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_QPRI_DIS) + return -EOPNOTSUPP; + + return (val & MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_QPRI_MASK) + >> MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_QPRI_SHIFT; +} + +static int mv88e639x_port_set_pcp_prio(struct mv88e6xxx_chip *chip, int po= rt, + u8 pcp, u8 prio, bool has_dei) +{ + u16 val, table; + u8 ptr; + int err; + + if (prio >=3D 8) + return -EINVAL; + + err =3D mv88e639x_port_ieeepmt_pcp_entry(pcp, has_dei, &table, &ptr); + if (err) + return err; + + err =3D mv88e6xxx_port_ieeepmt_read(chip, port, table, ptr, &val); + if (err) + return err; + + val &=3D ~MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_QPRI_DIS; + val &=3D ~MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_QPRI_MASK; + val |=3D (prio << MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_QPRI_SHIFT) & + MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_QPRI_MASK; + + return mv88e6xxx_port_ieeepmt_write(chip, port, table, ptr, val); +} + +static int mv88e6390_port_get_pcp_prio(struct mv88e6xxx_chip *chip, int po= rt, + u8 pcp) +{ + return mv88e639x_port_get_pcp_prio(chip, port, pcp, false); +} + +static int mv88e6390_port_set_pcp_prio(struct mv88e6xxx_chip *chip, int po= rt, + u8 pcp, u8 prio) +{ + return mv88e639x_port_set_pcp_prio(chip, port, pcp, prio, false); +} + +static int mv88e6393x_port_get_pcp_prio(struct mv88e6xxx_chip *chip, int p= ort, + u8 pcp) +{ + return mv88e639x_port_get_pcp_prio(chip, port, pcp, true); +} + +static int mv88e6393x_port_set_pcp_prio(struct mv88e6xxx_chip *chip, int p= ort, + u8 pcp, u8 prio) +{ + return mv88e639x_port_set_pcp_prio(chip, port, pcp, prio, true); +} + +const struct mv88e6xxx_dcb_ops mv88e6352_dcb_ops =3D { + .global_get_pcp_prio =3D mv88e6352_get_pcp_prio, + .global_set_pcp_prio =3D mv88e6352_set_pcp_prio, +}; + +const struct mv88e6xxx_dcb_ops mv88e6390_dcb_ops =3D { + .port_get_pcp_prio =3D mv88e6390_port_get_pcp_prio, + .port_set_pcp_prio =3D mv88e6390_port_set_pcp_prio, +}; + +const struct mv88e6xxx_dcb_ops mv88e6393x_dcb_ops =3D { + .port_get_pcp_prio =3D mv88e6393x_port_get_pcp_prio, + .port_set_pcp_prio =3D mv88e6393x_port_set_pcp_prio, +}; + +static int mv88e6xxx_dcb_get_pcp_prio(struct mv88e6xxx_chip *chip, int por= t, + u8 pcp) +{ + const struct mv88e6xxx_dcb_ops *dcb_ops =3D chip->info->ops->dcb_ops; + + if (!dcb_ops) + return -EOPNOTSUPP; + + if (dcb_ops->port_get_pcp_prio) + return dcb_ops->port_get_pcp_prio(chip, port, pcp); + + if (dcb_ops->global_get_pcp_prio) + return dcb_ops->global_get_pcp_prio(chip, pcp); + + return -EOPNOTSUPP; +} + +static int mv88e6xxx_dcb_set_pcp_prio(struct mv88e6xxx_chip *chip, int por= t, + u8 pcp, u8 prio) +{ + const struct mv88e6xxx_dcb_ops *dcb_ops =3D chip->info->ops->dcb_ops; + + if (!dcb_ops) + return -EOPNOTSUPP; + + if (dcb_ops->port_set_pcp_prio) + return dcb_ops->port_set_pcp_prio(chip, port, pcp, prio); + + if (dcb_ops->global_set_pcp_prio) + return dcb_ops->global_set_pcp_prio(chip, pcp, prio); + + return -EOPNOTSUPP; +} + +int mv88e6xxx_port_get_pcp_prio(struct dsa_switch *ds, int port, u8 pcp) +{ + struct mv88e6xxx_chip *chip =3D ds->priv; + int err; + + mv88e6xxx_reg_lock(chip); + err =3D mv88e6xxx_dcb_get_pcp_prio(chip, port, pcp); + mv88e6xxx_reg_unlock(chip); + + return err; +} + +int mv88e6xxx_port_add_pcp_prio(struct dsa_switch *ds, int port, u8 pcp, + u8 prio) +{ + struct mv88e6xxx_chip *chip =3D ds->priv; + int err; + + if (prio >=3D 8) + return -EINVAL; + + mv88e6xxx_reg_lock(chip); + err =3D mv88e6xxx_dcb_set_pcp_prio(chip, port, pcp, prio); + mv88e6xxx_reg_unlock(chip); + + return err; +} + +int mv88e6xxx_port_del_pcp_prio(struct dsa_switch *ds, int port, u8 pcp, + u8 prio) +{ + struct mv88e6xxx_chip *chip =3D ds->priv; + int err =3D 0; + + mv88e6xxx_reg_lock(chip); + if (mv88e6xxx_dcb_get_pcp_prio(chip, port, pcp) !=3D prio) + goto unlock; + + err =3D mv88e6xxx_dcb_set_pcp_prio(chip, port, pcp, 0); + +unlock: + mv88e6xxx_reg_unlock(chip); + return err; +} diff --git a/drivers/net/dsa/mv88e6xxx/dcb.h b/drivers/net/dsa/mv88e6xxx/dc= b.h new file mode 100644 index 000000000000..7a2124ec23ba --- /dev/null +++ b/drivers/net/dsa/mv88e6xxx/dcb.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + * + * Marvell 88E6xxx Switch DCB support + */ + +#ifndef _MV88E6XXX_DCB_H_ +#define _MV88E6XXX_DCB_H_ + +#include "chip.h" + +extern const struct mv88e6xxx_dcb_ops mv88e6352_dcb_ops; +extern const struct mv88e6xxx_dcb_ops mv88e6390_dcb_ops; +extern const struct mv88e6xxx_dcb_ops mv88e6393x_dcb_ops; + +int mv88e6xxx_port_get_pcp_prio(struct dsa_switch *ds, int port, u8 pcp); +int mv88e6xxx_port_add_pcp_prio(struct dsa_switch *ds, int port, u8 pcp, + u8 prio); +int mv88e6xxx_port_del_pcp_prio(struct dsa_switch *ds, int port, u8 pcp, + u8 prio); + +#endif /* _MV88E6XXX_DCB_H_ */ diff --git a/drivers/net/dsa/mv88e6xxx/port.c b/drivers/net/dsa/mv88e6xxx/p= ort.c index 23d1435db0d8..a8e2f8910b0a 100644 --- a/drivers/net/dsa/mv88e6xxx/port.c +++ b/drivers/net/dsa/mv88e6xxx/port.c @@ -1641,8 +1641,8 @@ int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *c= hip, int port) 0x7654); } =20 -static int mv88e6xxx_port_ieeepmt_write(struct mv88e6xxx_chip *chip, - int port, u16 table, u8 ptr, u16 data) +int mv88e6xxx_port_ieeepmt_write(struct mv88e6xxx_chip *chip, + int port, u16 table, u8 ptr, u16 data) { u16 reg; =20 @@ -1654,6 +1654,30 @@ static int mv88e6xxx_port_ieeepmt_write(struct mv88e= 6xxx_chip *chip, MV88E6390_PORT_IEEE_PRIO_MAP_TABLE, reg); } =20 +int mv88e6xxx_port_ieeepmt_read(struct mv88e6xxx_chip *chip, int port, + u16 table, u8 ptr, u16 *data) +{ + u16 reg; + int err; + + reg =3D table | + (ptr << __bf_shf(MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK)); + + err =3D mv88e6xxx_port_write(chip, port, + MV88E6390_PORT_IEEE_PRIO_MAP_TABLE, reg); + if (err) + return err; + + err =3D mv88e6xxx_port_read(chip, port, + MV88E6390_PORT_IEEE_PRIO_MAP_TABLE, ®); + if (err) + return err; + + *data =3D reg & MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK; + + return 0; +} + int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port) { int err, i; diff --git a/drivers/net/dsa/mv88e6xxx/port.h b/drivers/net/dsa/mv88e6xxx/p= ort.h index cf8655a13729..8bf0f3cbc4f0 100644 --- a/drivers/net/dsa/mv88e6xxx/port.h +++ b/drivers/net/dsa/mv88e6xxx/port.h @@ -457,11 +457,15 @@ #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP 0x1000 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP 0x2000 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP 0x3000 +#define MV88E6393X_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP_DEI 0x4000 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_DSCP 0x5000 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_DSCP 0x6000 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_DSCP 0x7000 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK 0x0e00 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK 0x01ff +#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_QPRI_DIS 0x0080 +#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_QPRI_MASK 0x0070 +#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_QPRI_SHIFT 4 =20 /* Offset 0x18: Port IEEE Priority Remapping Registers (0-3) */ #define MV88E6095_PORT_IEEE_PRIO_REMAP_0123 0x18 @@ -543,6 +547,10 @@ int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chi= p *chip, int port, u16 mode); int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port); int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port); +int mv88e6xxx_port_ieeepmt_write(struct mv88e6xxx_chip *chip, + int port, u16 table, u8 ptr, u16 data); +int mv88e6xxx_port_ieeepmt_read(struct mv88e6xxx_chip *chip, int port, + u16 table, u8 ptr, u16 *data); int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port, enum mv88e6xxx_egress_mode mode); int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, --=20 2.43.0