From nobody Mon Jun 8 08:30:33 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE4B73B637A; Thu, 4 Jun 2026 16:32:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780590780; cv=none; b=NiMAevvZy+Syuxy3KH8+j7fOhsGdacEY8bi+NpxqwH/C5qczzoduU7ayY0jcbLy+SuY7qy7lnbzHltdK+OjJHxaQwPgVcS8dryNel3W+bY7gpNfyLveqEBWzRJNmv1a0DA4j5SRFMgG/CVALG01yGvytyY/ZmYSMjuUY/itixUs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780590780; c=relaxed/simple; bh=/zxFcHp7S+pr6AnpRORp7rcfTIUVkf+kF2bJgK6VsRg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=oiS+UtJyQ76HUMGdEGP41EFyubOpcJFr1OC48B1XU5al2DpEmaWWQeuO01Q01w+outxDPV5bd+SNwBs6Qu+R7cQVcEyQre+R+tWyGngjj6cjC9FkEGRFuMKKqtrZVUTRkxRHGj3vIl1d3GQRh173EtxCrPsKNBny4Bup1k/FMvo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=brGPxMlK; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="brGPxMlK" Received: by smtp.kernel.org (Postfix) with ESMTPS id A666FC2BCC7; Thu, 4 Jun 2026 16:32:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1780590779; bh=/zxFcHp7S+pr6AnpRORp7rcfTIUVkf+kF2bJgK6VsRg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=brGPxMlKMQ/U/yL44iapFw7/Q/7ZXNg4jwbLtIdNK9SmIpFNcAPrdKYLjVatP98ei /u7CAbuSHr+tjH55uEv/zzOFBMSe1qhE1eaD8LRA7hVrrKvplW2RTvyDViisDoUSMI +iihybiipzNolMRM4ppdPHy+/6h5d27gmdUjnHwr35zzpJ8R4JT5iSKnDQwVVS5qQx qvC6xNZVSSCWYL2EmqOY8xCdHATiL6UxVYBvqJ7Vh1pZvo11UwlHLhzDKVMFnR3rgV Imo8UfYnOlciAka9Yv8pHNYYH/0pweS29aN9n3rpsBBDxcgExS57ImoZRa/D7X8zsi zzuSdHQj5C9Gw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B7C6CD6E77; Thu, 4 Jun 2026 16:32:59 +0000 (UTC) From: Ciprian Regus via B4 Relay Date: Thu, 04 Jun 2026 19:32:46 +0300 Subject: [PATCH net-next v3 01/13] dt-bindings: net: Add ADIN1140 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260604-adin1140-driver-v3-1-5debdb3173c4@analog.com> References: <20260604-adin1140-driver-v3-0-5debdb3173c4@analog.com> In-Reply-To: <20260604-adin1140-driver-v3-0-5debdb3173c4@analog.com> To: Parthiban Veerasooran , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Jonathan Corbet , Shuah Khan , Andrew Lunn , Heiner Kallweit , Russell King , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, devicetree@vger.kernel.org, Ciprian Regus X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780590774; l=3033; i=ciprian.regus@analog.com; s=20260330; h=from:subject:message-id; bh=SD0s7kL32zflcmzvhYpP4wswiaVrrA6tg9sWjWntb8Q=; b=z38lZROWZ8zoI1AIs66jVBqr6GbNaNYX226IDC0RneKOM2jFm53b0jOekbp2eH7xKxuQg3+OP qJ1piLfRjJ5CEU2G+9suuJSxcwuXJbs28i70wH3LtX+z3cl4OTxbxSd X-Developer-Key: i=ciprian.regus@analog.com; a=ed25519; pk=8WoNhI0kQcQUl8YqJO5ZevROYk9HP8lOIeIgIYgjfbc= X-Endpoint-Received: by B4 Relay for ciprian.regus@analog.com/20260330 with auth_id=703 X-Original-From: Ciprian Regus Reply-To: ciprian.regus@analog.com From: Ciprian Regus The ADIN1140 is a single port 10BASE-T1S Ethernet controller that includes both the MAC and a PHY in the same package. Signed-off-by: Ciprian Regus Reviewed-by: Conor Dooley --- v3 changelog: - set adi,ad3306 as a fallback compatible. v2 changelog: - Reorder the compatible entries in the dt schema (ad3306, adin1140). - Removed "dt-bindings" from the commit title and message. - Updated the DT example to use IRQ_TYPE_LEVEL_LOW instead of IRQ_TYPE_EDGE_FALLING for the interrupt trigger condition. - "implements" -> "tries to implement" in the description. - Removed the MAINTAINERS entry, as it will be added in a later patch in the series. - Reordered as the first patch of the series --- .../devicetree/bindings/net/adi,adin1140.yaml | 71 ++++++++++++++++++= ++++ 1 file changed, 71 insertions(+) diff --git a/Documentation/devicetree/bindings/net/adi,adin1140.yaml b/Docu= mentation/devicetree/bindings/net/adi,adin1140.yaml new file mode 100644 index 000000000000..739429c46253 --- /dev/null +++ b/Documentation/devicetree/bindings/net/adi,adin1140.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/adi,adin1140.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ADI ADIN1140 10BASE-T1S MAC-PHY + +maintainers: + - Ciprian Regus + +description: | + The ADIN1140 (also called AD3306) is a low power single port + 10BASE-T1S MAC-PHY. It integrates an Ethernet PHY with a MAC + and all the associated analog circuitry. + The device tries to implement the Open Alliance TC6 10BASE-T1x MAC-PHY + Serial Interface specification and is compliant with the + IEEE 802.3cg-2019 Ethernet standard for 10 Mbps single pair + Ethernet (SPE). The device has a 4-wire SPI interface for + communication between the MAC and host processor. + +allOf: + - $ref: /schemas/net/ethernet-controller.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + oneOf: + - items: + - const: adi,adin1140 + - const: adi,ad3306 + - const: adi,ad3306 + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 25000000 + + interrupts: + maxItems: 1 + description: Interrupt from the MAC-PHY for receive data available + and error conditions + +required: + - compatible + - reg + - interrupts + - spi-max-frequency + +unevaluatedProperties: false + +examples: + - | + #include + + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethernet@0 { + compatible =3D "adi,ad3306"; + reg =3D <0>; + spi-max-frequency =3D <23000000>; + + interrupt-parent =3D <&gpio>; + interrupts =3D <6 IRQ_TYPE_LEVEL_LOW>; + + local-mac-address =3D [ 00 11 22 33 44 55 ]; + }; + }; --=20 2.43.0 From nobody Mon Jun 8 08:30:33 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE40C3B6378; Thu, 4 Jun 2026 16:32:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780590780; cv=none; b=HB5RWkNqRO8JjqGLU3PDun/lIP7f+am2N7uLZhwhZ8k353BtZq6DoPLLoURBNd2bkC0wwMe7hkWVloZxyjVytvOtm4BZYJaW9Om8ok6yCdrBzebMhnn1ykIg5pCJ2KkciJJyqYyUTN47bTKjsBqBVA7fZmbywzUK1y0zKjos3rc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780590780; c=relaxed/simple; bh=P5Hsx7iN0ZJKNJxpu5gDXOiGz3XDeMfxO2eh0HfCy5c=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=h2iMVpq9p5DPyCRi0j0VRwn3NQPudCrUbp4zU0MPpUiRPq0NWWWuMS22IOhFgEmp8hFbtmpn7afC6oNMvOuojo7cpbl5ZnAyZoAMHlVNoQJSTd8tfeFzXRctuc6JE8IGTFaKxGDibCm1DMv+vCv2P2ACpxo7RIfeEiOtUFvKYhI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=hXeXweZy; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="hXeXweZy" Received: by smtp.kernel.org (Postfix) with ESMTPS id ACA83C2BCC9; Thu, 4 Jun 2026 16:32:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1780590779; bh=P5Hsx7iN0ZJKNJxpu5gDXOiGz3XDeMfxO2eh0HfCy5c=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=hXeXweZyhUc/Sm3U6dhe40X9LZEZDncDPgcDBqmNoHiPPT43AmtJXk0L5nuOSWvJT KjOL55X3gPvq9lA2eOpL0DLZTJeOJ5jVeuOnDm1oXEtQKTdwVZcY2fEcfSZE79jyOy ekAAQD8oAnXH1W0JAZJFLB+TrVPAiVOE3Q9lr5qiwmDGjBpKDvwwUFgOHRYpVmflla mZyurr6dGV1ukzrUAmyLGliVjym3a2iTY8/lLwMAYgSPaNVYjsaKJhvUzzbHW3S+AN joSYSwdsi852F1Wey3VOqsX6ChQRI8smwO8R/J7jkSPt38IxETEtMMIT/2Xo5w1NnO b4hoktALLbv+w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A0E3CD6E6D; Thu, 4 Jun 2026 16:32:59 +0000 (UTC) From: Ciprian Regus via B4 Relay Date: Thu, 04 Jun 2026 19:32:47 +0300 Subject: [PATCH net-next v3 02/13] net: ethernet: oa_tc6: Handle the OA TC6 SPI protected mode Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260604-adin1140-driver-v3-2-5debdb3173c4@analog.com> References: <20260604-adin1140-driver-v3-0-5debdb3173c4@analog.com> In-Reply-To: <20260604-adin1140-driver-v3-0-5debdb3173c4@analog.com> To: Parthiban Veerasooran , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Jonathan Corbet , Shuah Khan , Andrew Lunn , Heiner Kallweit , Russell King , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, devicetree@vger.kernel.org, Ciprian Regus X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780590774; l=8747; i=ciprian.regus@analog.com; s=20260330; h=from:subject:message-id; bh=kCAt/vN4HNMmjc4uXW4s9mQuZMv1tQf5HRwsq0UZfgo=; b=c83fcA99zMMCgalnGg9yYetaSn8pW4BYSuOl5FhWKknWRD+nXwrwpw0/Cf+XOJJ+0AOW7QGKi a6PCnSdwRZ4AHqDdGzjOKRRbCoLJ/WLcMR148HtDGGsBbXUB45fVKGA X-Developer-Key: i=ciprian.regus@analog.com; a=ed25519; pk=8WoNhI0kQcQUl8YqJO5ZevROYk9HP8lOIeIgIYgjfbc= X-Endpoint-Received: by B4 Relay for ciprian.regus@analog.com/20260330 with auth_id=703 X-Original-From: Ciprian Regus Reply-To: ciprian.regus@analog.com From: Ciprian Regus Implement the OA TC6 standard defined protected mode for control (register access) transactions. In addition to the current register access formats the oa_tc6 driver handles, 1's complement values of the data field are included (by both the host and the MACPHY) in the SPI transfer frames. This feature acts as an integrity check. Control write transactions look like this: |<- 32 bits ->|<--- data_size --->|<- 32 bits ->| MOSI: | ctrl header | reg write data | ignored | MISO: | (discard) | echoed ctrl hdr | echoed data | data_size (LEN =3D number of registers to read in a sequence): Unprotected: 32 x (LEN + 1) bits Protected: 2 x 32 x (LEN + 1) bits Control read transaction: |<- 32 bits ->|<--- 32 bits --> |<- data_size ->| MOSI: | ctrl header | ignored ... | MISO: | (discard) | echoed ctrl hdr | reg read data | data_size (LEN =3D number of registers to read in a sequence): Unprotected: 32 x (LEN + 1) bits Protected: 2 x 32 x (LEN + 1) bits Register data format ("reg write data" and "reg read data"): Unprotected: | W1 (normal) | W2 (normal) | ... | Wx (normal) | Protected: | W1 (normal) | W1 (complement) | ... | Wx (normal) | Wx (complement)| The protected mode state can be read from the bit 5 of CONFIG0 (0x4) register, and this setting is usually only configured during the MACPHY's reset (depending on the device it can be done by setting the state of a pin). We can read the protected mode configuration before any other register access and since the SPI transfer is initially sized for an unprotected read, the MACPHY's complement words are never clocked out and no checking is required. The data transactions (Ethernet frames) remain unchanged. Signed-off-by: Ciprian Regus --- v3 changelog: - no change v2 changelog: - Updated OA_TC6_CTRL_SPI_BUF_SIZE to always alloc the control transaction buffer size required by the protected mode, instead of calling krealloc if the PROTE bit is set. - Formatting to fit the 80 character column limit. --- drivers/net/ethernet/oa_tc6.c | 93 +++++++++++++++++++++++++++++++++++----= ---- 1 file changed, 76 insertions(+), 17 deletions(-) diff --git a/drivers/net/ethernet/oa_tc6.c b/drivers/net/ethernet/oa_tc6.c index 91a906a7918a..baba5aad84df 100644 --- a/drivers/net/ethernet/oa_tc6.c +++ b/drivers/net/ethernet/oa_tc6.c @@ -24,6 +24,7 @@ #define OA_TC6_REG_CONFIG0 0x0004 #define CONFIG0_SYNC BIT(15) #define CONFIG0_ZARFE_ENABLE BIT(12) +#define CONFIG0_PROTE BIT(5) =20 /* Status Register #0 */ #define OA_TC6_REG_STATUS0 0x0008 @@ -87,14 +88,17 @@ #define OA_TC6_PHY_C45_AUTO_NEG_MMS5 5 /* MMD 7 */ #define OA_TC6_PHY_C45_POWER_UNIT_MMS6 6 /* MMD 13 */ =20 +#define OA_TC6_CTRL_PROT_REPLY_SIZE 4 #define OA_TC6_CTRL_HEADER_SIZE 4 #define OA_TC6_CTRL_REG_VALUE_SIZE 4 #define OA_TC6_CTRL_IGNORED_SIZE 4 #define OA_TC6_CTRL_MAX_REGISTERS 128 -#define OA_TC6_CTRL_SPI_BUF_SIZE (OA_TC6_CTRL_HEADER_SIZE +\ - (OA_TC6_CTRL_MAX_REGISTERS *\ - OA_TC6_CTRL_REG_VALUE_SIZE) +\ - OA_TC6_CTRL_IGNORED_SIZE) +#define OA_TC6_CTRL_SPI_BUF_SIZE (OA_TC6_CTRL_HEADER_SIZE +\ + (OA_TC6_CTRL_MAX_REGISTERS *\ + (OA_TC6_CTRL_REG_VALUE_SIZE +\ + OA_TC6_CTRL_PROT_REPLY_SIZE)) +\ + OA_TC6_CTRL_IGNORED_SIZE) + #define OA_TC6_CHUNK_PAYLOAD_SIZE 64 #define OA_TC6_DATA_HEADER_SIZE 4 #define OA_TC6_CHUNK_SIZE (OA_TC6_DATA_HEADER_SIZE +\ @@ -129,6 +133,7 @@ struct oa_tc6 { u8 rx_chunks_available; bool rx_buf_overflow; bool int_flag; + bool prot_ctrl; }; =20 enum oa_tc6_header_type { @@ -212,25 +217,36 @@ static void oa_tc6_update_ctrl_write_data(struct oa_t= c6 *tc6, u32 value[], { __be32 *tx_buf =3D tc6->spi_ctrl_tx_buf + OA_TC6_CTRL_HEADER_SIZE; =20 - for (int i =3D 0; i < length; i++) + for (int i =3D 0; i < length; i++) { *tx_buf++ =3D cpu_to_be32(value[i]); + if (tc6->prot_ctrl) + *tx_buf++ =3D cpu_to_be32(~value[i]); + } } =20 -static u16 oa_tc6_calculate_ctrl_buf_size(u8 length) +static u16 oa_tc6_calculate_ctrl_buf_size(u8 length, bool ctrl_prot) { + u32 reply_size =3D OA_TC6_CTRL_REG_VALUE_SIZE; + + if (ctrl_prot) + reply_size +=3D OA_TC6_CTRL_PROT_REPLY_SIZE; + /* Control command consists 4 bytes header + 4 bytes register value for - * each register + 4 bytes ignored value. + * each register (+ 4 bytes for the register value complement in case + * protected mode is used) + 4 bytes ignored value. */ - return OA_TC6_CTRL_HEADER_SIZE + OA_TC6_CTRL_REG_VALUE_SIZE * length + + return OA_TC6_CTRL_HEADER_SIZE + reply_size * length + OA_TC6_CTRL_IGNORED_SIZE; } =20 static void oa_tc6_prepare_ctrl_spi_buf(struct oa_tc6 *tc6, u32 address, u32 value[], u8 length, - enum oa_tc6_register_op reg_op) + enum oa_tc6_register_op reg_op, + u16 buf_size) { __be32 *tx_buf =3D tc6->spi_ctrl_tx_buf; =20 + memset(tx_buf, 0, buf_size); *tx_buf =3D oa_tc6_prepare_ctrl_header(address, length, reg_op); =20 if (reg_op =3D=3D OA_TC6_CTRL_REG_WRITE) @@ -253,10 +269,12 @@ static int oa_tc6_check_ctrl_write_reply(struct oa_tc= 6 *tc6, u8 size) return 0; } =20 -static int oa_tc6_check_ctrl_read_reply(struct oa_tc6 *tc6, u8 size) +static int oa_tc6_check_ctrl_read_reply(struct oa_tc6 *tc6, u8 length) { - u32 *rx_buf =3D tc6->spi_ctrl_rx_buf + OA_TC6_CTRL_IGNORED_SIZE; - u32 *tx_buf =3D tc6->spi_ctrl_tx_buf; + __be32 *rx_buf =3D tc6->spi_ctrl_rx_buf + OA_TC6_CTRL_IGNORED_SIZE; + __be32 *tx_buf =3D tc6->spi_ctrl_tx_buf; + u32 complement; + u32 reply; =20 /* The echoed control read header must match with the one that was * transmitted. @@ -264,6 +282,20 @@ static int oa_tc6_check_ctrl_read_reply(struct oa_tc6 = *tc6, u8 size) if (*tx_buf !=3D *rx_buf) return -EPROTO; =20 + if (tc6->prot_ctrl) { + /* Skip past the echoed header to the value/complement pairs */ + rx_buf +=3D 1; + for (int i =3D 0; i < length; i++) { + reply =3D be32_to_cpu(rx_buf[0]); + complement =3D be32_to_cpu(rx_buf[1]); + + if (complement !=3D ~reply) + return -EPROTO; + + rx_buf +=3D 2; + } + } + return 0; } =20 @@ -273,8 +305,13 @@ static void oa_tc6_copy_ctrl_read_data(struct oa_tc6 *= tc6, u32 value[], __be32 *rx_buf =3D tc6->spi_ctrl_rx_buf + OA_TC6_CTRL_IGNORED_SIZE + OA_TC6_CTRL_HEADER_SIZE; =20 - for (int i =3D 0; i < length; i++) + for (int i =3D 0; i < length; i++) { value[i] =3D be32_to_cpu(*rx_buf++); + + /* skip complement word */ + if (tc6->prot_ctrl) + rx_buf++; + } } =20 static int oa_tc6_perform_ctrl(struct oa_tc6 *tc6, u32 address, u32 value[= ], @@ -283,10 +320,10 @@ static int oa_tc6_perform_ctrl(struct oa_tc6 *tc6, u3= 2 address, u32 value[], u16 size; int ret; =20 - /* Prepare control command and copy to SPI control buffer */ - oa_tc6_prepare_ctrl_spi_buf(tc6, address, value, length, reg_op); + size =3D oa_tc6_calculate_ctrl_buf_size(length, tc6->prot_ctrl); =20 - size =3D oa_tc6_calculate_ctrl_buf_size(length); + /* Prepare control command and copy to SPI control buffer */ + oa_tc6_prepare_ctrl_spi_buf(tc6, address, value, length, reg_op, size); =20 /* Perform SPI transfer */ ret =3D oa_tc6_spi_transfer(tc6, OA_TC6_CTRL_HEADER, size); @@ -301,7 +338,7 @@ static int oa_tc6_perform_ctrl(struct oa_tc6 *tc6, u32 = address, u32 value[], return oa_tc6_check_ctrl_write_reply(tc6, size); =20 /* Check echoed/received control read command reply for errors */ - ret =3D oa_tc6_check_ctrl_read_reply(tc6, size); + ret =3D oa_tc6_check_ctrl_read_reply(tc6, length); if (ret) return ret; =20 @@ -1224,6 +1261,20 @@ netdev_tx_t oa_tc6_start_xmit(struct oa_tc6 *tc6, st= ruct sk_buff *skb) } EXPORT_SYMBOL_GPL(oa_tc6_start_xmit); =20 +static int oa_tc6_check_ctrl_protection(struct oa_tc6 *tc6) +{ + u32 regval; + int ret; + + ret =3D oa_tc6_read_register(tc6, OA_TC6_REG_CONFIG0, ®val); + if (ret) + return ret; + + tc6->prot_ctrl =3D FIELD_GET(CONFIG0_PROTE, regval); + + return 0; +} + /** * oa_tc6_init - allocates and initializes oa_tc6 structure. * @spi: device with which data will be exchanged. @@ -1276,6 +1327,14 @@ struct oa_tc6 *oa_tc6_init(struct spi_device *spi, s= truct net_device *netdev) if (!tc6->spi_data_rx_buf) return NULL; =20 + /* Check the PROTE bit status so that we can reset the device */ + ret =3D oa_tc6_check_ctrl_protection(tc6); + if (ret) { + dev_err(&tc6->spi->dev, + "Failed to check the protection mode: %d\n", ret); + return NULL; + } + ret =3D oa_tc6_sw_reset_macphy(tc6); if (ret) { dev_err(&tc6->spi->dev, --=20 2.43.0 From nobody Mon Jun 8 08:30:33 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE3853B6360; Thu, 4 Jun 2026 16:32:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Thu, 4 Jun 2026 16:32:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1780590779; bh=mzsvcWgWrk/j+iP3V81lxgbhzpht86Bvc9U9KjjEXeY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=WIEMPvVuH52r9g63WIOsMhBDICsxUzuRif+0qsHq4xIHpq3swz8iHWkXj6qaJT9SB 2nVf6L/PV9ynN5fIYRkXTL7ME0eLavcrcJ71BiBFBqANJaONAVXWsjV7J59o1bEY2P yhbv3sjGw8/xqzmzN2Ay7EagFstDysBsVh/ONVwNf/0RzB5g1aXPqmxx0UJupIofof 4sLCAzZvJ7m/e4bTDdQqrT6t1Amd3nVH3y3q8lU2Dp9SCjD5i3udNKiTFtzLT/dMeR eVpuARZ27q9GyWZ4VlZ9Ufn34UHie19Mld7u/UxUK/rQbfUWHvBXTC8G4nrfho6RVm gG8WcXwPDK7Pg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7B25CD6E7B; Thu, 4 Jun 2026 16:32:59 +0000 (UTC) From: Ciprian Regus via B4 Relay Date: Thu, 04 Jun 2026 19:32:48 +0300 Subject: [PATCH net-next v3 03/13] net: ethernet: oa_tc6: add OA_TC6_BROKEN_PHY quirk flag Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260604-adin1140-driver-v3-3-5debdb3173c4@analog.com> References: <20260604-adin1140-driver-v3-0-5debdb3173c4@analog.com> In-Reply-To: <20260604-adin1140-driver-v3-0-5debdb3173c4@analog.com> To: Parthiban Veerasooran , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Jonathan Corbet , Shuah Khan , Andrew Lunn , Heiner Kallweit , Russell King , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, devicetree@vger.kernel.org, Ciprian Regus X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780590775; l=5115; i=ciprian.regus@analog.com; s=20260330; h=from:subject:message-id; bh=2FWHfvXb7tUvZHk+WgFVnjlf71OX2G3l7tmCwpA0aqc=; b=bDV/U/65sEX5NBT1vVAveAvcfCeY64ssKjOr94BPBRJedX5wQawhe/ojoaifzVRcyrx8QMX/F +QW5L6NQ1q3B2M2Lwa7tq8Je7aDDJTcp9pvV2KXQY2vXhUQmsbOsfy8 X-Developer-Key: i=ciprian.regus@analog.com; a=ed25519; pk=8WoNhI0kQcQUl8YqJO5ZevROYk9HP8lOIeIgIYgjfbc= X-Endpoint-Received: by B4 Relay for ciprian.regus@analog.com/20260330 with auth_id=703 X-Original-From: Ciprian Regus Reply-To: ciprian.regus@analog.com From: Ciprian Regus Some MAC-PHY devices need custom MDIO bus access functions to work around hardware issues. Add the OA_TC6_BROKEN_PHY quirk flag so drivers can opt in to skip oa_tc6's internal PHY init and manage the PHY themselves. When the flag is set, oa_tc6 skips MDIO bus registration, PHY discovery and PHY connection, leaving these to the driver. Drivers that do not set the flag retain the existing behavior. Update lan865x and the framework documentation accordingly. Signed-off-by: Ciprian Regus --- v3 changelog: - add the oa_tc6_quirks struct to the oa_tc6_init() parameters (along the spi_device and net_device), instead of adding everything in a single struct. v2 changelog: - Added the quirk flag field in the oa_tc6_config struct and a first value entry (OA_TC6_BROKEN_PHY) instead of the mii_bus struct. --- Documentation/networking/oa-tc6-framework.rst | 3 ++- drivers/net/ethernet/microchip/lan865x/lan865x.c | 2 +- drivers/net/ethernet/oa_tc6.c | 14 +++++++++++++- include/linux/oa_tc6.h | 11 ++++++++++- 4 files changed, 26 insertions(+), 4 deletions(-) diff --git a/Documentation/networking/oa-tc6-framework.rst b/Documentation/= networking/oa-tc6-framework.rst index fe2aabde923a..013824078cea 100644 --- a/Documentation/networking/oa-tc6-framework.rst +++ b/Documentation/networking/oa-tc6-framework.rst @@ -454,7 +454,8 @@ Device drivers API The include/linux/oa_tc6.h defines the following functions: =20 .. c:function:: struct oa_tc6 *oa_tc6_init(struct spi_device *spi, \ - struct net_device *netdev) + struct net_device *netdev, \ + struct oa_tc6_quirks *quirks) =20 Initialize OA TC6 lib. =20 diff --git a/drivers/net/ethernet/microchip/lan865x/lan865x.c b/drivers/net= /ethernet/microchip/lan865x/lan865x.c index 0277d9737369..26a2761332a5 100644 --- a/drivers/net/ethernet/microchip/lan865x/lan865x.c +++ b/drivers/net/ethernet/microchip/lan865x/lan865x.c @@ -346,7 +346,7 @@ static int lan865x_probe(struct spi_device *spi) spi_set_drvdata(spi, priv); INIT_WORK(&priv->multicast_work, lan865x_multicast_work_handler); =20 - priv->tc6 =3D oa_tc6_init(spi, netdev); + priv->tc6 =3D oa_tc6_init(spi, netdev, NULL); if (!priv->tc6) { ret =3D -ENODEV; goto free_netdev; diff --git a/drivers/net/ethernet/oa_tc6.c b/drivers/net/ethernet/oa_tc6.c index baba5aad84df..2a72f0c4b009 100644 --- a/drivers/net/ethernet/oa_tc6.c +++ b/drivers/net/ethernet/oa_tc6.c @@ -134,6 +134,7 @@ struct oa_tc6 { bool rx_buf_overflow; bool int_flag; bool prot_ctrl; + enum oa_tc6_quirk_flag quirk_flags; }; =20 enum oa_tc6_header_type { @@ -580,6 +581,9 @@ static int oa_tc6_phy_init(struct oa_tc6 *tc6) { int ret; =20 + if (tc6->quirk_flags & OA_TC6_BROKEN_PHY) + return 0; + ret =3D oa_tc6_check_phy_reg_direct_access_capability(tc6); if (ret) { netdev_err(tc6->netdev, @@ -616,6 +620,9 @@ static int oa_tc6_phy_init(struct oa_tc6 *tc6) =20 static void oa_tc6_phy_exit(struct oa_tc6 *tc6) { + if (tc6->quirk_flags & OA_TC6_BROKEN_PHY) + return; + phy_disconnect(tc6->phydev); oa_tc6_mdiobus_unregister(tc6); } @@ -1279,11 +1286,13 @@ static int oa_tc6_check_ctrl_protection(struct oa_t= c6 *tc6) * oa_tc6_init - allocates and initializes oa_tc6 structure. * @spi: device with which data will be exchanged. * @netdev: network device interface structure. + * @quirks: device specific modifiers for the OA TC6 protocol. * * Return: pointer reference to the oa_tc6 structure if the MAC-PHY * initialization is successful otherwise NULL. */ -struct oa_tc6 *oa_tc6_init(struct spi_device *spi, struct net_device *netd= ev) +struct oa_tc6 *oa_tc6_init(struct spi_device *spi, struct net_device *netd= ev, + struct oa_tc6_quirks *quirks) { struct oa_tc6 *tc6; int ret; @@ -1298,6 +1307,9 @@ struct oa_tc6 *oa_tc6_init(struct spi_device *spi, st= ruct net_device *netdev) mutex_init(&tc6->spi_ctrl_lock); spin_lock_init(&tc6->tx_skb_lock); =20 + if (quirks) + tc6->quirk_flags =3D quirks->quirk_flags; + /* Set the SPI controller to pump at realtime priority */ tc6->spi->rt =3D true; if (spi_setup(tc6->spi) < 0) diff --git a/include/linux/oa_tc6.h b/include/linux/oa_tc6.h index 15f58e3c56c7..62e3d89f80ed 100644 --- a/include/linux/oa_tc6.h +++ b/include/linux/oa_tc6.h @@ -12,7 +12,16 @@ =20 struct oa_tc6; =20 -struct oa_tc6 *oa_tc6_init(struct spi_device *spi, struct net_device *netd= ev); +enum oa_tc6_quirk_flag { + OA_TC6_BROKEN_PHY =3D BIT(0), +}; + +struct oa_tc6_quirks { + enum oa_tc6_quirk_flag quirk_flags; +}; + +struct oa_tc6 *oa_tc6_init(struct spi_device *spi, struct net_device *netd= ev, + struct oa_tc6_quirks *quirks); void oa_tc6_exit(struct oa_tc6 *tc6); int oa_tc6_write_register(struct oa_tc6 *tc6, u32 address, u32 value); int oa_tc6_write_registers(struct oa_tc6 *tc6, u32 address, u32 value[], --=20 2.43.0 From nobody Mon Jun 8 08:30:33 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F145E3B637C; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Su/F/RqH" Received: by smtp.kernel.org (Postfix) with ESMTPS id C2E81C2BCFA; Thu, 4 Jun 2026 16:32:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1780590779; bh=7e0V/xq7Qkbu9Dbbj2MlePvt6HUgkRd3jbrGzKEUKgE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Su/F/RqHvuoW2RrahDIpopswRuiO8GI5iUAvA+MjWsQX6SbSEjwbaNSAYob239/JT XADkQjDmDLSV/yeIJXm2+N4B2KGk7UNZ+cPRbd7B79Y1J2NmXXzAE4b/BbH1DSqeEX WrHmikZC2s4PDRPtEwZoe+fsInQJ3wTyoCOLjH9aCZmFIUNRTpr1FMHtU6/SI3X/3A rghN3w5NJL1bQ66K/UPliwvzDRqWWK63eH3xxaKXgzGdUx3QNljqEWqw5d3aCtP/RK ig+eev3qRa6R5/KZ+smb3G8H0f4OzIa1JaJpjRuB3ei2C7U0HlucWc+TY5e867LFsI p8YAnF7k0taBg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B7747CD6E75; Thu, 4 Jun 2026 16:32:59 +0000 (UTC) From: Ciprian Regus via B4 Relay Date: Thu, 04 Jun 2026 19:32:49 +0300 Subject: [PATCH net-next v3 04/13] net: ethernet: oa_tc6: Export the C45 access functions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260604-adin1140-driver-v3-4-5debdb3173c4@analog.com> References: <20260604-adin1140-driver-v3-0-5debdb3173c4@analog.com> In-Reply-To: <20260604-adin1140-driver-v3-0-5debdb3173c4@analog.com> To: Parthiban Veerasooran , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Jonathan Corbet , Shuah Khan , Andrew Lunn , Heiner Kallweit , Russell King , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, devicetree@vger.kernel.org, Ciprian Regus X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780590775; l=2308; i=ciprian.regus@analog.com; s=20260330; h=from:subject:message-id; bh=z7cSpX5t5HgjHdWjBI4GiWiysbSWbBu/ywbEFt955do=; b=N+F+ekPwZJy9QUJTAP1uYY26DS+HbG307fN9yNEgWxFo1noQ9rfAv9zd7mDhqvQCAW31UfhWk Pg20+29VhecAKdzHFApUtmzTleWmeIOe7+VGKnCyDgtFaVv4JR3taKD X-Developer-Key: i=ciprian.regus@analog.com; a=ed25519; pk=8WoNhI0kQcQUl8YqJO5ZevROYk9HP8lOIeIgIYgjfbc= X-Endpoint-Received: by B4 Relay for ciprian.regus@analog.com/20260330 with auth_id=703 X-Original-From: Ciprian Regus Reply-To: ciprian.regus@analog.com From: Ciprian Regus The C45 access functions can still be used by some Ethernet drivers which set the OA_TC6_BROKEN_PHY flag. Export them. Reviewed-by: Andrew Lunn Signed-off-by: Ciprian Regus --- v3 changelog: - no change v2 changelog: - New patch --- drivers/net/ethernet/oa_tc6.c | 10 ++++++---- include/linux/oa_tc6.h | 4 ++++ 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/oa_tc6.c b/drivers/net/ethernet/oa_tc6.c index 2a72f0c4b009..b37e398e30e3 100644 --- a/drivers/net/ethernet/oa_tc6.c +++ b/drivers/net/ethernet/oa_tc6.c @@ -499,8 +499,8 @@ static int oa_tc6_get_phy_c45_mms(int devnum) } } =20 -static int oa_tc6_mdiobus_read_c45(struct mii_bus *bus, int addr, int devn= um, - int regnum) +int oa_tc6_mdiobus_read_c45(struct mii_bus *bus, int addr, int devnum, + int regnum) { struct oa_tc6 *tc6 =3D bus->priv; u32 regval; @@ -516,9 +516,10 @@ static int oa_tc6_mdiobus_read_c45(struct mii_bus *bus= , int addr, int devnum, =20 return regval; } +EXPORT_SYMBOL_GPL(oa_tc6_mdiobus_read_c45); =20 -static int oa_tc6_mdiobus_write_c45(struct mii_bus *bus, int addr, int dev= num, - int regnum, u16 val) +int oa_tc6_mdiobus_write_c45(struct mii_bus *bus, int addr, int devnum, + int regnum, u16 val) { struct oa_tc6 *tc6 =3D bus->priv; int ret; @@ -529,6 +530,7 @@ static int oa_tc6_mdiobus_write_c45(struct mii_bus *bus= , int addr, int devnum, =20 return oa_tc6_write_register(tc6, (ret << 16) | regnum, val); } +EXPORT_SYMBOL_GPL(oa_tc6_mdiobus_write_c45); =20 static int oa_tc6_mdiobus_register(struct oa_tc6 *tc6) { diff --git a/include/linux/oa_tc6.h b/include/linux/oa_tc6.h index 62e3d89f80ed..2660eefa3504 100644 --- a/include/linux/oa_tc6.h +++ b/include/linux/oa_tc6.h @@ -31,3 +31,7 @@ int oa_tc6_read_registers(struct oa_tc6 *tc6, u32 address= , u32 value[], u8 length); netdev_tx_t oa_tc6_start_xmit(struct oa_tc6 *tc6, struct sk_buff *skb); int oa_tc6_zero_align_receive_frame_enable(struct oa_tc6 *tc6); +int oa_tc6_mdiobus_read_c45(struct mii_bus *bus, int addr, int devnum, + int regnum); +int oa_tc6_mdiobus_write_c45(struct mii_bus *bus, int addr, int devnum, + int regnum, u16 val); --=20 2.43.0 From nobody Mon Jun 8 08:30:33 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 251403B95E3; Thu, 4 Jun 2026 16:33:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780590780; cv=none; b=ZlICxsHCHKhljmbmuVhRzPU29J2Al0zY1B+3MZuxkL3VliFurVhWVgBHiMvVVD0EYPLNcyvyZB/fTJbYY0mL5ONm/ffMCr6efmCMBpN5GL5unyO+VVpXKWfhIjwC/0Mhw8O/AgI6oxQbeT5goel+hfo43liiQ6EntXJYg6a4FNE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780590780; c=relaxed/simple; bh=gHLpMozEh6f2gf2jM8Z5y7gDQUgutWrZiQNphZyscLI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mCc97/Jcx39Jc41tdTqQV2J/RPgRQznAVZHGfbCvKp1ZOtTJbF8bBNN+Xf92Vj9WZ3HJWJC/TxmTsjnrUc+HJDGtlAkAf7rAQjEyrwtqHCeJNFQIuSyw7fAUirWeHCnbAR0FYcslAOY+ly9o0yssPxuPPv459DXXrCe6JFAbx5M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=YUgnqFe3; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="YUgnqFe3" Received: by smtp.kernel.org (Postfix) with ESMTPS id D2160C2BCFF; Thu, 4 Jun 2026 16:32:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1780590779; bh=gHLpMozEh6f2gf2jM8Z5y7gDQUgutWrZiQNphZyscLI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=YUgnqFe3qpr/Jx0dk6rcxD0UPFTdtgiKCaBRiQmWYio+IMr5TzLnvMyp3OruA1meL nSiwjdaXGtAWQ8Z8Q1mu6Sj/ImjUj8wWydVHxea1R51YbuLwrzXXEjDmLjdMNmMD5g 2mAzr1xEWDW0/exT5EhMbghd2QNYYiPLbEME1WAlQtonUapG6VQ+OdEmfrCipMacWf 6TXahstx42/hA+7UC9vDomP4HDZqIaSSnRckCRWVVcc2bTo35XqsT7OuPboJWTyFMm uDIpK9gtQu2N3Re5bOA4gBC/TcDIu4JsaxMewx/X7cMwXoUBNb/4I5L45qD9NO/wZP W4jEaqD+8Z5Ww== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C76FDCD6E7D; Thu, 4 Jun 2026 16:32:59 +0000 (UTC) From: Ciprian Regus via B4 Relay Date: Thu, 04 Jun 2026 19:32:50 +0300 Subject: [PATCH net-next v3 05/13] net: ethernet: oa_tc6: Export standard defined registers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260604-adin1140-driver-v3-5-5debdb3173c4@analog.com> References: <20260604-adin1140-driver-v3-0-5debdb3173c4@analog.com> In-Reply-To: <20260604-adin1140-driver-v3-0-5debdb3173c4@analog.com> To: Parthiban Veerasooran , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Jonathan Corbet , Shuah Khan , Andrew Lunn , Heiner Kallweit , Russell King , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, devicetree@vger.kernel.org, Ciprian Regus X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780590775; l=5192; i=ciprian.regus@analog.com; s=20260330; h=from:subject:message-id; bh=SnykMoUwLndx3IdbcHLqPP0Y55/QSx2yLP1+rPkpPh8=; b=g+yTEdg1tc0U6Eedi+q/eHi5iB8W8/YUlWiBuoJTnR6lnnyjct/JH58SLj1ExawKpLnlLrIZL Dr7n62QOZQwDVL+EVtBpy8V+B0lZDLLxyZMtCDGd2T0MnlJ1XuojmhD X-Developer-Key: i=ciprian.regus@analog.com; a=ed25519; pk=8WoNhI0kQcQUl8YqJO5ZevROYk9HP8lOIeIgIYgjfbc= X-Endpoint-Received: by B4 Relay for ciprian.regus@analog.com/20260330 with auth_id=703 X-Original-From: Ciprian Regus Reply-To: ciprian.regus@analog.com From: Ciprian Regus Move defines for standard Open Alliance TC6 register addresses and subfields in the oa_tc6's header and add entries for the PHYID and CONFIG2. As such, other ethernet drivers that rely on oa_tc6 can use them directly. Signed-off-by: Ciprian Regus Reviewed-by: Andrew Lunn --- v3 changelog: - Only move the register definitions, without adding the OA_TC6_ prefix v2 changelog: - New patch --- drivers/net/ethernet/oa_tc6.c | 48 ---------------------------------------= ---- include/linux/oa_tc6.h | 48 +++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 48 insertions(+), 48 deletions(-) diff --git a/drivers/net/ethernet/oa_tc6.c b/drivers/net/ethernet/oa_tc6.c index b37e398e30e3..97df38207827 100644 --- a/drivers/net/ethernet/oa_tc6.c +++ b/drivers/net/ethernet/oa_tc6.c @@ -11,45 +11,6 @@ #include #include =20 -/* OPEN Alliance TC6 registers */ -/* Standard Capabilities Register */ -#define OA_TC6_REG_STDCAP 0x0002 -#define STDCAP_DIRECT_PHY_REG_ACCESS BIT(8) - -/* Reset Control and Status Register */ -#define OA_TC6_REG_RESET 0x0003 -#define RESET_SWRESET BIT(0) /* Software Reset */ - -/* Configuration Register #0 */ -#define OA_TC6_REG_CONFIG0 0x0004 -#define CONFIG0_SYNC BIT(15) -#define CONFIG0_ZARFE_ENABLE BIT(12) -#define CONFIG0_PROTE BIT(5) - -/* Status Register #0 */ -#define OA_TC6_REG_STATUS0 0x0008 -#define STATUS0_RESETC BIT(6) /* Reset Complete */ -#define STATUS0_HEADER_ERROR BIT(5) -#define STATUS0_LOSS_OF_FRAME_ERROR BIT(4) -#define STATUS0_RX_BUFFER_OVERFLOW_ERROR BIT(3) -#define STATUS0_TX_PROTOCOL_ERROR BIT(0) - -/* Buffer Status Register */ -#define OA_TC6_REG_BUFFER_STATUS 0x000B -#define BUFFER_STATUS_TX_CREDITS_AVAILABLE GENMASK(15, 8) -#define BUFFER_STATUS_RX_CHUNKS_AVAILABLE GENMASK(7, 0) - -/* Interrupt Mask Register #0 */ -#define OA_TC6_REG_INT_MASK0 0x000C -#define INT_MASK0_HEADER_ERR_MASK BIT(5) -#define INT_MASK0_LOSS_OF_FRAME_ERR_MASK BIT(4) -#define INT_MASK0_RX_BUFFER_OVERFLOW_ERR_MASK BIT(3) -#define INT_MASK0_TX_PROTOCOL_ERR_MASK BIT(0) - -/* PHY Clause 22 registers base address and mask */ -#define OA_TC6_PHY_STD_REG_ADDR_BASE 0xFF00 -#define OA_TC6_PHY_STD_REG_ADDR_MASK 0x1F - /* Control command header */ #define OA_TC6_CTRL_HEADER_DATA_NOT_CTRL BIT(31) #define OA_TC6_CTRL_HEADER_WRITE_NOT_READ BIT(29) @@ -79,15 +40,6 @@ #define OA_TC6_DATA_FOOTER_END_BYTE_OFFSET GENMASK(13, 8) #define OA_TC6_DATA_FOOTER_TX_CREDITS GENMASK(5, 1) =20 -/* PHY =E2=80=93 Clause 45 registers memory map selector (MMS) as per tabl= e 6 in the - * OPEN Alliance specification. - */ -#define OA_TC6_PHY_C45_PCS_MMS2 2 /* MMD 3 */ -#define OA_TC6_PHY_C45_PMA_PMD_MMS3 3 /* MMD 1 */ -#define OA_TC6_PHY_C45_VS_PLCA_MMS4 4 /* MMD 31 */ -#define OA_TC6_PHY_C45_AUTO_NEG_MMS5 5 /* MMD 7 */ -#define OA_TC6_PHY_C45_POWER_UNIT_MMS6 6 /* MMD 13 */ - #define OA_TC6_CTRL_PROT_REPLY_SIZE 4 #define OA_TC6_CTRL_HEADER_SIZE 4 #define OA_TC6_CTRL_REG_VALUE_SIZE 4 diff --git a/include/linux/oa_tc6.h b/include/linux/oa_tc6.h index 2660eefa3504..bbc42758a313 100644 --- a/include/linux/oa_tc6.h +++ b/include/linux/oa_tc6.h @@ -10,6 +10,54 @@ #include #include =20 +/* OPEN Alliance TC6 registers */ +/* Standard Capabilities Register */ +#define OA_TC6_REG_STDCAP 0x0002 +#define STDCAP_DIRECT_PHY_REG_ACCESS BIT(8) + +/* Reset Control and Status Register */ +#define OA_TC6_REG_RESET 0x0003 +#define RESET_SWRESET BIT(0) /* Software Reset */ + +/* Configuration Register #0 */ +#define OA_TC6_REG_CONFIG0 0x0004 +#define CONFIG0_SYNC BIT(15) +#define CONFIG0_ZARFE_ENABLE BIT(12) +#define CONFIG0_PROTE BIT(5) + +/* Status Register #0 */ +#define OA_TC6_REG_STATUS0 0x0008 +#define STATUS0_RESETC BIT(6) /* Reset Complete */ +#define STATUS0_HEADER_ERROR BIT(5) +#define STATUS0_LOSS_OF_FRAME_ERROR BIT(4) +#define STATUS0_RX_BUFFER_OVERFLOW_ERROR BIT(3) +#define STATUS0_TX_PROTOCOL_ERROR BIT(0) + +/* Buffer Status Register */ +#define OA_TC6_REG_BUFFER_STATUS 0x000B +#define BUFFER_STATUS_TX_CREDITS_AVAILABLE GENMASK(15, 8) +#define BUFFER_STATUS_RX_CHUNKS_AVAILABLE GENMASK(7, 0) + +/* Interrupt Mask Register #0 */ +#define OA_TC6_REG_INT_MASK0 0x000C +#define INT_MASK0_HEADER_ERR_MASK BIT(5) +#define INT_MASK0_LOSS_OF_FRAME_ERR_MASK BIT(4) +#define INT_MASK0_RX_BUFFER_OVERFLOW_ERR_MASK BIT(3) +#define INT_MASK0_TX_PROTOCOL_ERR_MASK BIT(0) + +/* PHY Clause 22 registers base address and mask */ +#define OA_TC6_PHY_STD_REG_ADDR_BASE 0xFF00 +#define OA_TC6_PHY_STD_REG_ADDR_MASK 0x1F + +/* PHY =E2=80=93 Clause 45 registers memory map selector (MMS) as per tabl= e 6 in the + * OPEN Alliance specification. + */ +#define OA_TC6_PHY_C45_PCS_MMS2 2 /* MMD 3 */ +#define OA_TC6_PHY_C45_PMA_PMD_MMS3 3 /* MMD 1 */ +#define OA_TC6_PHY_C45_VS_PLCA_MMS4 4 /* MMD 31 */ +#define OA_TC6_PHY_C45_AUTO_NEG_MMS5 5 /* MMD 7 */ +#define OA_TC6_PHY_C45_POWER_UNIT_MMS6 6 /* MMD 13 */ + struct oa_tc6; =20 enum oa_tc6_quirk_flag { --=20 2.43.0 From nobody Mon Jun 8 08:30:33 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 26E753B9935; Thu, 4 Jun 2026 16:33:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780590780; cv=none; b=MZPkGgbO6yJ5GCFWf0jaABub7+n58F6IEX3d8gFIV/VZA+htlEB0nWVB2DhNon10EYZ5RhGrR+coZyObUnXvAQmD/GooR1M0Y7LdBFIRgU4KpWtCF24RK5ANR0PHKkkwOTCGzC3avDp3msYSQ4MiXBn6fMTLoO0jITqLW/fw+f0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780590780; c=relaxed/simple; bh=szsxI7s4ajswbkCUFBTBD8d8vD1Z/ZedbsriN75zF5Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=k9tUxQSjmih8OlptkJ4ji73CDxRdEhBhGeXB9Rgtv/NSeybTOgi2yFR/+NMzyCfANmfBiAJG48IqGFG2j8m8Aca5ZdGN+3XVyN9g2V+nAQ4HrGQJGWTT/1Toy7dEn7I0MmBaccDMU3KVyG41suhJ9kaY/hhJh7z84EeNWNFw4RI= ARC-Authentication-Results: i=1; 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Thu, 4 Jun 2026 16:32:59 +0000 (UTC) From: Ciprian Regus via B4 Relay Date: Thu, 04 Jun 2026 19:32:51 +0300 Subject: [PATCH net-next v3 06/13] net: ethernet: oa_tc6: Add the OA_TC6_ prefix to standard registers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260604-adin1140-driver-v3-6-5debdb3173c4@analog.com> References: <20260604-adin1140-driver-v3-0-5debdb3173c4@analog.com> In-Reply-To: <20260604-adin1140-driver-v3-0-5debdb3173c4@analog.com> To: Parthiban Veerasooran , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Jonathan Corbet , Shuah Khan , Andrew Lunn , Heiner Kallweit , Russell King , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, devicetree@vger.kernel.org, Ciprian Regus X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780590775; l=7168; i=ciprian.regus@analog.com; s=20260330; h=from:subject:message-id; bh=guMxrl2Z2kGqnZvHBADy+lB8CINQv/UgNqNLCTsfsmM=; b=qSV7uo4g6HO9gWJSTpX39ORkUH3P5QHQOIHcFGVk+BmcnWEASaklHkjJZNPRFAj/u/KOB78xC Tct6uqcBIpADN/u6eGHSBpmEA/GGtY/r1wGqhQKsFufA/6Ns+OjG3Bb X-Developer-Key: i=ciprian.regus@analog.com; a=ed25519; pk=8WoNhI0kQcQUl8YqJO5ZevROYk9HP8lOIeIgIYgjfbc= X-Endpoint-Received: by B4 Relay for ciprian.regus@analog.com/20260330 with auth_id=703 X-Original-From: Ciprian Regus Reply-To: ciprian.regus@analog.com From: Ciprian Regus The OA TC6 standard registers are currently exported in a header file. Add the OA_TC6_ prefix to the register address and subfield mask macros to avoid future naming conflicts. Signed-off-by: Ciprian Regus Reviewed-by: Andrew Lunn --- v3 changelog: - New patch --- drivers/net/ethernet/oa_tc6.c | 35 ++++++++++++++++++----------------- include/linux/oa_tc6.h | 36 ++++++++++++++++++------------------ 2 files changed, 36 insertions(+), 35 deletions(-) diff --git a/drivers/net/ethernet/oa_tc6.c b/drivers/net/ethernet/oa_tc6.c index 97df38207827..92da5bb74cc7 100644 --- a/drivers/net/ethernet/oa_tc6.c +++ b/drivers/net/ethernet/oa_tc6.c @@ -397,7 +397,7 @@ static int oa_tc6_check_phy_reg_direct_access_capabilit= y(struct oa_tc6 *tc6) if (ret) return ret; =20 - if (!(regval & STDCAP_DIRECT_PHY_REG_ACCESS)) + if (!(regval & OA_TC6_STDCAP_DIRECT_PHY_REG_ACCESS)) return -ENODEV; =20 return 0; @@ -598,7 +598,7 @@ static int oa_tc6_read_status0(struct oa_tc6 *tc6) =20 static int oa_tc6_sw_reset_macphy(struct oa_tc6 *tc6) { - u32 regval =3D RESET_SWRESET; + u32 regval =3D OA_TC6_RESET_SWRESET; int ret; =20 ret =3D oa_tc6_write_register(tc6, OA_TC6_REG_RESET, regval); @@ -607,7 +607,7 @@ static int oa_tc6_sw_reset_macphy(struct oa_tc6 *tc6) =20 /* Poll for soft reset complete for every 1ms until 1s timeout */ ret =3D readx_poll_timeout(oa_tc6_read_status0, tc6, regval, - regval & STATUS0_RESETC, + regval & OA_TC6_STATUS0_RESETC, STATUS0_RESETC_POLL_DELAY, STATUS0_RESETC_POLL_TIMEOUT); if (ret) @@ -626,10 +626,10 @@ static int oa_tc6_unmask_macphy_error_interrupts(stru= ct oa_tc6 *tc6) if (ret) return ret; =20 - regval &=3D ~(INT_MASK0_TX_PROTOCOL_ERR_MASK | - INT_MASK0_RX_BUFFER_OVERFLOW_ERR_MASK | - INT_MASK0_LOSS_OF_FRAME_ERR_MASK | - INT_MASK0_HEADER_ERR_MASK); + regval &=3D ~(OA_TC6_INT_MASK0_TX_PROTOCOL_ERR_MASK | + OA_TC6_INT_MASK0_RX_BUFFER_OVERFLOW_ERR_MASK | + OA_TC6_INT_MASK0_LOSS_OF_FRAME_ERR_MASK | + OA_TC6_INT_MASK0_HEADER_ERR_MASK); =20 return oa_tc6_write_register(tc6, OA_TC6_REG_INT_MASK0, regval); } @@ -644,7 +644,7 @@ static int oa_tc6_enable_data_transfer(struct oa_tc6 *t= c6) return ret; =20 /* Enable configuration synchronization for data transfer */ - value |=3D CONFIG0_SYNC; + value |=3D OA_TC6_CONFIG0_SYNC; =20 return oa_tc6_write_register(tc6, OA_TC6_REG_CONFIG0, value); } @@ -687,25 +687,25 @@ static int oa_tc6_process_extended_status(struct oa_t= c6 *tc6) return ret; } =20 - if (FIELD_GET(STATUS0_RX_BUFFER_OVERFLOW_ERROR, value)) { + if (FIELD_GET(OA_TC6_STATUS0_RX_BUFFER_OVERFLOW_ERROR, value)) { tc6->rx_buf_overflow =3D true; oa_tc6_cleanup_ongoing_rx_skb(tc6); net_err_ratelimited("%s: Receive buffer overflow error\n", tc6->netdev->name); return -EAGAIN; } - if (FIELD_GET(STATUS0_TX_PROTOCOL_ERROR, value)) { + if (FIELD_GET(OA_TC6_STATUS0_TX_PROTOCOL_ERROR, value)) { netdev_err(tc6->netdev, "Transmit protocol error\n"); return -ENODEV; } /* TODO: Currently loss of frame and header errors are treated as * non-recoverable errors. They will be handled in the next version. */ - if (FIELD_GET(STATUS0_LOSS_OF_FRAME_ERROR, value)) { + if (FIELD_GET(OA_TC6_STATUS0_LOSS_OF_FRAME_ERROR, value)) { netdev_err(tc6->netdev, "Loss of frame error\n"); return -ENODEV; } - if (FIELD_GET(STATUS0_HEADER_ERROR, value)) { + if (FIELD_GET(OA_TC6_STATUS0_HEADER_ERROR, value)) { netdev_err(tc6->netdev, "Header error\n"); return -ENODEV; } @@ -1141,9 +1141,10 @@ static int oa_tc6_update_buffer_status_from_register= (struct oa_tc6 *tc6) if (ret) return ret; =20 - tc6->tx_credits =3D FIELD_GET(BUFFER_STATUS_TX_CREDITS_AVAILABLE, value); - tc6->rx_chunks_available =3D FIELD_GET(BUFFER_STATUS_RX_CHUNKS_AVAILABLE, - value); + tc6->tx_credits =3D FIELD_GET(OA_TC6_BUFFER_STATUS_TX_CREDITS_AVAILABLE, + value); + tc6->rx_chunks_available =3D + FIELD_GET(OA_TC6_BUFFER_STATUS_RX_CHUNKS_AVAILABLE, value); =20 return 0; } @@ -1183,7 +1184,7 @@ int oa_tc6_zero_align_receive_frame_enable(struct oa_= tc6 *tc6) return ret; =20 /* Set Zero-Align Receive Frame Enable */ - regval |=3D CONFIG0_ZARFE_ENABLE; + regval |=3D OA_TC6_CONFIG0_ZARFE_ENABLE; =20 return oa_tc6_write_register(tc6, OA_TC6_REG_CONFIG0, regval); } @@ -1231,7 +1232,7 @@ static int oa_tc6_check_ctrl_protection(struct oa_tc6= *tc6) if (ret) return ret; =20 - tc6->prot_ctrl =3D FIELD_GET(CONFIG0_PROTE, regval); + tc6->prot_ctrl =3D FIELD_GET(OA_TC6_CONFIG0_PROTE, regval); =20 return 0; } diff --git a/include/linux/oa_tc6.h b/include/linux/oa_tc6.h index bbc42758a313..bd369aac9c3b 100644 --- a/include/linux/oa_tc6.h +++ b/include/linux/oa_tc6.h @@ -13,37 +13,37 @@ /* OPEN Alliance TC6 registers */ /* Standard Capabilities Register */ #define OA_TC6_REG_STDCAP 0x0002 -#define STDCAP_DIRECT_PHY_REG_ACCESS BIT(8) +#define OA_TC6_STDCAP_DIRECT_PHY_REG_ACCESS BIT(8) =20 /* Reset Control and Status Register */ #define OA_TC6_REG_RESET 0x0003 -#define RESET_SWRESET BIT(0) /* Software Reset */ +#define OA_TC6_RESET_SWRESET BIT(0) /* Software Reset */ =20 /* Configuration Register #0 */ #define OA_TC6_REG_CONFIG0 0x0004 -#define CONFIG0_SYNC BIT(15) -#define CONFIG0_ZARFE_ENABLE BIT(12) -#define CONFIG0_PROTE BIT(5) +#define OA_TC6_CONFIG0_SYNC BIT(15) +#define OA_TC6_CONFIG0_ZARFE_ENABLE BIT(12) +#define OA_TC6_CONFIG0_PROTE BIT(5) =20 /* Status Register #0 */ #define OA_TC6_REG_STATUS0 0x0008 -#define STATUS0_RESETC BIT(6) /* Reset Complete */ -#define STATUS0_HEADER_ERROR BIT(5) -#define STATUS0_LOSS_OF_FRAME_ERROR BIT(4) -#define STATUS0_RX_BUFFER_OVERFLOW_ERROR BIT(3) -#define STATUS0_TX_PROTOCOL_ERROR BIT(0) +#define OA_TC6_STATUS0_RESETC BIT(6) /* Reset Complete */ +#define OA_TC6_STATUS0_HEADER_ERROR BIT(5) +#define OA_TC6_STATUS0_LOSS_OF_FRAME_ERROR BIT(4) +#define OA_TC6_STATUS0_RX_BUFFER_OVERFLOW_ERROR BIT(3) +#define OA_TC6_STATUS0_TX_PROTOCOL_ERROR BIT(0) =20 /* Buffer Status Register */ -#define OA_TC6_REG_BUFFER_STATUS 0x000B -#define BUFFER_STATUS_TX_CREDITS_AVAILABLE GENMASK(15, 8) -#define BUFFER_STATUS_RX_CHUNKS_AVAILABLE GENMASK(7, 0) +#define OA_TC6_REG_BUFFER_STATUS 0x000B +#define OA_TC6_BUFFER_STATUS_TX_CREDITS_AVAILABLE GENMASK(15, 8) +#define OA_TC6_BUFFER_STATUS_RX_CHUNKS_AVAILABLE GENMASK(7, 0) =20 /* Interrupt Mask Register #0 */ -#define OA_TC6_REG_INT_MASK0 0x000C -#define INT_MASK0_HEADER_ERR_MASK BIT(5) -#define INT_MASK0_LOSS_OF_FRAME_ERR_MASK BIT(4) -#define INT_MASK0_RX_BUFFER_OVERFLOW_ERR_MASK BIT(3) -#define INT_MASK0_TX_PROTOCOL_ERR_MASK BIT(0) +#define OA_TC6_REG_INT_MASK0 0x000C +#define OA_TC6_INT_MASK0_HEADER_ERR_MASK BIT(5) +#define OA_TC6_INT_MASK0_LOSS_OF_FRAME_ERR_MASK BIT(4) +#define OA_TC6_INT_MASK0_RX_BUFFER_OVERFLOW_ERR_MASK BIT(3) +#define OA_TC6_INT_MASK0_TX_PROTOCOL_ERR_MASK BIT(0) =20 /* PHY Clause 22 registers base address and mask */ #define OA_TC6_PHY_STD_REG_ADDR_BASE 0xFF00 --=20 2.43.0 From nobody Mon Jun 8 08:30:33 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C9DA47F2E6; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kQZHy0/K" Received: by smtp.kernel.org (Postfix) with ESMTPS id F1942C2BD05; Thu, 4 Jun 2026 16:32:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1780590780; bh=EiiJwbeqE8RjJeF4QP0nvNqSZ9G+lOLGNonOTjaJbcM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=kQZHy0/KYi0tx8NP7Ox6k1M168b+IvKOFtmlMwsz/dqFwXa346k3ZgwzPrIsCe2+c EzTvNby1zG5jPLAis9InnpnytDqWQPRGToK9noIrNepFtMfV/kaGjVMlUDEdo73Fqw 2L2wliInqR4AmyYu1G2w7aacFeLW317lDndJE7Z7Y2MEFYd2+oePFKcmzKV5LxWl9S ndBylVfAaQRrYavIoE3B8ZvDGvzlUyyNK9wpBz20xv/91wQ7dK/WoTq6GPTSPTouvU RaG6gRP8guGvKu0yJaD+I80+BairzJFwQaYVl7N8tkfYt/ng8xo4lkDEx3wTEdly9f rM34Fm1v3PAng== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8AD5CD6E75; Thu, 4 Jun 2026 16:32:59 +0000 (UTC) From: Ciprian Regus via B4 Relay Date: Thu, 04 Jun 2026 19:32:52 +0300 Subject: [PATCH net-next v3 07/13] net: ethernet: oa_tc6: Add read_mms/write_mms register access functions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260604-adin1140-driver-v3-7-5debdb3173c4@analog.com> References: <20260604-adin1140-driver-v3-0-5debdb3173c4@analog.com> In-Reply-To: <20260604-adin1140-driver-v3-0-5debdb3173c4@analog.com> To: Parthiban Veerasooran , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Jonathan Corbet , Shuah Khan , Andrew Lunn , Heiner Kallweit , Russell King , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, devicetree@vger.kernel.org, Ciprian Regus X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780590775; l=4012; i=ciprian.regus@analog.com; s=20260330; h=from:subject:message-id; bh=Qs1tSOe329iuRsJjQ6kWAX76EG3tpe12rcHknybT5xg=; b=aQwHUpEu648jILW5oYDKeC4CrUlr9oSoVWw7s+vTR1bG7LryUBbYFgDyMqS+GsAhp72segH7o C43csDrPmFuDKAiwJCmxgTjUH+SgPgYOaL6R3AeZlzZZVut8lg1NYM3 X-Developer-Key: i=ciprian.regus@analog.com; a=ed25519; pk=8WoNhI0kQcQUl8YqJO5ZevROYk9HP8lOIeIgIYgjfbc= X-Endpoint-Received: by B4 Relay for ciprian.regus@analog.com/20260330 with auth_id=703 X-Original-From: Ciprian Regus Reply-To: ciprian.regus@analog.com From: Ciprian Regus The Open Alliance TC6 standard defines multiple memory maps for the MAC-PHY's register space. These are used to separate standard, vendor and PHY MMD specific registers. Define register access functions that allow the caller to specify the MMS. Signed-off-by: Ciprian Regus --- v3 changelog: - replace the OA_TC6_MMS_REG() macro with the register access functions that allow passing an mms parameter. v2 changelog: - New patch --- drivers/net/ethernet/oa_tc6.c | 47 +++++++++++++++++++++++++++++++++++++++= ++++ include/linux/oa_tc6.h | 4 ++++ 2 files changed, 51 insertions(+) diff --git a/drivers/net/ethernet/oa_tc6.c b/drivers/net/ethernet/oa_tc6.c index 92da5bb74cc7..3807265bf0b5 100644 --- a/drivers/net/ethernet/oa_tc6.c +++ b/drivers/net/ethernet/oa_tc6.c @@ -61,6 +61,9 @@ #define STATUS0_RESETC_POLL_DELAY 1000 #define STATUS0_RESETC_POLL_TIMEOUT 1000000 =20 +#define OA_TC6_REG_MMS_MASK GENMASK(19, 16) +#define OA_TC6_REG_ADDR_MASK GENMASK(15, 0) + /* Internal structure for MAC-PHY drivers */ struct oa_tc6 { struct device *dev; @@ -344,6 +347,28 @@ int oa_tc6_read_register(struct oa_tc6 *tc6, u32 addre= ss, u32 *value) } EXPORT_SYMBOL_GPL(oa_tc6_read_register); =20 +/** + * oa_tc6_read_register_mms - function for reading a MAC-PHY register in a + * memory map other than 0. + * @tc6: oa_tc6 struct. + * @mms: Memory map selector for the register. + * @address: register address of the MAC-PHY to be read. + * @value: value read from the @address register address of the MAC-PHY. + * + * Return: 0 on success otherwise failed. + */ +int oa_tc6_read_register_mms(struct oa_tc6 *tc6, u8 mms, u32 address, + u32 *value) +{ + u32 mms_reg; + + mms_reg =3D FIELD_PREP(OA_TC6_REG_MMS_MASK, mms) | + FIELD_PREP(OA_TC6_REG_ADDR_MASK, address); + + return oa_tc6_read_registers(tc6, mms_reg, value, 1); +} +EXPORT_SYMBOL_GPL(oa_tc6_read_register_mms); + /** * oa_tc6_write_registers - function for writing multiple consecutive regi= sters. * @tc6: oa_tc6 struct. @@ -388,6 +413,28 @@ int oa_tc6_write_register(struct oa_tc6 *tc6, u32 addr= ess, u32 value) } EXPORT_SYMBOL_GPL(oa_tc6_write_register); =20 +/** + * oa_tc6_write_register_mms - function for writing a MAC-PHY register in a + * memory map other than 0. + * @tc6: oa_tc6 struct. + * @mms: Memory map selector for the register. + * @address: register address of the MAC-PHY to be written. + * @value: value to be written in the @address register address of the MAC= -PHY. + * + * Return: 0 on success otherwise failed. + */ +int oa_tc6_write_register_mms(struct oa_tc6 *tc6, u8 mms, u32 address, + u32 value) +{ + u32 mms_reg; + + mms_reg =3D FIELD_PREP(OA_TC6_REG_MMS_MASK, mms) | + FIELD_PREP(OA_TC6_REG_ADDR_MASK, address); + + return oa_tc6_write_registers(tc6, mms_reg, &value, 1); +} +EXPORT_SYMBOL_GPL(oa_tc6_write_register_mms); + static int oa_tc6_check_phy_reg_direct_access_capability(struct oa_tc6 *tc= 6) { u32 regval; diff --git a/include/linux/oa_tc6.h b/include/linux/oa_tc6.h index bd369aac9c3b..9fa4397303d1 100644 --- a/include/linux/oa_tc6.h +++ b/include/linux/oa_tc6.h @@ -72,9 +72,13 @@ struct oa_tc6 *oa_tc6_init(struct spi_device *spi, struc= t net_device *netdev, struct oa_tc6_quirks *quirks); void oa_tc6_exit(struct oa_tc6 *tc6); int oa_tc6_write_register(struct oa_tc6 *tc6, u32 address, u32 value); +int oa_tc6_write_register_mms(struct oa_tc6 *tc6, u8 mms, u32 address, + u32 value); int oa_tc6_write_registers(struct oa_tc6 *tc6, u32 address, u32 value[], u8 length); int oa_tc6_read_register(struct oa_tc6 *tc6, u32 address, u32 *value); +int oa_tc6_read_register_mms(struct oa_tc6 *tc6, u8 mms, u32 address, + u32 *value); int oa_tc6_read_registers(struct oa_tc6 *tc6, u32 address, u32 value[], u8 length); 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Thu, 4 Jun 2026 16:33:00 +0000 (UTC) From: Ciprian Regus via B4 Relay Date: Thu, 04 Jun 2026 19:32:53 +0300 Subject: [PATCH net-next v3 08/13] net: ethernet: oa_tc6: Use the read_mms/write_mms functions for C45 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260604-adin1140-driver-v3-8-5debdb3173c4@analog.com> References: <20260604-adin1140-driver-v3-0-5debdb3173c4@analog.com> In-Reply-To: <20260604-adin1140-driver-v3-0-5debdb3173c4@analog.com> To: Parthiban Veerasooran , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Jonathan Corbet , Shuah Khan , Andrew Lunn , Heiner Kallweit , Russell King , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, devicetree@vger.kernel.org, Ciprian Regus X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780590775; l=1799; i=ciprian.regus@analog.com; s=20260330; h=from:subject:message-id; bh=No7tofzB9UMLLlyfh1zygeZv8UoG526Pzr9YB3ygxVg=; b=+fIixh8ZhMl1Lv14YnbJKghAPM029c0RB8C8Mi04rvRxQf3WieUkK83N3GXWdts2wP7ttZ137 KOuV0kmn92wCwquyqoyNtwfnc2k9xCqGnKhdj47UmrW4QZX9OCMMKFs X-Developer-Key: i=ciprian.regus@analog.com; a=ed25519; pk=8WoNhI0kQcQUl8YqJO5ZevROYk9HP8lOIeIgIYgjfbc= X-Endpoint-Received: by B4 Relay for ciprian.regus@analog.com/20260330 with auth_id=703 X-Original-From: Ciprian Regus Reply-To: ciprian.regus@analog.com From: Ciprian Regus Accessing PHY MMD devices requires control transactions to registers in a memory map other than 0. Replace the current formatting of the register addresses with the oa_tc6_{read,write}_register_mms() functions. While we're here, introduce the mms variable to store the memory map returned by oa_tc6_get_phy_c45_mms() instead of ret, in order to improve the code readability. Signed-off-by: Ciprian Regus Reviewed-by: Andrew Lunn --- v3 changelog: - New patch --- drivers/net/ethernet/oa_tc6.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/oa_tc6.c b/drivers/net/ethernet/oa_tc6.c index 3807265bf0b5..691d293b8ee2 100644 --- a/drivers/net/ethernet/oa_tc6.c +++ b/drivers/net/ethernet/oa_tc6.c @@ -503,13 +503,14 @@ int oa_tc6_mdiobus_read_c45(struct mii_bus *bus, int = addr, int devnum, { struct oa_tc6 *tc6 =3D bus->priv; u32 regval; + int mms; int ret; =20 - ret =3D oa_tc6_get_phy_c45_mms(devnum); - if (ret < 0) - return ret; + mms =3D oa_tc6_get_phy_c45_mms(devnum); + if (mms < 0) + return mms; =20 - ret =3D oa_tc6_read_register(tc6, (ret << 16) | regnum, ®val); + ret =3D oa_tc6_read_register_mms(tc6, mms, regnum, ®val); if (ret) return ret; =20 @@ -521,13 +522,13 @@ int oa_tc6_mdiobus_write_c45(struct mii_bus *bus, int= addr, int devnum, int regnum, u16 val) { struct oa_tc6 *tc6 =3D bus->priv; - int ret; + int mms; =20 - ret =3D oa_tc6_get_phy_c45_mms(devnum); - if (ret < 0) - return ret; + mms =3D oa_tc6_get_phy_c45_mms(devnum); + if (mms < 0) + return mms; =20 - return oa_tc6_write_register(tc6, (ret << 16) | regnum, val); + return oa_tc6_write_register_mms(tc6, mms, regnum, val); } EXPORT_SYMBOL_GPL(oa_tc6_mdiobus_write_c45); =20 --=20 2.43.0 From nobody Mon Jun 8 08:30:33 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F832481A8D; Thu, 4 Jun 2026 16:33:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780590780; cv=none; b=aiKuMHQEnBGFWOokZ3sOmm4QZv6Kii0gvNNgQ/ZGqjkE09JLk5bRjJCuAaK7nxOAn1uqsGVkVrB41gSbTdRbiwUOBeQ0KQpvaEWCTsYyZYL6B5IQJlh4ENuoM8lBjxVJzergnNYheq8r0UsA9CLEcRaxyPBFa9Ty62HYjpr8QEU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780590780; c=relaxed/simple; bh=WxJeLSmnlvSp9HNlkuarFkmfHSAlWDR40P3hrDZjsAU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=o6cT9SLrJSP4Ju+t6VDUgcOtTHmqFl6oZctchZs49stRrG0Fecv9DMZtcGR09PBtN5hT+K9OqV8qwd+Es6KZVZkcJ7vwIEgMYsjF0AcvSwRrD2NxIyppidi9/A9b+ZGk5nc3OLgO1BMgXLuyXxJfnPZUO+rH5pVLUaFoCDn80jQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=fwyfYyu2; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="fwyfYyu2" Received: by smtp.kernel.org (Postfix) with ESMTPS id 1D8FAC2BCB8; Thu, 4 Jun 2026 16:33:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1780590780; bh=WxJeLSmnlvSp9HNlkuarFkmfHSAlWDR40P3hrDZjsAU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=fwyfYyu2ZUmYdDfTJcP+bz8EzH32BfuNU7as/rUuXcPAAwTYHb5trEGI/4qQZrY71 Tzl71Vpt6a0Fhfkzkv7GT+0GSIQq0aiq/6SWQAxC2sD2hj+mbY2O2/3Tscq2jJRJWz 826759c2Hqc+g3y6GqkF+tf4hVMYa96QvzLFeBRof0Q2u6swinOYmq7W5PT6iHnIXQ OK1VasW6FRwh3dgrZNaEUxjdb4WCThhP87JCollJTR0Lg4ELzmN06sc5pfZfZ1Y3xj ti7rbLVNEd+RYSRIum0wDGBJA3FX6nETY2x8FAU1cdR0LaigO6GfZ1cUjWok7DzqbE b5fDXqOHk4+5g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 16025CD6E7C; Thu, 4 Jun 2026 16:33:00 +0000 (UTC) From: Ciprian Regus via B4 Relay Date: Thu, 04 Jun 2026 19:32:54 +0300 Subject: [PATCH net-next v3 09/13] net: ethernet: oa_tc6: Add new register address defines Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260604-adin1140-driver-v3-9-5debdb3173c4@analog.com> References: <20260604-adin1140-driver-v3-0-5debdb3173c4@analog.com> In-Reply-To: <20260604-adin1140-driver-v3-0-5debdb3173c4@analog.com> To: Parthiban Veerasooran , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Jonathan Corbet , Shuah Khan , Andrew Lunn , Heiner Kallweit , Russell King , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, devicetree@vger.kernel.org, Ciprian Regus X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780590775; l=1033; i=ciprian.regus@analog.com; s=20260330; h=from:subject:message-id; bh=XLlVXJ5JKEByKuTG8wv/EPQZUEA1wZ12/OZMlAN0o6M=; b=15V6fMXtWlth7cs+frklZTL+9pejPfbLpZ56+JaRGzkPe89P0V6f+Cyymf71h6cm95rQUfTLz 66PxryZqTfaBoc3zYoMpHNWt4kc/bXNg/lH4JG2LGJnoySeGWrZUwYt X-Developer-Key: i=ciprian.regus@analog.com; a=ed25519; pk=8WoNhI0kQcQUl8YqJO5ZevROYk9HP8lOIeIgIYgjfbc= X-Endpoint-Received: by B4 Relay for ciprian.regus@analog.com/20260330 with auth_id=703 X-Original-From: Ciprian Regus Reply-To: ciprian.regus@analog.com From: Ciprian Regus Add macro defines for the CONFIG2 register and the MMS1 memory map. Signed-off-by: Ciprian Regus --- v3 changelog: - New patch --- include/linux/oa_tc6.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/linux/oa_tc6.h b/include/linux/oa_tc6.h index 9fa4397303d1..e6eca352b2c0 100644 --- a/include/linux/oa_tc6.h +++ b/include/linux/oa_tc6.h @@ -25,6 +25,9 @@ #define OA_TC6_CONFIG0_ZARFE_ENABLE BIT(12) #define OA_TC6_CONFIG0_PROTE BIT(5) =20 +/* Configuration Register #2 */ +#define OA_TC6_REG_CONFIG2 0x0006 + /* Status Register #0 */ #define OA_TC6_REG_STATUS0 0x0008 #define OA_TC6_STATUS0_RESETC BIT(6) /* Reset Complete */ @@ -49,6 +52,9 @@ #define OA_TC6_PHY_STD_REG_ADDR_BASE 0xFF00 #define OA_TC6_PHY_STD_REG_ADDR_MASK 0x1F =20 +/* Vendor specific memory map. */ +#define OA_TC6_VEND_MMS1 1 + /* PHY =E2=80=93 Clause 45 registers memory map selector (MMS) as per tabl= e 6 in the * OPEN Alliance specification. */ --=20 2.43.0 From nobody Mon Jun 8 08:30:33 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B817481AA2; Thu, 4 Jun 2026 16:33:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780590780; cv=none; b=LTa5DUElPcCCWDDcjWPlCtVL9TaxYg+zIdh6jIRTwE/4m5y+PsXrk7hncv0lhOxmm8lyztOFGc5kyJ9L1uWtrplbRXxFLsAGGaJd3Tff0XpZ67GpAX9hMZyI7sqVXFReuXtq2e8dcdvKLcwLWRWAH7tp4E/DK30OjygQrUR+IlQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780590780; c=relaxed/simple; bh=rEvULvmlnDRA4sCVLDbBlYEfqv7KSe1XTjHaDmbBasI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=H0KUYyOzisL5HDzYkEzAZqIox3A8LEwVlpJXuf93A8uN/AbPGbTMG8DFnbAQc2SKdNl0R04ubARv4waFToY5IW2Hz56B7hnRXH63/lmclVd5yi52XLszXP+JvC0AvBbwSoDFkWoS4OQmY+0kWDLNnGsTGADl7S1Yvtb7F07LN5g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=G3Fru6kI; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="G3Fru6kI" Received: by smtp.kernel.org (Postfix) with ESMTPS id 324AEC2BCF4; Thu, 4 Jun 2026 16:33:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1780590780; bh=rEvULvmlnDRA4sCVLDbBlYEfqv7KSe1XTjHaDmbBasI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=G3Fru6kIaVGr+aYfq7TtCzJwh0a5JvVFyzsBy5tLMycLCEnBryfVooT65r9hXxvnF lQK0Ja8qRIi4V5QX8qJ80ohpNZ5223M2TUmtKrwiy90IohOIiMFKkIcpDSsi28NoOF ck6Oc7fdmxwGZUuaYFjMxT6suvnZ+sUNlHYJM7QTxbzDwLoiL+z6Mc9CiTVFxx1jWY +FLQ4+GuWFigOJWPGMu9Z5Oyig1Al5uuKE76RErTE0fwcMnKdgJNu/6AD9ldi5Io5Z 3+Sx7rmECfjQQh/BwiCTLV0iahKBzfGs3QtLoc1GmywKe6WDCNIN13AGtWhqdkAziS ZlfjlzSrUekdQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29A33CD6E79; Thu, 4 Jun 2026 16:33:00 +0000 (UTC) From: Ciprian Regus via B4 Relay Date: Thu, 04 Jun 2026 19:32:55 +0300 Subject: [PATCH net-next v3 10/13] net: phy: add generic helpers for direct C45 MMD access Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260604-adin1140-driver-v3-10-5debdb3173c4@analog.com> References: <20260604-adin1140-driver-v3-0-5debdb3173c4@analog.com> In-Reply-To: <20260604-adin1140-driver-v3-0-5debdb3173c4@analog.com> To: Parthiban Veerasooran , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Jonathan Corbet , Shuah Khan , Andrew Lunn , Heiner Kallweit , Russell King , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, devicetree@vger.kernel.org, Ciprian Regus X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780590775; l=2682; i=ciprian.regus@analog.com; s=20260330; h=from:subject:message-id; bh=KEFIsY+nz2k4HZCe7o0fb2JTtI08zuGJ0BttX6Nj+lE=; b=nQJkHUs+QsBvezjO+21nfGJcNE8zwp5E65EP5hXQ/FO0/zsBT/iOZOy+k0+8l3adH6PTWmvTG F86AIruqA1rAzQFImNJ5mjzGfe5tYCh5zSZDDX317cNic1v1r5uyOVe X-Developer-Key: i=ciprian.regus@analog.com; a=ed25519; pk=8WoNhI0kQcQUl8YqJO5ZevROYk9HP8lOIeIgIYgjfbc= X-Endpoint-Received: by B4 Relay for ciprian.regus@analog.com/20260330 with auth_id=703 X-Original-From: Ciprian Regus Reply-To: ciprian.regus@analog.com From: Ciprian Regus Some PHYs support direct C45 register access but not C22 indirect MMD access (registers 0xD and 0xE). When discovered via C22, phylib routes MMD access through the indirect path, which won't work on these devices. Add genphy_read_mmd_c45() and genphy_write_mmd_c45() as read_mmd/ write_mmd callbacks that bypass the C22 indirect path and use the bus C45 accessors directly. Reviewed-by: Andrew Lunn Signed-off-by: Ciprian Regus --- v3 changelog: - no change v2 changelog: - New patch --- drivers/net/phy/phy_device.c | 25 +++++++++++++++++++++++++ include/linux/phy.h | 3 +++ 2 files changed, 28 insertions(+) diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index 3370eb822017..d33d096e700d 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -2764,6 +2764,31 @@ int genphy_read_abilities(struct phy_device *phydev) } EXPORT_SYMBOL(genphy_read_abilities); =20 +/* Some PHYs support direct C45 register access but not C22 indirect + * MMD access (registers 13 and 14). When discovered via C22, phylib + * routes MMD access through the indirect path, which won't work on + * these devices. These helpers bypass indirect access and use the bus + * C45 accessors directly. + */ +int genphy_read_mmd_c45(struct phy_device *phydev, int devnum, u16 regnum) +{ + struct mii_bus *bus =3D phydev->mdio.bus; + int addr =3D phydev->mdio.addr; + + return __mdiobus_c45_read(bus, addr, devnum, regnum); +} +EXPORT_SYMBOL(genphy_read_mmd_c45); + +int genphy_write_mmd_c45(struct phy_device *phydev, int devnum, u16 regnum, + u16 val) +{ + struct mii_bus *bus =3D phydev->mdio.bus; + int addr =3D phydev->mdio.addr; + + return __mdiobus_c45_write(bus, addr, devnum, regnum, val); +} +EXPORT_SYMBOL(genphy_write_mmd_c45); + /* This is used for the phy device which doesn't support the MMD extended * register access, but it does have side effect when we are trying to acc= ess * the MMD register via indirect method. diff --git a/include/linux/phy.h b/include/linux/phy.h index 199a7aaa341b..432d44188dbc 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -2297,6 +2297,9 @@ static inline int genphy_no_config_intr(struct phy_de= vice *phydev) { return 0; } +int genphy_read_mmd_c45(struct phy_device *phydev, int devnum, u16 regnum); +int genphy_write_mmd_c45(struct phy_device *phydev, int devnum, u16 regnum, + u16 val); int genphy_read_mmd_unsupported(struct phy_device *phdev, int devad, u16 regnum); int genphy_write_mmd_unsupported(struct phy_device *phdev, int devnum, --=20 2.43.0 From nobody Mon Jun 8 08:30:33 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 73A30481AB0; Thu, 4 Jun 2026 16:33:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780590780; cv=none; b=sw/Ai61bZD+URygggpkSvBLIOzdSVvizLCkGZwdGh5fhNf3K2vybd7OwjEw+UqIOIrsBfAouJGHgZ/lm7ooPEwJMLjK1Mkn0eqErMH1at7tJDzwJPbEz7WXQdioZvMYJkSaQ+Vkct+j9jChHQliEbZIN4KbO8ETk5EpA/JuyS78= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780590780; c=relaxed/simple; bh=+0sz9FwBA9o5uFK67oULtBM3+uyl7upIRQbA6uFPnQg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=j0IFhPGE89o9jXgsyZRq2U52bYxofCwsnYiA1qH9YZsi54XFq4ttVLswmfI1UKnyXC1SYwlj2y6aDt1eGczlw3ql2t7CdrGn3kohw3UgBP9SCfs1G88X7DADV6sxBmOcb8s2Ky58I0YnR/Vhf9sNEUNycH2NSPunznyCcSqC+UU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=R8YDfcGE; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="R8YDfcGE" Received: by smtp.kernel.org (Postfix) with ESMTPS id 4CCF3C2BCF6; Thu, 4 Jun 2026 16:33:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1780590780; bh=+0sz9FwBA9o5uFK67oULtBM3+uyl7upIRQbA6uFPnQg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=R8YDfcGEmEdmj1BR3bC54doqcaMJgi7+rHqEpFZrHGoapO9J0GnCedG/9LlcUzlyp 7ew5vn8IY8D8jXVxbd+dklJ0cFm9VzOnAAnVNfKm4j8ts3D0YturL+6rUp0nuH1bho y8rXTArgofGvWdUl+kPTOI9LhZvyrSegl5Cvt71p5MSAYXLbqiicxBTTkAxSHr1hgG TLlu1MyYeVpAmjcCpjb/BAQEIAqr/yfyRu95Vke6MDjj5LvCy8vhCs5H37Dl8tzhfi BXyyAeyZqrv9tKc1BHmgo3ugQqeBiNV4aJ9nkYdi2zvFk3krTpGggw0qOwd+CIb0+P IONJu4YB0R5vw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F103CD6E77; Thu, 4 Jun 2026 16:33:00 +0000 (UTC) From: Ciprian Regus via B4 Relay Date: Thu, 04 Jun 2026 19:32:56 +0300 Subject: [PATCH net-next v3 11/13] net: phy: microchip-t1s: use generic C45 MMD access helpers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260604-adin1140-driver-v3-11-5debdb3173c4@analog.com> References: <20260604-adin1140-driver-v3-0-5debdb3173c4@analog.com> In-Reply-To: <20260604-adin1140-driver-v3-0-5debdb3173c4@analog.com> To: Parthiban Veerasooran , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Jonathan Corbet , Shuah Khan , Andrew Lunn , Heiner Kallweit , Russell King , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, devicetree@vger.kernel.org, Ciprian Regus X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780590775; l=2613; i=ciprian.regus@analog.com; s=20260330; h=from:subject:message-id; bh=faPK/DX3mw0tSktXa1fye/FIW++DcevQxjmxvyg/zD8=; b=ud7NKDkrBW2tKYUXhENLT+NeqhArjh9XfyDFsn08aYyNXptmF+q8Nz2HPNRWMrRlIzFUiVKx2 mWJ6/nxYDOuDth3DTvaOWsDXSDyHW5VPLMn3RQp2FAZbXtAavGOg5Lr X-Developer-Key: i=ciprian.regus@analog.com; a=ed25519; pk=8WoNhI0kQcQUl8YqJO5ZevROYk9HP8lOIeIgIYgjfbc= X-Endpoint-Received: by B4 Relay for ciprian.regus@analog.com/20260330 with auth_id=703 X-Original-From: Ciprian Regus Reply-To: ciprian.regus@analog.com From: Ciprian Regus Replace the driver specific lan865x_phy_read_mmd() and lan865x_phy_write_mmd() with the shared genphy_read_mmd_c45() and genphy_write_mmd_c45() helpers. No functional change. Reviewed-by: Andrew Lunn Signed-off-by: Ciprian Regus --- v3 changelog: - no change v2 changelog: - New patch --- drivers/net/phy/microchip_t1s.c | 32 ++------------------------------ 1 file changed, 2 insertions(+), 30 deletions(-) diff --git a/drivers/net/phy/microchip_t1s.c b/drivers/net/phy/microchip_t1= s.c index e601d56b2507..73c23d311d72 100644 --- a/drivers/net/phy/microchip_t1s.c +++ b/drivers/net/phy/microchip_t1s.c @@ -506,34 +506,6 @@ static int lan86xx_read_status(struct phy_device *phyd= ev) return 0; } =20 -/* OPEN Alliance 10BASE-T1x compliance MAC-PHYs will have both C22 and - * C45 registers space. If the PHY is discovered via C22 bus protocol it a= ssumes - * it uses C22 protocol and always uses C22 registers indirect access to a= ccess - * C45 registers. This is because, we don't have a clean separation between - * C22/C45 register space and C22/C45 MDIO bus protocols. Resulting, PHY C= 45 - * registers direct access can't be used which can save multiple SPI bus a= ccess. - * To support this feature, set .read_mmd/.write_mmd in the PHY driver to = call - * .read_c45/.write_c45 in the OPEN Alliance framework - * drivers/net/ethernet/oa_tc6.c - */ -static int lan865x_phy_read_mmd(struct phy_device *phydev, int devnum, - u16 regnum) -{ - struct mii_bus *bus =3D phydev->mdio.bus; - int addr =3D phydev->mdio.addr; - - return __mdiobus_c45_read(bus, addr, devnum, regnum); -} - -static int lan865x_phy_write_mmd(struct phy_device *phydev, int devnum, - u16 regnum, u16 val) -{ - struct mii_bus *bus =3D phydev->mdio.bus; - int addr =3D phydev->mdio.addr; - - return __mdiobus_c45_write(bus, addr, devnum, regnum, val); -} - static struct phy_driver microchip_t1s_driver[] =3D { { PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVB1), @@ -584,8 +556,8 @@ static struct phy_driver microchip_t1s_driver[] =3D { .features =3D PHY_BASIC_T1S_P2MP_FEATURES, .config_init =3D lan865x_revb_config_init, .read_status =3D lan86xx_read_status, - .read_mmd =3D lan865x_phy_read_mmd, - .write_mmd =3D lan865x_phy_write_mmd, + .read_mmd =3D genphy_read_mmd_c45, + .write_mmd =3D genphy_write_mmd_c45, .get_plca_cfg =3D genphy_c45_plca_get_cfg, .set_plca_cfg =3D lan86xx_plca_set_cfg, .get_plca_status =3D genphy_c45_plca_get_status, --=20 2.43.0 From nobody Mon Jun 8 08:30:33 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 92936481FB9; Thu, 4 Jun 2026 16:33:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780590780; cv=none; b=dTfTnosLbepa+fmmUmMLUs3RxFyf0Zhm8aAnqEhv3G7TwDiMOiOxlo2oTW3nKjlDWoDZGmjgUON1wRtuJ+CBQ+gmV+1637Y1GPE5eFEG0GqI5sydxmZNAtDihX2AiNVnS7Mn+/hhaByMbPwimrTSVva8aoX4mtclha+GR08KeII= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780590780; c=relaxed/simple; bh=nY2LkXEzThAgdXIYf13ZUXPSsIevar8YNJIfg3L8i6E=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=e/7Zi9VVakX52bS7NflXq+i99aVedv6V7MBhidmeOUJehb13vxxc4Gjz4wGCaxTzEUil5XQqU0HCU515KENg1L8AfChXU7WPBCoSB3Yc+I3OempQ57uGMfxEiA/DcRgQdbW3AR+Mzpqo5xMI/PvhmG9aagc0X2HU2TWi091F8MQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=RXyobn88; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="RXyobn88" Received: by smtp.kernel.org (Postfix) with ESMTPS id 5F596C2BCC9; Thu, 4 Jun 2026 16:33:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1780590780; bh=nY2LkXEzThAgdXIYf13ZUXPSsIevar8YNJIfg3L8i6E=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=RXyobn88RzhXTOTGpCz5C5cGGml5v3E3nPy7RHGYZACCyffzswET2kCZ/eVRnj9WP jSoMaQw061vdiudHYzFnTj618q1fH+w7ti6fGVZk/cDIL8h8CkGWsaN/528w4UL7jz h7zi2wrtKFRTtyREUTqderUAnw+qtG4iMVKzZ9Pi/NnB2gbMV+ljMGS8z5baKkKrH3 Ts+lc/xEHmuNTOt4GxDlIQsYsSqOloxp8z1m5IOJymeDw7zSsHZu4L5lqvWVc9mBcD TUuwopMvrtQP4cu/j0TFu/MLDGtj8vr3Sy4LWESFDXqKmiGB/UeW3YXynqDT/3s2Zz eIaoHitV0tNsw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51BF3CD6E7E; Thu, 4 Jun 2026 16:33:00 +0000 (UTC) From: Ciprian Regus via B4 Relay Date: Thu, 04 Jun 2026 19:32:57 +0300 Subject: [PATCH net-next v3 12/13] net: phy: Add support for the ADIN1140 PHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260604-adin1140-driver-v3-12-5debdb3173c4@analog.com> References: <20260604-adin1140-driver-v3-0-5debdb3173c4@analog.com> In-Reply-To: <20260604-adin1140-driver-v3-0-5debdb3173c4@analog.com> To: Parthiban Veerasooran , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Jonathan Corbet , Shuah Khan , Andrew Lunn , Heiner Kallweit , Russell King , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, devicetree@vger.kernel.org, Ciprian Regus X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780590775; l=5029; i=ciprian.regus@analog.com; s=20260330; h=from:subject:message-id; bh=RQGJdAG/JyjBdhMCySkkhNvD6tajxV5dzXkURkDlPKM=; b=54bKJ5+RmCnQPq0cAuBbnLuQt5ctS60eYkLOO1v1oNRGa1tjlQ6B9S8n8hgLdJ7G4oPfvapLx 0kwvTZzDWpKDSA7FQRorvJxlnSqDJ14P0LzoRJEgnNdXRJB+evvywxL X-Developer-Key: i=ciprian.regus@analog.com; a=ed25519; pk=8WoNhI0kQcQUl8YqJO5ZevROYk9HP8lOIeIgIYgjfbc= X-Endpoint-Received: by B4 Relay for ciprian.regus@analog.com/20260330 with auth_id=703 X-Original-From: Ciprian Regus Reply-To: ciprian.regus@analog.com From: Ciprian Regus Add a driver for the ADIN1140's internal 10BASE-T1S PHY. The device doesn't implement autonegotiation, so the link is always reported as being up. The device implements both C22 and C45 MDIO access methods, but can only be discovered over C22, since the C45 MMD devices lack the MDIO_DEVID1 and MDIO_DEVID2 registers. The indirect C45 over C22 feature is not supported. Reviewed-by: Andrew Lunn Signed-off-by: Ciprian Regus --- v3 changelog: - no change v2 changelog: - No longer setting PHY_MAC_INTERRUPT in order to avoid state polling. - Replace the driver specific .read/write_mmd() functions with the ones exported from genphy. - Renamed the file to adin1140-phy.c in order to avoid module name conflicts with the adin1140 ethernet driver. --- MAINTAINERS | 7 ++++ drivers/net/phy/Kconfig | 6 ++++ drivers/net/phy/Makefile | 1 + drivers/net/phy/adin1140-phy.c | 72 ++++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 86 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index ca6c7425b45f..eda74f3154dc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1857,6 +1857,13 @@ S: Supported W: https://ez.analog.com/linux-software-drivers F: drivers/dma/dma-axi-dmac.c =20 +ANALOG DEVICES INC ETHERNET PHY DRIVERS +M: Ciprian Regus +L: netdev@vger.kernel.org +S: Maintained +W: https://ez.analog.com/linux-software-drivers +F: drivers/net/phy/adin1140-phy.c + ANALOG DEVICES INC IIO DRIVERS M: Lars-Peter Clausen M: Michael Hennerich diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 8b51bdc2e945..bd21a5dad366 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -124,6 +124,12 @@ config ADIN1100_PHY Currently supports the: - ADIN1100 - Robust,Industrial, Low Power 10BASE-T1L Ethernet PHY =20 +config ADIN1140_PHY + tristate "Analog Devices ADIN1140 10BASE-T1S PHY" + help + Adds support for the Analog Devices, Inc. ADIN1140's internal + 10BASE-T1S PHY. + config AMCC_QT2025_PHY tristate "AMCC QT2025 PHY" depends on RUST_PHYLIB_ABSTRACTIONS diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 05e4878af27a..73152845b0b2 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -29,6 +29,7 @@ obj-y +=3D $(sfp-obj-y) $(sfp-obj-m) =20 obj-$(CONFIG_ADIN_PHY) +=3D adin.o obj-$(CONFIG_ADIN1100_PHY) +=3D adin1100.o +obj-$(CONFIG_ADIN1140_PHY) +=3D adin1140-phy.o obj-$(CONFIG_AIR_EN8811H_PHY) +=3D air_en8811h.o obj-$(CONFIG_AMD_PHY) +=3D amd.o obj-$(CONFIG_AMCC_QT2025_PHY) +=3D qt2025.o diff --git a/drivers/net/phy/adin1140-phy.c b/drivers/net/phy/adin1140-phy.c new file mode 100644 index 000000000000..d35da4ad680d --- /dev/null +++ b/drivers/net/phy/adin1140-phy.c @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Driver for Analog Devices, Inc. ADIN1140 10BASE-T1S PHY + * + * Copyright 2026 Analog Devices Inc. + */ + +#include +#include +#include + +#define ADIN1140_PHY_ID 0x0283be00 + +#define ADIN1140_PCS_CTRL 0x08f3 +#define ADIN1140_PCS_CTRL_LOOPBACK BIT(14) + +static int adin1140_config_aneg(struct phy_device *phydev) +{ + /* phylib tries to clear BIT(12) in MDIO_CTRL1, since AN is disabled. + * However, on the ADIN1140, that field is non-standard, being used + * to control the reset status of the PHY (thus it needs to remain set). + */ + return 0; +} + +static int adin1140_loopback(struct phy_device *phydev, bool enable, int s= peed) +{ + if (enable && speed) + return -EOPNOTSUPP; + + return phy_modify_mmd(phydev, MDIO_MMD_PCS, ADIN1140_PCS_CTRL, + ADIN1140_PCS_CTRL_LOOPBACK, + enable ? ADIN1140_PCS_CTRL_LOOPBACK : 0); +} + +static int adin1140_read_status(struct phy_device *phydev) +{ + phydev->link =3D 1; + phydev->duplex =3D DUPLEX_HALF; + phydev->speed =3D SPEED_10; + phydev->autoneg =3D AUTONEG_DISABLE; + + return 0; +} + +static struct phy_driver adin1140_driver[] =3D { + { + PHY_ID_MATCH_EXACT(ADIN1140_PHY_ID), + .name =3D "ADIN1140_PHY", + .features =3D PHY_BASIC_T1S_P2MP_FEATURES, + .read_status =3D adin1140_read_status, + .config_aneg =3D adin1140_config_aneg, + .set_loopback =3D adin1140_loopback, + .read_mmd =3D genphy_read_mmd_c45, + .write_mmd =3D genphy_write_mmd_c45, + .get_plca_cfg =3D genphy_c45_plca_get_cfg, + .set_plca_cfg =3D genphy_c45_plca_set_cfg, + .get_plca_status =3D genphy_c45_plca_get_status, + }, +}; +module_phy_driver(adin1140_driver); + +static const struct mdio_device_id __maybe_unused adin1140_tbl[] =3D { + { PHY_ID_MATCH_EXACT(ADIN1140_PHY_ID) }, + { } +}; + +MODULE_DEVICE_TABLE(mdio, adin1140_tbl); + +MODULE_DESCRIPTION("Analog Devices, Inc. ADIN1140 10BASE-T1S PHY"); +MODULE_AUTHOR("Ciprian Regus "); +MODULE_LICENSE("GPL"); --=20 2.43.0 From nobody Mon Jun 8 08:30:33 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 92635481FB7; Thu, 4 Jun 2026 16:33:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780590780; cv=none; b=stOTkVaKUfO+FwxhMHg2YOhVdifIZhitSH0bOcxom40AW/FXDha0/TzGb88XVmOCES42NwZhjz4IMEP4zz8cm5CJb6dMw0xZd7EKupbWUe13ECovsm2fTwhh8acse+VafZc7Lgt6sskaEu3XgwE6FobZRSwZ2uBslt4Cc8P42Ps= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780590780; c=relaxed/simple; bh=rLLWXS4ozV6bkR5ClqKB7/M69q2+LRjfsLMePclB8j4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=UQhdX1p4x8LWdfegrT78bVTajmLvpFM/EXasQs2lZ7ReE/dWzlYzekHXEuHiCoLWDm2B9Iz68dTm9/i6vJwx6dDs4tt3hPYYAKmloRpCCNWkZQ08wmfANbSWlWs+tDeQMN64QGLGO+8YSys+QDwtn1EL5i6UfOKyaT/+ykvi5aQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=BzHrCipd; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="BzHrCipd" Received: by smtp.kernel.org (Postfix) with ESMTPS id 6FF06C2BCF5; Thu, 4 Jun 2026 16:33:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1780590780; bh=rLLWXS4ozV6bkR5ClqKB7/M69q2+LRjfsLMePclB8j4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=BzHrCipdkcC3f45mPneXdFQ5ODHITrjbdED1Vp3bf8BL0v7xZ6jgnIqvcYCurjSaA YaHaY1ws+t5/S7sMTjKOlAnt2+0LxnsIpY9enRqKJkiR1Bc+vkPFMbCKNYqVKA2hEZ OwwE/6E0gV6jEd3jxtC1W59SwU6YekMufuMl/3o9SWeGk6bmEP6VlNY1OjHAQ1QFt1 ZqAP6HyMsO+dpQY4gIjlnfppqqoLYc4f3LZCaBtSyBYWP5t1w0WTFiJdMAlpV1ReK1 CuI/KotiKy/8w44pMgfT6O3x3hs6k7rfBpOchJVGgZSXKstEEpnAZUaGu5bzcv/P9c 9rSWio1bEj5AA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63510CD6E75; Thu, 4 Jun 2026 16:33:00 +0000 (UTC) From: Ciprian Regus via B4 Relay Date: Thu, 04 Jun 2026 19:32:58 +0300 Subject: [PATCH net-next v3 13/13] net: ethernet: adi: Add a driver for the ADIN1140 MACPHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260604-adin1140-driver-v3-13-5debdb3173c4@analog.com> References: <20260604-adin1140-driver-v3-0-5debdb3173c4@analog.com> In-Reply-To: <20260604-adin1140-driver-v3-0-5debdb3173c4@analog.com> To: Parthiban Veerasooran , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Jonathan Corbet , Shuah Khan , Andrew Lunn , Heiner Kallweit , Russell King , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, devicetree@vger.kernel.org, Ciprian Regus X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780590775; l=30071; i=ciprian.regus@analog.com; s=20260330; h=from:subject:message-id; bh=HSV8nsa2UzrJv2aOst0+rJwlNliZQfqkkbI6RjiAoR8=; b=/jRXmeAAz4jrD9W4KStiD61JLNwmf3ZvV37G3K11gxKwCpvquH15Uz+KDyYXUfw7M5kcw+icT S3/tF0LE1AUCgStyrMk9/cRqptqUoV5CW9jFHcJc5Eh7OBV0L1OZ2US X-Developer-Key: i=ciprian.regus@analog.com; a=ed25519; pk=8WoNhI0kQcQUl8YqJO5ZevROYk9HP8lOIeIgIYgjfbc= X-Endpoint-Received: by B4 Relay for ciprian.regus@analog.com/20260330 with auth_id=703 X-Original-From: Ciprian Regus Reply-To: ciprian.regus@analog.com From: Ciprian Regus Add a driver for ADIN1140. The device is a 10BASE-T1S MAC-PHY (integrated in the same package) that connects to a CPU over an SPI bus, and implements the Open Alliance TC6 protocol for control and frame transfers. As such, this driver relies on oa_tc6 for the communication with the device. The device has an alternative name (AD3306), so the driver can be probed using one of the two compatible strings. For control transactions, ADIN1140 only implements the protected mode. The driver has a custom implementation for the mii_bus access methods as a workaround for hardware issues: 1. The OA TC6 standard defines the direct and indirect access modes for MDIO transactions. The ADIN1140 incorrectly advertises indirect mode only (supported capabilities register - 0x2, bit 9), while actually implementing just the direct mode. We cannot rely on the CAP register to choose an access method (which oa_tc6 does by default, even though it only implements the direct mode), so the driver has to use its own. 2. The ADIN1140 cannot access the C22 register space of the internal PHY, while the PHY is busy receiving frames. If that happens, the CONFIG0 and CONFIG2 registers of the MAC will get corrupted and the data transfer will stop. Those two registers configure settings for the transfer protocol between the MAC and host, so the value for some of their subfields shouldn't be changed while the netdev is up. Since we know the PHY is internal, the MAC driver can implement a custom mii_bus, which can intercept C22 accesses. Most of the registers mapped in the 0x0 - 0x3 range (the only ones the PHY offers) are read only, and their value can be read from somewhere else (e.g the PHYID 1 & 2 have the same value as 0x1 in the MAC memory map). For the fields that are R/W (loopback and AN/reset) in the control register, the PHY driver already implements the set_loopback() and config_aneg() functions. The C22 write function of the driver is a no-op and is used to protect against the ioctl MDIO access path. C45 accesses do not cause this issue, so we can properly implement them. Signed-off-by: Ciprian Regus --- v3 changelog: - Clear the unused destination address filter slots in adin1140_rx_mode_work(). This is required in case we remove multicast or unicast addresses from a netdev. - The device only allows destination MAC masks for the first 2 slots. Fix adin1140_mac_filter_set() to take this into account. - use oa_tc6_{write,read}_register_mms, since the OA_TC6_MMS_REG() macro was removed. Update the register address defines accordingly. - use the devres API for mdio and netdev alloc/register instead of manually managing those. - use dev_err_probe() in several places to simplify logging during probe. - use scoped_guard() instead of spin_lock/unlock(). Had to break some sequences in their own function to fit the 80 character limit. - fix the comment describing the reason for skb padding in the TX path. v2 changelog: - Exported statistics that match the ethtool_stats entries as such and kept the other ones custom, using ethtool strings. - Used phy_do_ioctl_running() for ndo_eth_ioctl. - Adapted the mii_bus and PHY handling to the newly added OA_TC6_BROKEN_PHY flag for oa_tc6. - Used the oa_tc6_mdiobus_read_c45/oa_tc6_mdiobus_write_c45 functions for the C45 read/write mii_bus operations. - Removed OA TC6 register definitions (e.g CONFIG2) from the adin1140 driver and instead used the ones exported from oa_tc6.h - Used OA_TC6_MMS_REG to define MMS registers instead of ADIN1140_MMS_REG. - Returned default values for the MII_PHYSID1/MII_PHYSID2. - Set the mii_bus->phy_mask, since the the same PHY will be registered 32 times otherwise. - Updated the MAINTAINERS entry to include the dt-bindings. --- MAINTAINERS | 8 + drivers/net/ethernet/adi/Kconfig | 12 + drivers/net/ethernet/adi/Makefile | 1 + drivers/net/ethernet/adi/adin1140.c | 815 ++++++++++++++++++++++++++++++++= ++++ 4 files changed, 836 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index eda74f3154dc..3d6da16c4312 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1857,6 +1857,14 @@ S: Supported W: https://ez.analog.com/linux-software-drivers F: drivers/dma/dma-axi-dmac.c =20 +ANALOG DEVICES INC ETHERNET DRIVERS +M: Ciprian Regus +L: netdev@vger.kernel.org +S: Maintained +W: https://ez.analog.com/linux-software-drivers +F: Documentation/devicetree/bindings/net/adi,adin1140.yaml +F: drivers/net/ethernet/adi/adin1140.c + ANALOG DEVICES INC ETHERNET PHY DRIVERS M: Ciprian Regus L: netdev@vger.kernel.org diff --git a/drivers/net/ethernet/adi/Kconfig b/drivers/net/ethernet/adi/Kc= onfig index 760a9a60bc15..bdb8ff7d15da 100644 --- a/drivers/net/ethernet/adi/Kconfig +++ b/drivers/net/ethernet/adi/Kconfig @@ -26,4 +26,16 @@ config ADIN1110 Say yes here to build support for Analog Devices ADIN1110 Low Power 10BASE-T1L Ethernet MAC-PHY. =20 +config ADIN1140 + tristate "Analog Devices ADIN1140 MAC-PHY" + depends on SPI + select ADIN1140_PHY + select OA_TC6 + help + Say yes here to build support for Analog Devices, Inc. ADIN1140 + 10BASE-T1S Ethernet MAC-PHY. + + To compile this driver as a module, choose M here. The module will be + called adin1140. + endif # NET_VENDOR_ADI diff --git a/drivers/net/ethernet/adi/Makefile b/drivers/net/ethernet/adi/M= akefile index d0383d94303c..0390ca8ccc49 100644 --- a/drivers/net/ethernet/adi/Makefile +++ b/drivers/net/ethernet/adi/Makefile @@ -4,3 +4,4 @@ # =20 obj-$(CONFIG_ADIN1110) +=3D adin1110.o +obj-$(CONFIG_ADIN1140) +=3D adin1140.o diff --git a/drivers/net/ethernet/adi/adin1140.c b/drivers/net/ethernet/adi= /adin1140.c new file mode 100644 index 000000000000..358e9a11c993 --- /dev/null +++ b/drivers/net/ethernet/adi/adin1140.c @@ -0,0 +1,815 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Driver for Analog Devices, Inc. ADIN1140 10BASE-T1S MAC-PHY + * + * Copyright 2026 Analog Devices Inc. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define ADIN1140_CONFIG2_FWD_UNK2HOST BIT(2) + +#define ADIN1140_MAC_P1_LOOP_ADDR_REG 0xC4 + +#define ADIN1140_MAC_ADDR_FILT_UPR_REG 0x50 +#define ADIN1140_MAC_ADDR_FILT_APPLY2PORT1 BIT(30) +#define ADIN1140_MAC_ADDR_FILT_TO_HOST BIT(16) + +#define ADIN1140_MAC_ADDR_FILT_LWR_REG 0x51 + +#define ADIN1140_MAC_ADDR_MASK_UPR_REG 0x70 +#define ADIN1140_MAC_ADDR_MASK_LWR_REG 0x71 + +#define ADIN1140_MAC_FILT_MC_SLOT 0U +#define ADIN1140_MAC_FILT_BC_SLOT 1U +#define ADIN1140_MAC_FILT_UC_SLOT 2U +#define ADIN1140_MAC_FILT_MAX_SLOT 16U +#define ADIN1140_MAC_FILT_MASK_LIMIT 2U + +#define ADIN1140_RX_FRAME_CNT 0xA1 +#define ADIN1140_RX_BC_FRAME_CNT 0xA2 +#define ADIN1140_RX_MC_FRAME_CNT 0xA3 +#define ADIN1140_RX_UC_FRAME_CNT 0xA4 +#define ADIN1140_RX_CRC_ERR_CNT 0xA5 +#define ADIN1140_RX_ALIGN_ERR_CNT 0xA6 +#define ADIN1140_RX_PREAMBLE_ERR_CNT 0xA7 +#define ADIN1140_RX_SHORT_ERR_CNT 0xA8 +#define ADIN1140_RX_LONG_ERR_CNT 0xA9 +#define ADIN1140_RX_PHY_ERR_CNT 0xAA +#define ADIN1140_RX_DRP_FULL_CNT 0xAB +#define ADIN1140_RX_DRP_FILTER_CNT 0xAD +#define ADIN1140_RX_IFG_ERR_CNT 0xAE +#define ADIN1140_TX_FRAME_CNT 0xB1 +#define ADIN1140_TX_BC_FRAME_CNT 0xB2 +#define ADIN1140_TX_MC_FRAME_CNT 0xB3 +#define ADIN1140_TX_UC_FRAME_CNT 0xB4 +#define ADIN1140_TX_SINGLE_COL_CNT 0xB5 +#define ADIN1140_TX_MULTI_COL_CNT 0xB6 +#define ADIN1140_TX_DEFERRED_CNT 0xB7 +#define ADIN1140_TX_LATE_COL_CNT 0xB8 +#define ADIN1140_TX_EXCESS_COL_CNT 0xB9 +#define ADIN1140_TX_UNDERRUN_CNT 0xBA + +/* ADIN1140_MAC_FILT_MAX_SLOT - 3 (multicast, broadcast and unicast + * reserved slots) + */ +#define ADIN1140_MAC_FILT_AVAIL 13U + +#define ADIN1140_PHY_CTRL_DEFAULT 0x1000 +#define ADIN1140_PHY_STATUS_DEFAULT 0x082D +#define ADIN1140_PHY_ID1 0x0283 +#define ADIN1140_PHY_ID2 0xBE00 + +#define ADIN1140_STATS_CHECK_DELAY (3 * HZ) + +enum adin1140_statistics_entry { + rx_frames, + rx_bc_frames, + rx_mc_frames, + rx_uc_frames, + rx_crc_errors, + rx_align_errors, + rx_preamble_errors, + rx_short_frame_errors, + rx_long_frame_errors, + rx_phy_errors, + rx_fifo_full_dropped, + rx_addr_filter_dropped, + rx_ifg_errors, + tx_frames, + tx_bc_frames, + tx_mc_frames, + tx_uc_frames, + tx_single_collision, + tx_multi_collision, + tx_deferred, + tx_late_collision, + tx_excess_collision, + tx_underrun, + ADIN1140_STATS_CNT, +}; + +struct adin1140_statistics_reg { + const char *name; + enum adin1140_statistics_entry idx; +}; + +struct adin1140_priv { + struct net_device *netdev; + struct oa_tc6 *tc6; + struct mii_bus *mdiobus; + struct phy_device *phydev; + struct work_struct rx_mode_work; + struct delayed_work stats_work; + + /* Protects stats[] from concurrent updates in adin1140_stats_work + * and reads in the get_stats functions + */ + spinlock_t stat_lock; + u64 stats[ADIN1140_STATS_CNT]; +}; + +static const u32 adin1140_stat_regs[] =3D { + [rx_frames] =3D ADIN1140_RX_FRAME_CNT, + [rx_bc_frames] =3D ADIN1140_RX_BC_FRAME_CNT, + [rx_mc_frames] =3D ADIN1140_RX_MC_FRAME_CNT, + [rx_uc_frames] =3D ADIN1140_RX_UC_FRAME_CNT, + [rx_crc_errors] =3D ADIN1140_RX_CRC_ERR_CNT, + [rx_align_errors] =3D ADIN1140_RX_ALIGN_ERR_CNT, + [rx_preamble_errors] =3D ADIN1140_RX_PREAMBLE_ERR_CNT, + [rx_short_frame_errors] =3D ADIN1140_RX_SHORT_ERR_CNT, + [rx_long_frame_errors] =3D ADIN1140_RX_LONG_ERR_CNT, + [rx_phy_errors] =3D ADIN1140_RX_PHY_ERR_CNT, + [rx_fifo_full_dropped] =3D ADIN1140_RX_DRP_FULL_CNT, + [rx_addr_filter_dropped] =3D ADIN1140_RX_DRP_FILTER_CNT, + [rx_ifg_errors] =3D ADIN1140_RX_IFG_ERR_CNT, + [tx_frames] =3D ADIN1140_TX_FRAME_CNT, + [tx_bc_frames] =3D ADIN1140_TX_BC_FRAME_CNT, + [tx_mc_frames] =3D ADIN1140_TX_MC_FRAME_CNT, + [tx_uc_frames] =3D ADIN1140_TX_UC_FRAME_CNT, + [tx_single_collision] =3D ADIN1140_TX_SINGLE_COL_CNT, + [tx_multi_collision] =3D ADIN1140_TX_MULTI_COL_CNT, + [tx_deferred] =3D ADIN1140_TX_DEFERRED_CNT, + [tx_late_collision] =3D ADIN1140_TX_LATE_COL_CNT, + [tx_excess_collision] =3D ADIN1140_TX_EXCESS_COL_CNT, + [tx_underrun] =3D ADIN1140_TX_UNDERRUN_CNT, +}; + +static const struct adin1140_statistics_reg adin1140_stats[] =3D { + {.name =3D "rx_unicast_frames", .idx =3D rx_uc_frames}, + {.name =3D "rx_preamble_errors", .idx =3D rx_preamble_errors}, + {.name =3D "rx_ifg_errors", .idx =3D rx_ifg_errors}, + {.name =3D "rx_addr_filter_dropped", .idx =3D rx_addr_filter_dropped}, + {.name =3D "tx_unicast_frames", .idx =3D tx_uc_frames}, +}; + +static int adin1140_mac_filter_set(struct adin1140_priv *priv, + const u8 *addr, const u8 *mask, + u8 slot) +{ + u32 reg_address; + u32 val; + int ret; + + if (slot >=3D ADIN1140_MAC_FILT_MAX_SLOT) + return -ENOSPC; + + reg_address =3D ADIN1140_MAC_ADDR_FILT_UPR_REG + 2 * slot; + + ret =3D oa_tc6_write_register_mms(priv->tc6, OA_TC6_VEND_MMS1, + reg_address, + get_unaligned_be16(&addr[0]) | + ADIN1140_MAC_ADDR_FILT_APPLY2PORT1 | + ADIN1140_MAC_ADDR_FILT_TO_HOST); + if (ret) + return ret; + + reg_address =3D ADIN1140_MAC_ADDR_FILT_LWR_REG + 2 * slot; + ret =3D oa_tc6_write_register_mms(priv->tc6, OA_TC6_VEND_MMS1, + reg_address, + get_unaligned_be32(&addr[2])); + if (ret) + return ret; + + /* Only the first 2 destination MAC filter slots support masking. + * For the other entries, the destination address in the received + * frame must match exactly. + */ + if (slot >=3D ADIN1140_MAC_FILT_MASK_LIMIT) + return 0; + + val =3D get_unaligned_be16(&mask[0]); + reg_address =3D ADIN1140_MAC_ADDR_MASK_UPR_REG + (2 * slot); + + ret =3D oa_tc6_write_register_mms(priv->tc6, OA_TC6_VEND_MMS1, + reg_address, val); + if (ret) + return ret; + + val =3D get_unaligned_be32(&mask[2]); + reg_address =3D ADIN1140_MAC_ADDR_MASK_LWR_REG + (2 * slot); + + return oa_tc6_write_register_mms(priv->tc6, OA_TC6_VEND_MMS1, + reg_address, val); +} + +static int adin1140_mac_filter_clear(struct adin1140_priv *priv, u8 slot) +{ + u8 mask[ETH_ALEN]; + u8 addr[ETH_ALEN]; + + memset(mask, 0xFF, ETH_ALEN); + memset(addr, 0x0, ETH_ALEN); + + return adin1140_mac_filter_set(priv, addr, mask, slot); +} + +static int adin1140_filter_unicast(struct adin1140_priv *priv) +{ + /* Only the first 2 filter slots support masking, so no unicast + * address will ever need a mask. The first slots are used for the + * all multicast and broadcast filter. + */ + return adin1140_mac_filter_set(priv, priv->netdev->dev_addr, NULL, + ADIN1140_MAC_FILT_UC_SLOT); +} + +static int adin1140_filter_all_multicast(struct adin1140_priv *priv, bool = en) +{ + u8 multicast_addr[ETH_ALEN] =3D {1, 0, 0, 0, 0, 0}; + + if (en) + return adin1140_mac_filter_set(priv, multicast_addr, + multicast_addr, + ADIN1140_MAC_FILT_MC_SLOT); + + return adin1140_mac_filter_clear(priv, ADIN1140_MAC_FILT_MC_SLOT); +} + +static int adin1140_filter_broadcast(struct adin1140_priv *priv, bool enab= led) +{ + u8 mask[ETH_ALEN]; + + if (enabled) { + memset(mask, 0xFF, ETH_ALEN); + return adin1140_mac_filter_set(priv, mask, mask, + ADIN1140_MAC_FILT_BC_SLOT); + } + + return adin1140_mac_filter_clear(priv, ADIN1140_MAC_FILT_BC_SLOT); +} + +static int adin1140_default_filter_config(struct adin1140_priv *priv) +{ + int ret; + + ret =3D adin1140_filter_broadcast(priv, true); + if (ret) + return ret; + + return adin1140_filter_unicast(priv); +} + +static int adin1140_promiscuous_mode(struct adin1140_priv *priv, bool enab= led) +{ + int ret; + u32 val; + + ret =3D oa_tc6_read_register(priv->tc6, OA_TC6_REG_CONFIG2, &val); + if (ret) + return ret; + + if (enabled) + val |=3D ADIN1140_CONFIG2_FWD_UNK2HOST; + else + val &=3D ~ADIN1140_CONFIG2_FWD_UNK2HOST; + + return oa_tc6_write_register(priv->tc6, OA_TC6_REG_CONFIG2, val); +} + +static void adin1140_rx_mode_work(struct work_struct *work) +{ + struct adin1140_priv *priv =3D container_of(work, struct adin1140_priv, + rx_mode_work); + struct netdev_hw_addr *ha; + bool all_multi, promisc; + u8 mask[ETH_ALEN]; + u8 start, end; + u32 mac_addrs; + u8 slot, i; + int ret; + + /* The ADIN1140 has 16 dest MAC address filter slots: + * 0 - reserved for all multicast filter. + * 1 - reserved for broadcast filter. + * 2 - reserved for the device's own unicast MAC. + * 3 -> 15 - available for other unicast/multicast filters. + */ + + mac_addrs =3D netdev_uc_count(priv->netdev) + + netdev_mc_count(priv->netdev); + + if (priv->netdev->flags & IFF_PROMISC) { + promisc =3D true; + all_multi =3D false; + } else if (priv->netdev->flags & IFF_ALLMULTI) { + promisc =3D false; + all_multi =3D true; + } else if (mac_addrs <=3D ADIN1140_MAC_FILT_AVAIL) { + promisc =3D false; + all_multi =3D false; + + slot =3D ADIN1140_MAC_FILT_UC_SLOT + 1; + memset(mask, 0xFF, ETH_ALEN); + + netdev_for_each_uc_addr(ha, priv->netdev) { + ret =3D adin1140_mac_filter_set(priv, ha->addr, mask, + slot); + if (ret) + return; + + slot++; + } + + netdev_for_each_mc_addr(ha, priv->netdev) { + ret =3D adin1140_mac_filter_set(priv, ha->addr, mask, + slot); + if (ret) + return; + + slot++; + } + + for (i =3D slot; i < ADIN1140_MAC_FILT_MAX_SLOT; i++) { + ret =3D adin1140_mac_filter_clear(priv, i); + if (ret) + return; + } + + } else { + /* The filter table is full. Enable promisc mode. */ + promisc =3D true; + all_multi =3D false; + + start =3D ADIN1140_MAC_FILT_UC_SLOT + 1; + end =3D ADIN1140_MAC_FILT_MAX_SLOT; + for (i =3D start; i < end; i++) { + ret =3D adin1140_mac_filter_clear(priv, i); + if (ret) + return; + } + } + + ret =3D adin1140_promiscuous_mode(priv, promisc); + if (ret) + return; + + adin1140_filter_all_multicast(priv, all_multi); +} + +static void adin1140_rx_mode(struct net_device *netdev) +{ + struct adin1140_priv *priv =3D netdev_priv(netdev); + + schedule_work(&priv->rx_mode_work); +} + +static void adin1140_stats_work(struct work_struct *work) +{ + struct delayed_work *dwork =3D to_delayed_work(work); + u64 stat_buff[ADIN1140_STATS_CNT] =3D {}; + struct adin1140_priv *priv; + u32 reg_val; + int ret; + u32 i; + + priv =3D container_of(dwork, struct adin1140_priv, stats_work); + + for (i =3D 0; i < ARRAY_SIZE(adin1140_stat_regs); i++) { + ret =3D oa_tc6_read_register_mms(priv->tc6, OA_TC6_VEND_MMS1, + adin1140_stat_regs[i], + ®_val); + if (ret) + break; + + stat_buff[i] =3D reg_val; + } + + scoped_guard(spinlock, &priv->stat_lock) + memcpy(&priv->stats, stat_buff, sizeof(priv->stats)); + + schedule_delayed_work(dwork, ADIN1140_STATS_CHECK_DELAY); +} + +static int adin1140_configure(struct adin1140_priv *priv) +{ + int ret; + + ret =3D oa_tc6_zero_align_receive_frame_enable(priv->tc6); + if (ret) + return ret; + + /* Disable MAC loopback */ + ret =3D oa_tc6_write_register_mms(priv->tc6, OA_TC6_VEND_MMS1, + ADIN1140_MAC_P1_LOOP_ADDR_REG, 0x0); + if (ret) + return ret; + + return adin1140_default_filter_config(priv); +} + +static int adin1140_open(struct net_device *netdev) +{ + struct adin1140_priv *priv =3D netdev_priv(netdev); + + schedule_delayed_work(&priv->stats_work, ADIN1140_STATS_CHECK_DELAY); + + phy_start(netdev->phydev); + netif_start_queue(netdev); + + return 0; +} + +static int adin1140_close(struct net_device *netdev) +{ + struct adin1140_priv *priv =3D netdev_priv(netdev); + + cancel_delayed_work_sync(&priv->stats_work); + + netif_stop_queue(netdev); + phy_stop(netdev->phydev); + + return 0; +} + +static netdev_tx_t adin1140_start_xmit(struct sk_buff *skb, + struct net_device *netdev) +{ + struct adin1140_priv *priv =3D netdev_priv(netdev); + + /* The MAC doesn't automatically pad the frame to a 60 byte minimum + * size in case the host sends a shorter skb, so we have to do it in + * the driver. The FCS will be added by the MAC. + */ + if (skb_put_padto(skb, ETH_ZLEN)) + return NETDEV_TX_OK; + + return oa_tc6_start_xmit(priv->tc6, skb); +} + +static int adin1140_set_mac_address(struct net_device *netdev, void *addr) +{ + struct adin1140_priv *priv =3D netdev_priv(netdev); + struct sockaddr *address =3D addr; + u8 mask[ETH_ALEN]; + int ret; + + ret =3D eth_prepare_mac_addr_change(netdev, addr); + if (ret < 0) + return ret; + + if (ether_addr_equal(address->sa_data, netdev->dev_addr)) + return 0; + + memset(mask, 0xFF, ETH_ALEN); + ret =3D adin1140_mac_filter_set(priv, address->sa_data, mask, + ADIN1140_MAC_FILT_UC_SLOT); + if (ret) + return ret; + + eth_commit_mac_addr_change(netdev, addr); + + return 0; +} + +static void __adin1140_ndo_get_stats64(struct adin1140_priv *priv, + struct rtnl_link_stats64 *storage) +{ + storage->rx_errors =3D priv->stats[rx_crc_errors] + + priv->stats[rx_align_errors] + + priv->stats[rx_preamble_errors] + + priv->stats[rx_short_frame_errors] + + priv->stats[rx_long_frame_errors] + + priv->stats[rx_phy_errors] + + priv->stats[rx_ifg_errors]; + + storage->tx_errors =3D priv->stats[tx_excess_collision] + + priv->stats[tx_underrun]; + + storage->rx_dropped =3D priv->stats[rx_fifo_full_dropped] + + priv->stats[rx_addr_filter_dropped]; + + storage->multicast =3D priv->stats[rx_mc_frames]; + + storage->collisions =3D priv->stats[tx_single_collision] + + priv->stats[tx_multi_collision]; + + storage->rx_length_errors =3D priv->stats[rx_short_frame_errors] + + priv->stats[rx_long_frame_errors]; + storage->rx_over_errors =3D priv->stats[rx_fifo_full_dropped]; + storage->rx_crc_errors =3D priv->stats[rx_crc_errors]; + storage->rx_frame_errors =3D priv->stats[rx_align_errors]; + storage->rx_missed_errors =3D priv->stats[rx_fifo_full_dropped]; + + storage->tx_aborted_errors =3D priv->stats[tx_excess_collision]; + storage->tx_fifo_errors =3D priv->stats[tx_underrun]; + storage->tx_window_errors =3D priv->stats[tx_late_collision]; +} + +static void adin1140_ndo_get_stats64(struct net_device *dev, + struct rtnl_link_stats64 *storage) +{ + struct adin1140_priv *priv =3D netdev_priv(dev); + + storage->rx_packets =3D priv->netdev->stats.rx_packets; + storage->tx_packets =3D priv->netdev->stats.tx_packets; + + storage->rx_bytes =3D priv->netdev->stats.rx_bytes; + storage->tx_bytes =3D priv->netdev->stats.tx_bytes; + + scoped_guard(spinlock, &priv->stat_lock) + __adin1140_ndo_get_stats64(priv, storage); +} + +static void adin1140_get_drvinfo(struct net_device *netdev, + struct ethtool_drvinfo *info) +{ + strscpy(info->driver, "ADIN1140", sizeof(info->driver)); + strscpy(info->bus_info, dev_name(netdev->dev.parent), + sizeof(info->bus_info)); +} + +static void adin1140_get_ethtool_stats(struct net_device *netdev, + struct ethtool_stats *stats, u64 *data) +{ + struct adin1140_priv *priv =3D netdev_priv(netdev); + u32 i; + + scoped_guard(spinlock, &priv->stat_lock) { + for (i =3D 0; i < ARRAY_SIZE(adin1140_stats); i++) + data[i] =3D priv->stats[adin1140_stats[i].idx]; + } +} + +static void adin1140_get_ethtool_strings(struct net_device *netdev, u32 ss= et, + u8 *p) +{ + u32 i; + + switch (sset) { + case ETH_SS_STATS: + for (i =3D 0; i < ARRAY_SIZE(adin1140_stats); i++) + ethtool_puts(&p, adin1140_stats[i].name); + + break; + } +} + +static int adin1140_get_sset_count(struct net_device *netdev, int sset) +{ + switch (sset) { + case ETH_SS_STATS: + return ARRAY_SIZE(adin1140_stats); + default: + return -EOPNOTSUPP; + } +} + +static void __adin1140_eth_mac_stats(struct adin1140_priv *priv, + struct ethtool_eth_mac_stats *mac_stats) +{ + mac_stats->FramesReceivedOK =3D priv->stats[rx_frames]; + mac_stats->BroadcastFramesReceivedOK =3D priv->stats[rx_bc_frames]; + mac_stats->MulticastFramesReceivedOK =3D priv->stats[rx_mc_frames]; + mac_stats->FrameCheckSequenceErrors =3D priv->stats[rx_crc_errors]; + mac_stats->AlignmentErrors =3D priv->stats[rx_align_errors]; + mac_stats->FrameTooLongErrors =3D priv->stats[rx_long_frame_errors]; + mac_stats->FramesLostDueToIntMACRcvError =3D + priv->stats[rx_fifo_full_dropped]; + mac_stats->FramesTransmittedOK =3D priv->stats[tx_frames]; + mac_stats->BroadcastFramesXmittedOK =3D priv->stats[tx_bc_frames]; + mac_stats->MulticastFramesXmittedOK =3D priv->stats[tx_mc_frames]; + mac_stats->SingleCollisionFrames =3D priv->stats[tx_single_collision]; + mac_stats->MultipleCollisionFrames =3D priv->stats[tx_multi_collision]; + mac_stats->FramesWithDeferredXmissions =3D priv->stats[tx_deferred]; + mac_stats->LateCollisions =3D priv->stats[tx_late_collision]; + mac_stats->FramesAbortedDueToXSColls =3D + priv->stats[tx_excess_collision]; + mac_stats->FramesLostDueToIntMACXmitError =3D priv->stats[tx_underrun]; +} + +static void adin1140_get_eth_mac_stats(struct net_device *netdev, + struct ethtool_eth_mac_stats *mac_stats) +{ + struct adin1140_priv *priv =3D netdev_priv(netdev); + + scoped_guard(spinlock, &priv->stat_lock) + __adin1140_eth_mac_stats(priv, mac_stats); +} + +static int adin1140_mdiobus_read(struct mii_bus *bus, int addr, int regnum) +{ + /* The ADIN1140's standard PHY C22 register map (OA TC6 0xFF00 - + * 0xFF1F), of which only 0xFF00 - 0xFF03 are implemented) cannot be + * accessed while frames are being received by the PHY. In case this + * happens the CONFIG0 and CONFIG2 register values will get corrupted, + * getting a random value. Both reads and writes cause the same + * behavior. This is a workaround that avoids MDIO accesses all + * together. Since this is a 10BASE-T1S PHY, only the loopback and + * reset (AN) bits in the control register (0x0) can be written. + * These functionalities have custom implementations in the PHY + * driver. C45 accesses do not cause this issue. + */ + + switch (regnum) { + case MII_BMCR: + return ADIN1140_PHY_CTRL_DEFAULT; + case MII_BMSR: + return ADIN1140_PHY_STATUS_DEFAULT; + case MII_PHYSID1: + return ADIN1140_PHY_ID1; + case MII_PHYSID2: + return ADIN1140_PHY_ID2; + default: + return 0xFFFF; + } +} + +static int adin1140_mdiobus_write(struct mii_bus *bus, int addr, int regnu= m, + u16 val) +{ + return -EIO; +} + +static int adin1140_mdio_register(struct adin1140_priv *priv, + struct spi_device *spidev) +{ + priv->mdiobus =3D devm_mdiobus_alloc(&spidev->dev); + if (!priv->mdiobus) + return dev_err_probe(&spidev->dev, -ENOMEM, + "MDIO bus alloc failed\n"); + + priv->mdiobus->name =3D "adin1140-mdiobus"; + priv->mdiobus->priv =3D priv->tc6; + priv->mdiobus->parent =3D &spidev->dev; + priv->mdiobus->phy_mask =3D GENMASK(31, 1); + priv->mdiobus->read =3D adin1140_mdiobus_read; + priv->mdiobus->write =3D adin1140_mdiobus_write; + priv->mdiobus->read_c45 =3D oa_tc6_mdiobus_read_c45; + priv->mdiobus->write_c45 =3D oa_tc6_mdiobus_write_c45; + + snprintf(priv->mdiobus->id, MII_BUS_ID_SIZE, "adin1140-%s.%u", + dev_name(&spidev->dev), spi_get_chipselect(spidev, 0)); + + return devm_mdiobus_register(&spidev->dev, priv->mdiobus); +} + +static void adin1140_handle_link_change(struct net_device *netdev) +{ + phy_print_status(netdev->phydev); +} + +static void adin1140_phy_remove(void *data) +{ + phy_disconnect(data); +} + +static int adin1140_phy_init(struct adin1140_priv *priv, + struct spi_device *spidev) +{ + int ret; + + ret =3D adin1140_mdio_register(priv, spidev); + if (ret) + return ret; + + priv->phydev =3D phy_find_first(priv->mdiobus); + if (!priv->phydev) + return dev_err_probe(&spidev->dev, -ENODEV, "No PHY found\n"); + + priv->phydev->is_internal =3D true; + ret =3D phy_connect_direct(priv->netdev, priv->phydev, + &adin1140_handle_link_change, + PHY_INTERFACE_MODE_INTERNAL); + if (ret) + return dev_err_probe(&spidev->dev, ret, + "Can't attach PHY to %s\n", + priv->mdiobus->id); + + ret =3D devm_add_action_or_reset(&spidev->dev, adin1140_phy_remove, + priv->phydev); + if (ret) + return ret; + + phy_attached_info(priv->phydev); + + return 0; +} + +static const struct ethtool_ops adin1140_ethtool_ops =3D { + .get_drvinfo =3D adin1140_get_drvinfo, + .get_link =3D ethtool_op_get_link, + .get_ethtool_stats =3D adin1140_get_ethtool_stats, + .get_sset_count =3D adin1140_get_sset_count, + .get_strings =3D adin1140_get_ethtool_strings, + .get_link_ksettings =3D phy_ethtool_get_link_ksettings, + .set_link_ksettings =3D phy_ethtool_set_link_ksettings, + .get_eth_mac_stats =3D adin1140_get_eth_mac_stats, +}; + +static const struct net_device_ops adin1140_netdev_ops =3D { + .ndo_open =3D adin1140_open, + .ndo_stop =3D adin1140_close, + .ndo_start_xmit =3D adin1140_start_xmit, + .ndo_set_mac_address =3D adin1140_set_mac_address, + .ndo_validate_addr =3D eth_validate_addr, + .ndo_set_rx_mode =3D adin1140_rx_mode, + .ndo_eth_ioctl =3D phy_do_ioctl_running, + .ndo_get_stats64 =3D adin1140_ndo_get_stats64, +}; + +static void adin1140_oa_tc6_remove(void *data) +{ + oa_tc6_exit(data); +} + +static void adin1140_cancel_rx_mode_work(void *data) +{ + cancel_work_sync(data); +} + +static int adin1140_probe(struct spi_device *spi) +{ + struct oa_tc6_quirks tc6_quirks =3D {}; + struct net_device *netdev; + struct adin1140_priv *priv; + int ret; + + netdev =3D devm_alloc_etherdev(&spi->dev, sizeof(struct adin1140_priv)); + if (!netdev) + return -ENOMEM; + + priv =3D netdev_priv(netdev); + priv->netdev =3D netdev; + spi_set_drvdata(spi, priv); + spin_lock_init(&priv->stat_lock); + + tc6_quirks.quirk_flags =3D OA_TC6_BROKEN_PHY; + + priv->tc6 =3D oa_tc6_init(spi, netdev, &tc6_quirks); + if (!priv->tc6) + return -ENODEV; + + ret =3D devm_add_action_or_reset(&spi->dev, adin1140_oa_tc6_remove, + priv->tc6); + if (ret) + return ret; + + ret =3D adin1140_phy_init(priv, spi); + if (ret) + return ret; + + if (device_get_ethdev_address(&spi->dev, netdev)) + eth_hw_addr_random(netdev); + + ret =3D adin1140_configure(priv); + if (ret) + return ret; + + INIT_WORK(&priv->rx_mode_work, adin1140_rx_mode_work); + INIT_DELAYED_WORK(&priv->stats_work, adin1140_stats_work); + + ret =3D devm_add_action_or_reset(&spi->dev, adin1140_cancel_rx_mode_work, + &priv->rx_mode_work); + if (ret) + return ret; + + netdev->if_port =3D IF_PORT_10BASET; + netdev->irq =3D spi->irq; + netdev->netdev_ops =3D &adin1140_netdev_ops; + netdev->ethtool_ops =3D &adin1140_ethtool_ops; + netdev->netns_immutable =3D true; + netdev->priv_flags |=3D IFF_LIVE_ADDR_CHANGE | + IFF_UNICAST_FLT; + + ret =3D devm_register_netdev(&spi->dev, netdev); + if (ret) + return dev_err_probe(&spi->dev, ret, + "Failed to register netdev"); + + return 0; +} + +static const struct spi_device_id adin1140_spi_id[] =3D { + { .name =3D "ad3306" }, + { .name =3D "adin1140" }, + {}, +}; +MODULE_DEVICE_TABLE(spi, adin1140_spi_id); + +static const struct of_device_id adin1140_match_table[] =3D { + { .compatible =3D "adi,ad3306" }, + { .compatible =3D "adi,adin1140" }, + { } +}; +MODULE_DEVICE_TABLE(of, adin1140_match_table); + +static struct spi_driver adin1140_driver =3D { + .driver =3D { + .name =3D "adin1140", + .of_match_table =3D adin1140_match_table, + }, + .probe =3D adin1140_probe, + .id_table =3D adin1140_spi_id, +}; +module_spi_driver(adin1140_driver); + +MODULE_DESCRIPTION("Analog Devices, Inc. ADIN1140 10BASE-T1S MAC-PHY"); +MODULE_AUTHOR("Ciprian Regus "); +MODULE_LICENSE("GPL"); --=20 2.43.0