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charset="utf-8" Hopper has its own sysmem flush page registers, but the Hopper framebuffer HAL was still programming the Ampere registers, so the flush address landed in the wrong location. Program Hopper's own registers instead. Open RM and Nouveau disagree on how these registers encode the address. This commit follows Open RM's approach. Note that this is still yet to be confirmed (tested) on real Hopper hardware. Signed-off-by: John Hubbard --- drivers/gpu/nova-core/fb/hal/gb202.rs | 12 +++++------ drivers/gpu/nova-core/fb/hal/gh100.rs | 31 ++++++++++++++++++++++++--- drivers/gpu/nova-core/regs.rs | 27 ++++++++++++++++++----- 3 files changed, 56 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/nova-core/fb/hal/gb202.rs b/drivers/gpu/nova-core/= fb/hal/gb202.rs index 038d1278c634..00554e349bde 100644 --- a/drivers/gpu/nova-core/fb/hal/gb202.rs +++ b/drivers/gpu/nova-core/fb/hal/gb202.rs @@ -30,11 +30,11 @@ impl RegisterBase for Gb202 { =20 fn read_sysmem_flush_page_gb202(bar: Bar0<'_>) -> u64 { let lo =3D u64::from( - bar.read(regs::NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_LO::of::= ()) + bar.read(regs::NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO::of::()) .adr(), ); let hi =3D u64::from( - bar.read(regs::NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI::of::= ()) + bar.read(regs::NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI::of::()) .adr(), ); =20 @@ -45,14 +45,14 @@ fn read_sysmem_flush_page_gb202(bar: Bar0<'_>) -> u64 { fn write_sysmem_flush_page_gb202(bar: Bar0<'_>, addr: Bounded) { // Write HI first. The hardware will trigger the flush on the LO write. bar.write( - regs::NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI::of::(), - regs::NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI::zeroed() + regs::NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI::of::(), + regs::NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI::zeroed() .with_adr(addr.shr::<32, 20>().cast::()), ); bar.write( - regs::NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_LO::of::(), + regs::NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO::of::(), // CAST: lower 32 bits. Hardware ignores bits 7:0. - regs::NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_LO::zeroed().with_adr(*a= ddr as u32), + regs::NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO::zeroed().with_adr(*= addr as u32), ); } =20 diff --git a/drivers/gpu/nova-core/fb/hal/gh100.rs b/drivers/gpu/nova-core/= fb/hal/gh100.rs index 5450c7254dad..6fd4f967cea5 100644 --- a/drivers/gpu/nova-core/fb/hal/gh100.rs +++ b/drivers/gpu/nova-core/fb/hal/gh100.rs @@ -2,24 +2,49 @@ // SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIA= TES. All rights reserved. =20 use kernel::{ + io::Io, + num::Bounded, prelude::*, sizes::SizeConstants, // }; =20 use crate::{ driver::Bar0, - fb::hal::FbHal, // + fb::hal::FbHal, + regs, // }; =20 struct Gh100; =20 +fn read_sysmem_flush_page_gh100(bar: Bar0<'_>) -> u64 { + let lo =3D u64::from(bar.read(regs::NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADD= R_LO).adr()); + let hi =3D u64::from(bar.read(regs::NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADD= R_HI).adr()); + + lo | (hi << 32) +} + +/// Write the sysmem flush page address through the Hopper FBHUB registers. +fn write_sysmem_flush_page_gh100(bar: Bar0<'_>, addr: Bounded) { + // Write HI first. The hardware will trigger the flush on the LO write. + bar.write_reg( + regs::NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI::zeroed() + .with_adr(addr.shr::<32, 20>().cast::()), + ); + bar.write_reg( + // CAST: lower 32 bits. Hardware ignores bits 7:0. + regs::NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_LO::zeroed().with_adr(*a= ddr as u32), + ); +} + impl FbHal for Gh100 { fn read_sysmem_flush_page(&self, bar: Bar0<'_>) -> u64 { - super::ga100::read_sysmem_flush_page_ga100(bar) + read_sysmem_flush_page_gh100(bar) } =20 fn write_sysmem_flush_page(&self, bar: Bar0<'_>, addr: u64) -> Result { - super::ga100::write_sysmem_flush_page_ga100(bar, addr); + let addr =3D Bounded::::try_new(addr).ok_or(EINVAL)?; + + write_sysmem_flush_page_gh100(bar, addr); =20 Ok(()) } diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 0f49c1ab83ad..a57e95140ec0 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -131,6 +131,22 @@ fn fmt(&self, f: &mut kernel::fmt::Formatter<'_>) -> k= ernel::fmt::Result { 23:0 adr_63_40; } =20 + /// Low bits of the physical system memory address used by the GPU to = perform sysmembar + /// operations on Hopper (see [`crate::fb::SysmemFlush`]). + /// + /// Unlike the Ampere `NV_PFB_NISO_FLUSH_SYSMEM_ADDR` registers, which= encode the address with + /// an 8-bit right-shift, the Hopper FBHUB registers take the raw addr= ess split into lower and + /// upper halves. Hardware ignores bits 7:0 of the LO register. + pub(crate) NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_LO(u32) @ 0x00100a34 { + 31:0 adr =3D> u32; + } + + /// High bits of the physical system memory address used by the GPU to= perform sysmembar + /// operations on Hopper (see [`crate::fb::SysmemFlush`]). + pub(crate) NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI(u32) @ 0x00100a38 { + 19:0 adr; + } + pub(crate) NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE(u32) @ 0x00100ce0 { 30:30 ecc_mode_enabled =3D> bool; 9:4 lower_mag; @@ -179,15 +195,16 @@ fn fmt(&self, f: &mut kernel::fmt::Formatter<'_>) -> = kernel::fmt::Result { 19:0 adr; } =20 - // GB20x sysmem flush registers, relative to the FBHUB0 base. Unlike t= he older - // NV_PFB_NISO_FLUSH_SYSMEM_ADDR registers which encode the address wi= th an 8-bit - // right-shift, these take the raw address split into lower and upper = halves. Hardware + // GB20x sysmem flush registers, relative to the FBHUB0 base. Like the= Hopper + // NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR registers, and unlike the older + // NV_PFB_NISO_FLUSH_SYSMEM_ADDR registers (which encode the address w= ith an 8-bit + // right-shift), these take the raw address split into lower and upper= halves. Hardware // ignores bits 7:0 of the LO register. - pub(crate) NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_LO(u32) @ Fbhub0Base + = 0x00001d58 { + pub(crate) NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO(u32) @ Fbhub0Base += 0x00001d58 { 31:0 adr =3D> u32; } =20 - pub(crate) NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI(u32) @ Fbhub0Base + = 0x00001d5c { + pub(crate) NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI(u32) @ Fbhub0Base += 0x00001d5c { 19:0 adr; } } --=20 2.54.0 From nobody Mon Jun 8 09:48:36 2026 Received: from SA9PR02CU001.outbound.protection.outlook.com (mail-southcentralusazon11013035.outbound.protection.outlook.com [40.93.196.35]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D85C64534A8 for ; Wed, 3 Jun 2026 23:50:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.196.35 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780530647; 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charset="utf-8" Two comments in the FSP Chain of Trust message setup had drifted from the code. One referred to a variable name that no longer exists, and another described the unused sysmem FRTS fields as future work rather than explaining why they are zero. Update both to describe the code as it stands. Signed-off-by: John Hubbard --- drivers/gpu/nova-core/fsp.rs | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nova-core/fsp.rs b/drivers/gpu/nova-core/fsp.rs index 8fc243c66e35..0e2c596f695a 100644 --- a/drivers/gpu/nova-core/fsp.rs +++ b/drivers/gpu/nova-core/fsp.rs @@ -110,7 +110,8 @@ fn new<'a>( fsp_fw: &'a FspFirmware, args: &'a FmcBootArgs, ) -> Result + 'a> { - // frts_offset is relative to FB end: FRTS_location =3D FB_END - f= rts_offset + // frts_vidmem_offset is measured from the end of FB, so FRTS sits= at + // (end of FB) - frts_vidmem_offset. let frts_vidmem_offset =3D if !args.resume { let frts_reserved_size =3D fb_layout.heap.len() + u64::from(fb= _layout.pmu_reserved_size); =20 @@ -143,8 +144,8 @@ fn new<'a>( msg.cot.gsp_fmc_sysmem_offset =3D fsp_fw.fmc_image.dma_handle(= ); msg.cot.frts_vidmem_offset =3D frts_vidmem_offset; msg.cot.frts_vidmem_size =3D frts_size; - // frts_sysmem_* intentionally left at zero for now, but will = be needed for e.g. - // systems without VRAM. + // frts_sysmem_* are left at zero because this path places FRT= S in vidmem. The sysmem + // fields point to an FRTS buffer in sysmem instead, for syste= ms without VRAM. msg.cot.gsp_boot_args_sysmem_offset =3D args.fmc_boot_params.d= ma_handle(); msg.cot.sigs =3D *fsp_fw.fmc_sigs; =20 --=20 2.54.0