From nobody Mon Jun 8 08:30:47 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 528E532F748; Wed, 3 Jun 2026 15:17:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780499822; cv=none; b=AJxUqkXfnFJMWEbpexi8S0bPSF4GbIFiwY/8gIvFbCHBa2tI0g4N9s3QCjxfAlXz4MgXNZy5ly4X9jG8tUalKcpsI4XoU4ANW1zF8urr/FRJN/w4+NiH6Z2Y0swJL83EX5SsvnmQFa0XRVrY80B0uUk0rbJYeUBV4txu5E6wIVU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780499822; c=relaxed/simple; bh=NyFiUec/36k2DOCc1WPXAm3C8qjmJZtAAuF0gZHzpEw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=aAS5j88CwRrQFhQ1wsRQPjTZGCVH/WkmT8L+Gim+fSTzxTLAyzlvSAF/HESROuVgkJtu9V+MbhpHS/wGQx9Zr6okSGBh1eOeEhaqJGtJrBBOOGiUW7jlSwYi6yC12oBTig6cufYT4C4eRrGxuDWEf2MnQnQEAtYbSULYMOjoyBE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=kMlO9bSg; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kMlO9bSg" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 916801F00898; Wed, 3 Jun 2026 15:16:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1780499821; bh=XDIwh/usRBAV/ZKdp5/gXu5Q82igijMkQ+3odZ715bY=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=kMlO9bSgDDfK9IaZgh+oRNmQjjS/tJpX6hT3IQt6mzIreMrATDG6ZWsJetANdEjmB A1dLXsBLbq+UzyaTb3i83jVIHAuqkhXi4k9xhoOOmoq5ByXgXzcsib3Kf5/OhNH5Gi tImJKhswvL1dJvPT4vNbQBFGJC5wZ6LvbWMSx+wMf1uttB5K0OPqm2FbPuFnFuhLP7 khN/yUTotX0EwfIA0YZ/sdU8TlVXqvpo+NxnmJiP6YnHzf//KXkr7Rgw73Ts81XVUY 5vvmGAX+1SpNUF8imXG4gSH6uArIHR5ma8cXlZSvskg9YDF9PgQ9uSxkwM8y+XPXMP e2iXMhVi20U+A== From: Claudiu Beznea To: geert+renesas@glider.be, linusw@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, magnus.damm@gmail.com, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: claudiu.beznea@kernel.org, claudiu.beznea@tuxon.dev, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea , stable@vger.kernel.org Subject: [PATCH v3 1/6] pinctrl: renesas: rzg2l: Use raw_spinlock_irqsave() on power source update Date: Wed, 3 Jun 2026 18:16:37 +0300 Message-ID: <20260603151642.4075678-2-claudiu.beznea@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260603151642.4075678-1-claudiu.beznea@kernel.org> References: <20260603151642.4075678-1-claudiu.beznea@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The rest of the driver uses raw_spin_lock_irqsave()/raw_spin_unlock_irqrestore() for locking. To avoid concurrency issues or deadlocks, use raw_spinlock_irqsave() via the scoped_guard() helper for power source updates as well. Fixes: bbe2277dedbe ("pinctrl: renesas: rzg2l: Add support for selecting po= wer source for {WDT,AWO,ISO}") Cc: stable@vger.kernel.org Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- Changes in v3: - none, this patch is new drivers/pinctrl/renesas/pinctrl-rzg2l.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 83c61dcb24b1..be52d47d77ae 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -1137,7 +1137,7 @@ static int rzg2l_set_power_source(struct rzg2l_pinctr= l *pctrl, u32 pin, u32 caps return pwr_reg; =20 if (pwr_reg =3D=3D OTHER_POC) { - scoped_guard(raw_spinlock, &pctrl->lock) { + scoped_guard(raw_spinlock_irqsave, &pctrl->lock) { val =3D readb(pctrl->base + pwr_reg); if (poc_val) val |=3D mask; --=20 2.43.0 From nobody Mon Jun 8 08:30:47 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2F51332F748; Wed, 3 Jun 2026 15:17:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780499826; cv=none; b=rEXU3Xa4hxM4HJI8S6sw1JP37++TfKyWNnqhs5ocv9M8lJBOWhstA8jyGaQM5TLGI3wqnnM/itKJpAbEF1I8MDU+mHNt0IMfbupqgNh/AZIo0EtSXffbypWWHWafWQ6Cf3mxChMdTQFCK3Jou1T3iTo9Jd91aWJcA+JRw5Q/rp0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780499826; c=relaxed/simple; bh=KAwwRlh/RMKVtoyH6mVoeb9aEYeXHypPZwSjpiLIs9A=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XgK7E4UDvLSYzsuR9j8Tcscuwq95JMPDKbr8awF/D5wnoxZ8w48rIn5WAQyMHtYOaZAu7Zchr6ESrouuKtXd+WXUmaqqDZBb/zvbCKmwGconp8+jBvGyppqrx+8uxwrRntCePuKB3NIeKl/fWJMp0nwBtAwVNPWfN55ah3vn8Ew= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=RznotSIb; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="RznotSIb" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6E7341F00893; Wed, 3 Jun 2026 15:17:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1780499824; bh=GLPA1SA17916TqvzHrE/rQnuy4M0MmRD+nnfgguNFsY=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=RznotSIbg+mbFokkGkLlEkJ7PD6plZEfbpuWjfN5fXp21/YKyUUy7POxy157ja4GN ZI10wvQjDta63JyL/BsipFDH3g+X59rP3jIoiHxMc9J1Jqo+vrl8S1/pmoL7u8ZQgM XNvwbQtLwjaaZ4tb9siq67f07SQl/pR/xzFepZ/nZp0Ftt7qWivmEO85LOLVMKc8Ap ossn0zxn3LAn24HnIOi7oJmfYL54c4X6kFFDA8nYRn6KZ9JC124OaYTcK6w4Xo5ne0 p9+ew5SrBo8otz/A/grchoN9vU7esJJIhzyrBj/1A89//30Vj2gW0fFB+08Nnfct/A 4yCHFhyI2bRWA== From: Claudiu Beznea To: geert+renesas@glider.be, linusw@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, magnus.damm@gmail.com, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: claudiu.beznea@kernel.org, claudiu.beznea@tuxon.dev, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea , Wolfram Sang Subject: [PATCH v3 2/6] pinctrl: renesas: rzg2l: Generalize the power source code Date: Wed, 3 Jun 2026 18:16:38 +0300 Message-ID: <20260603151642.4075678-3-claudiu.beznea@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260603151642.4075678-1-claudiu.beznea@kernel.org> References: <20260603151642.4075678-1-claudiu.beznea@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The current functions used to get/set the pin power source check the OTHER_POC register, which is specific to the RZ/G3L SoC only. To allow the code to be extended for other power source functionalities (e.g. I3C on RZ/G3S), generalize the functions used to get/set the pin power source. For this, introduce the struct rzg2l_register_masks data structure whose purpose is to store SoC specific register bit masks. The members of this structure are then used in rzg2l_caps_to_pwr_reg() to retrieve the bitmask corresponding to a SoC specific power source capability. The conversion between HW specific power source values and SW specific power source values is now handled through rzg2l_pwr_reg_val_to_ps() and rzg2l_ps_to_pwr_reg_val(). Finally, to keep the code generic, the register update in rzg2l_set_power_source() was changed to a read-modify-write approach to cover all cases. Tested-by: Wolfram Sang Signed-off-by: Claudiu Beznea --- Changes in v3: - collected tags Changes in v2: - none drivers/pinctrl/renesas/pinctrl-rzg2l.c | 177 +++++++++++++++--------- 1 file changed, 112 insertions(+), 65 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index be52d47d77ae..6f3760851460 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -186,6 +186,7 @@ #define PVDD_2500 2 /* I/O domain voltage 2.5V */ #define PVDD_1800 1 /* I/O domain voltage <=3D 1.8V */ #define PVDD_3300 0 /* I/O domain voltage >=3D 3.3V */ +#define PVDD_MASK 0x3 =20 #define PWPR_B0WI BIT(7) /* Bit Write Disable */ #define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */ @@ -268,6 +269,23 @@ struct rzg2l_register_offsets { u16 other_poc; }; =20 +/** + * struct rzg2l_register_masks - Masks for different RZ/G2L pinctrl functi= onalities + * @other_poc_pvdd1833_oth_awo_poc: PVDD1833_OTH_AWO_POC mask + * @other_poc_pvdd1833_oth_iso_poc: PVDD1833_OTH_ISO_POC mask + * @other_poc_wdtovf_n_poc: WDTOVF_N_POC mask + */ +struct rzg2l_register_masks { + union { + /* RZ/G3L masks */ + struct { + u8 other_poc_pvdd1833_oth_awo_poc; + u8 other_poc_pvdd1833_oth_iso_poc; + u8 other_poc_wdtovf_n_poc; + }; + }; +}; + /** * enum rzg2l_iolh_index - starting indices in IOLH specific arrays * @RZG2L_IOLH_IDX_1V8: starting index for 1V8 power source @@ -288,6 +306,8 @@ enum rzg2l_iolh_index { /** * struct rzg2l_hwcfg - hardware configuration data structure * @regs: hardware specific register offsets + * @masks: hardware specific masks for various functionalities available in + * the registers described by regs * @iolh_groupa_ua: IOLH group A uA specific values * @iolh_groupb_ua: IOLH group B uA specific values * @iolh_groupc_ua: IOLH group C uA specific values @@ -301,6 +321,7 @@ enum rzg2l_iolh_index { */ struct rzg2l_hwcfg { const struct rzg2l_register_offsets regs; + const struct rzg2l_register_masks masks; u16 iolh_groupa_ua[RZG2L_IOLH_IDX_MAX]; u16 iolh_groupb_ua[RZG2L_IOLH_IDX_MAX]; u16 iolh_groupc_ua[RZG2L_IOLH_IDX_MAX]; @@ -1047,27 +1068,73 @@ static void rzg2l_rmw_pin_config(struct rzg2l_pinct= rl *pctrl, u32 offset, } =20 static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs, - u32 caps, u8 *mask) + const struct rzg2l_register_masks *masks, + u32 caps, u16 *offset, u8 *mask) { - if (caps & PIN_CFG_IO_VMC_SD0) - return SD_CH(regs->sd_ch, 0); - if (caps & PIN_CFG_IO_VMC_SD1) - return SD_CH(regs->sd_ch, 1); - if (caps & PIN_CFG_IO_VMC_ETH0) - return ETH_POC(regs->eth_poc, 0); - if (caps & PIN_CFG_IO_VMC_ETH1) - return ETH_POC(regs->eth_poc, 1); - if (caps & PIN_CFG_IO_VMC_QSPI) - return QSPI; + *mask =3D PVDD_MASK; + + if (caps & PIN_CFG_IO_VMC_SD0) { + *offset =3D SD_CH(regs->sd_ch, 0); + return 0; + } + if (caps & PIN_CFG_IO_VMC_SD1) { + *offset =3D SD_CH(regs->sd_ch, 1); + return 0; + } + if (caps & PIN_CFG_IO_VMC_ETH0) { + *offset =3D ETH_POC(regs->eth_poc, 0); + return 0; + } + if (caps & PIN_CFG_IO_VMC_ETH1) { + *offset =3D ETH_POC(regs->eth_poc, 1); + return 0; + } + if (caps & PIN_CFG_IO_VMC_QSPI) { + *offset =3D regs->qspi; + return 0; + } if (caps & PIN_CFG_OTHER_POC_MASK) { + *offset =3D regs->other_poc; if (caps & PIN_CFG_PVDD1833_OTH_AWO_POC) - *mask =3D BIT(0); + *mask =3D masks->other_poc_pvdd1833_oth_awo_poc; else if (caps & PIN_CFG_PVDD1833_OTH_ISO_POC) - *mask =3D BIT(1); + *mask =3D masks->other_poc_pvdd1833_oth_iso_poc; else - *mask =3D BIT(2); + *mask =3D masks->other_poc_wdtovf_n_poc; + return 0; + } =20 - return OTHER_POC; + return -EINVAL; +} + +static int rzg2l_pwr_reg_val_to_ps(u8 val, u32 caps) +{ + switch (val) { + case PVDD_1800: + return 1800; + case PVDD_2500: + return 2500; + case PVDD_3300: + return 3300; + } + + return -EINVAL; +} + +static int rzg2l_ps_to_pwr_reg_val(u8 *val, u32 ps, u32 caps) +{ + switch (ps) { + case 1800: + *val =3D PVDD_1800; + return 0; + case 2500: + if (!(caps & (PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1))) + return -EINVAL; + *val =3D PVDD_2500; + return 0; + case 3300: + *val =3D PVDD_3300; + return 0; } =20 return -EINVAL; @@ -1077,76 +1144,51 @@ static int rzg2l_get_power_source(struct rzg2l_pinc= trl *pctrl, u32 pin, u32 caps { const struct rzg2l_hwcfg *hwcfg =3D pctrl->data->hwcfg; const struct rzg2l_register_offsets *regs =3D &hwcfg->regs; - u8 val, mask; - int pwr_reg; + const struct rzg2l_register_masks *masks =3D &hwcfg->masks; + u8 mask, val; + u16 offset; + int ret; =20 if (caps & PIN_CFG_SOFT_PS) return pctrl->settings[pin].power_source; =20 - pwr_reg =3D rzg2l_caps_to_pwr_reg(regs, caps, &mask); - if (pwr_reg < 0) - return pwr_reg; + ret =3D rzg2l_caps_to_pwr_reg(regs, masks, caps, &offset, &mask); + if (ret) + return ret; =20 - val =3D readb(pctrl->base + pwr_reg); - if (pwr_reg =3D=3D OTHER_POC) - val =3D field_get(mask, val); + val =3D readb(pctrl->base + offset); =20 - switch (val) { - case PVDD_1800: - return 1800; - case PVDD_2500: - return 2500; - case PVDD_3300: - return 3300; - default: - /* Should not happen. */ - return -EINVAL; - } + return rzg2l_pwr_reg_val_to_ps(field_get(mask, val), caps); } =20 static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u3= 2 caps, u32 ps) { const struct rzg2l_hwcfg *hwcfg =3D pctrl->data->hwcfg; const struct rzg2l_register_offsets *regs =3D &hwcfg->regs; - u8 poc_val, val, mask; - int pwr_reg; + const struct rzg2l_register_masks *masks =3D &hwcfg->masks; + u8 mask, val; + u16 offset; + int ret; =20 if (caps & PIN_CFG_SOFT_PS) { pctrl->settings[pin].power_source =3D ps; return 0; } =20 - switch (ps) { - case 1800: - poc_val =3D PVDD_1800; - break; - case 2500: - if (!(caps & (PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1))) - return -EINVAL; - poc_val =3D PVDD_2500; - break; - case 3300: - poc_val =3D PVDD_3300; - break; - default: - return -EINVAL; - } + ret =3D rzg2l_ps_to_pwr_reg_val(&val, ps, caps); + if (ret) + return ret; + + ret =3D rzg2l_caps_to_pwr_reg(regs, masks, caps, &offset, &mask); + if (ret) + return ret; =20 - pwr_reg =3D rzg2l_caps_to_pwr_reg(regs, caps, &mask); - if (pwr_reg < 0) - return pwr_reg; + scoped_guard(raw_spinlock_irqsave, &pctrl->lock) { + u8 tmp =3D readb(pctrl->base + offset); =20 - if (pwr_reg =3D=3D OTHER_POC) { - scoped_guard(raw_spinlock_irqsave, &pctrl->lock) { - val =3D readb(pctrl->base + pwr_reg); - if (poc_val) - val |=3D mask; - else - val &=3D ~mask; - writeb(val, pctrl->base + pwr_reg); - } - } else { - writeb(poc_val, pctrl->base + pwr_reg); + tmp &=3D ~mask; + tmp |=3D field_prep(mask, val); + writeb(tmp, pctrl->base + offset); } =20 pctrl->settings[pin].power_source =3D ps; @@ -3795,6 +3837,11 @@ static const struct rzg2l_hwcfg rzg3l_hwcfg =3D { .oen =3D 0x3018, .other_poc =3D OTHER_POC, }, + .masks =3D { + .other_poc_pvdd1833_oth_awo_poc =3D BIT(0), + .other_poc_pvdd1833_oth_iso_poc =3D BIT(1), + .other_poc_wdtovf_n_poc =3D BIT(2), + }, .iolh_groupa_ua =3D { /* 1v8 power source */ [RZG2L_IOLH_IDX_1V8] =3D 2200, 4400, 9000, 10000, --=20 2.43.0 From nobody Mon Jun 8 08:30:47 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2772A3D1AB9; Wed, 3 Jun 2026 15:17:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780499830; cv=none; b=neiv5IAiqF4i9ABnzFTKBAyANxI1eyQwqqC8edeY+OLO3pZLGitekgJfTVCb06aljfQOQcILlOkpUOAQ8PRuWeRpx7ItBcD5vuYDlW4dpeIrA07c73Ht47WRxuub6olu87zI4+YHbaaQsaKAvQKxLm49gxGYgP+4Q4LT5Z14C7I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780499830; c=relaxed/simple; bh=GVgjAVWVXbynufjGFxXsa0bKmm1lOm1h5fWN9ItYjeA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FYQF/QF3+Ou3crvR5C1sa5MD+44v441HT8gKkhpyayVFG9Pl/a1UmLpt9Adbz0k8NujN6Ol5p/PcvJELATVMdmwBG/g/7xgngPMWNTaNYlhrb+EQ68vn8QDBmD7STCWemgFxD+tZ9IjUgz97OJIa1olYWXTxsSRF0smHsn3wBPg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=nYhUWkwB; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="nYhUWkwB" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3D5971F00898; Wed, 3 Jun 2026 15:17:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1780499828; bh=iWTd2gkTfeXLtpXeXgM8TZo+rmIc+Lsx71mY8c2PamE=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=nYhUWkwBXMWtm/7R5Ov61ZB7Q8pqJP7WD/dj7rd04yvrNZnZGGdR4BOebID85UbiS TQd4YmNaDtrr2uMUJYAhfzbdPBkUyHyL/RFfJTbNf2GyPTaNroNXWLnT/b0KIWcZfk PnJMQpPUzu5FoZtsK0oewK+5o75JhAocY4dRpacIOEM38mi/3t3OXCRs0wbpcylsn6 YKxHpke9S61engCJ31scEK+t4OUG2FNuu5U5scogMj2fiCRu8J9tLv6pgiMRZd+o2t QtjjgqRoLooP05EUB5HcHssykgROh3s1vw4u5sSMbtPh4CyCG/iclsLyq+OSrYCamC /3qGw991jDrOw== From: Claudiu Beznea To: geert+renesas@glider.be, linusw@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, magnus.damm@gmail.com, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: claudiu.beznea@kernel.org, claudiu.beznea@tuxon.dev, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea , Wolfram Sang Subject: [PATCH v3 3/6] pinctrl: renesas: rzg2l: Drop defines present in struct rzg2l_hwcfg Date: Wed, 3 Jun 2026 18:16:39 +0300 Message-ID: <20260603151642.4075678-4-claudiu.beznea@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260603151642.4075678-1-claudiu.beznea@kernel.org> References: <20260603151642.4075678-1-claudiu.beznea@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Drop the QSPI and OTHER_POC register defines, which are SoC specific and accessible through struct rzg2l_hwcfg::{qspi, other_poc}. While at it move the assignement of rzg2l_hwcfg->regs->qspi upper to have the initializations as sorted (by offsets) as possible. Reviewed-by: Wolfram Sang Signed-off-by: Claudiu Beznea --- Changes in v3: - updated patch description - collected tags Changes in v2: - none drivers/pinctrl/renesas/pinctrl-rzg2l.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 6f3760851460..b52a85066f63 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -180,8 +180,6 @@ #define SMT(off) (0x3400 + (off) * 8) #define SD_CH(off, ch) ((off) + (ch) * 4) #define ETH_POC(off, ch) ((off) + (ch) * 4) -#define QSPI (0x3008) /* known on RZ/{G2L,G2LC,G2UL,Five} only */ -#define OTHER_POC (0x3028) /* known on RZ/G3L only */ =20 #define PVDD_2500 2 /* I/O domain voltage 2.5V */ #define PVDD_1800 1 /* I/O domain voltage <=3D 1.8V */ @@ -3816,9 +3814,9 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg =3D { .regs =3D { .pwpr =3D 0x3014, .sd_ch =3D 0x3000, + .qspi =3D 0x3008, .eth_poc =3D 0x300c, .oen =3D 0x3018, - .qspi =3D QSPI, }, .iolh_groupa_ua =3D { /* 3v3 power source */ @@ -3835,7 +3833,7 @@ static const struct rzg2l_hwcfg rzg3l_hwcfg =3D { .sd_ch =3D 0x3004, .eth_poc =3D 0x3010, .oen =3D 0x3018, - .other_poc =3D OTHER_POC, + .other_poc =3D 0x3028, }, .masks =3D { .other_poc_pvdd1833_oth_awo_poc =3D BIT(0), --=20 2.43.0 From nobody Mon Jun 8 08:30:47 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B4B63D1717; Wed, 3 Jun 2026 15:17:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780499834; cv=none; b=MBKR1VgowIh0Av5NkWSDpakV/M6A1CS7BYUQt5mZNoJla3aF/75jTqK9WKSUj3rlVLh2LY3X+yh77DZx9kQISuzjh+m8y3R0StbNQnfu25SqHxj1/v4YhQgiaOyOn0/IG2BrsIIHhEXcnMP6daGq3C525SmlxO4Vm+q6YpsZMic= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780499834; c=relaxed/simple; bh=LtTbRDsK4gjdoYdesANaiItjHA/I+jljw0J8rnBxa60=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gNfqzNYn+SnmQGRkYCwoaaTGCXUCond9CLSF3LwTH32QmMqIiiQelc/HGF+n75+eXFrBLL23j/xL5r4eAZuqf6RYMe3MnpmG4mH6aeOQ1Te31fVgBntXIUwwonBC2MkdKxYXCvhCK6APqoX6EFmLCmzUEAupuzKs0kno7qpNRcw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=U2tmbu5u; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="U2tmbu5u" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 388B91F00893; Wed, 3 Jun 2026 15:17:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1780499832; bh=aYa8cW3ExKVcGtvZx9/d68cn0QCtm1meSMNr+qL06Nk=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=U2tmbu5ufzgCRljltgRBMr9bjnPQoP/XzbPdZrBfY3M+OkRay5iHr13sAKG4mghw7 EKCYT2AOk6QNUAgPIzjkVuUUMKKXGYxboikCZu/VmO29ckBjyDo8YuCtgXbegcrexB lOzbyYK4WrNjFTOdwMRw+aMehEoDmb6IqgIVSCP6sOqkM9CDnKr3qSTQ+IL5R7QAVM 3NbKdECP7KjsWx5dmVUq/D/fJ1ww72YtPX/u4bAEb8590WF1bc+fhj+eoJTL+pXxtW Is6mHEwlmVyNSmHY/zg2FmXmKY3R3lY4QDD6gAw8HiMnMizP8NN138c5d18SZT8AuD ybar7Td20PT4A== From: Claudiu Beznea To: geert+renesas@glider.be, linusw@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, magnus.damm@gmail.com, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: claudiu.beznea@kernel.org, claudiu.beznea@tuxon.dev, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea , Conor Dooley , Wolfram Sang Subject: [PATCH v3 4/6] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Document the missing I3C power source option Date: Wed, 3 Jun 2026 18:16:40 +0300 Message-ID: <20260603151642.4075678-5-claudiu.beznea@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260603151642.4075678-1-claudiu.beznea@kernel.org> References: <20260603151642.4075678-1-claudiu.beznea@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The I3C pins on the Renesas RZ/G3S SoC can be powered at either 1.2V or 1.8V. Document the missing 1.2V power source option. Acked-by: Conor Dooley Reviewed-by: Wolfram Sang Signed-off-by: Claudiu Beznea --- Changes in v3: - collected tags Changes in v2: - collected tags .../devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.ya= ml index fb1fe1ea759f..32864c9add4a 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -129,7 +129,7 @@ additionalProperties: enum: [ 33, 50, 66, 100 ] power-source: description: I/O voltage in millivolt. - enum: [ 1800, 2500, 3300 ] + enum: [ 1200, 1800, 2500, 3300 ] slew-rate: true gpio-hog: true gpios: true --=20 2.43.0 From nobody Mon Jun 8 08:30:47 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36C683CBE6E; Wed, 3 Jun 2026 15:17:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780499838; cv=none; b=Jr72wbt6uq6xrh8YbD8KS590HTDBQIV/JScJNJ8XBMm/+fJowxrVOPTjL8pz24WEYwR6yItfmhj7x3jqQQnPjh0qzrwCUQXQehaX48hXtO4IP8xWoNtJncCNceiujo9ZdmcHaBscTExYSXtumDNn/ZcTNBb+uWWaBvdZ1fIAiWo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780499838; c=relaxed/simple; bh=J1kkX8u2FHxFISmABClS1R5aqNqzRnB1dhVJJ5HEc4I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oh8MDtO1ded6ImYg6Ur6xcPfvzu+B+FwYpsGp3fHpOEFE8IkSy/kPdFkHyJDPr3ZzA61uv+GyZjpvSloPVr1aMpU+Mk/MCLsrDjpakt94lQzWhy2eVLVY9oab/7PitZu/Zp7/L/HHMVZ+l3FK1MCY6HmeYdDjWAjop2aeQpf/YY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=JTdf8khi; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="JTdf8khi" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 532B21F00898; Wed, 3 Jun 2026 15:17:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1780499837; bh=XPCmppQDCS/VPvRcd5NSa0jwL94hAn6T/iBNBC2VjbI=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=JTdf8khiVcUTPOaaVxub2+4BkgbNSUo7Fw+m1451pcXYbRMy0PyLKOn0vZcHSUsXR Amg6pzQxSS5tKl7CnlpoDNrM7E5rcPbtr6lTu+z1VFlTQ8zXm1fOWAfQ54Gks81Kzf /au4MUrLCD50Fuzy1jdIFn7Bo3ODQ6RMM4B9VbAc3P4OFgwFn4dy+8a3IEwOkptD0d gBpGA6Ao8jIqrNKY22Nz2FoCqcQzYiSys5VMbwhAyyWJS/sGN0RlXuagMORPdDPTTi EElVvBMuWLhQGACxDEzQN5mAxJMP6XmhnCaRQQnIS6xUSFQ4y/6iqjj4UgoES9gyEM GF5CHv1GF1hgQ== From: Claudiu Beznea To: geert+renesas@glider.be, linusw@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, magnus.damm@gmail.com, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: claudiu.beznea@kernel.org, claudiu.beznea@tuxon.dev, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea , Wolfram Sang Subject: [PATCH v3 5/6] pinctrl: renesas: rzg2l: Add RZ/G3S support for selecting the I3C power source Date: Wed, 3 Jun 2026 18:16:41 +0300 Message-ID: <20260603151642.4075678-6-claudiu.beznea@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260603151642.4075678-1-claudiu.beznea@kernel.org> References: <20260603151642.4075678-1-claudiu.beznea@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The Renesas RZ/G3S I3C pins can be powered at either 1.8V or 1.2V. The pin controller provides a register to select between these two options. Update the Renesas RZ/G2L pin controller driver to allow selecting the I3C power source on RZ/G3S SoC. Reviewed-by: Wolfram Sang Tested-by: Wolfram Sang Signed-off-by: Claudiu Beznea --- Changes in v3: - collected tags Changes in v2: - none drivers/pinctrl/renesas/pinctrl-rzg2l.c | 73 +++++++++++++++++++++++-- 1 file changed, 68 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index b52a85066f63..9a0706fea220 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -69,6 +69,7 @@ #define PIN_CFG_PVDD1833_OTH_AWO_POC BIT(19) /* known on RZ/G3L only */ #define PIN_CFG_PVDD1833_OTH_ISO_POC BIT(20) /* known on RZ/G3L only */ #define PIN_CFG_WDTOVF_N_POC BIT(21) /* known on RZ/G3L only */ +#define PIN_CFG_IO_VMC_I3C BIT(22) =20 #define RZG2L_SINGLE_PIN BIT_ULL(63) /* Dedicated pin */ #define RZG2L_VARIABLE_CFG BIT_ULL(62) /* Variable cfg for port pins */ @@ -186,6 +187,9 @@ #define PVDD_3300 0 /* I/O domain voltage >=3D 3.3V */ #define PVDD_MASK 0x3 =20 +#define PVDD_I3C_1200 1 /* I3C I/O domain voltage 1.2V */ +#define PVDD_I3C_1800 0 /* I3C I/O domain voltage 1.8V */ + #define PWPR_B0WI BIT(7) /* Bit Write Disable */ #define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */ #define PWPR_REGWE_A BIT(6) /* PFC and PMC Register Write Enable on RZ/V2= H(P) */ @@ -257,6 +261,7 @@ static const struct pin_config_item renesas_rzv2h_conf_= items[] =3D { * @oen: OEN register offset * @qspi: QSPI register offset * @other_poc: OTHER_POC register offset + * @i3c_set: I3C_SET register offset */ struct rzg2l_register_offsets { u16 pwpr; @@ -265,6 +270,7 @@ struct rzg2l_register_offsets { u16 oen; u16 qspi; u16 other_poc; + u16 i3c_set; }; =20 /** @@ -272,6 +278,7 @@ struct rzg2l_register_offsets { * @other_poc_pvdd1833_oth_awo_poc: PVDD1833_OTH_AWO_POC mask * @other_poc_pvdd1833_oth_iso_poc: PVDD1833_OTH_ISO_POC mask * @other_poc_wdtovf_n_poc: WDTOVF_N_POC mask + * @i3c_set_poc: I3C_SET_POC mask */ struct rzg2l_register_masks { union { @@ -281,6 +288,11 @@ struct rzg2l_register_masks { u8 other_poc_pvdd1833_oth_iso_poc; u8 other_poc_wdtovf_n_poc; }; + + /* RZ/G3S masks */ + struct { + u8 i3c_set_poc; + }; }; }; =20 @@ -391,6 +403,7 @@ struct rzg2l_pinctrl_pin_settings { * @oen: Output Enable register cache * @other_poc: OTHER_POC register cache * @qspi: QSPI registers cache + * @i3c_set: I3C_SET register cache */ struct rzg2l_pinctrl_reg_cache { u8 *p; @@ -409,6 +422,7 @@ struct rzg2l_pinctrl_reg_cache { u8 oen; u8 other_poc; u8 qspi; + u8 i3c_set; }; =20 struct rzg2l_pinctrl { @@ -441,6 +455,7 @@ struct rzg2l_pinctrl { }; =20 static const u16 available_ps[] =3D { 1800, 2500, 3300 }; +static const u16 available_i3c_ps[] =3D { 1200, 1800 }; =20 static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl, u64 pincfg, @@ -1101,12 +1116,28 @@ static int rzg2l_caps_to_pwr_reg(const struct rzg2l= _register_offsets *regs, *mask =3D masks->other_poc_wdtovf_n_poc; return 0; } + if (caps & PIN_CFG_IO_VMC_I3C) { + *offset =3D regs->i3c_set; + *mask =3D masks->i3c_set_poc; + return 0; + } =20 return -EINVAL; } =20 static int rzg2l_pwr_reg_val_to_ps(u8 val, u32 caps) { + if (caps & PIN_CFG_IO_VMC_I3C) { + switch (val) { + case PVDD_I3C_1200: + return 1200; + case PVDD_I3C_1800: + return 1800; + } + + return -EINVAL; + } + switch (val) { case PVDD_1800: return 1800; @@ -1121,6 +1152,19 @@ static int rzg2l_pwr_reg_val_to_ps(u8 val, u32 caps) =20 static int rzg2l_ps_to_pwr_reg_val(u8 *val, u32 ps, u32 caps) { + if (caps & PIN_CFG_IO_VMC_I3C) { + switch (ps) { + case 1200: + *val =3D PVDD_I3C_1200; + return 0; + case 1800: + *val =3D PVDD_I3C_1800; + return 0; + } + + return -EINVAL; + } + switch (ps) { case 1800: *val =3D PVDD_1800; @@ -1194,12 +1238,21 @@ static int rzg2l_set_power_source(struct rzg2l_pinc= trl *pctrl, u32 pin, u32 caps return 0; } =20 -static bool rzg2l_ps_is_supported(u16 ps) +static bool rzg2l_ps_is_supported(u16 ps, u32 caps) { - unsigned int i; + unsigned int i, len; + const u16 *array; =20 - for (i =3D 0; i < ARRAY_SIZE(available_ps); i++) { - if (available_ps[i] =3D=3D ps) + if (caps & PIN_CFG_IO_VMC_I3C) { + array =3D available_i3c_ps; + len =3D ARRAY_SIZE(available_i3c_ps); + } else { + array =3D available_ps; + len =3D ARRAY_SIZE(available_ps); + } + + for (i =3D 0; i < len; i++) { + if (array[i] =3D=3D ps) return true; } =20 @@ -1800,7 +1853,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_d= ev *pctldev, =20 /* Apply power source. */ if (settings.power_source !=3D pctrl->settings[_pin].power_source) { - ret =3D rzg2l_ps_is_supported(settings.power_source); + ret =3D rzg2l_ps_is_supported(settings.power_source, cfg); if (!ret) return -EINVAL; =20 @@ -2498,6 +2551,8 @@ static const struct rzg2l_dedicated_configs rzg3s_ded= icated_pins[] =3D { { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x2, 0, PIN_CFG_IEN) }, { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x2, 1, PIN_CFG_IEN) }, { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0x6, 0, PIN_CFG_IOLH_A | PIN_C= FG_SOFT_PS) }, + { "I3C_SDA", RZG2L_SINGLE_PIN_PACK(0x9, 0, (PIN_CFG_IEN | PIN_CFG_IO_VMC_= I3C)) }, + { "I3C_SCL", RZG2L_SINGLE_PIN_PACK(0x9, 1, (PIN_CFG_IEN | PIN_CFG_IO_VMC_= I3C)) }, { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_= VMC_SD0)) }, { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN= | PIN_CFG_IO_VMC_SD0)) }, @@ -3717,6 +3772,8 @@ static int rzg2l_pinctrl_suspend_noirq(struct device = *dev) cache->oen =3D readb(pctrl->base + pctrl->data->hwcfg->regs.oen); if (regs->other_poc) cache->other_poc =3D readb(pctrl->base + regs->other_poc); + if (regs->i3c_set) + cache->i3c_set =3D readb(pctrl->base + regs->i3c_set); =20 if (pctrl->syscon) { int ret; @@ -3759,6 +3816,8 @@ static int rzg2l_pinctrl_resume_noirq(struct device *= dev) writeb(cache->qspi, pctrl->base + regs->qspi); if (regs->other_poc) writeb(cache->other_poc, pctrl->base + regs->other_poc); + if (regs->i3c_set) + writeb(cache->i3c_set, pctrl->base + regs->i3c_set); =20 raw_spin_lock_irqsave(&pctrl->lock, flags); rzg2l_oen_write_with_pwpr(pctrl, cache->oen); @@ -3871,8 +3930,12 @@ static const struct rzg2l_hwcfg rzg3s_hwcfg =3D { .pwpr =3D 0x3000, .sd_ch =3D 0x3004, .eth_poc =3D 0x3010, + .i3c_set =3D 0x301c, .oen =3D 0x3018, }, + .masks =3D { + .i3c_set_poc =3D BIT(2), + }, .iolh_groupa_ua =3D { /* 1v8 power source */ [RZG2L_IOLH_IDX_1V8] =3D 2200, 4400, 9000, 10000, --=20 2.43.0 From nobody Mon Jun 8 08:30:47 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D8AA3D6CAE; Wed, 3 Jun 2026 15:17:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780499842; cv=none; b=cU4JKaNUKLZ8n/PQ0oH4t01OD0EARZm4jlg2W1WBjui0g4qj2tfI+1X5lEegpqfmy6A+QRuLI0OGR4iHucnBKBEsHq1CzgA3B5BiDkqJOlCTs2pjRPnO9gQguqDJkHPRI+Xrcx932futVoa0Te0aFY820eDHWIye9LnwTIe5w3M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780499842; c=relaxed/simple; bh=5dQdT8sFOwJOLDSBxKJKCSW0yGjLmAHWOVYrFPkQKaI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=m5jx1zGuCfte10ZpIXLlzP5E+1CLXzEgoewq+ZPYg49jU/Zo/vu7y/XBHnMHRkerto87O1vb76jR3o2MjXaI/GMofGzct2liag8CK+I23q6WJaxBI3cUOTU5Z72FNZ/6JRFUUeIaRsHKAE8h1/orqNsE+1CZmOhYkBlmUUPdzkA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=FARz/q6Z; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FARz/q6Z" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 67EDC1F0089A; Wed, 3 Jun 2026 15:17:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1780499840; bh=oFlq/AL3VtP+pSmrs/29Y1Po0Fraz2VgZagy0oAiduE=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=FARz/q6Z3xhstGpddt3FEA0rKUlNDsU0dhaBY0QtG4qO01rJZ7emsK9tDvbw5xAoe r+kmQzbuAG37qIsEnIn4D/+xeJXiD6EadgRNMhK12ted7X5wI6k0pri+4cS3H9YWiu bg9GJe5YbpaVu554UYBamACJu0cIfMhzE8CEJmDQTuWOlk0ohG/C5mQXXi4TA3LrXO E2sKmGckHnYTraI6NvnG4GBINAP55nA2Y1vqpg8bf9mKv7Qw+MXylJATOwlrbdoAWU jdFxf36YJyNru8lcF159nDiI+swm8SSdQVNu1lycHMn+zHx2wapDvYJ8VcEDP3v/Fz zJzleLPJTOnfQ== From: Claudiu Beznea To: geert+renesas@glider.be, linusw@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, magnus.damm@gmail.com, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: claudiu.beznea@kernel.org, claudiu.beznea@tuxon.dev, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea , Wolfram Sang Subject: [PATCH v3 6/6] arm64: dts: renesas: rzg3s-smarc-som: Enable I3C Date: Wed, 3 Jun 2026 18:16:42 +0300 Message-ID: <20260603151642.4075678-7-claudiu.beznea@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260603151642.4075678-1-claudiu.beznea@kernel.org> References: <20260603151642.4075678-1-claudiu.beznea@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The Renesas RZ/G3S SMARC SoM board has a connector for I3C interface. Enable I3C. Reviewed-by: Wolfram Sang Tested-by: Wolfram Sang Signed-off-by: Claudiu Beznea --- Changes in v3: - collected tags Changes in v2: - dropped pinctrl sleep state .../boot/dts/renesas/rzg3s-smarc-som.dtsi | 18 ++++++++++++++++++ .../boot/dts/renesas/rzg3s-smarc-switches.h | 4 ++++ 2 files changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/= boot/dts/renesas/rzg3s-smarc-som.dtsi index b45acfe6288a..af7357fe4655 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -168,6 +168,14 @@ a0 80 30 30 9c }; }; =20 +&i3c { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i3c_pins>; + i2c-scl-hz =3D <400000>; + i3c-scl-hz =3D <12500000>; + status =3D "okay"; +}; + &pcie_port0 { clocks =3D <&versa3 5>; clock-names =3D "ref"; @@ -302,6 +310,16 @@ mux { }; }; =20 + i3c_pins: i3c { + pins =3D "I3C_SDA", "I3C_SCL"; +#if SW_CONFIG4 =3D=3D SW_ON + power-source =3D <1200>; +#else + power-source =3D <1800>; +#endif + input-enable; + }; + sdhi0_pins: sd0 { data { pins =3D "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h b/arch/arm6= 4/boot/dts/renesas/rzg3s-smarc-switches.h index bbf908a5322c..9cccc87da057 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h @@ -25,9 +25,13 @@ * @SW_CONFIG3: * SW_OFF - SD2 is connected to SoC * SW_ON - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC + * @SW_CONFIG4: + * SW_OFF - I3C voltage is 1.8V + * SW_ON - I3C voltage is 1.2V */ #define SW_CONFIG2 SW_OFF #define SW_CONFIG3 SW_ON +#define SW_CONFIG4 SW_OFF =20 /* * SW_OPT_MUX[x] switches' states: --=20 2.43.0