From nobody Mon Jun 8 08:28:39 2026 Received: from pdx-out-007.esa.us-west-2.outbound.mail-perimeter.amazon.com (pdx-out-007.esa.us-west-2.outbound.mail-perimeter.amazon.com [52.34.181.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E4BC3D1AAC; Wed, 3 Jun 2026 15:00:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=52.34.181.151 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780498836; cv=none; b=BATwl2cCActHlg5fntmlaBqyhN+NgaJUL+w6da78qItUcJJK4WEBbyIYjEVRgdmu2zSIBhqETXcS4RqW0HJaUe71nP1aB/O9JJxt06uf4bo+KnYFhiGQx5fYP5liLUagsplyedn0AA7nIUCqXPu4/gRribQck++/1ce39UM5Z4w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780498836; c=relaxed/simple; bh=MekWr4nJS+jU9QMiM28bHAY4E92bie/m0UF40+i9yYE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=qT13UI2MTSGBWFZBITAnSaMmDRgVcinO580eN4sYSNWjyu0OAhsi8tisMau7zA+vajVlS17SlgxT+drVT2mMtY+rJf11TCURlMty11xzPl3bbSue/J1nZCQoLoEdg0mgzgQofI24455VsUnQMzXgF92UPIBjlYNv3FhdB2XEHAk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amazon.com; spf=pass smtp.mailfrom=amazon.com; dkim=pass (2048-bit key) header.d=amazon.com header.i=@amazon.com header.b=pzKN8cB6; arc=none smtp.client-ip=52.34.181.151 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amazon.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amazon.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=amazon.com header.i=@amazon.com header.b="pzKN8cB6" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazoncorp2; t=1780498835; x=1812034835; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=D3ynmzKfeg3eucqq3bQ/oxYUDdHDjl1e9ZsAJ+TGUGI=; b=pzKN8cB6wc9n0uJziyWYKe0RPChOfJP3me+ra4CmSmahDUGFx71gunyu i9UR8DDDTnANwGlThbVrI3jVYdr8RxF1Ww2lKZbZfdHTh1vugfx72m91s nhy/7BeLGNHMdF42TUwKgFtCEgKAIJO8Jx1DWYUP0v9ygLYPntyvit5tP dIqTcnCgQvMpIsK7BDKELo++S2jXrlMT99v1rhjwhp/fTo67BaAnMzbgr rg+BzfZPdzmdVckg1V/K8NJCpIwghGRE9USiERxJTQjn4zYF7mHOkPA80 6FU18ikaOveXU5pSn/ebGbGUmX6MeB4bBWvtRqqbWR+l3fbBF56AiUDge w==; X-CSE-ConnectionGUID: xCgGdqx5TgOfrBY6T35XEA== X-CSE-MsgGUID: bDB5oeGIRe+qqR1CsJLEyA== X-IronPort-AV: E=Sophos;i="6.24,185,1774310400"; d="scan'208";a="21003015" Received: from ip-10-5-0-115.us-west-2.compute.internal (HELO smtpout.naws.us-west-2.prod.farcaster.email.amazon.dev) ([10.5.0.115]) by internal-pdx-out-007.esa.us-west-2.outbound.mail-perimeter.amazon.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2026 15:00:32 +0000 Received: from EX19MTAUWC002.ant.amazon.com [205.251.233.111:23080] by smtpin.naws.us-west-2.prod.farcaster.email.amazon.dev [10.0.40.245:2525] with esmtp (Farcaster) id b9492039-a994-4c34-9baa-4b1c6f9ea2e6; Wed, 3 Jun 2026 15:00:31 +0000 (UTC) X-Farcaster-Flow-ID: b9492039-a994-4c34-9baa-4b1c6f9ea2e6 Received: from EX19D001UWA001.ant.amazon.com (10.13.138.214) by EX19MTAUWC002.ant.amazon.com (10.250.64.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA) id 15.2.2562.37; Wed, 3 Jun 2026 15:00:31 +0000 Received: from dev-dsk-avivb-1b-e28f450e.eu-west-1.amazon.com (10.15.33.9) by EX19D001UWA001.ant.amazon.com (10.13.138.214) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA) id 15.2.2562.37; Wed, 3 Jun 2026 15:00:29 +0000 From: Aviv Bakal To: , , CC: , , , , , , Subject: [PATCH v5 1/2] perf/arm-cmn: Move DTM index data out of hw_perf_event Date: Wed, 3 Jun 2026 18:00:24 +0300 Message-ID: <20260603150025.30980-2-avivb@amazon.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260603150025.30980-1-avivb@amazon.com> References: <20260531110447.10095-1-avivb@amazon.com> <20260603150025.30980-1-avivb@amazon.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: EX19D038UWB002.ant.amazon.com (10.13.139.185) To EX19D001UWA001.ant.amazon.com (10.13.138.214) Content-Type: text/plain; charset="utf-8" From: Robin Murphy The amount of data we need to store all the per-DTM counter and watchpoint allocations is already testing the limits of hw_perf_event, and future CMNs are only likely to keep growing larger, so move these arrays out to separate memory allocations. As part of that we can use an explicit union for allocating cycle counters to dtc_cycles events, which is arguably nicer anyway. Signed-off-by: Robin Murphy Signed-off-by: Aviv Bakal Reviewed-by: Ilkka Koskinen --- drivers/perf/arm-cmn.c | 89 ++++++++++++++++++++++++++++-------------- 1 file changed, 59 insertions(+), 30 deletions(-) diff --git a/drivers/perf/arm-cmn.c b/drivers/perf/arm-cmn.c index f5305c8fdca4..f1978a53d1c1 100644 --- a/drivers/perf/arm-cmn.c +++ b/drivers/perf/arm-cmn.c @@ -597,17 +597,14 @@ static void arm_cmn_debugfs_init(struct arm_cmn *cmn,= int id) {} =20 struct arm_cmn_hw_event { struct arm_cmn_node *dn; - u64 dtm_idx[DIV_ROUND_UP(CMN_MAX_NODES_PER_EVENT * 2, 64)]; + union { + u64 *dtm_idx; + int cc_idx; + }; + unsigned long *wp_idx; s8 dtc_idx[CMN_MAX_DTCS]; u8 num_dns; u8 dtm_offset; - - /* - * WP config registers are divided to UP and DOWN events. We need to - * keep to track only one of them. - */ - DECLARE_BITMAP(wp_idx, CMN_MAX_XPS); - bool wide_sel; enum cmn_filter_select filter_sel; }; @@ -625,25 +622,42 @@ static struct arm_cmn_hw_event *to_cmn_hw(struct perf= _event *event) return (struct arm_cmn_hw_event *)&event->hw; } =20 -static void arm_cmn_set_index(u64 x[], unsigned int pos, unsigned int val) +static void arm_cmn_set_dtm_idx(struct arm_cmn_hw_event *hw, unsigned int = pos, unsigned int val) { - x[pos / 32] |=3D (u64)val << ((pos % 32) * 2); + hw->dtm_idx[pos / 32] |=3D (u64)val << ((pos % 32) * 2); } =20 -static unsigned int arm_cmn_get_index(u64 x[], unsigned int pos) +static unsigned int arm_cmn_get_dtm_idx(struct arm_cmn_hw_event *hw, unsig= ned int pos) { - return (x[pos / 32] >> ((pos % 32) * 2)) & 3; + return (hw->dtm_idx[pos / 32] >> ((pos % 32) * 2)) & 3; } =20 -static void arm_cmn_set_wp_idx(unsigned long *wp_idx, unsigned int pos, bo= ol val) +static u64 *arm_cmn_alloc_dtm_idx(void) +{ + return kzalloc(DIV_ROUND_UP(CMN_MAX_NODES_PER_EVENT * 2, 64) * sizeof(u64= ), GFP_KERNEL); +} + +static void arm_cmn_set_wp_idx(struct arm_cmn_hw_event *hw, unsigned int p= os, bool val) { if (val) - set_bit(pos, wp_idx); + set_bit(pos, hw->wp_idx); +} + +static unsigned int arm_cmn_get_wp_idx(struct arm_cmn_hw_event *hw, unsign= ed int pos) +{ + return test_bit(pos, hw->wp_idx); +} + +static unsigned long *arm_cmn_alloc_wp_idx(void) +{ + return bitmap_zalloc(CMN_MAX_XPS, GFP_KERNEL); } =20 -static unsigned int arm_cmn_get_wp_idx(unsigned long *wp_idx, unsigned int= pos) +static void arm_cmn_clear_idx(struct arm_cmn_hw_event *hw) { - return test_bit(pos, wp_idx); + memset(hw->dtm_idx, 0, DIV_ROUND_UP(CMN_MAX_NODES_PER_EVENT * 2, 64) * si= zeof(u64)); + if (hw->wp_idx) + bitmap_zero(hw->wp_idx, CMN_MAX_XPS); } =20 struct arm_cmn_event_attr { @@ -1376,7 +1390,7 @@ static int arm_cmn_get_assigned_wp_idx(struct perf_ev= ent *event, struct arm_cmn_hw_event *hw, unsigned int pos) { - return CMN_EVENT_EVENTID(event) + arm_cmn_get_wp_idx(hw->wp_idx, pos); + return CMN_EVENT_EVENTID(event) + arm_cmn_get_wp_idx(hw, pos); } =20 static void arm_cmn_claim_wp_idx(struct arm_cmn_dtm *dtm, @@ -1387,7 +1401,7 @@ static void arm_cmn_claim_wp_idx(struct arm_cmn_dtm *= dtm, struct arm_cmn_hw_event *hw =3D to_cmn_hw(event); =20 dtm->wp_event[wp_idx] =3D hw->dtc_idx[dtc]; - arm_cmn_set_wp_idx(hw->wp_idx, pos, wp_idx - CMN_EVENT_EVENTID(event)); + arm_cmn_set_wp_idx(hw, pos, wp_idx - CMN_EVENT_EVENTID(event)); } =20 static u32 arm_cmn_wp_config(struct perf_event *event, int wp_idx) @@ -1458,7 +1472,7 @@ static u64 arm_cmn_read_dtm(struct arm_cmn *cmn, stru= ct arm_cmn_hw_event *hw, dtm =3D &cmn->dtms[dn->dtm] + hw->dtm_offset; reg =3D readq_relaxed(dtm->base + offset); } - dtm_idx =3D arm_cmn_get_index(hw->dtm_idx, i); + dtm_idx =3D arm_cmn_get_dtm_idx(hw, i); count +=3D (u16)(reg >> (dtm_idx * 16)); } return count; @@ -1505,7 +1519,7 @@ static void arm_cmn_event_read(struct perf_event *eve= nt) unsigned long flags; =20 if (CMN_EVENT_TYPE(event) =3D=3D CMN_TYPE_DTC) { - delta =3D arm_cmn_read_cc(cmn->dtc + hw->dtc_idx[0]); + delta =3D arm_cmn_read_cc(cmn->dtc + hw->cc_idx); local64_add(delta, &event->count); return; } @@ -1572,7 +1586,7 @@ static void arm_cmn_event_start(struct perf_event *ev= ent, int flags) int i; =20 if (type =3D=3D CMN_TYPE_DTC) { - struct arm_cmn_dtc *dtc =3D cmn->dtc + hw->dtc_idx[0]; + struct arm_cmn_dtc *dtc =3D cmn->dtc + hw->cc_idx; =20 writel_relaxed(CMN_DT_DTC_CTL_DT_EN | CMN_DT_DTC_CTL_CG_DISABLE, dtc->base + CMN_DT_DTC_CTL); @@ -1590,7 +1604,7 @@ static void arm_cmn_event_start(struct perf_event *ev= ent, int flags) writeq_relaxed(mask, base + CMN_DTM_WPn_MASK(wp_idx)); } } else for_each_hw_dn(hw, dn, i) { - int dtm_idx =3D arm_cmn_get_index(hw->dtm_idx, i); + int dtm_idx =3D arm_cmn_get_dtm_idx(hw, i); =20 arm_cmn_set_event_sel_lo(dn, dtm_idx, CMN_EVENT_EVENTID(event), hw->wide_sel); @@ -1606,7 +1620,7 @@ static void arm_cmn_event_stop(struct perf_event *eve= nt, int flags) int i; =20 if (type =3D=3D CMN_TYPE_DTC) { - struct arm_cmn_dtc *dtc =3D cmn->dtc + hw->dtc_idx[0]; + struct arm_cmn_dtc *dtc =3D cmn->dtc + hw->cc_idx; =20 dtc->cc_active =3D false; writel_relaxed(CMN_DT_DTC_CTL_DT_EN, dtc->base + CMN_DT_DTC_CTL); @@ -1619,7 +1633,7 @@ static void arm_cmn_event_stop(struct perf_event *eve= nt, int flags) writeq_relaxed(~0ULL, base + CMN_DTM_WPn_VAL(wp_idx)); } } else for_each_hw_dn(hw, dn, i) { - int dtm_idx =3D arm_cmn_get_index(hw->dtm_idx, i); + int dtm_idx =3D arm_cmn_get_dtm_idx(hw, i); =20 arm_cmn_set_event_sel_lo(dn, dtm_idx, 0, hw->wide_sel); } @@ -1763,6 +1777,14 @@ static enum cmn_filter_select arm_cmn_filter_sel(con= st struct arm_cmn *cmn, } =20 =20 +static void arm_cmn_event_destroy(struct perf_event *event) +{ + struct arm_cmn_hw_event *hw =3D to_cmn_hw(event); + + kfree(hw->dtm_idx); + bitmap_free(hw->wp_idx); +} + static int arm_cmn_event_init(struct perf_event *event) { struct arm_cmn *cmn =3D to_cmn(event->pmu); @@ -1787,6 +1809,11 @@ static int arm_cmn_event_init(struct perf_event *eve= nt) if (type =3D=3D CMN_TYPE_DTC) return arm_cmn_validate_group(cmn, event); =20 + event->destroy =3D arm_cmn_event_destroy; + hw->dtm_idx =3D arm_cmn_alloc_dtm_idx(); + if (!hw->dtm_idx) + return -ENOMEM; + eventid =3D CMN_EVENT_EVENTID(event); /* For watchpoints we need the actual XP node here */ if (type =3D=3D CMN_TYPE_WP) { @@ -1797,6 +1824,9 @@ static int arm_cmn_event_init(struct perf_event *even= t) /* ...but the DTM may depend on which port we're watching */ if (cmn->multi_dtm) hw->dtm_offset =3D CMN_EVENT_WP_DEV_SEL(event) / 2; + hw->wp_idx =3D arm_cmn_alloc_wp_idx(); + if (!hw->wp_idx) + return -ENOMEM; } else if (type =3D=3D CMN_TYPE_XP && (cmn->part =3D=3D PART_CMN700 || cmn->part =3D=3D PART_CMN_S3)) { hw->wide_sel =3D true; @@ -1847,7 +1877,7 @@ static void arm_cmn_event_clear(struct arm_cmn *cmn, = struct perf_event *event, =20 while (i--) { struct arm_cmn_dtm *dtm =3D &cmn->dtms[hw->dn[i].dtm] + hw->dtm_offset; - unsigned int dtm_idx =3D arm_cmn_get_index(hw->dtm_idx, i); + unsigned int dtm_idx =3D arm_cmn_get_dtm_idx(hw, i); =20 if (type =3D=3D CMN_TYPE_WP) { int wp_idx =3D arm_cmn_get_assigned_wp_idx(event, hw, i); @@ -1861,8 +1891,7 @@ static void arm_cmn_event_clear(struct arm_cmn *cmn, = struct perf_event *event, dtm->pmu_config_low &=3D ~CMN__PMEVCNT_PAIRED(dtm_idx); writel_relaxed(dtm->pmu_config_low, dtm->base + CMN_DTM_PMU_CONFIG); } - memset(hw->dtm_idx, 0, sizeof(hw->dtm_idx)); - memset(hw->wp_idx, 0, sizeof(hw->wp_idx)); + arm_cmn_clear_idx(hw); =20 for_each_hw_dtc_idx(hw, j, idx) cmn->dtc[j].counters[idx] =3D NULL; @@ -1882,7 +1911,7 @@ static int arm_cmn_event_add(struct perf_event *event= , int flags) return -ENOSPC; =20 cmn->dtc[i].cycles =3D event; - hw->dtc_idx[0] =3D i; + hw->cc_idx =3D i; =20 if (flags & PERF_EF_START) arm_cmn_event_start(event, 0); @@ -1947,7 +1976,7 @@ static int arm_cmn_event_add(struct perf_event *event= , int flags) goto free_dtms; } =20 - arm_cmn_set_index(hw->dtm_idx, i, dtm_idx); + arm_cmn_set_dtm_idx(hw, i, dtm_idx); =20 dtm->input_sel[dtm_idx] =3D input_sel; shift =3D CMN__PMEVCNTn_GLOBAL_NUM_SHIFT(dtm_idx); @@ -1980,7 +2009,7 @@ static void arm_cmn_event_del(struct perf_event *even= t, int flags) arm_cmn_event_stop(event, PERF_EF_UPDATE); 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03 Jun 2026 15:00:33 +0000 Received: from EX19MTAUWA001.ant.amazon.com [205.251.233.236:26102] by smtpin.naws.us-west-2.prod.farcaster.email.amazon.dev [10.0.19.88:2525] with esmtp (Farcaster) id a7656433-0c55-46ee-a621-641430ec32f8; Wed, 3 Jun 2026 15:00:33 +0000 (UTC) X-Farcaster-Flow-ID: a7656433-0c55-46ee-a621-641430ec32f8 Received: from EX19D001UWA001.ant.amazon.com (10.13.138.214) by EX19MTAUWA001.ant.amazon.com (10.250.64.218) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA) id 15.2.2562.37; Wed, 3 Jun 2026 15:00:33 +0000 Received: from dev-dsk-avivb-1b-e28f450e.eu-west-1.amazon.com (10.15.33.9) by EX19D001UWA001.ant.amazon.com (10.13.138.214) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA) id 15.2.2562.37; Wed, 3 Jun 2026 15:00:31 +0000 From: Aviv Bakal To: , , CC: , , , , , , Subject: [PATCH v5 2/2] perf/arm-cmn: Add workarounds for CMN-S3 on Graviton5 Date: Wed, 3 Jun 2026 18:00:25 +0300 Message-ID: <20260603150025.30980-3-avivb@amazon.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260603150025.30980-1-avivb@amazon.com> References: <20260531110447.10095-1-avivb@amazon.com> <20260603150025.30980-1-avivb@amazon.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: EX19D038UWB002.ant.amazon.com (10.13.139.185) To EX19D001UWA001.ant.amazon.com (10.13.138.214) Content-Type: text/plain; charset="utf-8" Graviton5 uses a customised CMN-S3 implementation where certain discovery registers report zeroed fields. Add the following workarounds: - Introduce a dedicated ACPI HID to identify the Graviton5 CMN variant. - Derive the DTC domain from the XP node ID, since the unit info register reports it as zero. - Set the DTC logical ID from the XP's logical ID, since the node info register's logical ID field is also zeroed. Signed-off-by: Aviv Bakal Reviewed-by: Robin Murphy Reviewed-by: Ilkka Koskinen --- drivers/perf/arm-cmn.c | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/drivers/perf/arm-cmn.c b/drivers/perf/arm-cmn.c index f1978a53d1c1..3fb71d9a57eb 100644 --- a/drivers/perf/arm-cmn.c +++ b/drivers/perf/arm-cmn.c @@ -31,7 +31,8 @@ #define CMN_CHILD_NODE_ADDR GENMASK(29, 0) #define CMN_CHILD_NODE_EXTERNAL BIT(31) =20 -#define CMN_MAX_DIMENSION 12 +/* Some implementations use a mesh larger than the architectural max of 12= */ +#define CMN_MAX_DIMENSION 14 #define CMN_MAX_XPS (CMN_MAX_DIMENSION * CMN_MAX_DIMENSION) #define CMN_MAX_DTMS (CMN_MAX_XPS + (CMN_MAX_DIMENSION - 1) * 4) =20 @@ -214,6 +215,8 @@ enum cmn_part { PART_CMN700 =3D 0x43c, PART_CI700 =3D 0x43a, PART_CMN_S3 =3D 0x43e, + /* Synthetic part number, overridden to PART_CMN_S3 during discovery */ + PART_GRAVITON5 =3D 0xa5, }; =20 /* CMN-600 r0px shouldn't exist in silicon, thankfully */ @@ -2250,6 +2253,18 @@ static unsigned int arm_cmn_dtc_domain(struct arm_cm= n *cmn, void __iomem *xp_reg return FIELD_GET(CMN_DTM_UNIT_INFO_DTC_DOMAIN, readl_relaxed(xp_region + = offset)); } =20 +static unsigned int arm_cmn_graviton5_dtc_domain(u16 xp_id) +{ + unsigned int x =3D (xp_id >> 7) & 0xf; + unsigned int y =3D (xp_id >> 3) & 0xf; + + /* + * The unit info register reads as zero; derive the DTC domain from + * the XP's mesh coordinates over the 10x14 mesh. + */ + return (x / 5) + (y / 7) * 2; +} + static void arm_cmn_init_node_info(struct arm_cmn *cmn, u32 offset, struct= arm_cmn_node *node) { int level; @@ -2295,6 +2310,7 @@ static int arm_cmn_discover(struct arm_cmn *cmn, unsi= gned int rgn_offset) u64 reg; int i, j; size_t sz; + bool graviton5_workaround =3D false; =20 arm_cmn_init_node_info(cmn, rgn_offset, &cfg); if (cfg.type !=3D CMN_TYPE_CFG) @@ -2305,6 +2321,13 @@ static int arm_cmn_discover(struct arm_cmn *cmn, uns= igned int rgn_offset) reg =3D readq_relaxed(cfg_region + CMN_CFGM_PERIPH_ID_01); part =3D FIELD_GET(CMN_CFGM_PID0_PART_0, reg); part |=3D FIELD_GET(CMN_CFGM_PID1_PART_1, reg) << 8; + + /* Graviton5 has a customised CMN-S3 which needs some fixups */ + if (cmn->part =3D=3D PART_GRAVITON5) { + cmn->part =3D PART_CMN_S3; + graviton5_workaround =3D true; + } + /* 600AE is close enough that it's not really worth more complexity */ if (part =3D=3D PART_CMN600AE) part =3D PART_CMN600; @@ -2394,6 +2417,8 @@ static int arm_cmn_discover(struct arm_cmn *cmn, unsi= gned int rgn_offset) =20 if (cmn->part =3D=3D PART_CMN600) xp->dtc =3D -1; + else if (graviton5_workaround) + xp->dtc =3D arm_cmn_graviton5_dtc_domain(xp->id); else xp->dtc =3D arm_cmn_dtc_domain(cmn, xp_region); =20 @@ -2472,6 +2497,10 @@ static int arm_cmn_discover(struct arm_cmn *cmn, uns= igned int rgn_offset) =20 switch (dn->type) { case CMN_TYPE_DTC: + if (graviton5_workaround) { + /* Node info logical ID is zeroed; use the XP's */ + dn->logid =3D xp->logid; + } cmn->num_dtcs++; dn++; break; @@ -2687,6 +2716,7 @@ static const struct acpi_device_id arm_cmn_acpi_match= [] =3D { { "ARMHC650" }, { "ARMHC700" }, { "ARMHC003" }, + { "AMZN0070", PART_GRAVITON5 }, {} }; MODULE_DEVICE_TABLE(acpi, arm_cmn_acpi_match); --=20 2.47.3