From nobody Mon Jun 8 07:21:44 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7768D3750DC for ; Wed, 3 Jun 2026 09:08:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780477693; cv=none; b=nbrBSu3Tssa8SBjwITlclerUtKIgTJpXQ5gBWfUdoQpz6GNPTshYmnkCDLCnkSN3ElYC5rjwGeFHstr1TP+BqMtwwETlUt/U4nG5zGYKqieqLSmfYbQ10MamYIranc+pWV9A2uW4dPNjM5rW9cw3HOmGSDcQuj1xXAsJFimS+zc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780477693; c=relaxed/simple; bh=pO9UCkLcVCgzQJ15Oc5dy2H25WqqT7dvU0P6rp92XRk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CEbX0t87R4lr9VulxjlaQoEhksWxGr7fJzJ6MgjEBgYRzGBKXFApJAUa3zLbjGMvpYEUE/RM8MJpzvZYfjDNFg+O5FYGNctx9kNmuw0mbq7Ay5b9oiDmA18zg1fb+zioVNysFJWEZcaGMlA0Y+lBMYkYx6IDbpuEOZtDkDmX8TA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=it2knjau; arc=none smtp.client-ip=192.198.163.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="it2knjau" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1780477692; x=1812013692; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pO9UCkLcVCgzQJ15Oc5dy2H25WqqT7dvU0P6rp92XRk=; b=it2knjau3f0OtRzn6+bnSYkczBMXoxRn9uOmId8jWcPGDM+Q8NQhfq9i /y1x5tN30riRi1npDXj5taKU1dc/Eir3LEXOugKNULd7iCUg/16UI0WMm XOHk9rhJSt0Gywq/kVx/rEM5SxRsbvec9fhld9XX6a46GDlwDfeZgQ+uA baPGfJ2+O1OTQLX3ZEfRhub7WG5X05RtIvEz+I9USSgoF4jbhzjCObdl6 FThSE8Rn15xGeQu0AVc+Twn0Mkl1RiFJUl/XYjLCsAnB24v6XRMSFCwc1 xOi23noCrbzUtwxsJOiZnuL9O9Z5TecDjvC3OnYdFcLl2tYkuUC8y9eZz A==; X-CSE-ConnectionGUID: r79ugXWpSt6kIcr4EQsEbg== X-CSE-MsgGUID: v35MnA4XS6WFT1euq8RTaQ== X-IronPort-AV: E=McAfee;i="6800,10657,11805"; a="91852589" X-IronPort-AV: E=Sophos;i="6.24,184,1774335600"; d="scan'208";a="91852589" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2026 02:08:12 -0700 X-CSE-ConnectionGUID: BQT1qqSFT+egLyOiyZ2shA== X-CSE-MsgGUID: bBW3aLS9QeKJ8e3NHZEBRA== X-ExtLoop1: 1 Received: from ijarvine-mobl1.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.137]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2026 02:08:10 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V5 01/17] i3c: mipi-i3c-hci: Fix suspend behavior when bus disable falls back to software reset Date: Wed, 3 Jun 2026 12:07:38 +0300 Message-ID: <20260603090754.16252-2-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260603090754.16252-1-adrian.hunter@intel.com> References: <20260603090754.16252-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Software reset was introduced as a fallback if bus disable failed. The change was made in 2 places: the cleanup path and the suspend path. For the cleanup path (i3c_hci_bus_cleanup()), after software reset the function continues to do cleanup for the current I/O mode. For the suspend path (i3c_hci_rpm_suspend()), after software reset the function returns early. However software reset does not reset any Ring Headers in the Host Controller, so returning early is not the right thing to do. Instead, continue to call suspend for the current I/O mode, which for DMA mode will reset any Ring Headers. Note, although Ring Headers should not be active at this stage, performing this reset follows the procedure defined by the specification and keeps the suspend path consistent with the cleanup path. Note also, i3c_hci_sync_irq_inactive() is still called via the PIO and DMA hci->io->suspend() callbacks. Always return 0 because the device is quiesced as much as possible and returning a negative error code would unnecessarily prevent system suspend. Fixes: 9a258d1336f7 ("i3c: mipi-i3c-hci: Fallback to software reset when bu= s disable fails") Signed-off-by: Adrian Hunter Reviewed-by: Frank Li --- Changes in V4 and V5: None Changes in V3: Add Frank's rev'd-by Changes in V2: Always return 0 from suspend callback Amend commit message drivers/i3c/master/mipi-i3c-hci/core.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index b781dbed2165..afb0764b5e1f 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -762,15 +762,10 @@ static int i3c_hci_reset_and_init(struct i3c_hci *hci) int i3c_hci_rpm_suspend(struct device *dev) { struct i3c_hci *hci =3D dev_get_drvdata(dev); - int ret; =20 - ret =3D i3c_hci_bus_disable(hci); - if (ret) { - /* Fall back to software reset to disable the bus */ - ret =3D i3c_hci_software_reset(hci); - i3c_hci_sync_irq_inactive(hci); - return ret; - } + /* Fall back to software reset to disable the bus */ + if (i3c_hci_bus_disable(hci)) + i3c_hci_software_reset(hci); =20 hci->io->suspend(hci); =20 --=20 2.51.0 From nobody Mon Jun 8 07:21:44 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 905F637883D for ; Wed, 3 Jun 2026 09:08:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780477695; cv=none; b=rTwCTyI6eECrFwg9RK7gZVJE3k78fY0xVsM+EuCkvZNLddkQ2yE04NNOdZ+ksmvEbdFzsVE1FxMc3Ff0jAbTXKdZyBPVaok3YPw7AGMi8wRAybvfpIbQmwNnrX7Nj4rO7MGclvIPCerKF0oHYJNe8g2P3BVhQHuM0ojkg7PCYjY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780477695; c=relaxed/simple; bh=KP3kMxkM4Qaxsw8Trwrd+QR1CMRx14o7NA48dVHMewg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WCMhqqrG63OKTmwSaHpEEADs12aDYUuMgnrWTyHa1Usentxr+gvv0OqaH8dbpeCaA8wJ49O7hMTLNqmcOE7+x+Hx0M/ot+2dRs5Ks7+sOt18kFYDmWVPibiW1pmxDnYEL7PgndE02nY8PwlMMrA2yoqwHrYi5AuV8p7AVCCpWQE= ARC-Authentication-Results: i=1; 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X-CSE-ConnectionGUID: GUNmqkofRqWl8gWc43DJ9w== X-CSE-MsgGUID: WP+a0JR3Q3y53QL+xMruEw== X-IronPort-AV: E=McAfee;i="6800,10657,11805"; a="91852596" X-IronPort-AV: E=Sophos;i="6.24,184,1774335600"; d="scan'208";a="91852596" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2026 02:08:14 -0700 X-CSE-ConnectionGUID: B2lNsuIjSq6jtIDv6QcHGg== X-CSE-MsgGUID: O95FU69RSf+Qw4BpFVm/MA== X-ExtLoop1: 1 Received: from ijarvine-mobl1.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.137]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2026 02:08:12 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V5 02/17] i3c: mipi-i3c-hci: Preserve RUN bit when aborting DMA ring Date: Wed, 3 Jun 2026 12:07:39 +0300 Message-ID: <20260603090754.16252-3-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260603090754.16252-1-adrian.hunter@intel.com> References: <20260603090754.16252-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MIPI I3C HCI specification does not require the DMA ring RUN bit (RUN_STOP) to be cleared when issuing an ABORT. That allows the DMA ring to continue to receive IBIs, although an IBI is anyway not lost because it can be received once the ring restarts if the I3C device has not given up. Note, currently ABORT is only used on a timeout error path so the change has very little effect in practice. In the more common case of a transfer error, the ring (bundle) operation is halted by the controller anyway. Adjust the RING_CONTROL handling to set ABORT without clearing RUN_STOP, bringing the driver into alignment with the specification. Fixes: b795e68bf3073 ("i3c: mipi-i3c-hci: Correct RING_CTRL_ABORT handling = in DMA dequeue") Signed-off-by: Adrian Hunter Reviewed-by: Frank Li --- Changes in V4 and V5: None Changes in V3: Add Frank's rev'd-by Changes in V2: Improve commit message drivers/i3c/master/mipi-i3c-hci/dma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index e4daaa612055..bdffdd8b8923 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -554,7 +554,7 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, if (ring_status & RING_STATUS_RUNNING) { /* stop the ring */ reinit_completion(&rh->op_done); - rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE | RING_CTRL_ABORT); + rh_reg_write(RING_CONTROL, rh_reg_read(RING_CONTROL) | RING_CTRL_ABORT); wait_for_completion_timeout(&rh->op_done, HZ); ring_status =3D rh_reg_read(RING_STATUS); if (ring_status & RING_STATUS_RUNNING) { --=20 2.51.0 From nobody Mon Jun 8 07:21:44 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B4E5363C7C for ; Wed, 3 Jun 2026 09:08:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780477697; cv=none; b=bgVKXvCkxMMd2IPbDC7eL+OgX05BX4a8wlayPNJAhMRgQSTueot0GIjPgT85UgFQFYWeLkuVD6NqKeNoTx/Thmaa60dYkr636pis8eJf/9BMcrHg5ojQ5aKt4Ckvjj0oQ5+mHRuKK/HrtXx4J26B6ZCLZSqhUJn1sl9egREF+Yw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780477697; c=relaxed/simple; bh=VfVk0nSvQ64OhGZLsAGoQ13MEl4eNrUGeTRHkVeZGFQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=l1dgNUDvSbwQcSIwyGvYTcuW7jk6eKBgvo/GGhDappWYHR4RdDNNx2np0XpL7fPqAQD+0WZgdLpKnYZ2vITpzGsAtQGLzRIGE4q3gfd40AD/ZdVMwbe6syhY16GSsopmn5S1jfn4RfmOFlbzutdv32B3SoI6HupKnVCpHzrAHU8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=lKUt8RrV; arc=none smtp.client-ip=192.198.163.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="lKUt8RrV" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1780477696; x=1812013696; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VfVk0nSvQ64OhGZLsAGoQ13MEl4eNrUGeTRHkVeZGFQ=; b=lKUt8RrVd174fWHYeUElKKV0Um7qZRvdsSE98AZ6rGiBiII/96B5oI6Q zPs98T8JVySuSqS6h2MiSwED/E/Fvn7oT7pNoOC25octd59j+tPbp1pPP 3E7ZeNmoYNzHB98+tRpi24Lxn5Lo81BVvuVhivR9tYivEdpTaoD7D2wxr 4HDnGi7vO+9BSzafRD9pSqkQ7t3l9HFkxJiQ3OcALSW0MMA3eovRl9oia BO/REEF4H2W16hE4w9PnSYdeq6vZJ4j19UCogZLF6bUUEf9IMMuokOGIy iH1SsZE0JumcmQ9/mrHitw0b3zQ1lBy9JLjxMOpE8H7+S3/2HqfjTtVTy w==; X-CSE-ConnectionGUID: 0maa97TxS+i+H8PM1odMDg== X-CSE-MsgGUID: RbqBhEX0SgOEaDuqJb4Ouw== X-IronPort-AV: E=McAfee;i="6800,10657,11805"; a="91852601" X-IronPort-AV: E=Sophos;i="6.24,184,1774335600"; d="scan'208";a="91852601" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2026 02:08:16 -0700 X-CSE-ConnectionGUID: siH4FwTCS0CUwkEBkywvEg== X-CSE-MsgGUID: ub8G5ZZDQfSrPWb7y69gBA== X-ExtLoop1: 1 Received: from ijarvine-mobl1.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.137]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2026 02:08:14 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V5 03/17] i3c: mipi-i3c-hci: Prevent DMA enqueue while ring is aborting or in error Date: Wed, 3 Jun 2026 12:07:40 +0300 Message-ID: <20260603090754.16252-4-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260603090754.16252-1-adrian.hunter@intel.com> References: <20260603090754.16252-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Block the DMA enqueue path while a Ring abort is in progress or after an error condition has been detected. Previously, new transfers could be enqueued while the DMA Ring was being aborted or while error handling was underway. This allowed enqueue and error-recovery paths to run concurrently, potentially interfering with each other and corrupting Ring state. Introduce explicit enqueue blocking and a wait queue to serialize access: enqueue operations now wait until abort or error handling has completed before proceeding. Enqueue is unblocked once the Ring is safely restarted. Note, there is only 1 ring bundle configured, and a transfer error causes the controller to halt ring (bundle) operation, so there is only ever 1 outstanding error at a time. Furthermore, a later patch ensures that only the currently active transfer list can time out. Consequently, the DMA queue will not be unblocked while there are outstanding transfer errors or timeouts. Signed-off-by: Adrian Hunter Reviewed-by: Frank Li --- Changes in V5: None Changes in V4: Add Frank's Rev'd-by Changes in V3: None Changes in V2: Improve commit message drivers/i3c/master/mipi-i3c-hci/core.c | 1 + drivers/i3c/master/mipi-i3c-hci/dma.c | 25 +++++++++++++++++++++++-- drivers/i3c/master/mipi-i3c-hci/hci.h | 2 ++ 3 files changed, 26 insertions(+), 2 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index afb0764b5e1f..44617eb3a3f1 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -973,6 +973,7 @@ static int i3c_hci_probe(struct platform_device *pdev) =20 spin_lock_init(&hci->lock); mutex_init(&hci->control_mutex); + init_waitqueue_head(&hci->enqueue_wait_queue); =20 /* * Multi-bus instances share the same MMIO address range, but not diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index bdffdd8b8923..c3da6eab8eae 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -484,6 +484,12 @@ static int hci_dma_queue_xfer(struct i3c_hci *hci, =20 spin_lock_irq(&hci->lock); =20 + while (unlikely(hci->enqueue_blocked)) { + spin_unlock_irq(&hci->lock); + wait_event(hci->enqueue_wait_queue, !READ_ONCE(hci->enqueue_blocked)); + spin_lock_irq(&hci->lock); + } + if (n > rh->xfer_space) { spin_unlock_irq(&hci->lock); hci_dma_unmap_xfer(hci, xfer_list, n); @@ -539,6 +545,14 @@ static int hci_dma_queue_xfer(struct i3c_hci *hci, return 0; } =20 +static void hci_dma_unblock_enqueue(struct i3c_hci *hci) +{ + if (hci->enqueue_blocked) { + hci->enqueue_blocked =3D false; + wake_up_all(&hci->enqueue_wait_queue); + } +} + static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, struct hci_xfer *xfer_list, int n) { @@ -550,12 +564,17 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, =20 guard(mutex)(&hci->control_mutex); =20 + spin_lock_irq(&hci->lock); + ring_status =3D rh_reg_read(RING_STATUS); if (ring_status & RING_STATUS_RUNNING) { + hci->enqueue_blocked =3D true; + spin_unlock_irq(&hci->lock); /* stop the ring */ reinit_completion(&rh->op_done); rh_reg_write(RING_CONTROL, rh_reg_read(RING_CONTROL) | RING_CTRL_ABORT); wait_for_completion_timeout(&rh->op_done, HZ); + spin_lock_irq(&hci->lock); ring_status =3D rh_reg_read(RING_STATUS); if (ring_status & RING_STATUS_RUNNING) { /* @@ -567,8 +586,6 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, } } =20 - spin_lock_irq(&hci->lock); - for (i =3D 0; i < n; i++) { struct hci_xfer *xfer =3D xfer_list + i; int idx =3D xfer->ring_entry; @@ -604,6 +621,8 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE); rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE | RING_CTRL_RUN_STOP); =20 + hci_dma_unblock_enqueue(hci); + spin_unlock_irq(&hci->lock); =20 return did_unqueue; @@ -647,6 +666,8 @@ static void hci_dma_xfer_done(struct i3c_hci *hci, stru= ct hci_rh_data *rh) } if (xfer->completion) complete(xfer->completion); + if (RESP_STATUS(resp)) + hci->enqueue_blocked =3D true; } =20 done_ptr =3D (done_ptr + 1) % rh->xfer_entries; diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mip= i-i3c-hci/hci.h index f17f43494c1b..d630400ec945 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -54,6 +54,8 @@ struct i3c_hci { struct mutex control_mutex; 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03 Jun 2026 02:08:16 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V5 04/17] i3c: mipi-i3c-hci: Wait for DMA ring restart to complete Date: Wed, 3 Jun 2026 12:07:41 +0300 Message-ID: <20260603090754.16252-5-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260603090754.16252-1-adrian.hunter@intel.com> References: <20260603090754.16252-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Although hci_dma_dequeue_xfer() is serialized against itself via control_mutex, this does not guarantee that a DMA ring restart triggered by a previous invocation has fully completed. When the function is called again in rapid succession, the DMA ring may still be transitioning back to the running state, which may confound or disrupt further state changes. Address this by waiting for the DMA ring restart to complete before continuing. Signed-off-by: Adrian Hunter Reviewed-by: Frank Li --- Changes in V5: None Changes in V4: Add Frank's Rev'd-by Changes in V2 and V3: None drivers/i3c/master/mipi-i3c-hci/dma.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index c3da6eab8eae..3b14bc87bdf6 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -617,6 +617,7 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, } =20 /* restart the ring */ + reinit_completion(&rh->op_done); mipi_i3c_hci_resume(hci); rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE); rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE | RING_CTRL_RUN_STOP); @@ -625,6 +626,8 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, =20 spin_unlock_irq(&hci->lock); =20 + wait_for_completion_timeout(&rh->op_done, HZ); + return did_unqueue; } =20 --=20 2.51.0 From nobody Mon Jun 8 07:21:44 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C95B37BE7E for ; Wed, 3 Jun 2026 09:08:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780477702; cv=none; b=BqIKAgo+3HgTwjp9zGaPTtWd3fRSHo9iW5GrzhZiAKeqJhXrW4rr+58BhYAh3Cu18SoPpsRKoRLGOc300GnzwOgVLZhTcNxd8aIQilslRSyegdWGJ4bCcn1veBs16Okoc76Kx6YrCrz5cQ25QN4HtzQP+p9TpGheJOmYd4ojTmY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780477702; c=relaxed/simple; bh=FrOJT+GMlFZupkFUGhXMbzwd+H6FKn1hNvq7sark9fs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ge/AlBr33kzRCtlAa+Kq3nWOUgvCu5BYVV6yF5vgh3UhwAFdqq9Cns/Ow3ms7mOwlipSWetE+19J1I9SvovjTLotR0V5aN6H/LLBpiRzkL2yDtdODvWHugb9Q3TnSW/O5ZD1DHLVEAwSXjgqPx2FAVFqjax/RkrfIjxgMtPPr9U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=A6AC6HXm; arc=none smtp.client-ip=192.198.163.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="A6AC6HXm" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1780477700; x=1812013700; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FrOJT+GMlFZupkFUGhXMbzwd+H6FKn1hNvq7sark9fs=; b=A6AC6HXmDHnsd0zwnKOMfBXR7geJdnHildGI47LOBHJPYEpgtLKeTaU4 mRx0xWUMYevOX49A/y95HQJBNbSKVV2dhtHFZOwVQiTVzy2ZeOLj5XvW5 q6hRQ0T2tNTFpZzG24VvqRD3genDPeMvzF7GzXAsdwjtBFOsP+ZBBhpJ9 1oITkBQ3QiiBbAMIlnI64augxorVkwn8ejvkoffRqsZ6rW5njbLWiP/E4 PE2noHTY7YyAgxysPwGoyL8VX0EPhJ55V9TirSJyhvrkMnJigbKvB2iiG uWQaHY4V2S8P28aZauTGQ0e1zJLdpYk4+zIDj00gfIxqFOUqnkkM4rEig A==; X-CSE-ConnectionGUID: IjojpIXJTqKkA5NKZfX+GA== X-CSE-MsgGUID: xHvoPyybTHC9hFBdAUebFQ== X-IronPort-AV: E=McAfee;i="6800,10657,11805"; a="91852611" X-IronPort-AV: E=Sophos;i="6.24,184,1774335600"; d="scan'208";a="91852611" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2026 02:08:19 -0700 X-CSE-ConnectionGUID: m8tyBmAaRlaTx1atbB/jOQ== X-CSE-MsgGUID: 79qOXMN5QGyzRMZpz6f0tQ== X-ExtLoop1: 1 Received: from ijarvine-mobl1.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.137]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2026 02:08:18 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V5 05/17] i3c: mipi-i3c-hci: Move hci_dma_xfer_done() definition Date: Wed, 3 Jun 2026 12:07:42 +0300 Message-ID: <20260603090754.16252-6-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260603090754.16252-1-adrian.hunter@intel.com> References: <20260603090754.16252-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move hci_dma_xfer_done() earlier in the file to avoid a forward declaration needed by a subsequent change. No functional change. Signed-off-by: Adrian Hunter Reviewed-by: Frank Li --- Changes in V3, V4 and V5: None Changes in V2: Added Frank's Rev'd-by drivers/i3c/master/mipi-i3c-hci/dma.c | 98 +++++++++++++-------------- 1 file changed, 49 insertions(+), 49 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index 3b14bc87bdf6..ad47bb2890d6 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -545,6 +545,55 @@ static int hci_dma_queue_xfer(struct i3c_hci *hci, return 0; } =20 +static void hci_dma_xfer_done(struct i3c_hci *hci, struct hci_rh_data *rh) +{ + u32 op1_val, op2_val, resp, *ring_resp; + unsigned int tid, done_ptr =3D rh->done_ptr; + unsigned int done_cnt =3D 0; + struct hci_xfer *xfer; + + for (;;) { + op2_val =3D rh_reg_read(RING_OPERATION2); + if (done_ptr =3D=3D FIELD_GET(RING_OP2_CR_DEQ_PTR, op2_val)) + break; + + ring_resp =3D rh->resp + rh->resp_struct_sz * done_ptr; + resp =3D *ring_resp; + tid =3D RESP_TID(resp); + dev_dbg(&hci->master.dev, "resp =3D 0x%08x", resp); + + xfer =3D rh->src_xfers[done_ptr]; + if (!xfer) { + dev_dbg(&hci->master.dev, "orphaned ring entry"); + } else { + hci_dma_unmap_xfer(hci, xfer, 1); + rh->src_xfers[done_ptr] =3D NULL; + xfer->ring_entry =3D -1; + xfer->response =3D resp; + if (tid !=3D xfer->cmd_tid) { + dev_err(&hci->master.dev, + "response tid=3D%d when expecting %d\n", + tid, xfer->cmd_tid); + /* TODO: do something about it? */ + } + if (xfer->completion) + complete(xfer->completion); + if (RESP_STATUS(resp)) + hci->enqueue_blocked =3D true; + } + + done_ptr =3D (done_ptr + 1) % rh->xfer_entries; + rh->done_ptr =3D done_ptr; + done_cnt +=3D 1; + } + + rh->xfer_space +=3D done_cnt; + op1_val =3D rh_reg_read(RING_OPERATION1); + op1_val &=3D ~RING_OP1_CR_SW_DEQ_PTR; + op1_val |=3D FIELD_PREP(RING_OP1_CR_SW_DEQ_PTR, done_ptr); + rh_reg_write(RING_OPERATION1, op1_val); +} + static void hci_dma_unblock_enqueue(struct i3c_hci *hci) { if (hci->enqueue_blocked) { @@ -636,55 +685,6 @@ static int hci_dma_handle_error(struct i3c_hci *hci, s= truct hci_xfer *xfer_list, return hci_dma_dequeue_xfer(hci, xfer_list, n) ? -EIO : 0; } =20 -static void hci_dma_xfer_done(struct i3c_hci *hci, struct hci_rh_data *rh) -{ - u32 op1_val, op2_val, resp, *ring_resp; - unsigned int tid, done_ptr =3D rh->done_ptr; - unsigned int done_cnt =3D 0; - struct hci_xfer *xfer; - - for (;;) { - op2_val =3D rh_reg_read(RING_OPERATION2); - if (done_ptr =3D=3D FIELD_GET(RING_OP2_CR_DEQ_PTR, op2_val)) - break; - - ring_resp =3D rh->resp + rh->resp_struct_sz * done_ptr; - resp =3D *ring_resp; - tid =3D RESP_TID(resp); - dev_dbg(&hci->master.dev, "resp =3D 0x%08x", resp); - - xfer =3D rh->src_xfers[done_ptr]; - if (!xfer) { - dev_dbg(&hci->master.dev, "orphaned ring entry"); - } else { - hci_dma_unmap_xfer(hci, xfer, 1); - rh->src_xfers[done_ptr] =3D NULL; - xfer->ring_entry =3D -1; - xfer->response =3D resp; - if (tid !=3D xfer->cmd_tid) { - dev_err(&hci->master.dev, - "response tid=3D%d when expecting %d\n", - tid, xfer->cmd_tid); - /* TODO: do something about it? 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Ensure that state is current by explicitly invoking hci_dma_xfer_done() from the dequeue path. This handles cases where the interrupt handler has not (yet) run. Signed-off-by: Adrian Hunter Reviewed-by: Frank Li --- Changes in V3, V4 and V5: None Changes in V2: Added Frank's Rev'd-by drivers/i3c/master/mipi-i3c-hci/dma.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index ad47bb2890d6..de0f17706ac8 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -635,6 +635,8 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, } } =20 + hci_dma_xfer_done(hci, rh); + for (i =3D 0; i < n; i++) { struct hci_xfer *xfer =3D xfer_list + i; int idx =3D xfer->ring_entry; --=20 2.51.0 From nobody Mon Jun 8 07:21:44 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66FE8383990 for ; Wed, 3 Jun 2026 09:08:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780477705; cv=none; b=mPRietJ9BdUGRpO2ICqtVGeFZKOkn7WurHbR7+keD302Eo4lLZ88lboFx4tC21gJEv8RopcDJxsYWZxl/+U3MoMmDuQ0bB8JvKb1wfcZAJ7blj9c6psKEKHOiGO35Q4Tyfq8WOfA3I/AWmnJCHkYhYbUfyxKTXoMFUTwEpL4Wh8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780477705; c=relaxed/simple; bh=DsICVlOvRdlQaow2uDWMlLgbNbrKrTwlqv8CdDKZgsA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=B8u4svXkQjBeWyo53+KK+YvJOiucmUqlBdLo67I6lPR2oGubfkq02IWxOlEIZUPJu9n6cWiFZR7jPXlnK8FYOBlNJH3YSrDxrVpHdlOaRRFDRyyGHKQ3pAA7PxYYSUhfKwK8UoaD9d3i8Isr72SACmuvzfFR2eapGuwauSc51ik= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=PEcNWsKd; arc=none smtp.client-ip=192.198.163.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="PEcNWsKd" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1780477704; x=1812013704; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DsICVlOvRdlQaow2uDWMlLgbNbrKrTwlqv8CdDKZgsA=; b=PEcNWsKd+HQAneOVDs8O84zdQJw0NtIxDUo+fdlMtAWLQWRlPJ5kc0OX 1xR/mV/GA2n5x1fJ3m+ku0Wvbm1kUr7kHDjWWVX5PDEOdqHPoHRYJfqd+ HWNsOlSku4YIcNXy3oqCYKXKp5zTQ8gdGfTTotEDzHYNYR9K2JT8EPutq ktS1IYzFr5wrbYRmrrzzOaWesXVFWeHYdDWs8hyedbnDaT2R1aD3D6ifs x37H83i3FFRa37OxhB0ATbQBKfqwWD+rp/UdR6AoyQDSJYRFBYiPmGaTx TwdDyju8VsTbrWfp184KgzlKnteBIE/v1e5y5gAQOD0Dz9gUR+v6kBUmq A==; X-CSE-ConnectionGUID: 0N11YeBcTpGLPFgrlYXSPg== X-CSE-MsgGUID: 7yzuCPHXROiW4mjn11SJ6g== X-IronPort-AV: E=McAfee;i="6800,10657,11805"; a="91852625" X-IronPort-AV: E=Sophos;i="6.24,184,1774335600"; d="scan'208";a="91852625" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2026 02:08:23 -0700 X-CSE-ConnectionGUID: vINVySw1RcGb6vTgAO6PCA== X-CSE-MsgGUID: 45mm99X7T0W+Is7rdTjBuQ== X-ExtLoop1: 1 Received: from ijarvine-mobl1.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.137]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2026 02:08:21 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V5 07/17] i3c: mipi-i3c-hci: Complete transfer lists immediately on error Date: Wed, 3 Jun 2026 12:07:44 +0300 Message-ID: <20260603090754.16252-8-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260603090754.16252-1-adrian.hunter@intel.com> References: <20260603090754.16252-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In DMA mode, transfer lists are currently completed only when the final transfer in the list completes. If an earlier transfer fails, the list is left incomplete and callers wait until timeout. There is no need to wait for a timeout, as the completion path in i3c_hci_process_xfer() already checks for error status. Complete the transfer list as soon as any transfer in the list reports an error. This avoids unnecessary delays and spurious timeouts on error. Complete a transfer list completion immediately there is an error. Signed-off-by: Adrian Hunter Reviewed-by: Frank Li --- Changes in V5: None Changes in V4: Add Frank's Rev'd-by Changes in V3: None Changes in V2: Renamed completing_xfer to final_xfer drivers/i3c/master/mipi-i3c-hci/dma.c | 6 ++++-- drivers/i3c/master/mipi-i3c-hci/hci.h | 1 + 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index de0f17706ac8..83b553e1ab0b 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -502,6 +502,8 @@ static int hci_dma_queue_xfer(struct i3c_hci *hci, struct hci_xfer *xfer =3D xfer_list + i; u32 *ring_data =3D rh->xfer + rh->xfer_struct_sz * enqueue_ptr; =20 + xfer->final_xfer =3D xfer_list + n - 1; + /* store cmd descriptor */ *ring_data++ =3D xfer->cmd_desc[0]; *ring_data++ =3D xfer->cmd_desc[1]; @@ -576,8 +578,8 @@ static void hci_dma_xfer_done(struct i3c_hci *hci, stru= ct hci_rh_data *rh) tid, xfer->cmd_tid); /* TODO: do something about it? */ } - if (xfer->completion) - complete(xfer->completion); + if (xfer =3D=3D xfer->final_xfer || RESP_STATUS(resp)) + complete(xfer->final_xfer->completion); if (RESP_STATUS(resp)) hci->enqueue_blocked =3D true; } diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mip= i-i3c-hci/hci.h index d630400ec945..f07fc627d4d2 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -104,6 +104,7 @@ struct hci_xfer { struct { /* DMA specific */ struct i3c_dma *dma; + struct hci_xfer *final_xfer; int ring_number; int ring_entry; }; --=20 2.51.0 From nobody Mon Jun 8 07:21:44 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC72437CD2A for ; Wed, 3 Jun 2026 09:08:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780477707; cv=none; b=VKQdR8HmeIYCJRSV8lFICOEvZvGOElXh3ezep/cNaJYoxP5TvwS5DCF62kcy0HYbiJa+/BTN5fx4sy/pM2a8snYmnczhbpOq9B2tTRHlnoeEPcvFwBPBL7YFZeGZMrvsw3Ga1VP62U1vJYEHDKtzIKhpPZAC0CvKdHenk1/9rYU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780477707; c=relaxed/simple; bh=rw7N7Pd11uGRr4oX7ZhsDrNgVcm9Fa3zHLK8UBO3wuE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rc/y63ZwSHtElgiIoDejUaJ4A8EJNmFD0LdKmxkOa1sB8ae+Gln44ahU2ZA6vR62sL/R2AF3QU52UR602XeVROa8rmihyJhnq65WahLVyFHp14R5bOX6KPZa9k9FiJmdwlDcfMntTBTZj4R+XxOAAa0AQlqtB2+QIPFieRkA1m8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=LreF385L; arc=none smtp.client-ip=192.198.163.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="LreF385L" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1780477705; x=1812013705; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rw7N7Pd11uGRr4oX7ZhsDrNgVcm9Fa3zHLK8UBO3wuE=; b=LreF385LOcYWAidFgojPy9+f0My/oX5znbeznBTN4gx77WB5pQoYvHFQ SwkHWXNcItNrmRLQp3DXER9UqLD+0Et3SatrcGXu+q9UqiS80BpMeay8q IswY27tLyHmyO4uy7rie7EuqmvPG7tldJ24ZPlnOdz7HWRMMgDXBkt9CS z9tewdqJFHXsTzMuDyLMnnrpdQXMFzFuS47c0iQfWhWyw5qKvPz4PlRgd UCQe22MhxoKW6aLKA2KQSh31cwlZXDwlQDRfn3a2tgL6o2ZCtDBUOIBRL vL7Fn3p4M6wGjyDNF0PMSUnCkKhEHsq7gwSu4ySevxcKCEmoo8uflUi0G A==; X-CSE-ConnectionGUID: cE2CdijaQOa49Zd+6+E9Zg== X-CSE-MsgGUID: ZQKE48zpTceChy0KI23IiQ== X-IronPort-AV: E=McAfee;i="6800,10657,11805"; a="91852633" X-IronPort-AV: E=Sophos;i="6.24,184,1774335600"; d="scan'208";a="91852633" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2026 02:08:25 -0700 X-CSE-ConnectionGUID: s7J3NR37TmG4UpmO9XBmcA== X-CSE-MsgGUID: nYLlYqNRRh62lecRkDor4g== X-ExtLoop1: 1 Received: from ijarvine-mobl1.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.137]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2026 02:08:24 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V5 08/17] i3c: mipi-i3c-hci: Avoid restarting DMA ring after aborting wrong transfer Date: Wed, 3 Jun 2026 12:07:45 +0300 Message-ID: <20260603090754.16252-9-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260603090754.16252-1-adrian.hunter@intel.com> References: <20260603090754.16252-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Software ABORT of the DMA ring is used to recover from transfer list timeouts, but it is inherently racy. The intended transfer list may complete just before the ABORT takes effect, causing the subsequent transfer list to be aborted instead. In this case, an incomplete transfer list may remain in the ring and has not yet been processed by hci_dma_dequeue_xfer(). Restarting the DMA ring at that point can lead to unpredictable results. Detect when the next queued transfer is not the first entry of a transfer list and does not belong to the list currently being dequeued. In that case, skip restarting the DMA ring and defer recovery until a subsequent call to hci_dma_dequeue_xfer(), which will safely restart the ring once the incomplete list is handled. Signed-off-by: Adrian Hunter Reviewed-by: Frank Li --- Changes in V5: Added Frank's Rev'ed-by Changes in V3 and V4: None Changes in V2: Renamed completing_xfer to final_xfer drivers/i3c/master/mipi-i3c-hci/dma.c | 15 +++++++++++++++ drivers/i3c/master/mipi-i3c-hci/hci.h | 1 + 2 files changed, 16 insertions(+) diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index 83b553e1ab0b..8e27fb6f18f5 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -503,6 +503,7 @@ static int hci_dma_queue_xfer(struct i3c_hci *hci, u32 *ring_data =3D rh->xfer + rh->xfer_struct_sz * enqueue_ptr; =20 xfer->final_xfer =3D xfer_list + n - 1; + xfer->xfer_list_pos =3D i; =20 /* store cmd descriptor */ *ring_data++ =3D xfer->cmd_desc[0]; @@ -669,6 +670,20 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, } } =20 + /* + * A software ABORT may race with transfer completion and abort the next + * transfer list instead. Detect that case, and do not restart the ring. + * It will be handled by a subsequent dequeue. + */ + if (!did_unqueue) { + struct hci_xfer *xfer =3D rh->src_xfers[rh->done_ptr]; + + if (xfer && xfer->xfer_list_pos && xfer->final_xfer !=3D xfer_list->fina= l_xfer) { + spin_unlock_irq(&hci->lock); + return false; + } + } + /* restart the ring */ reinit_completion(&rh->op_done); mipi_i3c_hci_resume(hci); diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mip= i-i3c-hci/hci.h index f07fc627d4d2..83d4f13a68a3 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -107,6 +107,7 @@ struct hci_xfer { struct hci_xfer *final_xfer; int ring_number; int ring_entry; + int xfer_list_pos; }; }; }; --=20 2.51.0 From nobody Mon Jun 8 07:21:44 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E7E47379EE8 for ; Wed, 3 Jun 2026 09:08:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780477710; cv=none; b=tY3e6Z81ePO1C/5MlvI3N9Fd9XAxuaDYZ5QrgCsXXYD6N97vVkybpPvZZb9q9yTg68Rz6l/QXi6ZJEJ9iDUyuWFrH7C36VQf0rakdQH6Lp/nDnhP/ACuNya8kOi+j0NH9TU52Kfk8HrixDUKu6cLx3C1ILWnVzu14BRKBYZlsT8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780477710; c=relaxed/simple; bh=6RRaJreBve6mu8ti+xens3YsDLsfCy9RNn77rU5QanU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bBChmW6GP8gwZyNGMapWf7vzKF/mgag8jEaojsPKx+5T4J8WHwn3zdu8tFEXBqsyFU2UK/KHX1g2n7xzQcebpXOj8VLpUYJMgfwApf8+8B63/b3LIKVgF56frc8H8tGGWTYxu4vtWdLaXcRFFtGxftPDr7WjukgN3doTJQMcK2w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=cOODCrfp; arc=none smtp.client-ip=192.198.163.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="cOODCrfp" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1780477708; x=1812013708; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6RRaJreBve6mu8ti+xens3YsDLsfCy9RNn77rU5QanU=; b=cOODCrfpRhp6YRYzPtaxhxA/hpl7xu7cunkNYktTJX08TkwZLbHc0IdI vp6YpvbvS0F+xqhuyDeO6Oc19ekinQtiBCqciLh2n7wNRCdhPY1xHia3c l1F3+zSFSJexKBWcT9sQhVmlk3IOyRJyy9W5fedyJpW/vP3dkbBxsXJRG SIyjEvsadWu0rDILL6Y0c1R/39ASmw+NrYViJ8pd2ezHq7t6RpHyX5Wma vbG5w7qq7pAdy0FV+D1gmcARDaUzUYG2HWHjpMOh6wkNR/XXxzAqFHjC3 LDpHBx1Xc1mYYShQxeWZVx9aCO67PR/gwI9T5exvuSX21VA9K9YuHaVMa A==; X-CSE-ConnectionGUID: pfHyPjmzRpaOrUOaNtKOEg== X-CSE-MsgGUID: XAb0VjNGS3CJEiuVtWHR0w== X-IronPort-AV: E=McAfee;i="6800,10657,11805"; a="91852638" X-IronPort-AV: E=Sophos;i="6.24,184,1774335600"; d="scan'208";a="91852638" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2026 02:08:27 -0700 X-CSE-ConnectionGUID: 1Abb0JRZR7q72dnxBmwMtw== X-CSE-MsgGUID: HfR3/B5/QSWWqvhzM+ZQ9A== X-ExtLoop1: 1 Received: from ijarvine-mobl1.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.137]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2026 02:08:25 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V5 09/17] i3c: mipi-i3c-hci: Add DMA ring abort/reset quirk for Intel controllers Date: Wed, 3 Jun 2026 12:07:46 +0300 Message-ID: <20260603090754.16252-10-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260603090754.16252-1-adrian.hunter@intel.com> References: <20260603090754.16252-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some Intel I3C HCI controllers cannot reliably restart a DMA ring after an ABORT. Additional queue resets are required to recover, and must be performed using PIO reset bits even while operating in DMA mode. This behavior is non-standard. Introduce a controller quirk to opt into the required PIO queue resets after a DMA ring abort, and enable it for Intel LPSS I3C controllers. Signed-off-by: Adrian Hunter Reviewed-by: Frank Li --- Changes in V5: Added Frank's Rev'ed-by Changes in V4: Inline HCI_QUIRK_DMA_ABORT_REQUIRES_PIO_RESET check at call site instead of using a helper function Changes in V2 and V3: None drivers/i3c/master/mipi-i3c-hci/core.c | 15 ++++++++++++++- drivers/i3c/master/mipi-i3c-hci/dma.c | 4 ++++ drivers/i3c/master/mipi-i3c-hci/hci.h | 2 ++ 3 files changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index 44617eb3a3f1..770235ad6b25 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -240,6 +240,18 @@ void mipi_i3c_hci_pio_reset(struct i3c_hci *hci) reg_write(RESET_CONTROL, RX_FIFO_RST | TX_FIFO_RST | RESP_QUEUE_RST); } =20 +#define ALL_QUEUES_RST (CMD_QUEUE_RST | RESP_QUEUE_RST | RX_FIFO_RST | TX_= FIFO_RST | IBI_QUEUE_RST) + +void mipi_i3c_hci_pio_reset_all_queues(struct i3c_hci *hci) +{ + u32 regval; + + reg_write(RESET_CONTROL, ALL_QUEUES_RST); + if (readx_poll_timeout_atomic(reg_read, RESET_CONTROL, regval, + !(regval & ALL_QUEUES_RST), 0, 20)) + dev_err(&hci->master.dev, "%s: Reset queues failed\n", __func__); +} + /* located here rather than dct.c because needed bits are in core reg spac= e */ void mipi_i3c_hci_dct_index_reset(struct i3c_hci *hci) { @@ -1040,7 +1052,8 @@ MODULE_DEVICE_TABLE(acpi, i3c_hci_acpi_match); static const struct platform_device_id i3c_hci_driver_ids[] =3D { { .name =3D "intel-lpss-i3c", HCI_QUIRK_RPM_ALLOWED | HCI_QUIRK_RPM_IBI_ALLOWED | - HCI_QUIRK_RPM_PARENT_MANAGED }, + HCI_QUIRK_RPM_PARENT_MANAGED | + HCI_QUIRK_DMA_ABORT_REQUIRES_PIO_RESET }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(platform, i3c_hci_driver_ids); diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index 8e27fb6f18f5..906de7dbfdb5 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -638,6 +638,10 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, } } =20 + if ((hci->quirks & HCI_QUIRK_DMA_ABORT_REQUIRES_PIO_RESET) && + (rh_reg_read(RING_STATUS) & RING_STATUS_ABORTED)) + mipi_i3c_hci_pio_reset_all_queues(hci); + hci_dma_xfer_done(hci, rh); =20 for (i =3D 0; i < n; i++) { diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mip= i-i3c-hci/hci.h index 83d4f13a68a3..01237b12d32e 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -156,10 +156,12 @@ struct i3c_hci_dev_data { #define HCI_QUIRK_RPM_ALLOWED BIT(5) /* Runtime PM allowed */ #define HCI_QUIRK_RPM_IBI_ALLOWED BIT(6) /* IBI and Hot-Join allowed whil= e runtime suspended */ #define HCI_QUIRK_RPM_PARENT_MANAGED BIT(7) /* Runtime PM managed by pare= nt device */ +#define HCI_QUIRK_DMA_ABORT_REQUIRES_PIO_RESET BIT(8) /* Do PIO queue SW = resets after DMA abort */ =20 /* global functions */ void mipi_i3c_hci_resume(struct i3c_hci *hci); void mipi_i3c_hci_pio_reset(struct i3c_hci *hci); +void mipi_i3c_hci_pio_reset_all_queues(struct i3c_hci *hci); void mipi_i3c_hci_dct_index_reset(struct i3c_hci *hci); void amd_set_od_pp_timing(struct i3c_hci *hci); void amd_set_resp_buf_thld(struct i3c_hci *hci); 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charset="utf-8" Factor out hci_dma_abort() from hci_dma_dequeue_xfer() in preparation for further changes. Signed-off-by: Adrian Hunter Reviewed-by: Frank Li --- Changes in V5: Added Frank's Rev'ed-by Changes in V4: New patch drivers/i3c/master/mipi-i3c-hci/dma.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index 906de7dbfdb5..f2d33068b8df 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -597,6 +597,13 @@ static void hci_dma_xfer_done(struct i3c_hci *hci, str= uct hci_rh_data *rh) rh_reg_write(RING_OPERATION1, op1_val); } =20 +static void hci_dma_abort(struct hci_rh_data *rh) +{ + reinit_completion(&rh->op_done); + rh_reg_write(RING_CONTROL, rh_reg_read(RING_CONTROL) | RING_CTRL_ABORT); + wait_for_completion_timeout(&rh->op_done, HZ); +} + static void hci_dma_unblock_enqueue(struct i3c_hci *hci) { if (hci->enqueue_blocked) { @@ -623,9 +630,7 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, hci->enqueue_blocked =3D true; spin_unlock_irq(&hci->lock); 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03 Jun 2026 02:08:29 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V5 11/17] i3c: mipi-i3c-hci: Add DMA ring abort quirk for Intel controllers Date: Wed, 3 Jun 2026 12:07:48 +0300 Message-ID: <20260603090754.16252-12-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260603090754.16252-1-adrian.hunter@intel.com> References: <20260603090754.16252-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" DMA rings can be aborted either per-ring via RING_CONTROL or globally via HC_CONTROL_ABORT. The driver currently relies on the per-ring mechanism. Some Intel I3C HCI controllers require HC_CONTROL_ABORT to be asserted before a DMA ring abort is effective. This behavior is non-standard. Introduce a controller quirk to select the required abort method and enable it for Intel LPSS I3C controllers. Signed-off-by: Adrian Hunter Reviewed-by: Frank Li --- Changes in V5: Added Frank's Rev'ed-by Changes in V4: Factor out hci_dma_abort() into a preceding patch Make hci_dma_requires_hc_abort_quirk() return void and move quirk check to caller Changes in V2 and V3: None drivers/i3c/master/mipi-i3c-hci/core.c | 18 ++++++++++++++++-- drivers/i3c/master/mipi-i3c-hci/dma.c | 17 +++++++++++++++-- drivers/i3c/master/mipi-i3c-hci/hci.h | 2 ++ 3 files changed, 33 insertions(+), 4 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index 770235ad6b25..8274c84b16be 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -231,7 +231,20 @@ static void i3c_hci_bus_cleanup(struct i3c_master_cont= roller *m) =20 void mipi_i3c_hci_resume(struct i3c_hci *hci) { - reg_set(HC_CONTROL, HC_CONTROL_RESUME); + u32 reg =3D reg_read(HC_CONTROL); + + reg |=3D HC_CONTROL_RESUME; + reg &=3D ~HC_CONTROL_ABORT; + reg_write(HC_CONTROL, reg); +} + +void mipi_i3c_hci_abort(struct i3c_hci *hci) +{ + u32 reg =3D reg_read(HC_CONTROL); + + reg &=3D ~HC_CONTROL_RESUME; /* Do not set resume */ + reg |=3D HC_CONTROL_ABORT; + reg_write(HC_CONTROL, reg); } =20 /* located here rather than pio.c because needed bits are in core reg spac= e */ @@ -1053,7 +1066,8 @@ static const struct platform_device_id i3c_hci_driver= _ids[] =3D { { .name =3D "intel-lpss-i3c", HCI_QUIRK_RPM_ALLOWED | HCI_QUIRK_RPM_IBI_ALLOWED | HCI_QUIRK_RPM_PARENT_MANAGED | - HCI_QUIRK_DMA_ABORT_REQUIRES_PIO_RESET }, + HCI_QUIRK_DMA_ABORT_REQUIRES_PIO_RESET | + HCI_QUIRK_DMA_REQUIRES_HC_ABORT }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(platform, i3c_hci_driver_ids); diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index f2d33068b8df..f9023cb3c5a2 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -597,8 +597,21 @@ static void hci_dma_xfer_done(struct i3c_hci *hci, str= uct hci_rh_data *rh) rh_reg_write(RING_OPERATION1, op1_val); } =20 -static void hci_dma_abort(struct hci_rh_data *rh) +static void hci_dma_requires_hc_abort_quirk(struct i3c_hci *hci, struct hc= i_rh_data *rh) { + reinit_completion(&rh->op_done); + mipi_i3c_hci_abort(hci); + wait_for_completion_timeout(&rh->op_done, HZ); + rh_reg_write(RING_CONTROL, rh_reg_read(RING_CONTROL) | RING_CTRL_ABORT); +} + +static void hci_dma_abort(struct i3c_hci *hci, struct hci_rh_data *rh) +{ + if (hci->quirks & HCI_QUIRK_DMA_REQUIRES_HC_ABORT) { + hci_dma_requires_hc_abort_quirk(hci, rh); + return; + } + reinit_completion(&rh->op_done); rh_reg_write(RING_CONTROL, rh_reg_read(RING_CONTROL) | RING_CTRL_ABORT); wait_for_completion_timeout(&rh->op_done, HZ); @@ -630,7 +643,7 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, hci->enqueue_blocked =3D true; spin_unlock_irq(&hci->lock); /* stop the ring */ - hci_dma_abort(rh); + hci_dma_abort(hci, rh); spin_lock_irq(&hci->lock); ring_status =3D rh_reg_read(RING_STATUS); if (ring_status & RING_STATUS_RUNNING) { diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mip= i-i3c-hci/hci.h index 01237b12d32e..97c31a315a6e 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -157,9 +157,11 @@ struct i3c_hci_dev_data { #define HCI_QUIRK_RPM_IBI_ALLOWED BIT(6) /* IBI and Hot-Join allowed whil= e runtime suspended */ #define HCI_QUIRK_RPM_PARENT_MANAGED BIT(7) /* Runtime PM managed by pare= nt device */ #define HCI_QUIRK_DMA_ABORT_REQUIRES_PIO_RESET BIT(8) /* Do PIO queue SW = resets after DMA abort */ +#define HCI_QUIRK_DMA_REQUIRES_HC_ABORT BIT(9) /* Use HC_CONTROL ABORT t= o abort DMA */ =20 /* global functions */ void mipi_i3c_hci_resume(struct i3c_hci *hci); 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03 Jun 2026 02:08:31 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V5 12/17] i3c: mipi-i3c-hci: Factor out reset-and-restore helper Date: Wed, 3 Jun 2026 12:07:49 +0300 Message-ID: <20260603090754.16252-13-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260603090754.16252-1-adrian.hunter@intel.com> References: <20260603090754.16252-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Factor the reset-and-restore sequence out of i3c_hci_rpm_resume() into a separate helper. This allows the same logic to be reused for recovery paths in subsequent changes without duplicating suspend/resume handling. No functional change. Signed-off-by: Adrian Hunter Reviewed-by: Frank Li --- Changes in V5: None Changes in V4: Add Frank's Rev'd by Changes in V3: None Changes in V2: Drop redundant i3c_hci_sync_irq_inactive(hci) from i3c_hci_reset_and_restore() because it is called by hci->io->suspend() anyway drivers/i3c/master/mipi-i3c-hci/core.c | 19 +++++++++++++++++-- drivers/i3c/master/mipi-i3c-hci/hci.h | 2 ++ 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index 8274c84b16be..12a0122fb709 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -798,9 +798,8 @@ int i3c_hci_rpm_suspend(struct device *dev) } EXPORT_SYMBOL_GPL(i3c_hci_rpm_suspend); =20 -int i3c_hci_rpm_resume(struct device *dev) +static int i3c_hci_do_reset_and_restore(struct i3c_hci *hci) { - struct i3c_hci *hci =3D dev_get_drvdata(dev); int ret; =20 ret =3D i3c_hci_reset_and_init(hci); @@ -821,6 +820,22 @@ int i3c_hci_rpm_resume(struct device *dev) =20 return 0; } + +int i3c_hci_reset_and_restore(struct i3c_hci *hci) +{ + i3c_hci_bus_disable(hci); + + hci->io->suspend(hci); + + return i3c_hci_do_reset_and_restore(hci); +} + +int i3c_hci_rpm_resume(struct device *dev) +{ + struct i3c_hci *hci =3D dev_get_drvdata(dev); + + return i3c_hci_do_reset_and_restore(hci); +} EXPORT_SYMBOL_GPL(i3c_hci_rpm_resume); =20 static int i3c_hci_runtime_suspend(struct device *dev) diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mip= i-i3c-hci/hci.h index 97c31a315a6e..a3151c26827e 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -175,4 +175,6 @@ int i3c_hci_process_xfer(struct i3c_hci *hci, struct hc= i_xfer *xfer, int n); int i3c_hci_rpm_suspend(struct device *dev); int i3c_hci_rpm_resume(struct device *dev); =20 +int i3c_hci_reset_and_restore(struct i3c_hci *hci); + #endif --=20 2.51.0 From nobody Mon Jun 8 07:21:44 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A7AE3380FF9 for ; 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a="91852656" X-IronPort-AV: E=Sophos;i="6.24,184,1774335600"; d="scan'208";a="91852656" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2026 02:08:34 -0700 X-CSE-ConnectionGUID: cjYEjkP7T5GNiKRJ1uX2tA== X-CSE-MsgGUID: UIIs+bvPTa+uqRSw+JnVzQ== X-ExtLoop1: 1 Received: from ijarvine-mobl1.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.137]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2026 02:08:33 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V5 13/17] i3c: mipi-i3c-hci: Add DMA-mode recovery for internal controller errors Date: Wed, 3 Jun 2026 12:07:50 +0300 Message-ID: <20260603090754.16252-14-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260603090754.16252-1-adrian.hunter@intel.com> References: <20260603090754.16252-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Handle internal I3C HCI errors when operating in DMA mode by adding a simple recovery mechanism. On detection of an internal controller error, mark recovery as needed and attempt to restore operation by performing a software reset followed by state restore. To keep recovery straightforward on this unlikely error path, all currently queued transfers are terminated and completed with an error. This allows the controller to resume operation after internal failures rather than remaining permanently stuck. Note, internal errors indicated by INTR_HC_INTERNAL_ERR, cause the controller to stop. Signed-off-by: Adrian Hunter Reviewed-by: Frank Li --- Changes in V5: Added Frank's Rev'd-by Changes in V4: None Changes in V3: When erroring out transfers, ensure the final transfer of a transfer list is processed last Changes in V2: Rename completing_xfer to final_xfer Add hci_dma_xfer_done() before checking for an already complete transfer Improve commit message drivers/i3c/master/mipi-i3c-hci/cmd.h | 6 ++ drivers/i3c/master/mipi-i3c-hci/core.c | 1 + drivers/i3c/master/mipi-i3c-hci/dma.c | 93 +++++++++++++++++++++++--- drivers/i3c/master/mipi-i3c-hci/hci.h | 1 + 4 files changed, 92 insertions(+), 9 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/cmd.h b/drivers/i3c/master/mip= i-i3c-hci/cmd.h index b1bf87daa651..7bada7b4b2de 100644 --- a/drivers/i3c/master/mipi-i3c-hci/cmd.h +++ b/drivers/i3c/master/mipi-i3c-hci/cmd.h @@ -65,4 +65,10 @@ struct hci_cmd_ops { extern const struct hci_cmd_ops mipi_i3c_hci_cmd_v1; extern const struct hci_cmd_ops mipi_i3c_hci_cmd_v2; =20 +static inline void hci_cmd_set_resp_err(u32 *response, int resp_err) +{ + *response &=3D ~RESP_ERR_FIELD; + *response |=3D FIELD_PREP(RESP_ERR_FIELD, resp_err); +} + #endif diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index 12a0122fb709..69dcf5dad3a5 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -668,6 +668,7 @@ static irqreturn_t i3c_hci_irq_handler(int irq, void *d= ev_id) if (val & INTR_HC_INTERNAL_ERR) { dev_err(&hci->master.dev, "Host Controller Internal Error\n"); val &=3D ~INTR_HC_INTERNAL_ERR; + hci->recovery_needed =3D true; } =20 if (val) diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index f9023cb3c5a2..f39a6ce2aad5 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -9,6 +9,7 @@ */ =20 #include +#include #include #include #include @@ -258,6 +259,10 @@ static void hci_dma_init_rh(struct i3c_hci *hci, struc= t hci_rh_data *rh, int i) rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE); rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE | RING_CTRL_RUN_STOP); =20 + /* + * Do not clear the entries of rh->src_xfers because the recovery uses + * them. In other cases they should be NULL anyway. + */ rh->done_ptr =3D 0; rh->ibi_chunk_ptr =3D 0; rh->xfer_space =3D rh->xfer_entries; @@ -362,7 +367,7 @@ static int hci_dma_init(struct i3c_hci *hci) rh->resp =3D dma_alloc_coherent(rings->sysdev, resps_sz, &rh->resp_dma, GFP_KERNEL); rh->src_xfers =3D - kmalloc_objs(*rh->src_xfers, rh->xfer_entries); + kzalloc_objs(*rh->src_xfers, rh->xfer_entries); ret =3D -ENOMEM; if (!rh->xfer || !rh->resp || !rh->src_xfers) goto err_out; @@ -572,13 +577,15 @@ static void hci_dma_xfer_done(struct i3c_hci *hci, st= ruct hci_rh_data *rh) hci_dma_unmap_xfer(hci, xfer, 1); rh->src_xfers[done_ptr] =3D NULL; xfer->ring_entry =3D -1; - xfer->response =3D resp; if (tid !=3D xfer->cmd_tid) { dev_err(&hci->master.dev, "response tid=3D%d when expecting %d\n", tid, xfer->cmd_tid); - /* TODO: do something about it? */ + hci->recovery_needed =3D true; + if (!RESP_STATUS(resp)) + hci_cmd_set_resp_err(&resp, RESP_ERR_HC_TERMINATED); } + xfer->response =3D resp; if (xfer =3D=3D xfer->final_xfer || RESP_STATUS(resp)) complete(xfer->final_xfer->completion); if (RESP_STATUS(resp)) @@ -625,6 +632,60 @@ static void hci_dma_unblock_enqueue(struct i3c_hci *hc= i) } } =20 +static void hci_dma_error_out_rh(struct i3c_hci *hci, struct hci_rh_data *= rh) +{ + /* + * The entries of rh->src_xfers are not cleared by + * i3c_hci_reset_and_restore(), so can be used here. Do 2 passes so + * that the final_xfer of an xfer list is always processed last. + */ + for (int pass =3D 0; pass < 2; pass++) + for (int i =3D 0; i < rh->xfer_entries; i++) { + struct hci_xfer *xfer =3D rh->src_xfers[i]; + + if (!xfer || (!pass && xfer =3D=3D xfer->final_xfer)) + continue; + hci_dma_unmap_xfer(hci, xfer, 1); + rh->src_xfers[i] =3D NULL; + xfer->ring_entry =3D -1; + hci_cmd_set_resp_err(&xfer->response, RESP_ERR_HC_TERMINATED); + if (xfer =3D=3D xfer->final_xfer) + complete(xfer->final_xfer->completion); + } +} + +static void hci_dma_error_out_all(struct i3c_hci *hci) +{ + struct hci_rings_data *rings =3D hci->io_data; + + for (int i =3D 0; i < rings->total; i++) + hci_dma_error_out_rh(hci, &rings->headers[i]); +} + +static void hci_dma_recovery(struct i3c_hci *hci) +{ + int ret; + + dev_err(&hci->master.dev, "Attempting to recover from internal errors\n"); + + for (int i =3D 0; i < 3; i++) { + ret =3D i3c_hci_reset_and_restore(hci); + if (!ret) + break; + dev_err(&hci->master.dev, "Reset and restore failed, error %d\n", ret); + /* Just in case the controller is busy, give it some time */ + msleep(1000); + } + + spin_lock_irq(&hci->lock); + hci_dma_error_out_all(hci); + hci_dma_unblock_enqueue(hci); + hci->recovery_needed =3D false; + spin_unlock_irq(&hci->lock); + + dev_err(&hci->master.dev, "Recovery %s\n", ret ? "failed!" : "done"); +} + static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, struct hci_xfer *xfer_list, int n) { @@ -640,6 +701,17 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, =20 ring_status =3D rh_reg_read(RING_STATUS); if (ring_status & RING_STATUS_RUNNING) { + /* + * The transfer may have already completed, especially + * if recovery has just run. Do nothing in that case. + */ + hci_dma_xfer_done(hci, rh); + if (xfer_list->final_xfer->ring_entry < 0 && + !hci->recovery_needed && !hci->enqueue_blocked && + ring_status =3D=3D (RING_STATUS_ENABLED | RING_STATUS_RUNNING)) { + spin_unlock_irq(&hci->lock); + return false; + } hci->enqueue_blocked =3D true; spin_unlock_irq(&hci->lock); /* stop the ring */ @@ -647,12 +719,8 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, spin_lock_irq(&hci->lock); ring_status =3D rh_reg_read(RING_STATUS); if (ring_status & RING_STATUS_RUNNING) { - /* - * We're deep in it if ever this condition is ever met. - * Hardware might still be writing to memory, etc. - */ - dev_crit(&hci->master.dev, "unable to abort the ring\n"); - WARN_ON(1); + dev_err(&hci->master.dev, "Unable to abort the DMA ring\n"); + hci->recovery_needed =3D true; } } =20 @@ -662,6 +730,13 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, =20 hci_dma_xfer_done(hci, rh); =20 + if (hci->recovery_needed) { + hci->enqueue_blocked =3D true; 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charset="utf-8" When a transfer list is only partially completed due to an error, hci_dma_dequeue_xfer() overwrites the remaining DMA ring entries with NoOp commands and restarts the ring to flush them out. While NoOp commands are expected to complete successfully, they may still fail to complete if the DMA ring is stuck. Explicitly wait for the NoOp commands to finish, and trigger controller recovery if they do not complete or report an error. This ensures that partially completed transfer lists are reliably resolved and that a stuck ring is recovered promptly. Signed-off-by: Adrian Hunter Reviewed-by: Frank Li --- Changes in V5: None Changes in V4: Add Frank's Rev'd-by Changes in V3: None Changes in V2: Rename completing_xfer to final_xfer Add missing reinit_completion() drivers/i3c/master/mipi-i3c-hci/dma.c | 39 ++++++++++++++++++++++----- 1 file changed, 33 insertions(+), 6 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index f39a6ce2aad5..0fd56bbb84ef 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -686,11 +686,33 @@ static void hci_dma_recovery(struct i3c_hci *hci) dev_err(&hci->master.dev, "Recovery %s\n", ret ? "failed!" : "done"); } =20 +static bool hci_dma_wait_for_noop(struct i3c_hci *hci, struct hci_xfer *xf= er_list, int n, + int noop_pos) +{ + struct completion *done =3D xfer_list->final_xfer->completion; + bool timeout =3D !wait_for_completion_timeout(done, HZ); + u32 error =3D timeout; + + for (int i =3D noop_pos; i < n && !error; i++) + error =3D RESP_STATUS(xfer_list[i].response); + + if (!error) + return true; + + if (timeout) + dev_err(&hci->master.dev, "NoOp timeout error\n"); + else + dev_err(&hci->master.dev, "NoOp error %u\n", error); + + return false; +} + static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, struct hci_xfer *xfer_list, int n) { struct hci_rings_data *rings =3D hci->io_data; struct hci_rh_data *rh =3D &rings->headers[xfer_list[0].ring_number]; + int noop_pos =3D -1; unsigned int i; bool did_unqueue =3D false; u32 ring_status; @@ -698,7 +720,7 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, guard(mutex)(&hci->control_mutex); =20 spin_lock_irq(&hci->lock); - +restart: ring_status =3D rh_reg_read(RING_STATUS); if (ring_status & RING_STATUS_RUNNING) { /* @@ -757,11 +779,10 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, *ring_data++ =3D 0; } =20 - /* disassociate this xfer struct */ - rh->src_xfers[idx] =3D NULL; - - /* and unmap it */ - hci_dma_unmap_xfer(hci, xfer, 1); + if (noop_pos < 0) { + reinit_completion(xfer->final_xfer->completion); + noop_pos =3D i; + } =20 did_unqueue =3D true; } @@ -793,6 +814,12 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, =20 wait_for_completion_timeout(&rh->op_done, HZ); =20 + if (did_unqueue && !hci_dma_wait_for_noop(hci, xfer_list, n, noop_pos)) { + spin_lock_irq(&hci->lock); + hci->recovery_needed =3D true; + goto restart; + } + return did_unqueue; } =20 --=20 2.51.0 From nobody Mon Jun 8 07:21:44 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A92B43CEE1 for ; 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a="91852666" X-IronPort-AV: E=Sophos;i="6.24,184,1774335600"; d="scan'208";a="91852666" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2026 02:08:38 -0700 X-CSE-ConnectionGUID: AUweQzF1QfuHqYH75qhHvw== X-CSE-MsgGUID: 3mtNN/afSymihOkQIkE4Mw== X-ExtLoop1: 1 Received: from ijarvine-mobl1.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.137]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2026 02:08:36 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V5 15/17] i3c: mipi-i3c-hci: Base timeouts on actual transfer start time Date: Wed, 3 Jun 2026 12:07:52 +0300 Message-ID: <20260603090754.16252-16-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260603090754.16252-1-adrian.hunter@intel.com> References: <20260603090754.16252-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Transfer timeouts are currently measured from the point where a transfer list is queued to the controller. This can cause transfers to time out before they have actually started, if earlier queued transfers consume the timeout interval. Fix this by recording when a transfer reaches the head of the queue and adjusting the timeout calculation to start from that point. The existing low-overhead completion-based timeout mechanism is preserved, but care is taken to ensure the transfer start time is consistently recorded for both PIO and DMA paths. This prevents premature timeouts while retaining efficient timeout handling. Signed-off-by: Adrian Hunter Reviewed-by: Frank Li --- Changes in V5: Added Frank's Rev'd-by Changes in V4: Rename start_time to start_jiffies Changes in V3: None Changes in V2: Do not flag the next transfer as started when there is an error which halts the controller Instead flag it started at the end of hci_dma_dequeue_xfer() Use hci_start_xfer() in pio.c drivers/i3c/master/mipi-i3c-hci/core.c | 19 ++++++++++++++++++- drivers/i3c/master/mipi-i3c-hci/dma.c | 19 ++++++++++++++++++- drivers/i3c/master/mipi-i3c-hci/hci.h | 11 +++++++++++ drivers/i3c/master/mipi-i3c-hci/pio.c | 1 + 4 files changed, 48 insertions(+), 2 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index 69dcf5dad3a5..c6edbbedfdd7 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -275,13 +275,30 @@ int i3c_hci_process_xfer(struct i3c_hci *hci, struct = hci_xfer *xfer, int n) { struct completion *done =3D xfer[n - 1].completion; unsigned long timeout =3D xfer[n - 1].timeout; + unsigned long remaining_timeout =3D timeout; + long time_taken; + bool started; int ret; =20 + xfer[0].started =3D false; + ret =3D hci->io->queue_xfer(hci, xfer, n); if (ret) return ret; =20 - if (!wait_for_completion_timeout(done, timeout)) { + while (!wait_for_completion_timeout(done, remaining_timeout)) { + scoped_guard(spinlock_irqsave, &hci->lock) { + started =3D xfer[0].started; + time_taken =3D jiffies - xfer[0].start_jiffies; + } + /* Keep waiting if xfer has not started */ + if (!started) + continue; + /* Recalculate timeout based on actual start time */ + if (time_taken < timeout) { + remaining_timeout =3D timeout - time_taken; + continue; + } if (hci->io->dequeue_xfer(hci, xfer, n)) { dev_err(&hci->master.dev, "%s: timeout error\n", __func__); return -ETIMEDOUT; diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index 0fd56bbb84ef..9a01c740760f 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -543,6 +543,9 @@ static int hci_dma_queue_xfer(struct i3c_hci *hci, enqueue_ptr =3D (enqueue_ptr + 1) % rh->xfer_entries; } =20 + if (rh->xfer_space =3D=3D rh->xfer_entries) + hci_start_xfer(xfer_list); + rh->xfer_space -=3D n; =20 op1_val &=3D ~RING_OP1_CR_ENQ_PTR; @@ -558,6 +561,7 @@ static void hci_dma_xfer_done(struct i3c_hci *hci, stru= ct hci_rh_data *rh) u32 op1_val, op2_val, resp, *ring_resp; unsigned int tid, done_ptr =3D rh->done_ptr; unsigned int done_cnt =3D 0; + bool start_next =3D false; struct hci_xfer *xfer; =20 for (;;) { @@ -588,8 +592,14 @@ static void hci_dma_xfer_done(struct i3c_hci *hci, str= uct hci_rh_data *rh) xfer->response =3D resp; if (xfer =3D=3D xfer->final_xfer || RESP_STATUS(resp)) complete(xfer->final_xfer->completion); - if (RESP_STATUS(resp)) + else + hci_start_xfer(xfer); + if (RESP_STATUS(resp)) { hci->enqueue_blocked =3D true; + start_next =3D false; + } else { + start_next =3D true; + } } =20 done_ptr =3D (done_ptr + 1) % rh->xfer_entries; @@ -598,6 +608,10 @@ static void hci_dma_xfer_done(struct i3c_hci *hci, str= uct hci_rh_data *rh) } =20 rh->xfer_space +=3D done_cnt; + if (start_next && rh->xfer_space < rh->xfer_entries) { + xfer =3D rh->src_xfers[done_ptr]; + hci_start_xfer(xfer); + } op1_val =3D rh_reg_read(RING_OPERATION1); op1_val &=3D ~RING_OP1_CR_SW_DEQ_PTR; op1_val |=3D FIELD_PREP(RING_OP1_CR_SW_DEQ_PTR, done_ptr); @@ -810,6 +824,9 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, =20 hci_dma_unblock_enqueue(hci); =20 + if (rh->xfer_space < rh->xfer_entries) + hci_start_xfer(rh->src_xfers[rh->done_ptr]); + spin_unlock_irq(&hci->lock); =20 wait_for_completion_timeout(&rh->op_done, HZ); diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mip= i-i3c-hci/hci.h index 4bf2c66c97b4..30297823ca85 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -11,6 +11,7 @@ #define HCI_H =20 #include +#include =20 /* 32-bit word aware bit and mask macros */ #define W0_MASK(h, l) GENMASK((h) - 0, (l) - 0) @@ -88,11 +89,13 @@ struct hci_xfer { u32 cmd_desc[4]; u32 response; bool rnw; + bool started; void *data; unsigned int data_len; unsigned int cmd_tid; struct completion *completion; unsigned long timeout; + unsigned long start_jiffies; union { struct { /* PIO specific */ @@ -123,6 +126,14 @@ static inline void hci_free_xfer(struct hci_xfer *xfer= , unsigned int n) kfree(xfer); } =20 +static inline void hci_start_xfer(struct hci_xfer *xfer) +{ + if (!xfer->started) { + xfer->started =3D true; + xfer->start_jiffies =3D jiffies; + } +} + /* This abstracts PIO vs DMA operations */ struct hci_io_ops { bool (*irq_handler)(struct i3c_hci *hci); diff --git a/drivers/i3c/master/mipi-i3c-hci/pio.c b/drivers/i3c/master/mip= i-i3c-hci/pio.c index 8f48a81e65ab..6b8cc5f2b4d2 100644 --- a/drivers/i3c/master/mipi-i3c-hci/pio.c +++ b/drivers/i3c/master/mipi-i3c-hci/pio.c @@ -605,6 +605,7 @@ static bool hci_pio_process_cmd(struct i3c_hci *hci, st= ruct hci_pio_data *pio) * Finally send the command. */ hci_pio_write_cmd(hci, pio->curr_xfer); + hci_start_xfer(pio->curr_xfer); /* * And move on. */ --=20 2.51.0 From nobody Mon Jun 8 07:21:44 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 529E843DA39 for ; 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charset="utf-8" dma_alloc_coherent() allocates memory in whole pages, which can waste space when command and response queues are allocated separately. Allocate the DMA command and response queues from a single coherent allocation instead, while preserving the required 4-byte alignment. This reduces memory overhead without changing behavior. Signed-off-by: Adrian Hunter Reviewed-by: Frank Li --- Changes in V5: Added Frank's Rev'd-by Changes in V4: Cache allocation size in rh->xfer_alloc_sz to avoid recomputing in hci_dma_free() Changes in V3: None Changes in V2: Check for failed allocation before assignments to avoid doing arithmetic with NULL pointers drivers/i3c/master/mipi-i3c-hci/dma.c | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index 9a01c740760f..0136f3064ada 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -130,7 +130,7 @@ struct hci_rh_data { dma_addr_t xfer_dma, resp_dma, ibi_status_dma, ibi_data_dma; unsigned int xfer_entries, ibi_status_entries, ibi_chunks_total; unsigned int xfer_struct_sz, resp_struct_sz, ibi_status_sz, ibi_chunk_sz; - unsigned int done_ptr, ibi_chunk_ptr, xfer_space; + unsigned int xfer_alloc_sz, done_ptr, ibi_chunk_ptr, xfer_space; struct hci_xfer **src_xfers; struct completion op_done; }; @@ -187,13 +187,7 @@ static void hci_dma_free(void *data) rh =3D &rings->headers[i]; =20 if (rh->xfer) - dma_free_coherent(rings->sysdev, - rh->xfer_struct_sz * rh->xfer_entries, - rh->xfer, rh->xfer_dma); - if (rh->resp) - dma_free_coherent(rings->sysdev, - rh->resp_struct_sz * rh->xfer_entries, - rh->resp, rh->resp_dma); + dma_free_coherent(rings->sysdev, rh->xfer_alloc_sz, rh->xfer, rh->xfer_= dma); kfree(rh->src_xfers); if (rh->ibi_status) dma_free_coherent(rings->sysdev, @@ -359,18 +353,19 @@ static int hci_dma_init(struct i3c_hci *hci) dev_dbg(&hci->master.dev, "xfer_struct_sz =3D %d, resp_struct_sz =3D %d", rh->xfer_struct_sz, rh->resp_struct_sz); - xfers_sz =3D rh->xfer_struct_sz * rh->xfer_entries; + xfers_sz =3D round_up(rh->xfer_struct_sz * rh->xfer_entries, 4); resps_sz =3D rh->resp_struct_sz * rh->xfer_entries; + rh->xfer_alloc_sz =3D xfers_sz + resps_sz; =20 - rh->xfer =3D dma_alloc_coherent(rings->sysdev, xfers_sz, + rh->xfer =3D dma_alloc_coherent(rings->sysdev, rh->xfer_alloc_sz, &rh->xfer_dma, GFP_KERNEL); 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03 Jun 2026 02:08:40 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V5 17/17] i3c: mipi-i3c-hci: Increase DMA transfer ring size to maximum Date: Wed, 3 Jun 2026 12:07:54 +0300 Message-ID: <20260603090754.16252-18-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260603090754.16252-1-adrian.hunter@intel.com> References: <20260603090754.16252-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The DMA transfer ring is currently limited to 16 entries, despite the MIPI I3C HCI supporting up to 32 devices. When the ring lacks space for a new transfer list, the driver returns -EBUSY, which can be unexpected for clients. Increase the DMA transfer ring size to the maximum supported value of 255 entries. This effectively eliminates ring-space exhaustion in practice and avoids the complexity of adding secondary queuing mechanisms. Even at the maximum size, the memory overhead remains small (approximately 24 bytes per entry by default). Signed-off-by: Adrian Hunter Reviewed-by: Frank Li --- Changes in V5: None Changes in V4: Add Frank's Rev'd-by Changes in V2 and V3: None drivers/i3c/master/mipi-i3c-hci/dma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index 0136f3064ada..5c6ae2055618 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -27,7 +27,7 @@ */ =20 #define XFER_RINGS 1 /* max: 8 */ -#define XFER_RING_ENTRIES 16 /* max: 255 */ +#define XFER_RING_ENTRIES 255 /* max: 255 */ =20 #define IBI_RINGS 1 /* max: 8 */ #define IBI_STATUS_RING_ENTRIES 32 /* max: 255 */ --=20 2.51.0