From nobody Mon Jun 8 06:39:38 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9DAF1405874; Wed, 3 Jun 2026 06:59:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780469986; cv=none; b=dD7RqucCmGoJ3mO6URWxtUnog8saCMI9+3PVeBe6QGbunnNuR1hKCwpkS9r+o6svQ7PHQ4kMAbw1QJDr+5e//G6nZwCenXCDq1qlsibmjWTIUEfZ/AN0Jbnh8RQ4Ean2RQcao8wf6lQA+VYeLHYQrDPgj/pJ/sFCEyWUtpcf278= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780469986; c=relaxed/simple; bh=FCaxCnHUNBLytx1qTehEeuA0qhUzKqnQxc/0700VcrQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=m1rOFnO90A1ksdJnE8QXLe4FMMFv0x7iwdWuVWlsN9VBjD/7+6p7/En98MgKkWhKq5t20kyBJfFcMcb2WlufqlUGh/Bw/AM9f6acxf50peTXfPd+lJ0FmCsnyLGWxq7RLXDl6GHcP6Z1eyUSch9G9UOjjRBNTlnpLdsZ8bhxyuc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realsil.com.cn; spf=pass smtp.mailfrom=realsil.com.cn; dkim=pass (2048-bit key) header.d=realsil.com.cn header.i=@realsil.com.cn header.b=dCgbqgfQ; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realsil.com.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realsil.com.cn Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=realsil.com.cn header.i=@realsil.com.cn header.b="dCgbqgfQ" X-SpamFilter-By: ArmorX SpamTrap 5.80 with qID 6536xJ0213643786, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=realsil.com.cn; s=dkim; t=1780469959; bh=Yx6ZtT/WPpSKU82LHR5gK89KHZT7iZS78k/qRj3b7n4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=dCgbqgfQjB7jGMC7YkmsSFc5+kgze3woxRR8JvRzYk+0P5lkeehtbOEn45cqiBaFH PnUE+4sXIY4Gkbz47dfOrwx6bDcBPv/GMzHpAsIv+v7ZVqZmlcjyVZ/6VuJnZa0YMV LpBg5K2uSnfvUIYcfvZNU/iLHKnP8qAjL9z/keQB5krC1EmId+0Gi0ItkNa+Yu61zU E+SalevNg6XIN8KZOvLEnY2DAgoKaxH3Q5Y3Og84Z3PnuQYvJf0YdCYAKB8g4JFIh9 +WUHLbbtaeUeIDuVp4h1PXlxkzRrpZzaYVcNToBs8+4DR8zNwFvRf3x7GrmO025ODM mxdzDGCeG0jig== Received: from RS-EX-MBS2.realsil.com.cn ([172.29.17.102]) by rtits2.realtek.com.tw (8.15.2/3.28/5.94) with ESMTPS id 6536xJ0213643786 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 3 Jun 2026 14:59:19 +0800 Received: from RS-EX-MBS2.realsil.com.cn (172.29.17.102) by RS-EX-MBS2.realsil.com.cn (172.29.17.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Wed, 3 Jun 2026 14:59:19 +0800 Received: from 172.29.37.154 (172.29.37.152) by RS-EX-MBS2.realsil.com.cn (172.29.17.102) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Wed, 3 Jun 2026 14:59:19 +0800 From: javen To: , , , , , , , CC: , , Javen Xu Subject: [PATCH net-next v1 1/5] net: phy: realtek: add support for dummy phy Date: Wed, 3 Jun 2026 14:59:12 +0800 Message-ID: <20260603065916.334-2-javen_xu@realsil.com.cn> X-Mailer: git-send-email 2.50.1.windows.1 In-Reply-To: <20260603065916.334-1-javen_xu@realsil.com.cn> References: <20260603065916.334-1-javen_xu@realsil.com.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Javen Xu Add support for rtl8116af dummy phy driver, match phy id and read link speed from MII_BMCR. Signed-off-by: Javen Xu --- drivers/net/phy/realtek/realtek_main.c | 54 ++++++++++++++++++++++++++ include/net/phy/realtek_phy.h | 1 + 2 files changed, 55 insertions(+) diff --git a/drivers/net/phy/realtek/realtek_main.c b/drivers/net/phy/realt= ek/realtek_main.c index 27268811f564..9b92828c49d9 100644 --- a/drivers/net/phy/realtek/realtek_main.c +++ b/drivers/net/phy/realtek/realtek_main.c @@ -2659,6 +2659,47 @@ static int rtlgen_sfp_get_features(struct phy_device= *phydev) return 0; } =20 +static int rtl8116af_sfp_get_features(struct phy_device *phydev) +{ + linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, + phydev->supported); + + phydev->speed =3D SPEED_1000; + phydev->duplex =3D DUPLEX_FULL; + + phydev->port =3D PORT_FIBRE; + + return 0; +} + +static int rtl8116af_sfp_read_status(struct phy_device *phydev) +{ + int val, err; + + err =3D genphy_update_link(phydev); + if (err) + return err; + + if (!phydev->link) + return 0; + + val =3D phy_read(phydev, MII_BMCR); + if (val < 0) + return val; + + if (val & BMCR_SPEED1000) + phydev->speed =3D SPEED_1000; + else if (val & BMCR_SPEED100) + phydev->speed =3D SPEED_100; + + if (val & BMCR_FULLDPLX) + phydev->duplex =3D DUPLEX_FULL; + else + phydev->duplex =3D DUPLEX_HALF; + + return 0; +} + static int rtlgen_sfp_read_status(struct phy_device *phydev) { int val, err; @@ -2947,6 +2988,19 @@ static struct phy_driver realtek_drvs[] =3D { .write_page =3D rtl821x_write_page, .read_mmd =3D rtl822x_read_mmd, .write_mmd =3D rtl822x_write_mmd, + }, { + PHY_ID_MATCH_EXACT(PHY_ID_RTL8116AF_DUMMY), + .name =3D "RTL8116af PHY Mode", + .flags =3D PHY_IS_INTERNAL, + .get_features =3D rtl8116af_sfp_get_features, + .config_aneg =3D rtlgen_sfp_config_aneg, + .read_status =3D rtl8116af_sfp_read_status, + .suspend =3D genphy_suspend, + .resume =3D rtlgen_resume, + .read_page =3D rtl821x_read_page, + .write_page =3D rtl821x_write_page, + .read_mmd =3D rtl822x_read_mmd, + .write_mmd =3D rtl822x_write_mmd, }, { PHY_ID_MATCH_EXACT(0x001ccad0), .name =3D "RTL8224 2.5Gbps PHY", diff --git a/include/net/phy/realtek_phy.h b/include/net/phy/realtek_phy.h index d683bc1b0659..cbf91af0ead6 100644 --- a/include/net/phy/realtek_phy.h +++ b/include/net/phy/realtek_phy.h @@ -3,5 +3,6 @@ #define _REALTEK_PHY_H =20 #define PHY_ID_RTL_DUMMY_SFP 0x001ccbff +#define PHY_ID_RTL8116AF_DUMMY 0x001ccbfe =20 #endif /* _REALTEK_PHY_H */ --=20 2.43.0 From nobody Mon Jun 8 06:39:38 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 89FE3405859; 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charset="utf-8" From: Javen Xu Move some functions forward to avoid adding a forward declaration. Signed-off-by: Javen Xu --- drivers/net/ethernet/realtek/r8169_main.c | 84 +++++++++++------------ 1 file changed, 42 insertions(+), 42 deletions(-) diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethern= et/realtek/r8169_main.c index ec4fc21fa21f..1e2e4074d343 100644 --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c @@ -1113,6 +1113,23 @@ DECLARE_RTL_COND(rtl_ocp_gphy_cond) return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; } =20 +/* Work around a hw issue with RTL8168g PHY, the quirk disables + * PHY MCU interrupts before PHY power-down. + */ +static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int val= ue) +{ + switch (tp->mac_version) { + case RTL_GIGA_MAC_VER_40: + if (value & BMCR_RESET || !(value & BMCR_PDOWN)) + rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); + else + rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); + break; + default: + break; + } +}; + static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 d= ata) { if (rtl_ocp_reg_failure(reg)) @@ -1123,19 +1140,20 @@ static void r8168_phy_ocp_write(struct rtl8169_priv= ate *tp, u32 reg, u32 data) rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); } =20 -static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) +static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int val= ue) { - if (rtl_ocp_reg_failure(reg)) - return 0; + if (reg =3D=3D 0x1f) { + tp->ocp_base =3D value ? value << 4 : OCP_STD_PHY_BASE; + return; + } =20 - /* Return dummy MII_PHYSID2 in SFP mode to match SFP PHY driver */ - if (tp->sfp_mode && reg =3D=3D (OCP_STD_PHY_BASE + 2 * MII_PHYSID2)) - return PHY_ID_RTL_DUMMY_SFP & 0xffff; + if (tp->ocp_base !=3D OCP_STD_PHY_BASE) + reg -=3D 0x10; =20 - RTL_W32(tp, GPHY_OCP, reg << 15); + if (tp->ocp_base =3D=3D OCP_STD_PHY_BASE && reg =3D=3D MII_BMCR) + rtl8168g_phy_suspend_quirk(tp, value); =20 - return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? - (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; + r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); } =20 static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32= data) @@ -1177,6 +1195,21 @@ static u16 r8168_mac_ocp_read(struct rtl8169_private= *tp, u32 reg) return val; } =20 +static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) +{ + if (rtl_ocp_reg_failure(reg)) + return 0; + + /* Return dummy MII_PHYSID2 in SFP mode to match SFP PHY driver */ + if (tp->sfp_mode && reg =3D=3D (OCP_STD_PHY_BASE + 2 * MII_PHYSID2)) + return PHY_ID_RTL_DUMMY_SFP & 0xffff; + + RTL_W32(tp, GPHY_OCP, reg << 15); + + return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? + (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; +} + static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 = mask, u16 set) { @@ -1229,39 +1262,6 @@ static void rtl_sfp_reset(struct rtl8169_private *tp) r8127_sfp_sds_phy_reset(tp); } =20 -/* Work around a hw issue with RTL8168g PHY, the quirk disables - * PHY MCU interrupts before PHY power-down. - */ -static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int val= ue) -{ - switch (tp->mac_version) { - case RTL_GIGA_MAC_VER_40: - if (value & BMCR_RESET || !(value & BMCR_PDOWN)) - rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); 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Wed, 3 Jun 2026 14:59:19 +0800 Received: from RS-EX-MBS2.realsil.com.cn (172.29.17.102) by RS-EX-MBS2.realsil.com.cn (172.29.17.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Wed, 3 Jun 2026 14:59:19 +0800 Received: from 172.29.37.154 (172.29.37.152) by RS-EX-MBS2.realsil.com.cn (172.29.17.102) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Wed, 3 Jun 2026 14:59:19 +0800 From: javen To: , , , , , , , CC: , , Javen Xu Subject: [PATCH net-next v1 3/5] r8169: fix RTL8116af link readiness bug Date: Wed, 3 Jun 2026 14:59:14 +0800 Message-ID: <20260603065916.334-4-javen_xu@realsil.com.cn> X-Mailer: git-send-email 2.50.1.windows.1 In-Reply-To: <20260603065916.334-1-javen_xu@realsil.com.cn> References: <20260603065916.334-1-javen_xu@realsil.com.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Javen Xu For saving power, RTL8116af can not read link status from standard phy register. Instead, we should read link status through mac register. Signed-off-by: Javen Xu --- drivers/net/ethernet/realtek/r8169_main.c | 73 +++++++++++++++++++---- 1 file changed, 61 insertions(+), 12 deletions(-) diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethern= et/realtek/r8169_main.c index 1e2e4074d343..56653608633a 100644 --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c @@ -454,6 +454,12 @@ enum rtl8125_registers { =20 #define RX_FETCH_DFLT_8125 (8 << 27) =20 +#define OCP_SDS_ADDR_REG 0xEB10 +#define OCP_SDS_CMD_REG 0xEB0E +#define OCP_SDS_DATA_REG 0xEB14 +#define SDS_CMD_READ 0x0001 +#define RTL_SDS_C22_BASE 0x40 + enum rtl_register_content { /* InterruptStatusBits */ SYSErr =3D 0x8000, @@ -728,6 +734,12 @@ enum rtl_dash_type { RTL_DASH_25_BP, }; =20 +enum rtl_sfp_mode { + RTL_SFP_NONE, + RTL_SFP_8116_AF, + RTL_SFP_8127_ATF, +}; + struct rtl8169_private { void __iomem *mmio_addr; /* memory map physical address */ struct pci_dev *pci_dev; @@ -736,6 +748,7 @@ struct rtl8169_private { struct napi_struct napi; enum mac_version mac_version; enum rtl_dash_type dash_type; + enum rtl_sfp_mode sfp_mode; u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ u32 dirty_tx; @@ -762,7 +775,6 @@ struct rtl8169_private { unsigned supports_gmii:1; unsigned aspm_manageable:1; unsigned dash_enabled:1; - bool sfp_mode:1; dma_addr_t counters_phys_addr; struct rtl8169_counters *counters; struct rtl8169_tc_offsets tc_offset; @@ -1195,13 +1207,42 @@ static u16 r8168_mac_ocp_read(struct rtl8169_privat= e *tp, u32 reg) return val; } =20 +static u16 rtl8116af_sds_read(struct rtl8169_private *tp, u16 sds_reg) +{ + r8168_mac_ocp_write(tp, OCP_SDS_ADDR_REG, sds_reg); + r8168_mac_ocp_write(tp, OCP_SDS_CMD_REG, SDS_CMD_READ); + return r8168_mac_ocp_read(tp, OCP_SDS_DATA_REG); +} + +static bool rtl_is_8116af(struct rtl8169_private *tp) +{ + return tp->mac_version =3D=3D RTL_GIGA_MAC_VER_52 && + (r8168_mac_ocp_read(tp, 0xdc00) & 0x0078) =3D=3D 0x0030 && + (r8168_mac_ocp_read(tp, 0xd006) & 0x00ff) =3D=3D 0x0000; +} + static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) { if (rtl_ocp_reg_failure(reg)) return 0; =20 + if (tp->sfp_mode =3D=3D RTL_SFP_8116_AF) { + switch (reg) { + case OCP_STD_PHY_BASE + 2 * MII_PHYSID1: + return upper_16_bits(PHY_ID_RTL8116AF_DUMMY); + case OCP_STD_PHY_BASE + 2 * MII_PHYSID2: + return lower_16_bits(PHY_ID_RTL8116AF_DUMMY); + case OCP_STD_PHY_BASE + 2 * MII_BMSR: + return rtl8116af_sds_read(tp, RTL_SDS_C22_BASE + MII_BMSR); + case OCP_STD_PHY_BASE + 2 * MII_BMCR: + return rtl8116af_sds_read(tp, RTL_SDS_C22_BASE + MII_BMCR); + default: + break; + } + } + /* Return dummy MII_PHYSID2 in SFP mode to match SFP PHY driver */ - if (tp->sfp_mode && reg =3D=3D (OCP_STD_PHY_BASE + 2 * MII_PHYSID2)) + if (tp->sfp_mode =3D=3D RTL_SFP_8127_ATF && reg =3D=3D (OCP_STD_PHY_BASE = + 2 * MII_PHYSID2)) return PHY_ID_RTL_DUMMY_SFP & 0xffff; =20 RTL_W32(tp, GPHY_OCP, reg << 15); @@ -1578,6 +1619,20 @@ static bool rtl_dash_is_enabled(struct rtl8169_priva= te *tp) } } =20 +static enum rtl_sfp_mode rtl_get_sfp_mode(struct rtl8169_private *tp) +{ + if (rtl_is_8125(tp)) { + u16 data =3D r8168_mac_ocp_read(tp, 0xd006); + + if ((data & 0xff) =3D=3D 0x07) + return RTL_SFP_8127_ATF; + } else if (rtl_is_8116af(tp)) { + return RTL_SFP_8116_AF; + } + + return RTL_SFP_NONE; +} + static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp) { switch (tp->mac_version) { @@ -2394,7 +2449,7 @@ static int rtl8169_set_link_ksettings(struct net_devi= ce *ndev, int duplex =3D cmd->base.duplex; int speed =3D cmd->base.speed; =20 - if (!tp->sfp_mode) + if (tp->sfp_mode !=3D RTL_SFP_8127_ATF) return phy_ethtool_ksettings_set(phydev, cmd); =20 if (cmd->base.autoneg !=3D AUTONEG_DISABLE) @@ -2552,7 +2607,7 @@ static void rtl8169_init_phy(struct rtl8169_private *= tp) tp->pci_dev->subsystem_device =3D=3D 0xe000) phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); =20 - if (tp->sfp_mode) + if (tp->sfp_mode =3D=3D RTL_SFP_8127_ATF) rtl_sfp_init(tp); =20 /* We may have called phy_speed_down before */ @@ -5010,7 +5065,7 @@ static void rtl8169_down(struct rtl8169_private *tp) phy_stop(tp->phydev); =20 /* Reset SerDes PHY to bring down fiber link */ - if (tp->sfp_mode) + if (tp->sfp_mode =3D=3D RTL_SFP_8127_ATF) rtl_sfp_reset(tp); =20 rtl8169_update_counters(tp); @@ -5679,13 +5734,7 @@ static int rtl_init_one(struct pci_dev *pdev, const = struct pci_device_id *ent) } tp->aspm_manageable =3D !rc; =20 - if (rtl_is_8125(tp)) { - u16 data =3D r8168_mac_ocp_read(tp, 0xd006); - - if ((data & 0xff) =3D=3D 0x07) - tp->sfp_mode =3D true; - } - + tp->sfp_mode =3D rtl_get_sfp_mode(tp); tp->dash_type =3D rtl_get_dash_type(tp); tp->dash_enabled =3D rtl_dash_is_enabled(tp); =20 --=20 2.43.0 From nobody Mon Jun 8 06:39:38 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 39D1640B6D1; Wed, 3 Jun 2026 06:59:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780469985; cv=none; b=kwO0FWmilwWGwr9QuDpuFzoWcSOiq3V4RYWzIu2IU3xN9v5rx9JbnGAqSSeK+83hzNObudZhKI3jccocy9AyfV5KMZ4cC/niHKTYjObHyFUgyUy2D7hyB+MOiSNmQaQ7NBKJWt2w6wwauS572O5foSNFGgHjQiHDcXOmUPB8b3A= ARC-Message-Signature: i=1; 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Wed, 3 Jun 2026 14:59:19 +0800 Received: from 172.29.37.154 (172.29.37.152) by RS-EX-MBS2.realsil.com.cn (172.29.17.102) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Wed, 3 Jun 2026 14:59:19 +0800 From: javen To: , , , , , , , CC: , , Javen Xu Subject: [PATCH net-next v1 4/5] r8169: add ltr support for RTL8116af Date: Wed, 3 Jun 2026 14:59:15 +0800 Message-ID: <20260603065916.334-5-javen_xu@realsil.com.cn> X-Mailer: git-send-email 2.50.1.windows.1 In-Reply-To: <20260603065916.334-1-javen_xu@realsil.com.cn> References: <20260603065916.334-1-javen_xu@realsil.com.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Javen Xu This patch adds ltr support for RTL8116af, enables RTL8116af enter l1.2 state. This makes sense for the system to enter c10 state. Signed-off-by: Javen Xu --- drivers/net/ethernet/realtek/r8169_main.c | 31 +++++++++++++++++++---- 1 file changed, 26 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethern= et/realtek/r8169_main.c index 56653608633a..5db15137f216 100644 --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c @@ -334,11 +334,13 @@ enum rtl_registers { ALDPS_LTR =3D 0xe0a2, LTR_OBFF_LOCK =3D 0xe032, LTR_SNOOP =3D 0xe034, + SEND_LTR_MSG =3D 0xe038, =20 #define ALDPS_LTR_EN BIT(0) #define LTR_OBFF_LOCK_EN BIT(0) #define LINK_SPEED_CHANGE_EN BIT(14) #define LTR_SNOOP_EN GENMASK(15, 14) +#define LTR_MSG_EN BIT(0) }; =20 enum rtl8168_8101_registers { @@ -3153,8 +3155,22 @@ static void rtl_enable_ltr(struct rtl8169_private *t= p) r8168_mac_ocp_write(tp, 0xcdf2, 0x9003); r8168_mac_ocp_modify(tp, LTR_OBFF_LOCK, 0x0000, LINK_SPEED_CHANGE_EN); break; - case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: case RTL_GIGA_MAC_VER_52: + r8168_mac_ocp_write(tp, 0xcdd0, 0x9003); + r8168_mac_ocp_modify(tp, LTR_SNOOP, 0x0000, LTR_SNOOP_EN); + r8168_mac_ocp_write(tp, 0xe02c, 0x1880); + r8168_mac_ocp_write(tp, 0xe02e, 0x4880); + r8168_mac_ocp_modify(tp, ALDPS_LTR, 0x0000, ALDPS_LTR_EN); + r8168_mac_ocp_write(tp, 0xcdd8, 0x9003); + r8168_mac_ocp_write(tp, 0xcdda, 0x9003); + r8168_mac_ocp_write(tp, 0xcddc, 0x9003); + r8168_mac_ocp_write(tp, 0xcdd2, 0x883c); + r8168_mac_ocp_write(tp, 0xcdd4, 0x8c12); + r8168_mac_ocp_write(tp, 0xcdd6, 0x9003); + r8168_mac_ocp_write(tp, 0xe0a6, 0x9003); + r8168_mac_ocp_write(tp, 0xe0a8, 0x9003); + break; + case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: r8168_mac_ocp_modify(tp, ALDPS_LTR, 0x0000, ALDPS_LTR_EN); RTL_W8(tp, COMBO_LTR_EXTEND, RTL_R8(tp, COMBO_LTR_EXTEND) | COMBO_LTR_EX= TEND_EN); fallthrough; @@ -3174,6 +3190,7 @@ static void rtl_enable_ltr(struct rtl8169_private *tp) } /* chip can trigger LTR */ r8168_mac_ocp_modify(tp, LTR_OBFF_LOCK, 0x0003, LTR_OBFF_LOCK_EN); + r8168_mac_ocp_modify(tp, SEND_LTR_MSG, 0x0000, LTR_MSG_EN); } =20 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool ena= ble) @@ -3207,6 +3224,7 @@ static void rtl_hw_aspm_clkreq_enable(struct rtl8169_= private *tp, bool enable) rtl_enable_ltr(tp); switch (tp->mac_version) { case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: + case RTL_GIGA_MAC_VER_52: case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: /* reset ephy tx/rx disable timer */ r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); @@ -3219,6 +3237,7 @@ static void rtl_hw_aspm_clkreq_enable(struct rtl8169_= private *tp, bool enable) } else { switch (tp->mac_version) { case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: + case RTL_GIGA_MAC_VER_52: case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); break; @@ -3732,7 +3751,9 @@ static void rtl_hw_start_8117(struct rtl8169_private = *tp) =20 rtl_eri_set_bits(tp, 0xd4, 0x0010); =20 - rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); + rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4000); + + r8168_mac_ocp_write(tp, 0xe098, 0xc302); =20 rtl_disable_rxdvgate(tp); =20 @@ -3757,9 +3778,9 @@ static void rtl_hw_start_8117(struct rtl8169_private = *tp) } =20 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0000); - r8168_mac_ocp_write(tp, 0xea80, 0x0003); - r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); - r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); + r8168_mac_ocp_write(tp, 0xea80, 0x0000); + r8168_mac_ocp_modify(tp, 0xe052, 0x0009, 0x0000); + r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x045f); =20 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); r8168_mac_ocp_write(tp, 0xe63e, 0x0000); --=20 2.43.0 From nobody Mon Jun 8 06:39:38 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A7B0B409620; Wed, 3 Jun 2026 06:59:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780469985; cv=none; b=M7vm33g1vzs++GGEjSqQAP/oRjf75nl4YD0MfeKc4UZ5iImbeLhElisJhYqbnQrj4IbweNBlQMk44dD3vhbCj6GwQL5JTw4N9uoU9x6gNiHhqbxIcH/yZvNMexDH3AvD3WGClfIov7h507MNO+53F0kDF9pvLPFwrC/joT9O+ls= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780469985; c=relaxed/simple; bh=5oF24+QgNRDqV1rY1wjnWqyUj6Bm0F/UhtC+TFpT0lg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=fTEpMs0mNuB9f//i819V6K1tnP5uzkEOFVf8UcWh2B3O+I+AIENHZW3UQWJSjx9+NG/4EG+1/FK3Zluzt2JvkCj9FxeCArY752ungScHBcccnAuV+OmliuhTPiy7NBu7pJuuGVdUSXuVoQreU6fezYDSKBcGRuU6IUvM8HTvMTQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realsil.com.cn; spf=pass smtp.mailfrom=realsil.com.cn; dkim=pass (2048-bit key) header.d=realsil.com.cn header.i=@realsil.com.cn header.b=Dw2Q0Myt; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realsil.com.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realsil.com.cn Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=realsil.com.cn header.i=@realsil.com.cn header.b="Dw2Q0Myt" X-SpamFilter-By: ArmorX SpamTrap 5.80 with qID 6536xK0313643786, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=realsil.com.cn; s=dkim; t=1780469960; bh=noRw64KBgx4W8m91UcHG96FC1h2z9tnNyn/WjAASIq4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=Dw2Q0MytaPNN/IpMcwAlrC13W70osS/zvbs/qIx/C7fSYE5WTJyMHHcq4bEUSJXOU t19aB0Ovjcql97Sz8iYi+xZ7kSYpm1PP8PNMcDm7p7oAuSIeGYVH/Q6YeIjLp4U4/3 6BRyYpdi1/usNx6qzJtlOKs5itZKU0zP4pdYisduRjdke3YxHwygo2WMfUOD4KLKxP 9gPzWzCRYgzDNHpX89rsXv1oj6rqZxfoEntxTHkzdPi38Z8LA8FsFOt6nLINYOTzSV Csx9avflhh+1R9yY64nLpL+XnSXaS8jCJxF+iVR5u37xYzYtrJ3br2e5YvolZMBDB4 nNFKt3sV1YXtQ== Received: from RS-EX-MBS2.realsil.com.cn ([172.29.17.102]) by rtits2.realtek.com.tw (8.15.2/3.28/5.94) with ESMTPS id 6536xK0313643786 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 3 Jun 2026 14:59:20 +0800 Received: from RS-EX-MBS2.realsil.com.cn (172.29.17.102) by RS-EX-MBS2.realsil.com.cn (172.29.17.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Wed, 3 Jun 2026 14:59:20 +0800 Received: from 172.29.37.154 (172.29.37.152) by RS-EX-MBS2.realsil.com.cn (172.29.17.102) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Wed, 3 Jun 2026 14:59:20 +0800 From: javen To: , , , , , , , CC: , , Javen Xu Subject: [PATCH net-next v1 5/5] r8169: fix RTL8116af can not enter s0idle and c10 Date: Wed, 3 Jun 2026 14:59:16 +0800 Message-ID: <20260603065916.334-6-javen_xu@realsil.com.cn> X-Mailer: git-send-email 2.50.1.windows.1 In-Reply-To: <20260603065916.334-1-javen_xu@realsil.com.cn> References: <20260603065916.334-1-javen_xu@realsil.com.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Javen Xu RTL8116AF is a multi-function device. Functions 2 to 7 are hidden from the PCI core and return an all-ones response when their vendor ID is read, so they are not enumerated as normal PCI functions. However, these hidden functions can still affect platform power management. If they are left in D0 or keep ASPM disabled, the platform may fail to enter the low-power s0ix state and the CPU package may fail to enter Package C10. Put functions 2 to 7 into D3hot and enable ASPM on their PCIe link control register. Since these functions are hidden, access their configuration space through pci_bus_read_config_dword() / pci_bus_write_config_dword() using the same slot and the target function numbers. Ignore functions that return a PCI error response when reading their configuration space. Signed-off-by: Javen Xu --- drivers/net/ethernet/realtek/r8169_main.c | 31 +++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethern= et/realtek/r8169_main.c index 5db15137f216..cf73915c48bc 100644 --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c @@ -341,6 +341,9 @@ enum rtl_registers { #define LINK_SPEED_CHANGE_EN BIT(14) #define LTR_SNOOP_EN GENMASK(15, 14) #define LTR_MSG_EN BIT(0) +#define RTL8116AF_FUNC_PM_CSR 0x80 +#define RTL8116AF_FUNC_EXP_LNKCTL 0x44 +#define RTL_PM_D3HOT GENMASK(1, 0) }; =20 enum rtl8168_8101_registers { @@ -3731,6 +3734,33 @@ static void rtl_hw_start_8168ep_3(struct rtl8169_pri= vate *tp) r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); } =20 +static void rtl_disable_hidden_function(struct pci_dev *pdev) +{ + unsigned int slot =3D PCI_SLOT(pdev->devfn); + struct pci_bus *bus =3D pdev->bus; + unsigned int devfn; + int func; + int ret; + u32 val; + + for (func =3D 2; func < 8; func++) { + devfn =3D PCI_DEVFN(slot, func); + + ret =3D pci_bus_read_config_dword(bus, devfn, RTL8116AF_FUNC_PM_CSR, &va= l); + if (!ret && !PCI_POSSIBLE_ERROR(val)) { + val &=3D ~(PCI_PM_CTRL_STATE_MASK | PCI_PM_CTRL_PME_ENABLE); + val |=3D (RTL_PM_D3HOT | PCI_PM_CTRL_PME_ENABLE); + pci_bus_write_config_dword(bus, devfn, RTL8116AF_FUNC_PM_CSR, val); + } + + ret =3D pci_bus_read_config_dword(bus, devfn, RTL8116AF_FUNC_EXP_LNKCTL,= &val); + if (!ret && !PCI_POSSIBLE_ERROR(val)) { + val |=3D PCI_EXP_LNKCTL_ASPMC; + pci_bus_write_config_dword(bus, devfn, RTL8116AF_FUNC_EXP_LNKCTL, val); + } + } +} + static void rtl_hw_start_8117(struct rtl8169_private *tp) { static const struct ephy_info e_info_8117[] =3D { @@ -3787,6 +3817,7 @@ static void rtl_hw_start_8117(struct rtl8169_private = *tp) r8168_mac_ocp_write(tp, 0xc094, 0x0000); r8168_mac_ocp_write(tp, 0xc09e, 0x0000); =20 + rtl_disable_hidden_function(tp->pci_dev); /* firmware is for MAC only */ r8169_apply_firmware(tp); } --=20 2.43.0