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Tue, 02 Jun 2026 23:57:36 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Wolfram Sang , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , Conor Dooley Subject: [PATCH v17 01/17] dt-bindings: mmc: renesas,sdhi: Document RZ/G3L (r9a08g046) SoC Date: Wed, 3 Jun 2026 07:57:01 +0100 Message-ID: <20260603065731.93243-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260603065731.93243-1-biju.das.jz@bp.renesas.com> References: <20260603065731.93243-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Document the RZ/G3L (r9a08g046) SDHI controller. The RZ/G3L SDHI controller is similar to RZ/G2L but has five clocks (core, clkh, cd, aclk, aclkm) and three resets (rst, axim, axis), so update the clocks/clock-names maximum to 5 and resets/reset-names maximum to 3. It has an internal divider for all modes except HS400, and a 2048-bit divider compared to 512 on others. Acked-by: Conor Dooley Signed-off-by: Biju Das --- v1->v2: * Collected tag. --- .../devicetree/bindings/mmc/renesas,sdhi.yaml | 101 +++++++++++++----- 1 file changed, 75 insertions(+), 26 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Docu= mentation/devicetree/bindings/mmc/renesas,sdhi.yaml index 4d66966ce290..16cb395403f6 100644 --- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml +++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml @@ -18,6 +18,7 @@ properties: - renesas,sdhi-r7s9210 # SH-Mobile AG5 - renesas,sdhi-r8a73a4 # R-Mobile APE6 - renesas,sdhi-r8a7740 # R-Mobile A1 + - renesas,sdhi-r9a08g046 # RZ/G3L - renesas,sdhi-r9a09g057 # RZ/V2H(P) - renesas,sdhi-sh73a0 # R-Mobile APE6 - items: @@ -86,11 +87,11 @@ properties: =20 clocks: minItems: 1 - maxItems: 4 + maxItems: 5 =20 clock-names: minItems: 1 - maxItems: 4 + maxItems: 5 =20 dmas: minItems: 4 @@ -116,7 +117,12 @@ properties: maxItems: 1 =20 resets: - maxItems: 1 + minItems: 1 + maxItems: 3 + + reset-names: + minItems: 1 + maxItems: 3 =20 pinctrl-0: minItems: 1 @@ -155,60 +161,101 @@ allOf: properties: compatible: contains: - enum: - - renesas,sdhi-r9a09g057 - - renesas,rzg2l-sdhi + const: renesas,sdhi-r9a08g046 then: properties: clocks: items: - description: IMCLK, SDHI channel main clock1. - description: CLK_HS, SDHI channel High speed clock which o= perates - 4 times that of SDHI channel main clock1. + 2 times that of SDHI channel main clock1. - description: IMCLK2, SDHI channel main clock2. When this c= lock is turned off, external SD card detection cannot= be detected. - - description: ACLK, SDHI channel bus clock. + - description: ACLK/IACLKS, SDHI channel bus clock. + - description: IACLKM, SDHI channel bus clock m. clock-names: items: - const: core - const: clkh - const: cd - const: aclk + - const: aclkm + resets: + items: + - description: rst, Core reset. + - description: axim, SDHI axi bus reset m. + - description: axis, SDHI axi bus reset s. + reset-names: + items: + - const: rst + - const: axim + - const: axis required: - clock-names - resets + - reset-names else: if: properties: compatible: contains: enum: - - renesas,rcar-gen2-sdhi - - renesas,rcar-gen3-sdhi - - renesas,rcar-gen4-sdhi + - renesas,sdhi-r9a09g057 + - renesas,rzg2l-sdhi then: properties: clocks: - minItems: 1 - maxItems: 3 - clock-names: - minItems: 1 - uniqueItems: true items: - - const: core - - enum: [ clkh, cd ] - - const: cd - else: - properties: - clocks: - minItems: 1 - maxItems: 2 + - description: IMCLK, SDHI channel main clock1. + - description: CLK_HS, SDHI channel High speed clock which= operates + 4 times that of SDHI channel main clock1. + - description: IMCLK2, SDHI channel main clock2. When this= clock is + turned off, external SD card detection cann= ot be + detected. + - description: ACLK, SDHI channel bus clock. clock-names: - minItems: 1 items: - const: core + - const: clkh - const: cd + - const: aclk + resets: + maxItems: 1 + required: + - clock-names + - resets + else: + if: + properties: + compatible: + contains: + enum: + - renesas,rcar-gen2-sdhi + - renesas,rcar-gen3-sdhi + - renesas,rcar-gen4-sdhi + then: + properties: + clocks: + minItems: 1 + maxItems: 3 + clock-names: + minItems: 1 + uniqueItems: true + items: + - const: core + - enum: [ clkh, cd ] + - const: cd + else: + properties: + clocks: + minItems: 1 + maxItems: 2 + clock-names: + minItems: 1 + items: + - const: core + - const: cd =20 - if: properties: @@ -247,7 +294,9 @@ allOf: properties: compatible: contains: - const: renesas,sdhi-r9a09g057 + enum: + - renesas,sdhi-r9a08g046 + - renesas,sdhi-r9a09g057 then: properties: vqmmc-regulator: --=20 2.43.0 From nobody Mon Jun 8 06:38:26 2026 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 582563F4DDF for ; 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charset="utf-8" From: Biju Das Add clock and reset entries for SDHI. Signed-off-by: Biju Das --- v1->v2: * No change. --- drivers/clk/renesas/r9a08g046-cpg.c | 92 +++++++++++++++++++++++++++++ 1 file changed, 92 insertions(+) diff --git a/drivers/clk/renesas/r9a08g046-cpg.c b/drivers/clk/renesas/r9a0= 8g046-cpg.c index a57638734ce7..272922b76e1e 100644 --- a/drivers/clk/renesas/r9a08g046-cpg.c +++ b/drivers/clk/renesas/r9a08g046-cpg.c @@ -17,10 +17,13 @@ /* RZ/G3L Specific registers. */ #define G3L_CPG_PL2_DDIV (0x204) #define G3L_CPG_PL3_DDIV (0x208) +#define G3L_CPG_SDHI_DDIV (0x218) #define G3L_CPG_CA55CORE_DDIV (0x234) #define G3L_CPG_RSCI_DDIV (0x238) #define G3L_CPG_RSPI_DDIV (0x23c) +#define G3L_CPG_SDHI_DSEL (0x244) #define G3L_CLKDIVSTATUS (0x280) +#define G3L_CLKSELSTATUS (0x284) #define G3L_CPG_ETH_SSEL (0x410) #define G3L_CPG_RSCI_SSEL (0x414) #define G3L_CPG_RSPI_SSEL (0x418) @@ -30,6 +33,9 @@ #define G3L_DIVPL2A DDIV_PACK(G3L_CPG_PL2_DDIV, 0, 2) #define G3L_DIVPL2B DDIV_PACK(G3L_CPG_PL2_DDIV, 4, 2) #define G3L_DIVPL3A DDIV_PACK(G3L_CPG_PL3_DDIV, 0, 2) +#define G3L_DIV_SDHI0 DDIV_PACK(G3L_CPG_SDHI_DDIV, 0, 2) +#define G3L_DIV_SDHI1 DDIV_PACK(G3L_CPG_SDHI_DDIV, 4, 2) +#define G3L_DIV_SDHI2 DDIV_PACK(G3L_CPG_SDHI_DDIV, 8, 2) #define G3L_DIV_CA55_CORE0 DDIV_PACK(G3L_CPG_CA55CORE_DDIV, 0, 3) #define G3L_DIV_CA55_CORE1 DDIV_PACK(G3L_CPG_CA55CORE_DDIV, 4, 3) #define G3L_DIV_CA55_CORE2 DDIV_PACK(G3L_CPG_CA55CORE_DDIV, 8, 3) @@ -61,8 +67,18 @@ #define G3L_DIV_RSPI0_STS DDIV_PACK(G3L_CLKDIVSTATUS, 20, 1) #define G3L_DIV_RSPI1_STS DDIV_PACK(G3L_CLKDIVSTATUS, 21, 1) #define G3L_DIV_RSPI2_STS DDIV_PACK(G3L_CLKDIVSTATUS, 22, 1) +#define G3L_DIV_SDHI0_STS DDIV_PACK(G3L_CLKDIVSTATUS, 24, 1) +#define G3L_DIV_SDHI1_STS DDIV_PACK(G3L_CLKDIVSTATUS, 25, 1) +#define G3L_DIV_SDHI2_STS DDIV_PACK(G3L_CLKDIVSTATUS, 26, 1) + +#define G3L_SEL_SDHI0_STS SEL_PLL_PACK(G3L_CLKSELSTATUS, 16, 1) +#define G3L_SEL_SDHI1_STS SEL_PLL_PACK(G3L_CLKSELSTATUS, 17, 1) +#define G3L_SEL_SDHI2_STS SEL_PLL_PACK(G3L_CLKSELSTATUS, 18, 1) =20 /* RZ/G3L Specific clocks select. */ +#define G3L_SEL_SDHI0 SEL_PLL_PACK(G3L_CPG_SDHI_DSEL, 0, 2) +#define G3L_SEL_SDHI1 SEL_PLL_PACK(G3L_CPG_SDHI_DSEL, 4, 2) +#define G3L_SEL_SDHI2 SEL_PLL_PACK(G3L_CPG_SDHI_DSEL, 8, 2) #define G3L_SEL_ETH0_TX SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 0, 1) #define G3L_SEL_ETH0_RX SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 1, 1) #define G3L_SEL_ETH0_RM SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 2, 1) @@ -94,6 +110,7 @@ enum clk_ids { =20 /* Internal Core Clocks */ CLK_PLL1, + CLK_PLL1_DIV2, CLK_PLL2, CLK_PLL2_DIV2, CLK_PLL2_DIV2_4, @@ -117,16 +134,29 @@ enum clk_ids { CLK_SEL_RSPI0, CLK_SEL_RSPI1, CLK_SEL_RSPI2, + CLK_SEL_SDHI0, + CLK_SEL_SDHI1, + CLK_SEL_SDHI2, CLK_ETH0_TR, CLK_ETH0_RM, CLK_ETH1_TR, CLK_ETH1_RM, + CLK_SD0_DIV2, + CLK_SD1_DIV2, + CLK_SD2_DIV2, =20 /* Module Clocks */ MOD_CLK_BASE, }; =20 /* Divider tables */ +static const struct clk_div_table dtable_1_4[] =3D { + { 0, 1 }, + { 1, 2 }, + { 2, 4 }, + { 0, 0 }, +}; + static const struct clk_div_table dtable_1_8[] =3D { { 0, 1 }, { 1, 2 }, @@ -190,11 +220,15 @@ static const char * const sel_eth1_tx[] =3D { ".div_e= th1_tr", "eth1_txc_tx_clk" }; static const char * const sel_eth1_rx[] =3D { ".div_eth1_tr", "eth1_rxc_rx= _clk" }; static const char * const sel_eth1_rm[] =3D { ".pll6_div10", "eth1_rxc_rx_= clk" }; static const char * const sel_rsci_rspi[] =3D { ".pll2_div5", ".pll2_div6"= , ".pll2_div7", ".pll2_div2_4" }; +static const char * const sel_sdhi[] =3D { ".pll2_div2", ".pll1_div2", ".= pll6", ".pll2_div6" }; static const char * const sel_eth0_clk_tx_i[] =3D { ".sel_eth0_tx", ".div_= eth0_rm" }; static const char * const sel_eth0_clk_rx_i[] =3D { ".sel_eth0_rx", ".div_= eth0_rm" }; static const char * const sel_eth1_clk_tx_i[] =3D { ".sel_eth1_tx", ".div_= eth1_rm" }; static const char * const sel_eth1_clk_rx_i[] =3D { ".sel_eth1_rx", ".div_= eth1_rm" }; =20 +/* Mux clock indices tables. */ +static const u32 mtable_sd[] =3D { 0, 1, 2, 3 }; + static const struct cpg_core_clk r9a08g046_core_clks[] __initconst =3D { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), @@ -210,6 +244,7 @@ static const struct cpg_core_clk r9a08g046_core_clks[] = __initconst =3D { DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3), DEF_G3L_PLL(".pll6", CLK_PLL6, CLK_EXTAL, CPG_PLL_CONF(0x50, 0), 500000000UL), + DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 1, 2), DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2), DEF_FIXED(".pll2_div2_4", CLK_PLL2_DIV2_4, CLK_PLL2_DIV2, 1, 4), DEF_FIXED(".pll2_div5", CLK_PLL2_DIV5, CLK_PLL2, 1, 5), @@ -217,6 +252,12 @@ static const struct cpg_core_clk r9a08g046_core_clks[]= __initconst =3D { DEF_FIXED(".pll2_div7", CLK_PLL2_DIV7, CLK_PLL2, 1, 7), DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), DEF_FIXED(".pll6_div10", CLK_PLL6_DIV10, CLK_PLL6, 1, 10), + DEF_SD_MUX(".sel_sdhi0", CLK_SEL_SDHI0, G3L_SEL_SDHI0, G3L_SEL_SDHI0_STS,= sel_sdhi, + mtable_sd, 0, NULL), + DEF_SD_MUX(".sel_sdhi1", CLK_SEL_SDHI1, G3L_SEL_SDHI1, G3L_SEL_SDHI1_STS,= sel_sdhi, + mtable_sd, 0, NULL), + DEF_SD_MUX(".sel_sdhi2", CLK_SEL_SDHI2, G3L_SEL_SDHI2, G3L_SEL_SDHI2_STS,= sel_sdhi, + mtable_sd, 0, NULL), DEF_MUX(".sel_rsci0", CLK_SEL_RSCI0, G3L_SEL_RSCI0, sel_rsci_rspi), DEF_MUX(".sel_rsci1", CLK_SEL_RSCI1, G3L_SEL_RSCI1, sel_rsci_rspi), DEF_MUX(".sel_rsci2", CLK_SEL_RSCI2, G3L_SEL_RSCI2, sel_rsci_rspi), @@ -264,6 +305,18 @@ static const struct cpg_core_clk r9a08g046_core_clks[]= __initconst =3D { dtable_1_8, 0, 200000000UL, 0, NULL), DEF_G3S_DIV("P19", R9A08G046_CLK_P19, CLK_SEL_RSPI2, G3L_DIV_RSPI2, G3L_D= IV_RSPI2_STS, dtable_1_8, 0, 200000000UL, 0, NULL), + DEF_G3S_DIV("SD0", R9A08G046_CLK_SD0, CLK_SEL_SDHI0, G3L_DIV_SDHI0, G3L_D= IV_SDHI0_STS, + dtable_1_4, 800000000UL, 600000000UL, CLK_SET_RATE_PARENT, + rzg3s_cpg_div_clk_notifier), + DEF_G3S_DIV("SD1", R9A08G046_CLK_SD1, CLK_SEL_SDHI1, G3L_DIV_SDHI1, G3L_D= IV_SDHI1_STS, + dtable_1_4, 800000000UL, 600000000UL, CLK_SET_RATE_PARENT, + rzg3s_cpg_div_clk_notifier), + DEF_G3S_DIV("SD2", R9A08G046_CLK_SD2, CLK_SEL_SDHI2, G3L_DIV_SDHI2, G3L_D= IV_SDHI2_STS, + dtable_1_4, 800000000UL, 600000000UL, CLK_SET_RATE_PARENT, + rzg3s_cpg_div_clk_notifier), + DEF_FIXED(".sd0_div2", CLK_SD0_DIV2, R9A08G046_CLK_SD0, 1, 2), + DEF_FIXED(".sd1_div2", CLK_SD1_DIV2, R9A08G046_CLK_SD1, 1, 2), + DEF_FIXED(".sd2_div2", CLK_SD2_DIV2, R9A08G046_CLK_SD2, 1, 2), DEF_FIXED("HP", R9A08G046_CLK_HP, CLK_PLL6_DIV10, 1, 1), DEF_MUX_FLAGS("ETHTX01", R9A08G046_CLK_ETHTX01, G3L_SEL_ETH0_CLK_TX_I, se= l_eth0_clk_tx_i, CLK_SET_RATE_PARENT), @@ -297,6 +350,36 @@ static const struct rzg2l_mod_clk r9a08g046_mod_clks[]= =3D { MSTOP(BUS_REG0, BIT(0))), DEF_MOD("wdt0_clk", R9A08G046_WDT0_CLK, R9A08G046_OSCCLK, 0x548, 1, MSTOP(BUS_REG0, BIT(0))), + DEF_MOD("sdhi0_imclk", R9A08G046_SDHI0_IMCLK, CLK_SD0_DIV2, 0x554, 0, + MSTOP(BUS_PERI_COM, BIT(0))), + DEF_MOD("sdhi0_imclk2", R9A08G046_SDHI0_IMCLK2, CLK_SD0_DIV2, 0x554, 1, + MSTOP(BUS_PERI_COM, BIT(0))), + DEF_MOD("sdhi0_clk_hs", R9A08G046_SDHI0_CLK_HS, R9A08G046_CLK_SD0, 0x554= , 2, + MSTOP(BUS_PERI_COM, BIT(0))), + DEF_MOD("sdhi0_iaclks", R9A08G046_SDHI0_IACLKS, R9A08G046_CLK_P1, 0x554,= 3, + MSTOP(BUS_PERI_COM, BIT(0))), + DEF_MOD("sdhi0_iaclkm", R9A08G046_SDHI0_IACLKM, R9A08G046_CLK_P1, 0x554,= 12, + MSTOP(BUS_PERI_COM, BIT(0))), + DEF_MOD("sdhi1_imclk", R9A08G046_SDHI1_IMCLK, CLK_SD1_DIV2, 0x554, 4, + MSTOP(BUS_PERI_COM, BIT(1))), + DEF_MOD("sdhi1_imclk2", R9A08G046_SDHI1_IMCLK2, CLK_SD1_DIV2, 0x554, 5, + MSTOP(BUS_PERI_COM, BIT(1))), + DEF_MOD("sdhi1_clk_hs", R9A08G046_SDHI1_CLK_HS, R9A08G046_CLK_SD1, 0x554= , 6, + MSTOP(BUS_PERI_COM, BIT(1))), + DEF_MOD("sdhi1_iaclks", R9A08G046_SDHI1_IACLKS, R9A08G046_CLK_P1, 0x554,= 7, + MSTOP(BUS_PERI_COM, BIT(1))), + DEF_MOD("sdhi1_iaclkm", R9A08G046_SDHI1_IACLKM, R9A08G046_CLK_P1, 0x554,= 13, + MSTOP(BUS_PERI_COM, BIT(1))), + DEF_MOD("sdhi2_imclk", R9A08G046_SDHI2_IMCLK, CLK_SD2_DIV2, 0x554, 8, + MSTOP(BUS_PERI_COM, BIT(11))), + DEF_MOD("sdhi2_imclk2", R9A08G046_SDHI2_IMCLK2, CLK_SD2_DIV2, 0x554, 9, + MSTOP(BUS_PERI_COM, BIT(11))), + DEF_MOD("sdhi2_clk_hs", R9A08G046_SDHI2_CLK_HS, R9A08G046_CLK_SD2, 0x554= , 10, + MSTOP(BUS_PERI_COM, BIT(11))), + DEF_MOD("sdhi2_iaclks", R9A08G046_SDHI2_IACLKS, R9A08G046_CLK_P1, 0x554,= 11, + MSTOP(BUS_PERI_COM, BIT(11))), + DEF_MOD("sdhi2_iaclkm", R9A08G046_SDHI2_IACLKM, R9A08G046_CLK_P1, 0x554,= 14, + MSTOP(BUS_PERI_COM, BIT(11))), DEF_MOD("ssi0_pclk2", R9A08G046_SSI0_PCLK2, R9A08G046_CLK_P0, 0x570, 0, MSTOP(BUS_MCPU1, BIT(10))), DEF_MOD("ssi0_pclk_sfr", R9A08G046_SSI0_PCLK_SFR, R9A08G046_CLK_P0, 0x570= , 1, @@ -412,6 +495,15 @@ static const struct rzg2l_reset r9a08g046_resets[] =3D= { DEF_RST(R9A08G046_DMAC_ARESETN, 0x82c, 0), DEF_RST(R9A08G046_DMAC_RST_ASYNC, 0x82c, 1), DEF_RST(R9A08G046_WDT0_PRESETN, 0x848, 0), + DEF_RST(R9A08G046_SDHI0_IXRST, 0x854, 0), + DEF_RST(R9A08G046_SDHI1_IXRST, 0x854, 1), + DEF_RST(R9A08G046_SDHI2_IXRST, 0x854, 2), + DEF_RST(R9A08G046_SDHI0_IXRSTAXIM, 0x854, 3), + DEF_RST(R9A08G046_SDHI0_IXRSTAXIS, 0x854, 4), + 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Uytterhoeven , Linus Walleij Cc: Biju Das , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v17 03/17] pinctrl: renesas: rzg2l: Add SD channel POC support for RZ/G3L Date: Wed, 3 Jun 2026 07:57:03 +0100 Message-ID: <20260603065731.93243-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260603065731.93243-1-biju.das.jz@bp.renesas.com> References: <20260603065731.93243-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Biju Das Add power-on control (POC) support for SD channels 1 and 2 on the RZ/G3L SoC (r9a08g046). Introduce PIN_CFG_IO_VMC_SD2 capability flag (bit 22) and SD_CH2_POC register offset (0x3024). Extend rzg2l_caps_to_pwr_reg() to return SD_CH2_POC when PIN_CFG_IO_VMC_SD2 is set. Replace RZG3L_MPXED_PIN_FUNCS() with RZG2L_MPXED_COMMON_PIN_FUNCS() for port PG and PH pins, dropping PIN_CFG_SOFT_PS which is inappropriate for SD pins, and annotate them with PIN_CFG_IO_VMC_SD1 and PIN_CFG_IO_VMC_SD2 respectively. Annotate all RZ/G3L SD0 dedicated pins (CLK, CMD, RST#, DS, DAT0=E2=80=93DA= T7) with PIN_CFG_IO_VMC_SD0 so that power-source register lookups work correctly for those pins. Add sd_ch2 field to rzg2l_register_offsets and rzg2l_pinctrl_reg_cache to save and restore the SD_CH2_POC register across suspend/resume cycles. Signed-off-by: Biju Das --- v1->v2: * No change. --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 74 +++++++++++++++++-------- 1 file changed, 50 insertions(+), 24 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 83c61dcb24b1..b1d4b2b9e176 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -69,6 +69,7 @@ #define PIN_CFG_PVDD1833_OTH_AWO_POC BIT(19) /* known on RZ/G3L only */ #define PIN_CFG_PVDD1833_OTH_ISO_POC BIT(20) /* known on RZ/G3L only */ #define PIN_CFG_WDTOVF_N_POC BIT(21) /* known on RZ/G3L only */ +#define PIN_CFG_IO_VMC_SD2 BIT(22) /* known on RZ/G3L only */ =20 #define RZG2L_SINGLE_PIN BIT_ULL(63) /* Dedicated pin */ #define RZG2L_VARIABLE_CFG BIT_ULL(62) /* Variable cfg for port pins */ @@ -258,6 +259,7 @@ static const struct pin_config_item renesas_rzv2h_conf_= items[] =3D { * @oen: OEN register offset * @qspi: QSPI register offset * @other_poc: OTHER_POC register offset + * @sd_ch2: SD_CH2_POC register offset */ struct rzg2l_register_offsets { u16 pwpr; @@ -266,6 +268,7 @@ struct rzg2l_register_offsets { u16 oen; u16 qspi; u16 other_poc; + u16 sd_ch2; }; =20 /** @@ -372,6 +375,7 @@ struct rzg2l_pinctrl_pin_settings { * @oen: Output Enable register cache * @other_poc: OTHER_POC register cache * @qspi: QSPI registers cache + * @sd_ch2: SD_CH2_POC registers cache */ struct rzg2l_pinctrl_reg_cache { u8 *p; @@ -390,6 +394,7 @@ struct rzg2l_pinctrl_reg_cache { u8 oen; u8 other_poc; u8 qspi; + u8 sd_ch2; }; =20 struct rzg2l_pinctrl { @@ -474,20 +479,32 @@ static const u64 r9a08g046_variable_pin_cfg[] =3D { RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 5, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 6, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 7, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), - RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 0, RZG3L_MPXED_PIN_FUNCS(B)), - RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 1, RZG3L_MPXED_PIN_FUNCS(B) | PIN_C= FG_IEN), - RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 2, RZG3L_MPXED_PIN_FUNCS(B) | PIN_C= FG_IEN), - RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 3, RZG3L_MPXED_PIN_FUNCS(B) | PIN_C= FG_IEN), - RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 4, RZG3L_MPXED_PIN_FUNCS(B) | PIN_C= FG_IEN), - RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 5, RZG3L_MPXED_PIN_FUNCS(B) | PIN_C= FG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 0, RZG2L_MPXED_COMMON_PIN_FUNCS(B) | + PIN_CFG_IO_VMC_SD1), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 1, RZG2L_MPXED_COMMON_PIN_FUNCS(B) | + PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 2, RZG2L_MPXED_COMMON_PIN_FUNCS(B) | + PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 3, RZG2L_MPXED_COMMON_PIN_FUNCS(B) = | PIN_CFG_IEN | + PIN_CFG_IO_VMC_SD1), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 4, RZG2L_MPXED_COMMON_PIN_FUNCS(B) | + PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 5, RZG2L_MPXED_COMMON_PIN_FUNCS(B) | + PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 6, RZG3L_MPXED_PIN_FUNCS_POC(B, ISO= )), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 7, RZG3L_MPXED_PIN_FUNCS_POC(B, ISO= )), - RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 0, RZG3L_MPXED_PIN_FUNCS(B)), - RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 1, RZG3L_MPXED_PIN_FUNCS(B) | PIN_C= FG_IEN), - RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 2, RZG3L_MPXED_PIN_FUNCS(B) | PIN_C= FG_IEN), - RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 3, RZG3L_MPXED_PIN_FUNCS(B) | PIN_C= FG_IEN), - RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 4, RZG3L_MPXED_PIN_FUNCS(B) | PIN_C= FG_IEN), - RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 5, RZG3L_MPXED_PIN_FUNCS(B) | PIN_C= FG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 0, RZG2L_MPXED_COMMON_PIN_FUNCS(B) | + PIN_CFG_IO_VMC_SD2), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 1, RZG2L_MPXED_COMMON_PIN_FUNCS(B) | + PIN_CFG_IEN | PIN_CFG_IO_VMC_SD2), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 2, RZG2L_MPXED_COMMON_PIN_FUNCS(B) | + PIN_CFG_IEN | PIN_CFG_IO_VMC_SD2), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 3, RZG2L_MPXED_COMMON_PIN_FUNCS(B) | + PIN_CFG_IEN | PIN_CFG_IO_VMC_SD2), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 4, RZG2L_MPXED_COMMON_PIN_FUNCS(B) | + PIN_CFG_IEN | PIN_CFG_IO_VMC_SD2), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 5, RZG2L_MPXED_COMMON_PIN_FUNCS(B) | + PIN_CFG_IEN | PIN_CFG_IO_VMC_SD2), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 0, RZG3L_MPXED_PIN_FUNCS(A) | PIN_C= FG_IEN), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 1, RZG3L_MPXED_PIN_FUNCS(A)), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 2, RZG3L_MPXED_PIN_FUNCS(A)), @@ -1053,6 +1070,8 @@ static int rzg2l_caps_to_pwr_reg(const struct rzg2l_r= egister_offsets *regs, return SD_CH(regs->sd_ch, 0); if (caps & PIN_CFG_IO_VMC_SD1) return SD_CH(regs->sd_ch, 1); + if (caps & PIN_CFG_IO_VMC_SD2) + return regs->sd_ch2; if (caps & PIN_CFG_IO_VMC_ETH0) return ETH_POC(regs->eth_poc, 0); if (caps & PIN_CFG_IO_VMC_ETH1) @@ -2677,28 +2696,28 @@ static const struct rzg2l_dedicated_configs rzg3l_d= edicated_pins[] =3D { (PIN_CFG_IOLH_A | PIN_CFG_PUPD | PIN_CFG_PVDD1833_OTH_AWO_POC)) }, { "SCIF0_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1, (PIN_CFG_IOLH_A | PIN_CFG_PUPD | PIN_CFG_PVDD1833_OTH_AWO_POC)) }, - { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0, PIN_CFG_IOLH_B) }, + { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0, PIN_CFG_IOLH_B | PIN_CFG_IO_VM= C_SD0) }, { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1, - (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, - { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x9, 2, PIN_CFG_IOLH_B) }, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD | PIN_CFG_IO_VMC_SD0)) }, + { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x9, 2, PIN_CFG_IOLH_B | PIN_CFG_IO_V= MC_SD0) }, { "SD0_DS", RZG2L_SINGLE_PIN_PACK(0x9, 5, - (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD | PIN_CFG_IO_VMC_SD0)) }, { "SD0_DAT0", RZG2L_SINGLE_PIN_PACK(0x0a, 0, - (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD | PIN_CFG_IO_VMC_SD0)) }, { "SD0_DAT1", RZG2L_SINGLE_PIN_PACK(0x0a, 1, - (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD | PIN_CFG_IO_VMC_SD0)) }, { "SD0_DAT2", RZG2L_SINGLE_PIN_PACK(0x0a, 2, - (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD | PIN_CFG_IO_VMC_SD0)) }, { "SD0_DAT3", RZG2L_SINGLE_PIN_PACK(0x0a, 3, - (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD | PIN_CFG_IO_VMC_SD0)) }, { "SD0_DAT4", RZG2L_SINGLE_PIN_PACK(0x0a, 4, - (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD | PIN_CFG_IO_VMC_SD0)) }, { "SD0_DAT5", RZG2L_SINGLE_PIN_PACK(0x0a, 5, - (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD | PIN_CFG_IO_VMC_SD0)) }, { "SD0_DAT6", RZG2L_SINGLE_PIN_PACK(0x0a, 6, - (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD | PIN_CFG_IO_VMC_SD0)) }, { "SD0_DAT7", RZG2L_SINGLE_PIN_PACK(0x0a, 7, - (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD | PIN_CFG_IO_VMC_SD0)) }, }; =20 static const u32 r9a08g046_clone_channel_data[] =3D { @@ -3672,6 +3691,9 @@ static int rzg2l_pinctrl_suspend_noirq(struct device = *dev) cache->eth_poc[i] =3D readb(pctrl->base + ETH_POC(regs->eth_poc, i)); } =20 + if (regs->sd_ch2) + cache->sd_ch2 =3D readb(pctrl->base + regs->sd_ch2); + if (regs->qspi) cache->qspi =3D readb(pctrl->base + regs->qspi); cache->oen =3D readb(pctrl->base + pctrl->data->hwcfg->regs.oen); @@ -3724,6 +3746,9 @@ static int rzg2l_pinctrl_resume_noirq(struct device *= dev) rzg2l_oen_write_with_pwpr(pctrl, cache->oen); raw_spin_unlock_irqrestore(&pctrl->lock, flags); =20 + if (regs->sd_ch2) + writeb(cache->sd_ch2, pctrl->base + regs->sd_ch2); + for (u8 i =3D 0; i < 2; i++) { if (regs->sd_ch) writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i)); @@ -3794,6 +3819,7 @@ static const struct rzg2l_hwcfg rzg3l_hwcfg =3D { .eth_poc =3D 0x3010, .oen =3D 0x3018, .other_poc =3D OTHER_POC, + .sd_ch2 =3D 0x3024, }, .iolh_groupa_ua =3D { /* 1v8 power source */ --=20 2.43.0 From nobody Mon Jun 8 06:38:26 2026 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3AFE93F5BF8 for ; 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charset="utf-8" From: Biju Das Remove extra spaces in the renesas_sdhi_of_data struct definition, replacing the tab/space mix used to align tmio_ocr_mask with a single space, consistent with kernel coding style. Signed-off-by: Biju Das --- v1->v2: * No change. --- drivers/mmc/host/renesas_sdhi.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/host/renesas_sdhi.h b/drivers/mmc/host/renesas_sdh= i.h index afc36a407c2c..09bf9b24a8c3 100644 --- a/drivers/mmc/host/renesas_sdhi.h +++ b/drivers/mmc/host/renesas_sdhi.h @@ -25,7 +25,7 @@ struct renesas_sdhi_scc { =20 struct renesas_sdhi_of_data { unsigned long tmio_flags; - u32 tmio_ocr_mask; + u32 tmio_ocr_mask; unsigned long capabilities; unsigned long capabilities2; enum dma_slave_buswidth dma_buswidth; --=20 2.43.0 From nobody Mon Jun 8 06:38:26 2026 Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D7C43FB7FC for ; Wed, 3 Jun 2026 06:57:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.53 ARC-Seal: i=1; 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charset="utf-8" From: Biju Das Remove extra tabs used to align .of_data and .quirks fields in the of_rza2_compatible struct initializer, replacing them with single space, consistent with kernel coding style. Signed-off-by: Biju Das --- v1->v2: * No change. --- drivers/mmc/host/renesas_sdhi_internal_dmac.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/ho= st/renesas_sdhi_internal_dmac.c index 024edc4e5fe6..08cf1604ef1d 100644 --- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c +++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c @@ -272,8 +272,8 @@ static const struct renesas_sdhi_of_data_with_quirks of= _rcar_gen3_nohs400_compat }; =20 static const struct renesas_sdhi_of_data_with_quirks of_rza2_compatible = =3D { - .of_data =3D &of_data_rza2, - .quirks =3D &sdhi_quirks_fixed_addr, + .of_data =3D &of_data_rza2, + .quirks =3D &sdhi_quirks_fixed_addr, }; =20 static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] =3D= { --=20 2.43.0 From nobody Mon Jun 8 06:38:26 2026 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1FD2A3FBEC0 for ; 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Tue, 02 Jun 2026 23:57:42 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a700:7301:179c:89ab:19f6:9ba4]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-490b79d90bdsm9001855e9.0.2026.06.02.23.57.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 23:57:41 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Wolfram Sang , Ulf Hansson Cc: Biju Das , linux-mmc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v17 06/17] mmc: renesas_sdhi: Introduce renesas_sdhi_hw_info to abstract clock mask Date: Wed, 3 Jun 2026 07:57:06 +0100 Message-ID: <20260603065731.93243-7-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260603065731.93243-1-biju.das.jz@bp.renesas.com> References: <20260603065731.93243-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The RZ/G3L SoC has 11 divider bits and requires a different clock mask in renesas_sdhi_set_clock(). Add a new renesas_sdhi_hw_info struct to hold hardware-specific parameters, starting with clk_mask. This replaces the hardcoded constant in renesas_sdhi_set_clock() with a value sourced from the per-device hw_info, and widens the clk variable from u32 to u64 accordingly, as clk_mask for RZ/G3L exceeds 32 bits. Wire hw_info through renesas_sdhi_of_data_with_quirks (internalDMAC path) and a new renesas_sdhi_of_data_with_info wrapper (sysDMAC path), and plumb it into renesas_sdhi_probe() so it is stored in the per-instance renesas_sdhi struct. All existing users are assigned sdhi_hw_info_generic, preserving current behaviour. No functional change. Signed-off-by: Biju Das --- v1->v2: * No change. --- drivers/mmc/host/renesas_sdhi.h | 12 ++++ drivers/mmc/host/renesas_sdhi_core.c | 7 +- drivers/mmc/host/renesas_sdhi_internal_dmac.c | 16 ++++- drivers/mmc/host/renesas_sdhi_sys_dmac.c | 66 ++++++++++++++----- 4 files changed, 81 insertions(+), 20 deletions(-) diff --git a/drivers/mmc/host/renesas_sdhi.h b/drivers/mmc/host/renesas_sdh= i.h index 09bf9b24a8c3..a7fc525b7218 100644 --- a/drivers/mmc/host/renesas_sdhi.h +++ b/drivers/mmc/host/renesas_sdhi.h @@ -41,6 +41,15 @@ struct renesas_sdhi_of_data { =20 #define SDHI_CALIB_TABLE_MAX 32 =20 +struct renesas_sdhi_hw_info { + u64 clk_mask; +}; + +struct renesas_sdhi_of_data_with_info { + const struct renesas_sdhi_of_data *of_data; + const struct renesas_sdhi_hw_info *info; +}; + #define sdhi_has_quirk(p, q) ((p)->quirks && (p)->quirks->q) =20 struct renesas_sdhi_quirks { @@ -57,6 +66,7 @@ struct renesas_sdhi_quirks { struct renesas_sdhi_of_data_with_quirks { const struct renesas_sdhi_of_data *of_data; const struct renesas_sdhi_quirks *quirks; + const struct renesas_sdhi_hw_info *info; }; =20 /* We want both end_flags to be set before we mark DMA as finished */ @@ -79,6 +89,7 @@ struct renesas_sdhi { struct tmio_mmc_data mmc_data; struct renesas_sdhi_dma dma_priv; const struct renesas_sdhi_quirks *quirks; + const struct renesas_sdhi_hw_info *info; struct pinctrl *pinctrl; struct pinctrl_state *pins_default, *pins_uhs; void __iomem *scc_ctl; @@ -106,6 +117,7 @@ struct renesas_sdhi { int renesas_sdhi_probe(struct platform_device *pdev, const struct tmio_mmc_dma_ops *dma_ops, const struct renesas_sdhi_of_data *of_data, + const struct renesas_sdhi_hw_info *info, const struct renesas_sdhi_quirks *quirks); void renesas_sdhi_remove(struct platform_device *pdev); int renesas_sdhi_suspend(struct device *dev); diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesa= s_sdhi_core.c index f9ec78d699f4..2ff40950f209 100644 --- a/drivers/mmc/host/renesas_sdhi_core.c +++ b/drivers/mmc/host/renesas_sdhi_core.c @@ -193,8 +193,9 @@ static unsigned int renesas_sdhi_clk_update(struct tmio= _mmc_host *host, static void renesas_sdhi_set_clock(struct tmio_mmc_host *host, unsigned int new_clock) { + struct renesas_sdhi *priv =3D host_to_priv(host); unsigned int clk_margin; - u32 clk =3D 0, clock; + u64 clk =3D 0, clock; =20 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); @@ -213,7 +214,7 @@ static void renesas_sdhi_set_clock(struct tmio_mmc_host= *host, * provided for actual_clock in renesas_sdhi_clk_update(). */ clk_margin =3D new_clock >> 10; - for (clk =3D 0x80000080; new_clock + clk_margin >=3D (clock << 1); clk >>= =3D 1) + for (clk =3D priv->info->clk_mask; new_clock + clk_margin >=3D (clock << = 1); clk >>=3D 1) clock <<=3D 1; =20 /* 1/1 clock is option */ @@ -1055,6 +1056,7 @@ static const struct regulator_desc renesas_sdhi_vqmmc= _regulator =3D { int renesas_sdhi_probe(struct platform_device *pdev, const struct tmio_mmc_dma_ops *dma_ops, const struct renesas_sdhi_of_data *of_data, + const struct renesas_sdhi_hw_info *info, const struct renesas_sdhi_quirks *quirks) { struct tmio_mmc_data *mmd =3D pdev->dev.platform_data; @@ -1079,6 +1081,7 @@ int renesas_sdhi_probe(struct platform_device *pdev, if (!priv) return -ENOMEM; =20 + priv->info =3D info; priv->quirks =3D quirks; mmc_data =3D &priv->mmc_data; dma_priv =3D &priv->dma_priv; diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/ho= st/renesas_sdhi_internal_dmac.c index 08cf1604ef1d..512ed70b3779 100644 --- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c +++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c @@ -232,48 +232,61 @@ static const struct soc_device_attribute sdhi_quirks_= match[] =3D { { /* Sentinel. */ } }; =20 +static const struct renesas_sdhi_hw_info sdhi_hw_info_generic =3D { + .clk_mask =3D 0x80000080, +}; + static const struct renesas_sdhi_of_data_with_quirks of_r8a7795_compatible= =3D { .of_data =3D &of_data_rcar_gen3, .quirks =3D &sdhi_quirks_bad_taps2367, + .info =3D &sdhi_hw_info_generic, }; =20 static const struct renesas_sdhi_of_data_with_quirks of_r8a77961_compatibl= e =3D { .of_data =3D &of_data_rcar_gen3, .quirks =3D &sdhi_quirks_bad_taps1357, + .info =3D &sdhi_hw_info_generic, }; =20 static const struct renesas_sdhi_of_data_with_quirks of_r8a77965_compatibl= e =3D { .of_data =3D &of_data_rcar_gen3, .quirks =3D &sdhi_quirks_r8a77965, + .info =3D &sdhi_hw_info_generic, }; =20 static const struct renesas_sdhi_of_data_with_quirks of_r8a77970_compatibl= e =3D { .of_data =3D &of_data_rcar_gen3_no_sdh_fallback, .quirks =3D &sdhi_quirks_nohs400, + .info =3D &sdhi_hw_info_generic, }; =20 static const struct renesas_sdhi_of_data_with_quirks of_r8a77990_compatibl= e =3D { .of_data =3D &of_data_rcar_gen3, .quirks =3D &sdhi_quirks_r8a77990, + .info =3D &sdhi_hw_info_generic, }; =20 static const struct renesas_sdhi_of_data_with_quirks of_rzg2l_compatible = =3D { .of_data =3D &of_data_rcar_gen3, .quirks =3D &sdhi_quirks_rzg2l, + .info =3D &sdhi_hw_info_generic, }; =20 static const struct renesas_sdhi_of_data_with_quirks of_rcar_gen3_compatib= le =3D { .of_data =3D &of_data_rcar_gen3, + .info =3D &sdhi_hw_info_generic, }; =20 static const struct renesas_sdhi_of_data_with_quirks of_rcar_gen3_nohs400_= compatible =3D { .of_data =3D &of_data_rcar_gen3, .quirks =3D &sdhi_quirks_nohs400, + .info =3D &sdhi_hw_info_generic, }; =20 static const struct renesas_sdhi_of_data_with_quirks of_rza2_compatible = =3D { .of_data =3D &of_data_rza2, .quirks =3D &sdhi_quirks_fixed_addr, + .info =3D &sdhi_hw_info_generic, }; =20 static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] =3D= { @@ -599,7 +612,8 @@ static int renesas_sdhi_internal_dmac_probe(struct plat= form_device *pdev) dma_set_max_seg_size(dev, 0xffffffff); =20 return renesas_sdhi_probe(pdev, &renesas_sdhi_internal_dmac_dma_ops, - of_data_quirks->of_data, quirks); + of_data_quirks->of_data, of_data_quirks->info, + quirks); } =20 static const struct dev_pm_ops renesas_sdhi_internal_dmac_dev_pm_ops =3D { diff --git a/drivers/mmc/host/renesas_sdhi_sys_dmac.c b/drivers/mmc/host/re= nesas_sdhi_sys_dmac.c index 9215600f03a2..1291970c2810 100644 --- a/drivers/mmc/host/renesas_sdhi_sys_dmac.c +++ b/drivers/mmc/host/renesas_sdhi_sys_dmac.c @@ -73,23 +73,51 @@ static const struct renesas_sdhi_of_data of_rcar_gen2_c= ompatible =3D { .max_blk_count =3D UINT_MAX / TMIO_MAX_BLK_SIZE, }; =20 +static const struct renesas_sdhi_hw_info sdhi_hw_info_generic =3D { + .clk_mask =3D 0x80000080, +}; + +static const struct renesas_sdhi_of_data_with_info of_default_cfg_info =3D= { + .of_data =3D &of_default_cfg, + .info =3D &sdhi_hw_info_generic, +}; + +static const struct renesas_sdhi_of_data_with_info of_rz_compatible_info = =3D { + .of_data =3D &of_rz_compatible, + .info =3D &sdhi_hw_info_generic, +}; + +static const struct renesas_sdhi_of_data_with_info of_rcar_gen1_compatible= _info =3D { + .of_data =3D &of_rcar_gen1_compatible, + .info =3D &sdhi_hw_info_generic, +}; + +static const struct renesas_sdhi_of_data_with_info of_rcar_gen2_compatible= _info =3D { + .of_data =3D &of_rcar_gen2_compatible, + .info =3D &sdhi_hw_info_generic, +}; + +static const struct renesas_sdhi_of_data_with_info of_shmobile_info =3D { + .info =3D &sdhi_hw_info_generic, +}; + static const struct of_device_id renesas_sdhi_sys_dmac_of_match[] =3D { - { .compatible =3D "renesas,sdhi-sh73a0", .data =3D &of_default_cfg, }, - { .compatible =3D "renesas,sdhi-r8a73a4", .data =3D &of_default_cfg, }, - { .compatible =3D "renesas,sdhi-r8a7740", .data =3D &of_default_cfg, }, - { .compatible =3D "renesas,sdhi-r7s72100", .data =3D &of_rz_compatible, }, - { .compatible =3D "renesas,sdhi-r8a7778", .data =3D &of_rcar_gen1_compati= ble, }, - { .compatible =3D "renesas,sdhi-r8a7779", .data =3D &of_rcar_gen1_compati= ble, }, - { .compatible =3D "renesas,sdhi-r8a7743", .data =3D &of_rcar_gen2_compati= ble, }, - { .compatible =3D "renesas,sdhi-r8a7745", .data =3D &of_rcar_gen2_compati= ble, }, - { .compatible =3D "renesas,sdhi-r8a7790", .data =3D &of_rcar_gen2_compati= ble, }, - { .compatible =3D "renesas,sdhi-r8a7791", .data =3D &of_rcar_gen2_compati= ble, }, - { .compatible =3D "renesas,sdhi-r8a7792", .data =3D &of_rcar_gen2_compati= ble, }, - { .compatible =3D "renesas,sdhi-r8a7793", .data =3D &of_rcar_gen2_compati= ble, }, - { .compatible =3D "renesas,sdhi-r8a7794", .data =3D &of_rcar_gen2_compati= ble, }, - { .compatible =3D "renesas,rcar-gen1-sdhi", .data =3D &of_rcar_gen1_compa= tible, }, - { .compatible =3D "renesas,rcar-gen2-sdhi", .data =3D &of_rcar_gen2_compa= tible, }, - { .compatible =3D "renesas,sdhi-shmobile" }, + { .compatible =3D "renesas,sdhi-sh73a0", .data =3D &of_default_cfg_info, = }, + { .compatible =3D "renesas,sdhi-r8a73a4", .data =3D &of_default_cfg_info,= }, + { .compatible =3D "renesas,sdhi-r8a7740", .data =3D &of_default_cfg_info,= }, + { .compatible =3D "renesas,sdhi-r7s72100", .data =3D &of_rz_compatible_in= fo, }, + { .compatible =3D "renesas,sdhi-r8a7778", .data =3D &of_rcar_gen1_compati= ble_info, }, + { .compatible =3D "renesas,sdhi-r8a7779", .data =3D &of_rcar_gen1_compati= ble_info, }, + { .compatible =3D "renesas,sdhi-r8a7743", .data =3D &of_rcar_gen2_compati= ble_info, }, + { .compatible =3D "renesas,sdhi-r8a7745", .data =3D &of_rcar_gen2_compati= ble_info, }, + { .compatible =3D "renesas,sdhi-r8a7790", .data =3D &of_rcar_gen2_compati= ble_info, }, + { .compatible =3D "renesas,sdhi-r8a7791", .data =3D &of_rcar_gen2_compati= ble_info, }, + { .compatible =3D "renesas,sdhi-r8a7792", .data =3D &of_rcar_gen2_compati= ble_info, }, + { .compatible =3D "renesas,sdhi-r8a7793", .data =3D &of_rcar_gen2_compati= ble_info, }, + { .compatible =3D "renesas,sdhi-r8a7794", .data =3D &of_rcar_gen2_compati= ble_info, }, + { .compatible =3D "renesas,rcar-gen1-sdhi", .data =3D &of_rcar_gen1_compa= tible_info, }, + { .compatible =3D "renesas,rcar-gen2-sdhi", .data =3D &of_rcar_gen2_compa= tible_info, }, + { .compatible =3D "renesas,sdhi-shmobile", .data =3D &of_shmobile_info, = }, {}, }; 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Tue, 02 Jun 2026 23:57:43 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a700:7301:179c:89ab:19f6:9ba4]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-490b79d90bdsm9001855e9.0.2026.06.02.23.57.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 23:57:42 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Wolfram Sang , Ulf Hansson Cc: Biju Das , linux-mmc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v17 07/17] mmc: renesas_sdhi: Add max_divider to renesas_sdhi_hw_info Date: Wed, 3 Jun 2026 07:57:07 +0100 Message-ID: <20260603065731.93243-8-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260603065731.93243-1-biju.das.jz@bp.renesas.com> References: <20260603065731.93243-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The RZ/G3L SoC has a maximum divider value of 2048 compared to 512 on the rest of the SoCs. Add a max_divider field to renesas_sdhi_hw_info and replace the hardcoded value in renesas_sdhi_clk_enable() and renesas_sdhi_set_clock() with max_divider. All existing users are assigned max_divider =3D 512 via sdhi_hw_info_generic in both the internal and sys DMAC paths, preserving current behaviour. No functional change. Signed-off-by: Biju Das --- v1->v2: * No change --- drivers/mmc/host/renesas_sdhi.h | 1 + drivers/mmc/host/renesas_sdhi_core.c | 4 ++-- drivers/mmc/host/renesas_sdhi_internal_dmac.c | 1 + drivers/mmc/host/renesas_sdhi_sys_dmac.c | 1 + 4 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/renesas_sdhi.h b/drivers/mmc/host/renesas_sdh= i.h index a7fc525b7218..a42934e6d49d 100644 --- a/drivers/mmc/host/renesas_sdhi.h +++ b/drivers/mmc/host/renesas_sdhi.h @@ -43,6 +43,7 @@ struct renesas_sdhi_of_data { =20 struct renesas_sdhi_hw_info { u64 clk_mask; + unsigned int max_divider; }; =20 struct renesas_sdhi_of_data_with_info { diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesa= s_sdhi_core.c index 2ff40950f209..16ed6fd8470d 100644 --- a/drivers/mmc/host/renesas_sdhi_core.c +++ b/drivers/mmc/host/renesas_sdhi_core.c @@ -117,7 +117,7 @@ static int renesas_sdhi_clk_enable(struct tmio_mmc_host= *host) * Minimum frequency is the minimum input clock frequency * divided by our maximum divider. */ - mmc->f_min =3D max(clk_round_rate(priv->clk, 1) / 512, 1L); + mmc->f_min =3D max(clk_round_rate(priv->clk, 1) / priv->info->max_divider= , 1L); =20 /* enable 16bit data access on SDBUF as default */ renesas_sdhi_sdbuf_width(host, 16); @@ -206,7 +206,7 @@ static void renesas_sdhi_set_clock(struct tmio_mmc_host= *host, } =20 host->mmc->actual_clock =3D renesas_sdhi_clk_update(host, new_clock); - clock =3D host->mmc->actual_clock / 512; + clock =3D host->mmc->actual_clock / priv->info->max_divider; =20 /* * Add a margin of 1/1024 rate higher to the clock rate in order diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/ho= st/renesas_sdhi_internal_dmac.c index 512ed70b3779..84b1b38ca465 100644 --- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c +++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c @@ -234,6 +234,7 @@ static const struct soc_device_attribute sdhi_quirks_ma= tch[] =3D { =20 static const struct renesas_sdhi_hw_info sdhi_hw_info_generic =3D { .clk_mask =3D 0x80000080, + .max_divider =3D 512, }; =20 static const struct renesas_sdhi_of_data_with_quirks of_r8a7795_compatible= =3D { diff --git a/drivers/mmc/host/renesas_sdhi_sys_dmac.c b/drivers/mmc/host/re= nesas_sdhi_sys_dmac.c index 1291970c2810..9d34551c6836 100644 --- a/drivers/mmc/host/renesas_sdhi_sys_dmac.c +++ b/drivers/mmc/host/renesas_sdhi_sys_dmac.c @@ -75,6 +75,7 @@ static const struct renesas_sdhi_of_data of_rcar_gen2_com= patible =3D { =20 static const struct renesas_sdhi_hw_info sdhi_hw_info_generic =3D { .clk_mask =3D 0x80000080, + .max_divider =3D 512, }; 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Tue, 02 Jun 2026 23:57:43 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Wolfram Sang , Ulf Hansson Cc: Biju Das , linux-mmc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v17 08/17] mmc: renesas_sdhi: Add tuning_delay hw_info flag Date: Wed, 3 Jun 2026 07:57:08 +0100 Message-ID: <20260603065731.93243-9-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260603065731.93243-1-biju.das.jz@bp.renesas.com> References: <20260603065731.93243-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das As per the RZ/G2L hardware manual, the TMPOUT bit field in the SCC_TMPPORT register needs to be set to 0 when transferring at 3.3V, and to 1 when transferring at 1.8V. Add a tuning_delay bitfield to renesas_sdhi_hw_info to indicate hardware that requires an adjustment when the signal voltage changes. Add sdhi_hw_info_rzg2l with tuning_delay =3D 1 and assign it to of_rzg2l_compatible, enabling the adjustment for RZ/G2L. All other platforms retain sdhi_hw_info_generic with tuning_delay =3D 0 and are unaffected. Signed-off-by: Biju Das --- v1->v2: * No change. --- drivers/mmc/host/renesas_sdhi.h | 2 + drivers/mmc/host/renesas_sdhi_core.c | 83 +++++++++++-------- drivers/mmc/host/renesas_sdhi_internal_dmac.c | 8 +- 3 files changed, 58 insertions(+), 35 deletions(-) diff --git a/drivers/mmc/host/renesas_sdhi.h b/drivers/mmc/host/renesas_sdh= i.h index a42934e6d49d..a3c5fa368242 100644 --- a/drivers/mmc/host/renesas_sdhi.h +++ b/drivers/mmc/host/renesas_sdhi.h @@ -44,6 +44,8 @@ struct renesas_sdhi_of_data { struct renesas_sdhi_hw_info { u64 clk_mask; unsigned int max_divider; + /* hardware features */ + unsigned tuning_delay:1; /* Has tuning delay */ }; =20 struct renesas_sdhi_of_data_with_info { diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesa= s_sdhi_core.c index 16ed6fd8470d..868ba6a6919e 100644 --- a/drivers/mmc/host/renesas_sdhi_core.c +++ b/drivers/mmc/host/renesas_sdhi_core.c @@ -257,40 +257,6 @@ static int renesas_sdhi_card_busy(struct mmc_host *mmc) TMIO_STAT_DAT0); } =20 -static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc, - struct mmc_ios *ios) -{ - struct tmio_mmc_host *host =3D mmc_priv(mmc); - struct renesas_sdhi *priv =3D host_to_priv(host); - struct pinctrl_state *pin_state; - int ret; - - switch (ios->signal_voltage) { - case MMC_SIGNAL_VOLTAGE_330: - pin_state =3D priv->pins_default; - break; - case MMC_SIGNAL_VOLTAGE_180: - pin_state =3D priv->pins_uhs; - break; - default: - return -EINVAL; - } - - /* - * If anything is missing, assume signal voltage is fixed at - * 3.3V and succeed/fail accordingly. - */ - if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state)) - return ios->signal_voltage =3D=3D - MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL; - - ret =3D mmc_regulator_set_vqmmc(host->mmc, ios); - if (ret < 0) - return ret; - - return pinctrl_select_state(priv->pinctrl, pin_state); -} - /* SCC registers */ #define SH_MOBILE_SDHI_SCC_DTCNTL 0x000 #define SH_MOBILE_SDHI_SCC_TAPSET 0x002 @@ -351,6 +317,55 @@ static inline void sd_scc_write32(struct tmio_mmc_host= *host, writel(val, priv->scc_ctl + (addr << host->bus_shift)); } =20 +static void renesas_sdhi_set_hw_adjustment_delay(struct tmio_mmc_host *hos= t) +{ + struct renesas_sdhi *priv =3D host_to_priv(host); + + if (!priv->info->tuning_delay) + return; + + if (host->mmc->ios.signal_voltage =3D=3D MMC_SIGNAL_VOLTAGE_330) + sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 0x0); + else + sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 0x1); +} + +static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc, + struct mmc_ios *ios) +{ + struct tmio_mmc_host *host =3D mmc_priv(mmc); + struct renesas_sdhi *priv =3D host_to_priv(host); + struct pinctrl_state *pin_state; + int ret; + + switch (ios->signal_voltage) { + case MMC_SIGNAL_VOLTAGE_330: + pin_state =3D priv->pins_default; + break; + case MMC_SIGNAL_VOLTAGE_180: + pin_state =3D priv->pins_uhs; + break; + default: + return -EINVAL; + } + + /* + * If anything is missing, assume signal voltage is fixed at + * 3.3V and succeed/fail accordingly. + */ + if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state)) + return ios->signal_voltage =3D=3D + MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL; + + ret =3D mmc_regulator_set_vqmmc(host->mmc, ios); + if (ret < 0) + return ret; + + renesas_sdhi_set_hw_adjustment_delay(host); + + return pinctrl_select_state(priv->pinctrl, pin_state); +} + static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host) { struct renesas_sdhi *priv; diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/ho= st/renesas_sdhi_internal_dmac.c index 84b1b38ca465..d056c3586e6f 100644 --- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c +++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c @@ -237,6 +237,12 @@ static const struct renesas_sdhi_hw_info sdhi_hw_info_= generic =3D { .max_divider =3D 512, }; =20 +static const struct renesas_sdhi_hw_info sdhi_hw_info_rzg2l =3D { + .clk_mask =3D 0x80000080, + .max_divider =3D 512, + .tuning_delay =3D 1, +}; + static const struct renesas_sdhi_of_data_with_quirks of_r8a7795_compatible= =3D { .of_data =3D &of_data_rcar_gen3, .quirks =3D &sdhi_quirks_bad_taps2367, @@ -270,7 +276,7 @@ static const struct renesas_sdhi_of_data_with_quirks of= _r8a77990_compatible =3D { static const struct renesas_sdhi_of_data_with_quirks of_rzg2l_compatible = =3D { .of_data =3D &of_data_rcar_gen3, .quirks =3D &sdhi_quirks_rzg2l, - .info =3D &sdhi_hw_info_generic, + .info =3D &sdhi_hw_info_rzg2l, }; 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Tue, 02 Jun 2026 23:57:44 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Wolfram Sang , Ulf Hansson Cc: Biju Das , linux-mmc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v17 09/17] mmc: renesas_sdhi: Add internal_divider hw_info flag for clk rate adjustment Date: Wed, 3 Jun 2026 07:57:09 +0100 Message-ID: <20260603065731.93243-10-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260603065731.93243-1-biju.das.jz@bp.renesas.com> References: <20260603065731.93243-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The RZ/G3L SoC has an internal divider for all modes except HS400 mode. Add an internal_divider bitfield to renesas_sdhi_hw_info and a divider field to the renesas_sdhi instance struct. During probe, if internal_divider is set and the device does not have the mmc-hs400-1_8v property, priv->divider is set to 2; otherwise it defaults to 1. This divider is then applied in renesas_sdhi_clk_update() when setting the clk rate relative to clkh, replacing the implicit divide-by-1 that was previously assumed. No users set internal_divider yet; this patch only introduces the infrastructure. No functional change for existing platforms. Signed-off-by: Biju Das --- v1->v2: * No change. --- drivers/mmc/host/renesas_sdhi.h | 3 +++ drivers/mmc/host/renesas_sdhi_core.c | 7 ++++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/renesas_sdhi.h b/drivers/mmc/host/renesas_sdh= i.h index a3c5fa368242..0ca8ec27c320 100644 --- a/drivers/mmc/host/renesas_sdhi.h +++ b/drivers/mmc/host/renesas_sdhi.h @@ -46,6 +46,7 @@ struct renesas_sdhi_hw_info { unsigned int max_divider; /* hardware features */ unsigned tuning_delay:1; /* Has tuning delay */ + unsigned internal_divider:1; /* Has internal divider */ }; =20 struct renesas_sdhi_of_data_with_info { @@ -112,6 +113,8 @@ struct renesas_sdhi { struct reset_control *rstc; struct tmio_mmc_host *host; struct regulator_dev *rdev; + + unsigned int divider; }; =20 #define host_to_priv(host) \ diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesa= s_sdhi_core.c index 868ba6a6919e..8e2fb19b994b 100644 --- a/drivers/mmc/host/renesas_sdhi_core.c +++ b/drivers/mmc/host/renesas_sdhi_core.c @@ -185,7 +185,7 @@ static unsigned int renesas_sdhi_clk_update(struct tmio= _mmc_host *host, clk_set_rate(ref_clk, best_freq); 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Tue, 02 Jun 2026 23:57:45 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a700:7301:179c:89ab:19f6:9ba4]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-490b79d90bdsm9001855e9.0.2026.06.02.23.57.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 23:57:45 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Wolfram Sang , Ulf Hansson , Philipp Zabel Cc: Biju Das , linux-mmc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v17 10/17] mmc: renesas_sdhi: Add optional axis/axim reset controls Date: Wed, 3 Jun 2026 07:57:10 +0100 Message-ID: <20260603065731.93243-11-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260603065731.93243-1-biju.das.jz@bp.renesas.com> References: <20260603065731.93243-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The RZ/G3L SoC has axis/axim resets compared to other SoCs. Add two optional reset controls, rstc_axis and rstc_axim, to the renesas_sdhi struct. Both are acquired at probe time using devm_reset_control_get_optional_exclusive_deasserted() with the "axis" and "axim" reset names respectively. Include them alongside the existing rstc in bulk reset/assert/deassert operations: triggered together in renesas_sdhi_reset(), and managed via reset_control_bulk_assert/deassert() in the suspend and resume paths, replacing the previous single-control calls. Being optional, these resets are a no-op on platforms that do not provide them, so existing behaviour is preserved. Signed-off-by: Biju Das --- v1->v2: * No change. --- drivers/mmc/host/renesas_sdhi.h | 2 ++ drivers/mmc/host/renesas_sdhi_core.c | 26 +++++++++++++++++++++++--- 2 files changed, 25 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/renesas_sdhi.h b/drivers/mmc/host/renesas_sdh= i.h index 0ca8ec27c320..6c024e7f69e1 100644 --- a/drivers/mmc/host/renesas_sdhi.h +++ b/drivers/mmc/host/renesas_sdhi.h @@ -111,6 +111,8 @@ struct renesas_sdhi { unsigned int tap_set; =20 struct reset_control *rstc; + struct reset_control *rstc_axis; + struct reset_control *rstc_axim; struct tmio_mmc_host *host; struct regulator_dev *rdev; =20 diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesa= s_sdhi_core.c index 8e2fb19b994b..699872766f88 100644 --- a/drivers/mmc/host/renesas_sdhi_core.c +++ b/drivers/mmc/host/renesas_sdhi_core.c @@ -615,6 +615,8 @@ static void renesas_sdhi_reset(struct tmio_mmc_host *ho= st, bool preserve) sd_status =3D sd_ctrl_read32(host, CTL_SD_STATUS); =20 reset_control_reset(priv->rstc); + reset_control_reset(priv->rstc_axis); + reset_control_reset(priv->rstc_axim); /* Unknown why but without polling reset status, it will hang */ read_poll_timeout(reset_control_status, ret, ret =3D=3D 0, 1, 100, false, priv->rstc); @@ -1128,6 +1130,14 @@ int renesas_sdhi_probe(struct platform_device *pdev, if (IS_ERR(priv->rstc)) return PTR_ERR(priv->rstc); =20 + priv->rstc_axim =3D devm_reset_control_get_optional_exclusive_deasserted(= &pdev->dev, "axim"); + if (IS_ERR(priv->rstc_axim)) + return PTR_ERR(priv->rstc_axim); + + priv->rstc_axis =3D devm_reset_control_get_optional_exclusive_deasserted(= &pdev->dev, "axis"); + if (IS_ERR(priv->rstc_axis)) + return PTR_ERR(priv->rstc_axis); + priv->pinctrl =3D devm_pinctrl_get(&pdev->dev); if (!IS_ERR(priv->pinctrl)) { priv->pins_default =3D pinctrl_lookup_state(priv->pinctrl, @@ -1351,13 +1361,18 @@ int renesas_sdhi_suspend(struct device *dev) { struct tmio_mmc_host *host =3D dev_get_drvdata(dev); struct renesas_sdhi *priv =3D host_to_priv(host); + struct reset_control_bulk_data resets[] =3D { + { .rstc =3D priv->rstc }, + { .rstc =3D priv->rstc_axim }, + { .rstc =3D priv->rstc_axis }, + }; int ret; =20 ret =3D pm_runtime_force_suspend(dev); if (ret) return ret; =20 - ret =3D reset_control_assert(priv->rstc); + ret =3D reset_control_bulk_assert(ARRAY_SIZE(resets), resets); if (ret) pm_runtime_force_resume(dev); =20 @@ -1369,15 +1384,20 @@ int renesas_sdhi_resume(struct device *dev) { struct tmio_mmc_host *host =3D dev_get_drvdata(dev); struct renesas_sdhi *priv =3D host_to_priv(host); + struct reset_control_bulk_data resets[] =3D { + { .rstc =3D priv->rstc }, + { .rstc =3D priv->rstc_axim }, + { .rstc =3D priv->rstc_axis }, + }; int ret; =20 - ret =3D reset_control_deassert(priv->rstc); + ret =3D reset_control_bulk_deassert(ARRAY_SIZE(resets), resets); if (ret) return ret; =20 ret =3D pm_runtime_force_resume(dev); if (ret) - reset_control_assert(priv->rstc); + reset_control_bulk_assert(ARRAY_SIZE(resets), resets); =20 return ret; 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Tue, 02 Jun 2026 23:57:46 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Wolfram Sang , Ulf Hansson Cc: Biju Das , linux-mmc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v17 11/17] mmc: renesas_sdhi: Add RZ/G3L SDHI support Date: Wed, 3 Jun 2026 07:57:11 +0100 Message-ID: <20260603065731.93243-12-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260603065731.93243-1-biju.das.jz@bp.renesas.com> References: <20260603065731.93243-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add support for the RZ/G3L (r9a08g046) SDHI controller, which has a new hardware version register and also has different tuning registers, internal clk divider, 11 bit divider, 3 resets and 5 clocks compared to other SoCs. Similar to RZ/G2L SoCs it need tuning delay. Signed-off-by: Biju Das --- v1->v2: * No change. --- drivers/mmc/host/renesas_sdhi_core.c | 23 +++++++--- drivers/mmc/host/renesas_sdhi_internal_dmac.c | 42 +++++++++++++++++++ 2 files changed, 59 insertions(+), 6 deletions(-) diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesa= s_sdhi_core.c index 699872766f88..ee1b1f70c9e3 100644 --- a/drivers/mmc/host/renesas_sdhi_core.c +++ b/drivers/mmc/host/renesas_sdhi_core.c @@ -59,6 +59,7 @@ #define SDHI_VER_GEN2_SDR104 0xcb0d #define SDHI_VER_GEN3_SD 0xcc10 #define SDHI_VER_GEN3_SDMMC 0xcd10 +#define SDHI_VER_RZ_G3L_SDMMC 0xce10 =20 #define SDHI_GEN3_MMC0_ADDR 0xee140000 =20 @@ -79,6 +80,7 @@ static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host= *host, int width) break; case SDHI_VER_GEN3_SD: case SDHI_VER_GEN3_SDMMC: + case SDHI_VER_RZ_G3L_SDMMC: if (width =3D=3D 64) val =3D HOST_MODE_GEN3_64BIT; else if (width =3D=3D 32) @@ -205,7 +207,8 @@ static void renesas_sdhi_set_clock(struct tmio_mmc_host= *host, goto out; } =20 - host->mmc->actual_clock =3D renesas_sdhi_clk_update(host, new_clock); + host->mmc->actual_clock =3D renesas_sdhi_clk_update(host, new_clock) / + (priv->info->internal_divider ? 2 : 1); clock =3D host->mmc->actual_clock / priv->info->max_divider; =20 /* @@ -265,12 +268,14 @@ static int renesas_sdhi_card_busy(struct mmc_host *mm= c) #define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008 #define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A #define SH_MOBILE_SDHI_SCC_SMPCMP 0x00C -#define SH_MOBILE_SDHI_SCC_TMPPORT2 0x00E +#define SH_MOBILE_SDHI_SCC_TMPPORT2 0x00E /* G3L: SDm_SCC_HS400MODE1 */ +#define RZG3L_SDHI_SCC_HWADJ2 0x010 #define SH_MOBILE_SDHI_SCC_TMPPORT3 0x014 -#define SH_MOBILE_SDHI_SCC_TMPPORT4 0x016 -#define SH_MOBILE_SDHI_SCC_TMPPORT5 0x018 -#define SH_MOBILE_SDHI_SCC_TMPPORT6 0x01A -#define SH_MOBILE_SDHI_SCC_TMPPORT7 0x01C +#define SH_MOBILE_SDHI_SCC_TMPPORT4 0x016 /* R-Car */ +#define SH_MOBILE_SDHI_SCC_TMPPORT5 0x018 /* R-Car */ +#define SH_MOBILE_SDHI_SCC_TMPPORT6 0x01A /* R-Car */ +#define SH_MOBILE_SDHI_SCC_TMPPORT7 0x01C /* R-Car */ +#define RZG3L_SDHI_SCC_HWADJ4 0x022 =20 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0) #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16 @@ -393,6 +398,9 @@ static unsigned int renesas_sdhi_init_tuning(struct tmi= o_mmc_host *host) =20 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); =20 + if (priv->info->internal_divider) + sd_scc_write32(host, priv, RZG3L_SDHI_SCC_HWADJ4, 0x0); + sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); =20 @@ -727,6 +735,9 @@ static int renesas_sdhi_execute_tuning(struct mmc_host = *mmc, u32 opcode) if (!priv->tap_num) return 0; /* Tuning is not supported */ =20 + if (priv->info->tuning_delay && priv->tap_num =3D=3D 8) + sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 0x0); + if (priv->tap_num * 2 >=3D sizeof(priv->taps) * BITS_PER_BYTE) { dev_err(&host->pdev->dev, "Too many taps, please update 'taps' in tmio_mmc_host!\n"); diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/ho= st/renesas_sdhi_internal_dmac.c index d056c3586e6f..fb8a70d28eed 100644 --- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c +++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c @@ -89,6 +89,13 @@ static struct renesas_sdhi_scc rcar_gen3_scc_taps[] =3D { }, }; =20 +static struct renesas_sdhi_scc rzg3l_scc_taps[] =3D { + { + .clk_rate =3D 0, + .tap =3D 0x00000300, + }, +}; + static const struct renesas_sdhi_of_data of_data_rza2 =3D { .tmio_flags =3D TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | TMIO_MMC_HAVE_CBSY, @@ -104,6 +111,23 @@ static const struct renesas_sdhi_of_data of_data_rza2 = =3D { .max_segs =3D 1, }; =20 +static const struct renesas_sdhi_of_data of_data_rzg3l =3D { + .tmio_flags =3D TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | + TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2 | + TMIO_MMC_64BIT_DATA_PORT, + .capabilities =3D MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | + MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY, + .capabilities2 =3D MMC_CAP2_NO_WRITE_PROTECT | MMC_CAP2_MERGE_CAPABLE, + .bus_shift =3D 2, + .scc_offset =3D 0x1000, + .taps =3D rzg3l_scc_taps, + .taps_num =3D ARRAY_SIZE(rzg3l_scc_taps), + /* DMAC can handle 32bit blk count but only 1 segment */ + .max_blk_count =3D UINT_MAX / TMIO_MAX_BLK_SIZE, + .max_segs =3D 1, + .sdhi_flags =3D SDHI_FLAG_NEED_CLKH_FALLBACK, +}; + static const struct renesas_sdhi_of_data of_data_rcar_gen3 =3D { .tmio_flags =3D TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2 | @@ -217,6 +241,10 @@ static const struct renesas_sdhi_quirks sdhi_quirks_rz= g2l =3D { .hs400_disabled =3D true, }; =20 +static const struct renesas_sdhi_quirks sdhi_quirks_rzg3l =3D { + .fixed_addr_mode =3D true, +}; + /* * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of n= ow. * So, we want to treat them equally and only have a match for ES1.2 to en= force @@ -243,6 +271,13 @@ static const struct renesas_sdhi_hw_info sdhi_hw_info_= rzg2l =3D { .tuning_delay =3D 1, }; =20 +static const struct renesas_sdhi_hw_info sdhi_hw_info_rzg3l =3D { + .clk_mask =3D 0x200000200, + .max_divider =3D 2048, + .tuning_delay =3D 1, + .internal_divider =3D 1, +}; + static const struct renesas_sdhi_of_data_with_quirks of_r8a7795_compatible= =3D { .of_data =3D &of_data_rcar_gen3, .quirks =3D &sdhi_quirks_bad_taps2367, @@ -296,6 +331,12 @@ static const struct renesas_sdhi_of_data_with_quirks o= f_rza2_compatible =3D { .info =3D &sdhi_hw_info_generic, }; =20 +static const struct renesas_sdhi_of_data_with_quirks of_rzg3l_compatible = =3D { + .of_data =3D &of_data_rzg3l, + .quirks =3D &sdhi_quirks_rzg3l, + .info =3D &sdhi_hw_info_rzg3l, +}; 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Tue, 02 Jun 2026 23:57:47 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a700:7301:179c:89ab:19f6:9ba4]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-490b79d90bdsm9001855e9.0.2026.06.02.23.57.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 23:57:47 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Wolfram Sang , Ulf Hansson Cc: Biju Das , linux-mmc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v17 12/17] mmc: renesas_sdhi: Save and restore IOVS across suspend/resume Date: Wed, 3 Jun 2026 07:57:12 +0100 Message-ID: <20260603065731.93243-13-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260603065731.93243-1-biju.das.jz@bp.renesas.com> References: <20260603065731.93243-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The SD_STATUS register, specifically the IOVS (I/O Voltage Switch) bit, is not automatically restored after a suspend/resume cycle, causing the regulator to report an incorrect voltage on resume. Fix this by caching the CTL_SD_STATUS register value in the renesas_sdhi private struct at suspend time and writing it back during resume. The save/restore is only performed when a regulator device (rdev) is present, as the IOVS bit is only relevant in that context. Signed-off-by: Biju Das --- v1->v2: * No change. --- drivers/mmc/host/renesas_sdhi.h | 1 + drivers/mmc/host/renesas_sdhi_core.c | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/drivers/mmc/host/renesas_sdhi.h b/drivers/mmc/host/renesas_sdh= i.h index 6c024e7f69e1..10f634349da9 100644 --- a/drivers/mmc/host/renesas_sdhi.h +++ b/drivers/mmc/host/renesas_sdhi.h @@ -117,6 +117,7 @@ struct renesas_sdhi { struct regulator_dev *rdev; =20 unsigned int divider; + u32 cache_sd_status; }; =20 #define host_to_priv(host) \ diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesa= s_sdhi_core.c index ee1b1f70c9e3..974acdf110d3 100644 --- a/drivers/mmc/host/renesas_sdhi_core.c +++ b/drivers/mmc/host/renesas_sdhi_core.c @@ -1379,6 +1379,9 @@ int renesas_sdhi_suspend(struct device *dev) }; int ret; =20 + if (priv->rdev) + priv->cache_sd_status =3D sd_ctrl_read32(host, CTL_SD_STATUS); + ret =3D pm_runtime_force_suspend(dev); if (ret) return ret; @@ -1410,6 +1413,9 @@ int renesas_sdhi_resume(struct device *dev) if (ret) reset_control_bulk_assert(ARRAY_SIZE(resets), resets); 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Tue, 02 Jun 2026 23:57:48 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Wolfram Sang , Ulf Hansson Cc: Biju Das , linux-mmc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v17 13/17] mmc: renesas_sdhi: Add RZ/G3L HS400 support Date: Wed, 3 Jun 2026 07:57:13 +0100 Message-ID: <20260603065731.93243-14-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260603065731.93243-1-biju.das.jz@bp.renesas.com> References: <20260603065731.93243-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add HS400 support for RZ/G3L SoC. Signed-off-by: Biju Das --- v1->v2: * No change. --- drivers/mmc/host/renesas_sdhi.h | 1 + drivers/mmc/host/renesas_sdhi_core.c | 17 +++++++++++++++-- drivers/mmc/host/renesas_sdhi_internal_dmac.c | 1 + 3 files changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/renesas_sdhi.h b/drivers/mmc/host/renesas_sdh= i.h index 10f634349da9..92b66116f044 100644 --- a/drivers/mmc/host/renesas_sdhi.h +++ b/drivers/mmc/host/renesas_sdhi.h @@ -47,6 +47,7 @@ struct renesas_sdhi_hw_info { /* hardware features */ unsigned tuning_delay:1; /* Has tuning delay */ unsigned internal_divider:1; /* Has internal divider */ + unsigned scc_hs400_mode2:1; /* Has scc hs400 mode2 */ }; =20 struct renesas_sdhi_of_data_with_info { diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesa= s_sdhi_core.c index 974acdf110d3..282107d06114 100644 --- a/drivers/mmc/host/renesas_sdhi_core.c +++ b/drivers/mmc/host/renesas_sdhi_core.c @@ -186,8 +186,12 @@ static unsigned int renesas_sdhi_clk_update(struct tmi= o_mmc_host *host, =20 clk_set_rate(ref_clk, best_freq); =20 - if (priv->clkh) + if (priv->clkh) { + if (priv->info->internal_divider && host->mmc->ios.timing =3D=3D MMC_TIM= ING_MMC_HS400) + clkh_shift =3D 1; + clk_set_rate(priv->clk, (best_freq >> clkh_shift) * priv->divider); + } =20 return clk_get_rate(priv->clk); } @@ -229,7 +233,7 @@ static void renesas_sdhi_set_clock(struct tmio_mmc_host= *host, } =20 clock =3D clk & CLK_CTL_DIV_MASK; - if (clock !=3D CLK_CTL_DIV_MASK) + if (clock !=3D CLK_CTL_DIV_MASK && clock !=3D 0) host->mmc->actual_clock /=3D (1 << (ffs(clock) + 1)); =20 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clock); @@ -275,6 +279,7 @@ static int renesas_sdhi_card_busy(struct mmc_host *mmc) #define SH_MOBILE_SDHI_SCC_TMPPORT5 0x018 /* R-Car */ #define SH_MOBILE_SDHI_SCC_TMPPORT6 0x01A /* R-Car */ #define SH_MOBILE_SDHI_SCC_TMPPORT7 0x01C /* R-Car */ +#define RZG3L_SDHI_SCC_HS400MODE2 0x020 #define RZG3L_SDHI_SCC_HWADJ4 0x022 =20 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0) @@ -308,6 +313,7 @@ static int renesas_sdhi_card_busy(struct mmc_host *mmc) #define SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE 0xa5000000 #define SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK 0x1f #define SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE BIT(7) +#define RZG3L_SDHI_SCC_HS400MODE2_HS400EN2 BIT(0) =20 static inline u32 sd_scc_read32(struct tmio_mmc_host *host, struct renesas_sdhi *priv, int addr) @@ -437,6 +443,10 @@ static void renesas_sdhi_hs400_complete(struct mmc_hos= t *mmc) SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) | sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); =20 + if (priv->info->scc_hs400_mode2) + sd_scc_write32(host, priv, RZG3L_SDHI_SCC_HS400MODE2, + RZG3L_SDHI_SCC_HS400MODE2_HS400EN2); + sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | sd_scc_read32(host, priv, @@ -578,6 +588,9 @@ static void renesas_sdhi_reset_hs400_mode(struct tmio_m= mc_host *host, SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) & sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); =20 + if (priv->info->scc_hs400_mode2) + sd_scc_write32(host, priv, RZG3L_SDHI_SCC_HS400MODE2, 0x0); + if (sdhi_has_quirk(priv, hs400_calib_table) || sdhi_has_quirk(priv, hs400= _bad_taps)) renesas_sdhi_adjust_hs400_mode_disable(host); =20 diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/ho= st/renesas_sdhi_internal_dmac.c index fb8a70d28eed..83d348fb5eeb 100644 --- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c +++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c @@ -276,6 +276,7 @@ static const struct renesas_sdhi_hw_info sdhi_hw_info_r= zg3l =3D { .max_divider =3D 2048, .tuning_delay =3D 1, .internal_divider =3D 1, + .scc_hs400_mode2 =3D 1, }; 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Tue, 02 Jun 2026 23:57:49 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Wolfram Sang , Ulf Hansson Cc: Biju Das , linux-mmc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v17 14/17] mmc: renesas_sdhi: Add HS400 enhanced strobe support for RZ/G3L Date: Wed, 3 Jun 2026 07:57:14 +0100 Message-ID: <20260603065731.93243-15-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260603065731.93243-1-biju.das.jz@bp.renesas.com> References: <20260603065731.93243-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add an hs400_es bitfield to renesas_sdhi_hw_info and implement renesas_sdhi_hs400_enhanced_strobe(), registered as host->ops.hs400_enhanced_strobe for all SCC-capable controllers. Signed-off-by: Biju Das --- v1->v2: * No change. --- drivers/mmc/host/renesas_sdhi.h | 1 + drivers/mmc/host/renesas_sdhi_core.c | 53 ++++++++++++++++--- drivers/mmc/host/renesas_sdhi_internal_dmac.c | 1 + 3 files changed, 49 insertions(+), 6 deletions(-) diff --git a/drivers/mmc/host/renesas_sdhi.h b/drivers/mmc/host/renesas_sdh= i.h index 92b66116f044..1a837d0c9479 100644 --- a/drivers/mmc/host/renesas_sdhi.h +++ b/drivers/mmc/host/renesas_sdhi.h @@ -48,6 +48,7 @@ struct renesas_sdhi_hw_info { unsigned tuning_delay:1; /* Has tuning delay */ unsigned internal_divider:1; /* Has internal divider */ unsigned scc_hs400_mode2:1; /* Has scc hs400 mode2 */ + unsigned hs400_es:1; /* Has hs400 enhanced strobe */ }; =20 struct renesas_sdhi_of_data_with_info { diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesa= s_sdhi_core.c index 282107d06114..2a70a2e64b9c 100644 --- a/drivers/mmc/host/renesas_sdhi_core.c +++ b/drivers/mmc/host/renesas_sdhi_core.c @@ -274,7 +274,7 @@ static int renesas_sdhi_card_busy(struct mmc_host *mmc) #define SH_MOBILE_SDHI_SCC_SMPCMP 0x00C #define SH_MOBILE_SDHI_SCC_TMPPORT2 0x00E /* G3L: SDm_SCC_HS400MODE1 */ #define RZG3L_SDHI_SCC_HWADJ2 0x010 -#define SH_MOBILE_SDHI_SCC_TMPPORT3 0x014 +#define SH_MOBILE_SDHI_SCC_TMPPORT3 0x014 /* G3L: SDm_SCC_HWADJ3 */ #define SH_MOBILE_SDHI_SCC_TMPPORT4 0x016 /* R-Car */ #define SH_MOBILE_SDHI_SCC_TMPPORT5 0x018 /* R-Car */ #define SH_MOBILE_SDHI_SCC_TMPPORT6 0x01A /* R-Car */ @@ -298,8 +298,9 @@ static int renesas_sdhi_card_busy(struct mmc_host *mmc) #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24) #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR (BIT(8) | BIT(24)) =20 -#define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4) -#define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31) +#define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4) +#define SH_MOBILE_SDHI_SCC_HS400MODE1_ENHANCED_STROBE BIT(30) +#define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31) =20 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT4 register */ #define SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0) @@ -574,6 +575,8 @@ static void renesas_sdhi_adjust_hs400_mode_disable(stru= ct tmio_mmc_host *host) static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host, struct renesas_sdhi *priv) { + unsigned long val; + sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); =20 @@ -583,10 +586,12 @@ static void renesas_sdhi_reset_hs400_mode(struct tmio= _mmc_host *host, =20 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); =20 + val =3D ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | SH_MOBILE_SDHI_SCC_TMPPOR= T2_HS400OSEL); + if (priv->info->hs400_es) + val &=3D ~SH_MOBILE_SDHI_SCC_HS400MODE1_ENHANCED_STROBE; + sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, - ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | - SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) & - sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); + val & sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); =20 if (priv->info->scc_hs400_mode2) sd_scc_write32(host, priv, RZG3L_SDHI_SCC_HS400MODE2, 0x0); @@ -783,6 +788,41 @@ static int renesas_sdhi_execute_tuning(struct mmc_host= *mmc, u32 opcode) return ret; } =20 +static void renesas_sdhi_hs400_enhanced_strobe(struct mmc_host *mmc, + struct mmc_ios *ios) +{ + struct tmio_mmc_host *host =3D mmc_priv(mmc); + struct renesas_sdhi *priv =3D host_to_priv(host); + u32 val =3D sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2); + + if (!priv->info->hs400_es) + return; + + if (ios->enhanced_strobe) { + sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, + ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL & + sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); + + sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, + ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN & + sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL)); + + sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, BIT(8) | BIT(9)); + sd_scc_write32(host, priv, RZG3L_SDHI_SCC_HWADJ2, 0xFF); + sd_ctrl_write16(host, CTL_SDIF_MODE, SDIF_MODE_HS400 | + sd_ctrl_read16(host, CTL_SDIF_MODE)); + sd_scc_write32(host, priv, RZG3L_SDHI_SCC_HS400MODE2, + RZG3L_SDHI_SCC_HS400MODE2_HS400EN2); + + val |=3D SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | + SH_MOBILE_SDHI_SCC_HS400MODE1_ENHANCED_STROBE; + } else { + val &=3D ~SH_MOBILE_SDHI_SCC_HS400MODE1_ENHANCED_STROBE; + } + + sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, val); +} + static bool renesas_sdhi_manual_correction(struct tmio_mmc_host *host, boo= l use_4tap) { struct renesas_sdhi *priv =3D host_to_priv(host); @@ -1333,6 +1373,7 @@ int renesas_sdhi_probe(struct platform_device *pdev, host->ops.prepare_hs400_tuning =3D renesas_sdhi_prepare_hs400_tuning; host->ops.hs400_downgrade =3D renesas_sdhi_disable_scc; host->ops.hs400_complete =3D renesas_sdhi_hs400_complete; + host->ops.hs400_enhanced_strobe =3D renesas_sdhi_hs400_enhanced_strobe; } =20 sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, host->sdcard_irq_mask_al= l); diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/ho= st/renesas_sdhi_internal_dmac.c index 83d348fb5eeb..a021ebb46070 100644 --- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c +++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c @@ -277,6 +277,7 @@ static const struct renesas_sdhi_hw_info sdhi_hw_info_r= zg3l =3D { .tuning_delay =3D 1, .internal_divider =3D 1, .scc_hs400_mode2 =3D 1, + .hs400_es =3D 1, }; =20 static const struct renesas_sdhi_of_data_with_quirks of_r8a7795_compatible= =3D { --=20 2.43.0 From nobody Mon Jun 8 06:38:26 2026 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 45AE93FF884 for ; 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Tue, 02 Jun 2026 23:57:50 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a700:7301:179c:89ab:19f6:9ba4]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-490b79d90bdsm9001855e9.0.2026.06.02.23.57.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 23:57:50 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v17 15/17] arm64: dts: renesas: r9a08g046: Add SDHI nodes for RZ/G3L SoC and SDHI1 pincontrol on SMARC EVK Date: Wed, 3 Jun 2026 07:57:15 +0100 Message-ID: <20260603065731.93243-16-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260603065731.93243-1-biju.das.jz@bp.renesas.com> References: <20260603065731.93243-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add device tree nodes for the three SDHI controllers (SDHI{0,1,2}) on the RZ/G3L SoC (r9a08g046) and enable SDHI1 on the RZ/G3L SMARC EVK platform with pincontrol and GPIO-based voltage switching regulator support. Signed-off-by: Biju Das --- v1->v2: * No change. --- arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 73 ++++++++++++++- .../boot/dts/renesas/r9a08g046l48-smarc.dts | 88 +++++++++++++++++++ 2 files changed, 160 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/d= ts/renesas/r9a08g046.dtsi index c63a857f0e5b..ff2de3f192b5 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi @@ -762,9 +762,80 @@ dmac: dma-controller@11820000 { dma-channels =3D <16>; }; =20 + sdhi0: mmc@11c00000 { + compatible =3D "renesas,sdhi-r9a08g046"; + reg =3D <0x0 0x11c00000 0 0x10000>; + interrupts =3D , + ; + clocks =3D <&cpg CPG_MOD R9A08G046_SDHI0_IMCLK>, + <&cpg CPG_MOD R9A08G046_SDHI0_CLK_HS>, + <&cpg CPG_MOD R9A08G046_SDHI0_IMCLK2>, + <&cpg CPG_MOD R9A08G046_SDHI0_IACLKS>, + <&cpg CPG_MOD R9A08G046_SDHI0_IACLKM>; + clock-names =3D "core", "clkh", "cd", "aclk", "aclkm"; + max-frequency =3D <150000000>; + resets =3D <&cpg R9A08G046_SDHI0_IXRST>, + <&cpg R9A08G046_SDHI0_IXRSTAXIM>, + <&cpg R9A08G046_SDHI0_IXRSTAXIS>; + reset-names =3D "rst", "axim", "axis"; + power-domains =3D <&cpg>; + status =3D "disabled"; + }; + sdhi1: mmc@11c10000 { + compatible =3D "renesas,sdhi-r9a08g046"; reg =3D <0x0 0x11c10000 0 0x10000>; - /* placeholder */ + interrupts =3D , + ; + clocks =3D <&cpg CPG_MOD R9A08G046_SDHI1_IMCLK>, + <&cpg CPG_MOD R9A08G046_SDHI1_CLK_HS>, + <&cpg CPG_MOD R9A08G046_SDHI1_IMCLK2>, + <&cpg CPG_MOD R9A08G046_SDHI1_IACLKS>, + <&cpg CPG_MOD R9A08G046_SDHI1_IACLKM>; + clock-names =3D "core", "clkh", "cd", "aclk", "aclkm"; + max-frequency =3D <150000000>; + resets =3D <&cpg R9A08G046_SDHI1_IXRST>, + <&cpg R9A08G046_SDHI1_IXRSTAXIM>, + <&cpg R9A08G046_SDHI1_IXRSTAXIS>; + reset-names =3D "rst", "axim", "axis"; + power-domains =3D <&cpg>; + status =3D "disabled"; + + sdhi1_vqmmc: vqmmc-regulator { + regulator-name =3D "SDHI1-VQMMC"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-ramp-delay =3D <1200>; + status =3D "disabled"; + }; + }; + + sdhi2: mmc@11c20000 { + compatible =3D "renesas,sdhi-r9a08g046"; + reg =3D <0x0 0x11c20000 0 0x10000>; + interrupts =3D , + ; + clocks =3D <&cpg CPG_MOD R9A08G046_SDHI2_IMCLK>, + <&cpg CPG_MOD R9A08G046_SDHI2_CLK_HS>, + <&cpg CPG_MOD R9A08G046_SDHI2_IMCLK2>, + <&cpg CPG_MOD R9A08G046_SDHI2_IACLKS>, + <&cpg CPG_MOD R9A08G046_SDHI2_IACLKM>; + clock-names =3D "core", "clkh", "cd", "aclk", "aclkm"; + max-frequency =3D <150000000>; + resets =3D <&cpg R9A08G046_SDHI2_IXRST>, + <&cpg R9A08G046_SDHI2_IXRSTAXIM>, + <&cpg R9A08G046_SDHI2_IXRSTAXIS>; + reset-names =3D "rst", "axim", "axis"; + power-domains =3D <&cpg>; + status =3D "disabled"; + + sdhi2_vqmmc: vqmmc-regulator { + regulator-name =3D "SDHI2-VQMMC"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-ramp-delay =3D <1200>; + status =3D "disabled"; + }; }; =20 eth0: ethernet@11c30000 { diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts b/arch/arm6= 4/boot/dts/renesas/r9a08g046l48-smarc.dts index 624fcaea350f..a4cc07408b3f 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts @@ -14,6 +14,7 @@ #define SW_GPIO4 1 #define SW_I3C_EN 0 #define SW_SER0_PMOD 1 +#define SW_SDIO_M2E 0 =20 #define PMOD_GPIO4 0 #define PMOD_GPIO6 0 @@ -38,6 +39,7 @@ / { aliases { i2c2 =3D &i2c2; i2c3 =3D &i2c3; + mmc1 =3D &sdhi1; serial0 =3D &rsci2; serial1 =3D &rsci3; serial2 =3D &rsci1; @@ -69,6 +71,19 @@ codec_dai: codec { }; }; #endif + +#if RZ_BOOT_MODE3 + vqmmc_sd1_pvdd: regulator-vqmmc-sd1-pvdd { + compatible =3D "regulator-gpio"; + regulator-name =3D "SD1_PVDD"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + gpios =3D <&pinctrl RZG3L_GPIO(J, 1) GPIO_ACTIVE_HIGH>; + gpios-states =3D <0>; + states =3D <3300000 0>, <1800000 1>; + regulator-ramp-delay =3D <1200>; + }; +#endif }; =20 &i2c2 { @@ -175,6 +190,68 @@ scif0_pins: scif0 { power-source =3D <1800>; }; =20 +#if RZ_BOOT_MODE3 + sd1-pwr-en-hog { + gpio-hog; + gpios =3D ; + output-high; + line-name =3D "sd1_pwr_en"; + }; +#endif + + sdhi1_pins: sd1 { + sd1-cd { + pinmux =3D ; /* SD1_CD */ + }; + + sd1-clk { + pinmux =3D ; /* SD1_CLK */ + power-source =3D <3300>; + }; + + sd1-cmd { + pinmux =3D ; /* SD1_CMD */ + input-enable; + power-source =3D <3300>; + bias-pull-up; + }; + + sd1-data { + pinmux =3D , /* SD1_DAT0 */ + , /* SD1_DAT1 */ + , /* SD1_DAT2 */ + ; /* SD1_DAT3 */ + input-enable; + power-source =3D <3300>; + }; + }; + + sdhi1_uhs_pins: sd1-uhs { + sd1-cd { + pinmux =3D ; /* SD1_CD */ + }; + + sd1-clk { + pinmux =3D ; /* SD1_CLK */ + power-source =3D <1800>; + }; + + sd1-cmd { + pinmux =3D ; /* SD1_CMD */ + input-enable; + power-source =3D <1800>; + }; + + sd1-data { + pinmux =3D , /* SD1_DAT0 */ + , /* SD1_DAT1 */ + , /* SD1_DAT2 */ + ; /* SD1_DAT3 */ + input-enable; + power-source =3D <1800>; + }; + }; + ssi0_pins: ssi0 { pinmux =3D , /* SSIF0_RXD */ , /* SSIF0_BCK */ @@ -219,6 +296,17 @@ &scif0 { pinctrl-names =3D "default"; }; =20 +#if RZ_BOOT_MODE3 +&sdhi1 { + pinctrl-0 =3D <&sdhi1_pins>; + pinctrl-1 =3D <&sdhi1_uhs_pins>; + pinctrl-names =3D "default", "state_uhs"; + + vmmc-supply =3D <®_3p3v>; + vqmmc-supply =3D <&vqmmc_sd1_pvdd>; +}; +#endif + #if !SW_SD2_EN &ssi0 { clocks =3D <&cpg CPG_MOD R9A08G046_SSI0_PCLK2>, --=20 2.43.0 From nobody Mon Jun 8 06:38:26 2026 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54A173FFAA7 for ; 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Tue, 02 Jun 2026 23:57:51 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a700:7301:179c:89ab:19f6:9ba4]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-490b79d90bdsm9001855e9.0.2026.06.02.23.57.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 23:57:51 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v17 16/17] arm64: dts: renesas: rzg3l-smarc-som: Enable SD/eMMC on SDHI0 Date: Wed, 3 Jun 2026 07:57:16 +0100 Message-ID: <20260603065731.93243-17-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260603065731.93243-1-biju.das.jz@bp.renesas.com> References: <20260603065731.93243-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add support for enabling SD card or eMMC on SDHI0 on the RZ/G3L SMARC SoM. The selection between SD and eMMC is controlled by the SW_SD0_DEV_SEL macro in the board DTS, which must match the position of switch SYS.1 on the SoM. By default, eMMC is enabled. Signed-off-by: Biju Das --- v1->v2: * No change. --- .../boot/dts/renesas/r9a08g046l48-smarc.dts | 1 + .../boot/dts/renesas/rzg3l-smarc-som.dtsi | 111 ++++++++++++++++++ 2 files changed, 112 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts b/arch/arm6= 4/boot/dts/renesas/r9a08g046l48-smarc.dts index a4cc07408b3f..2f16a2bb6dc8 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts @@ -9,6 +9,7 @@ =20 /* Switch selection settings */ #define RZ_BOOT_MODE3 1 +#define SW_SD0_DEV_SEL 0 #define SW_SD2_EN 0 #define SW_DPI_EN 0 #define SW_GPIO4 1 diff --git a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi b/arch/arm64/= boot/dts/renesas/rzg3l-smarc-som.dtsi index 091a227233cb..446c7780cb30 100644 --- a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi @@ -9,6 +9,10 @@ * Please set the below switch position on the SoM and the corresponding m= acro * on the board DTS: * + * Switch position SYS.1, Macro SW_SD0_DEV_SEL: + * 0 - SD0 is connected to eMMC (default) + * 1 - SD0 is connected to uSD0 card + * * Switch position SYS.2, Macro SW_I3C_EN: * 0 - SMARC_I2C_GP is enabled * 1 - I3C is enabled @@ -37,6 +41,7 @@ aliases { ethernet0 =3D ð0; ethernet1 =3D ð1; i2c0 =3D &i2c0; + mmc0 =3D &sdhi0; }; =20 memory@48000000 { @@ -63,6 +68,19 @@ reg_3p3v: regulator-3p3v { regulator-always-on; }; =20 +#if SW_SD0_DEV_SEL + vqmmc_sd0_pvdd: vqmmc-sd0-pvdd { + compatible =3D "regulator-gpio"; + regulator-name =3D "SD0_PVDD"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + gpios =3D <&pinctrl RZG3L_GPIO(L, 4) GPIO_ACTIVE_HIGH>; + gpios-states =3D <0>; + states =3D <3300000 0>, <1800000 1>; + regulator-ramp-delay =3D <1200>; + }; +#endif + x2_clk: x2-clock { compatible =3D "fixed-clock"; #clock-cells =3D <0>; @@ -216,7 +234,100 @@ i2c0_pins: i2c0 { pinmux =3D , /* RIIC0_SCL */ ; /* RIIC0_SDA */ }; + + sd0-pwr-en-hog { + gpio-hog; + gpios =3D ; + output-high; + line-name =3D "sd0_pwr_en"; + }; + + sdhi0_emmc_pins: sd0-emmc { + sd0-ctrl { + pins =3D "SD0_CLK", "SD0_CMD"; + power-source =3D <1800>; + }; + + sd0-data { + pins =3D "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", + "SD0_DAT4", "SD0_DAT5", "SD0_DAT6", "SD0_DAT7"; + power-source =3D <1800>; + }; + + sd0-rst { + pins =3D "SD0_RST#"; + power-source =3D <1800>; + }; + + sd0-ds { + pins =3D "SD0_DS"; + power-source =3D <1800>; + }; + }; + + sdhi0_usd_pins: sd0-usd { + sd0-cd { + pinmux =3D ; /* SD0_CD */ + }; + + sd0-ctrl { + pins =3D "SD0_CLK", "SD0_CMD"; + power-source =3D <3300>; + }; + + sd0-data { + pins =3D "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3"; + power-source =3D <3300>; + }; + }; + + sdhi0_usd_uhs_pins: sd0-usd-uhs { + sd0-cd { + pinmux =3D ; /* SD0_CD */ + }; + + sd0-ctrl { + pins =3D "SD0_CLK", "SD0_CMD"; + power-source =3D <1800>; + }; + + sd0-data { + pins =3D "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3"; + power-source =3D <1800>; + }; + }; +}; + +#if (SW_SD0_DEV_SEL) +&sdhi0 { + pinctrl-0 =3D <&sdhi0_usd_pins>; + pinctrl-1 =3D <&sdhi0_usd_uhs_pins>; + pinctrl-names =3D "default", "state_uhs"; + + vmmc-supply =3D <®_3p3v>; + vqmmc-supply =3D <&vqmmc_sd0_pvdd>; + bus-width =3D <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status =3D "okay"; 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Tue, 02 Jun 2026 23:57:52 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a700:7301:179c:89ab:19f6:9ba4]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-490b79d90bdsm9001855e9.0.2026.06.02.23.57.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 23:57:52 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v17 17/17] arm64: dts: renesas: rzg3l-smarc-som: Enable SDHI2 Date: Wed, 3 Jun 2026 07:57:17 +0100 Message-ID: <20260603065731.93243-18-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260603065731.93243-1-biju.das.jz@bp.renesas.com> References: <20260603065731.93243-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Enable SDHI2 on the RZ/G3L SMARC EVK platform using the internal voltage regulator for voltage switching. SDHI2 signals are muxed with I2S0; the selection is controlled by the SW_SD2_EN macro in the board DTS, which must match the position of switch SYS.4 on the SoM. By default, I2S0 is enabled. Signed-off-by: Biju Das --- v1->v2: * No change. --- .../boot/dts/renesas/rzg3l-smarc-som.dtsi | 88 +++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi b/arch/arm64/= boot/dts/renesas/rzg3l-smarc-som.dtsi index 446c7780cb30..3d5e6b8489a9 100644 --- a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi @@ -42,6 +42,7 @@ aliases { ethernet1 =3D ð1; i2c0 =3D &i2c0; mmc0 =3D &sdhi0; + mmc2 =3D &sdhi2; }; =20 memory@48000000 { @@ -296,6 +297,74 @@ sd0-data { power-source =3D <1800>; }; }; + + sdhi2_pins: sd2 { + sd2-cd { + pinmux =3D ; /* SD2_CD */ + }; + + sd2-clk { + pinmux =3D ; /* SD2_CLK */ + power-source =3D <3300>; + }; + + sd2-cmd { + pinmux =3D ; /* SD2_CMD */ + input-enable; + power-source =3D <3300>; + }; + + sd2-data { + pinmux =3D , /* SD2_DAT0 */ + , /* SD2_DAT1 */ + , /* SD2_DAT2 */ + ; /* SD2_DAT3 */ + input-enable; + power-source =3D <3300>; + }; + + sd2-iovs { + pinmux =3D ; /* SD2_IOVS */ + }; + + sd2-pwen { + pinmux =3D ; /* SD2_PWEN */ + }; + }; + + sdhi2_pins_uhs: sd2-uhs { + sd2-cd { + pinmux =3D ; /* SD2_CD */ + }; + + sd2-clk { + pinmux =3D ; /* SD2_CLK */ + power-source =3D <1800>; + }; + + sd2-cmd { + pinmux =3D ; /* SD2_CMD */ + input-enable; + power-source =3D <1800>; + }; + + sd2-data { + pinmux =3D , /* SD2_DAT0 */ + , /* SD2_DAT1 */ + , /* SD2_DAT2 */ + ; /* SD2_DAT3 */ + input-enable; + power-source =3D <1800>; + }; + + sd2-iovs { + pinmux =3D ; /* SD2_IOVS */ + }; + + sd2-pwen { + pinmux =3D ; /* SD2_PWEN */ + }; + }; }; =20 #if (SW_SD0_DEV_SEL) @@ -329,6 +398,25 @@ &sdhi0 { }; #endif =20 +#if SW_SD2_EN +&sdhi2 { + pinctrl-0 =3D <&sdhi2_pins>; + pinctrl-1 =3D <&sdhi2_pins_uhs>; + pinctrl-names =3D "default", "state_uhs"; + + vmmc-supply =3D <®_3p3v>; + vqmmc-supply =3D <&sdhi2_vqmmc>; + bus-width =3D <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status =3D "okay"; +}; + +&sdhi2_vqmmc { + status =3D "okay"; +}; +#endif + &wdt0 { timeout-sec =3D <60>; status =3D "okay"; --=20 2.43.0