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([183.91.15.56]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c164f6e294sm8461085ad.6.2026.06.02.20.58.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 20:58:38 -0700 (PDT) From: phucduc.bui@gmail.com To: Heiko Stuebner , Mark Brown , Liam Girdwood Cc: Nicolas Frattaroli , Jaroslav Kysela , Takashi Iwai , linux-sound@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, bui duc phuc Subject: [PATCH 1/3] ASoC: rockchip: rockchip_i2s: Use guard() for spin locks Date: Wed, 3 Jun 2026 10:57:39 +0700 Message-ID: <20260603035741.68893-2-phucduc.bui@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260603035741.68893-1-phucduc.bui@gmail.com> References: <20260603035741.68893-1-phucduc.bui@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: bui duc phuc Clean up the code using guard() for spin locks. Merely code refactoring, and no behavior change. Signed-off-by: bui duc phuc --- NOTE: This patch is compile-tested only. sound/soc/rockchip/rockchip_i2s.c | 160 +++++++++++++++--------------- 1 file changed, 80 insertions(+), 80 deletions(-) diff --git a/sound/soc/rockchip/rockchip_i2s.c b/sound/soc/rockchip/rockchi= p_i2s.c index 0a0a95b4f520..5a5087f4ae03 100644 --- a/sound/soc/rockchip/rockchip_i2s.c +++ b/sound/soc/rockchip/rockchip_i2s.c @@ -127,52 +127,52 @@ static int rockchip_snd_txctrl(struct rk_i2s_dev *i2s= , int on) unsigned int val =3D 0; int ret =3D 0; =20 - spin_lock(&i2s->lock); - if (on) { - ret =3D regmap_update_bits(i2s->regmap, I2S_DMACR, - I2S_DMACR_TDE_ENABLE, - I2S_DMACR_TDE_ENABLE); - if (ret < 0) - goto end; - ret =3D regmap_update_bits(i2s->regmap, I2S_XFER, - I2S_XFER_TXS_START | I2S_XFER_RXS_START, - I2S_XFER_TXS_START | I2S_XFER_RXS_START); - if (ret < 0) - goto end; - i2s->tx_start =3D true; - } else { - i2s->tx_start =3D false; - - ret =3D regmap_update_bits(i2s->regmap, I2S_DMACR, - I2S_DMACR_TDE_ENABLE, - I2S_DMACR_TDE_DISABLE); - if (ret < 0) - goto end; - - if (!i2s->rx_start) { + scoped_guard(spinlock, &i2s->lock) { + if (on) { + ret =3D regmap_update_bits(i2s->regmap, I2S_DMACR, + I2S_DMACR_TDE_ENABLE, + I2S_DMACR_TDE_ENABLE); + if (ret < 0) + break; ret =3D regmap_update_bits(i2s->regmap, I2S_XFER, I2S_XFER_TXS_START | I2S_XFER_RXS_START, - I2S_XFER_TXS_STOP | I2S_XFER_RXS_STOP); + I2S_XFER_TXS_START | I2S_XFER_RXS_START); if (ret < 0) - goto end; - udelay(150); - ret =3D regmap_update_bits(i2s->regmap, I2S_CLR, - I2S_CLR_TXC | I2S_CLR_RXC, - I2S_CLR_TXC | I2S_CLR_RXC); - if (ret < 0) - goto end; - ret =3D regmap_read_poll_timeout_atomic(i2s->regmap, - I2S_CLR, - val, - val =3D=3D 0, - 20, - 200); + break; + i2s->tx_start =3D true; + } else { + i2s->tx_start =3D false; + + ret =3D regmap_update_bits(i2s->regmap, I2S_DMACR, + I2S_DMACR_TDE_ENABLE, + I2S_DMACR_TDE_DISABLE); if (ret < 0) - dev_warn(i2s->dev, "fail to clear: %d\n", ret); + break; + + if (!i2s->rx_start) { + ret =3D regmap_update_bits(i2s->regmap, I2S_XFER, + I2S_XFER_TXS_START | I2S_XFER_RXS_START, + I2S_XFER_TXS_STOP | I2S_XFER_RXS_STOP); + if (ret < 0) + break; + udelay(150); + ret =3D regmap_update_bits(i2s->regmap, I2S_CLR, + I2S_CLR_TXC | I2S_CLR_RXC, + I2S_CLR_TXC | I2S_CLR_RXC); + if (ret < 0) + break; + ret =3D regmap_read_poll_timeout_atomic(i2s->regmap, + I2S_CLR, + val, + val =3D=3D 0, + 20, + 200); + if (ret < 0) + dev_warn(i2s->dev, "fail to clear: %d\n", ret); + } } } -end: - spin_unlock(&i2s->lock); + if (ret < 0) dev_err(i2s->dev, "lrclk update failed\n"); =20 @@ -184,53 +184,53 @@ static int rockchip_snd_rxctrl(struct rk_i2s_dev *i2s= , int on) unsigned int val =3D 0; int ret =3D 0; =20 - spin_lock(&i2s->lock); - if (on) { - ret =3D regmap_update_bits(i2s->regmap, I2S_DMACR, - I2S_DMACR_RDE_ENABLE, - I2S_DMACR_RDE_ENABLE); - if (ret < 0) - goto end; - - ret =3D regmap_update_bits(i2s->regmap, I2S_XFER, - I2S_XFER_TXS_START | I2S_XFER_RXS_START, - I2S_XFER_TXS_START | I2S_XFER_RXS_START); - if (ret < 0) - goto end; - i2s->rx_start =3D true; - } else { - i2s->rx_start =3D false; - - ret =3D regmap_update_bits(i2s->regmap, I2S_DMACR, - I2S_DMACR_RDE_ENABLE, - I2S_DMACR_RDE_DISABLE); - if (ret < 0) - goto end; + scoped_guard(spinlock, &i2s->lock) { + if (on) { + ret =3D regmap_update_bits(i2s->regmap, I2S_DMACR, + I2S_DMACR_RDE_ENABLE, + I2S_DMACR_RDE_ENABLE); + if (ret < 0) + break; =20 - if (!i2s->tx_start) { ret =3D regmap_update_bits(i2s->regmap, I2S_XFER, I2S_XFER_TXS_START | I2S_XFER_RXS_START, - I2S_XFER_TXS_STOP | I2S_XFER_RXS_STOP); + I2S_XFER_TXS_START | I2S_XFER_RXS_START); if (ret < 0) - goto end; - udelay(150); - ret =3D regmap_update_bits(i2s->regmap, I2S_CLR, - I2S_CLR_TXC | I2S_CLR_RXC, - I2S_CLR_TXC | I2S_CLR_RXC); - if (ret < 0) - goto end; - ret =3D regmap_read_poll_timeout_atomic(i2s->regmap, - I2S_CLR, - val, - val =3D=3D 0, - 20, - 200); + break; + i2s->rx_start =3D true; + } else { + i2s->rx_start =3D false; + + ret =3D regmap_update_bits(i2s->regmap, I2S_DMACR, + I2S_DMACR_RDE_ENABLE, + I2S_DMACR_RDE_DISABLE); if (ret < 0) - dev_warn(i2s->dev, "fail to clear: %d\n", ret); + break; + + if (!i2s->tx_start) { + ret =3D regmap_update_bits(i2s->regmap, I2S_XFER, + I2S_XFER_TXS_START | I2S_XFER_RXS_START, + I2S_XFER_TXS_STOP | I2S_XFER_RXS_STOP); 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([183.91.15.56]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c164f6e294sm8461085ad.6.2026.06.02.20.58.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 20:58:43 -0700 (PDT) From: phucduc.bui@gmail.com To: Heiko Stuebner , Mark Brown , Liam Girdwood Cc: Nicolas Frattaroli , Jaroslav Kysela , Takashi Iwai , linux-sound@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, bui duc phuc Subject: [PATCH 2/3] ASoC: rockchip: i2s-tdm: Use guard() for spin locks Date: Wed, 3 Jun 2026 10:57:40 +0700 Message-ID: <20260603035741.68893-3-phucduc.bui@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260603035741.68893-1-phucduc.bui@gmail.com> References: <20260603035741.68893-1-phucduc.bui@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: bui duc phuc Clean up the code using guard() for spin locks. Merely code refactoring, and no behavior change. Signed-off-by: bui duc phuc --- NOTE: This patch is compile-tested only. sound/soc/rockchip/rockchip_i2s_tdm.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/sound/soc/rockchip/rockchip_i2s_tdm.c b/sound/soc/rockchip/roc= kchip_i2s_tdm.c index fc52149ed6ae..3f3db28b8940 100644 --- a/sound/soc/rockchip/rockchip_i2s_tdm.c +++ b/sound/soc/rockchip/rockchip_i2s_tdm.c @@ -285,9 +285,8 @@ static void rockchip_snd_txrxctrl(struct snd_pcm_substr= eam *substream, struct snd_soc_dai *dai, int on) { struct rk_i2s_tdm_dev *i2s_tdm =3D to_info(dai); - unsigned long flags; =20 - spin_lock_irqsave(&i2s_tdm->lock, flags); + guard(spinlock_irqsave)(&i2s_tdm->lock); if (on) { if (substream->stream =3D=3D SNDRV_PCM_STREAM_PLAYBACK) rockchip_enable_tde(i2s_tdm->regmap); @@ -313,7 +312,6 @@ static void rockchip_snd_txrxctrl(struct snd_pcm_substr= eam *substream, I2S_CLR_TXC | I2S_CLR_RXC); } } - spin_unlock_irqrestore(&i2s_tdm->lock, flags); } =20 static void rockchip_snd_txctrl(struct rk_i2s_tdm_dev *i2s_tdm, int on) @@ -587,12 +585,11 @@ static int rockchip_i2s_trcm_mode(struct snd_pcm_subs= tream *substream, unsigned int fmt) { struct rk_i2s_tdm_dev *i2s_tdm =3D to_info(dai); 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([183.91.15.56]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c164f6e294sm8461085ad.6.2026.06.02.20.58.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 20:58:48 -0700 (PDT) From: phucduc.bui@gmail.com To: Heiko Stuebner , Mark Brown , Liam Girdwood Cc: Nicolas Frattaroli , Jaroslav Kysela , Takashi Iwai , linux-sound@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, bui duc phuc Subject: [PATCH 3/3] ASoC: rockchip: rockchip_sai: Use guard() for spin locks Date: Wed, 3 Jun 2026 10:57:41 +0700 Message-ID: <20260603035741.68893-4-phucduc.bui@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260603035741.68893-1-phucduc.bui@gmail.com> References: <20260603035741.68893-1-phucduc.bui@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: bui duc phuc Clean up the code using guard() for spin locks. Merely code refactoring, and no behavior change. Signed-off-by: bui duc phuc --- NOTE: This patch is compile-tested only. sound/soc/rockchip/rockchip_sai.c | 258 +++++++++++++++--------------- 1 file changed, 127 insertions(+), 131 deletions(-) diff --git a/sound/soc/rockchip/rockchip_sai.c b/sound/soc/rockchip/rockchi= p_sai.c index ed393e5034a4..9104f4dedb15 100644 --- a/sound/soc/rockchip/rockchip_sai.c +++ b/sound/soc/rockchip/rockchip_sai.c @@ -18,7 +18,6 @@ #include #include #include - #include "rockchip_sai.h" =20 #define DRV_NAME "rockchip-sai" @@ -216,14 +215,12 @@ static void rockchip_sai_xfer_clk_stop_and_wait(struc= t rk_sai_dev *sai, unsigned static int rockchip_sai_runtime_suspend(struct device *dev) { struct rk_sai_dev *sai =3D dev_get_drvdata(dev); - unsigned long flags; =20 rockchip_sai_fsync_lost_detect(sai, 0); rockchip_sai_fsync_err_detect(sai, 0); =20 - spin_lock_irqsave(&sai->xfer_lock, flags); - rockchip_sai_xfer_clk_stop_and_wait(sai, NULL); - spin_unlock_irqrestore(&sai->xfer_lock, flags); + scoped_guard(spinlock_irqsave, &sai->xfer_lock) + rockchip_sai_xfer_clk_stop_and_wait(sai, NULL); =20 regcache_cache_only(sai->regmap, true); /* @@ -483,7 +480,6 @@ static int rockchip_sai_set_fmt(struct snd_soc_dai *dai= , unsigned int fmt) struct rk_sai_dev *sai =3D snd_soc_dai_get_drvdata(dai); unsigned int mask =3D 0, val =3D 0; unsigned int clk_gates; - unsigned long flags; int ret =3D 0; =20 pm_runtime_get_sync(dai->dev); @@ -499,56 +495,56 @@ static int rockchip_sai_set_fmt(struct snd_soc_dai *d= ai, unsigned int fmt) sai->is_master_mode =3D false; break; default: - ret =3D -EINVAL; - goto err_pm_put; - } - - spin_lock_irqsave(&sai->xfer_lock, flags); - rockchip_sai_xfer_clk_stop_and_wait(sai, &clk_gates); - if (sai->initialized) { - if (sai->has_capture && sai->has_playback) - rockchip_sai_xfer_stop(sai, -1); - else if (sai->has_capture) - rockchip_sai_xfer_stop(sai, SNDRV_PCM_STREAM_CAPTURE); - else - rockchip_sai_xfer_stop(sai, SNDRV_PCM_STREAM_PLAYBACK); - } else { - rockchip_sai_clear(sai, 0); - sai->initialized =3D true; + pm_runtime_put(dai->dev); + return -EINVAL; } =20 - regmap_update_bits(sai->regmap, SAI_CKR, mask, val); + scoped_guard(spinlock_irqsave, &sai->xfer_lock) { + rockchip_sai_xfer_clk_stop_and_wait(sai, &clk_gates); + if (sai->initialized) { + if (sai->has_capture && sai->has_playback) + rockchip_sai_xfer_stop(sai, -1); + else if (sai->has_capture) + rockchip_sai_xfer_stop(sai, SNDRV_PCM_STREAM_CAPTURE); + else + rockchip_sai_xfer_stop(sai, SNDRV_PCM_STREAM_PLAYBACK); + } else { + rockchip_sai_clear(sai, 0); + sai->initialized =3D true; + } =20 - mask =3D SAI_CKR_CKP_MASK | SAI_CKR_FSP_MASK; - switch (fmt & SND_SOC_DAIFMT_INV_MASK) { - case SND_SOC_DAIFMT_NB_NF: - val =3D SAI_CKR_CKP_NORMAL | SAI_CKR_FSP_NORMAL; - break; - case SND_SOC_DAIFMT_NB_IF: - val =3D SAI_CKR_CKP_NORMAL | SAI_CKR_FSP_INVERTED; - break; - case SND_SOC_DAIFMT_IB_NF: - val =3D SAI_CKR_CKP_INVERTED | SAI_CKR_FSP_NORMAL; - break; - case SND_SOC_DAIFMT_IB_IF: - val =3D SAI_CKR_CKP_INVERTED | SAI_CKR_FSP_INVERTED; - break; - default: - ret =3D -EINVAL; - goto err_xfer_unlock; - } + regmap_update_bits(sai->regmap, SAI_CKR, mask, val); + + mask =3D SAI_CKR_CKP_MASK | SAI_CKR_FSP_MASK; + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + val =3D SAI_CKR_CKP_NORMAL | SAI_CKR_FSP_NORMAL; + break; + case SND_SOC_DAIFMT_NB_IF: + val =3D SAI_CKR_CKP_NORMAL | SAI_CKR_FSP_INVERTED; + break; + case SND_SOC_DAIFMT_IB_NF: + val =3D SAI_CKR_CKP_INVERTED | SAI_CKR_FSP_NORMAL; + break; + case SND_SOC_DAIFMT_IB_IF: + val =3D SAI_CKR_CKP_INVERTED | SAI_CKR_FSP_INVERTED; + break; + default: + ret =3D -EINVAL; + break; + } =20 - regmap_update_bits(sai->regmap, SAI_CKR, mask, val); + if (ret =3D=3D 0) { + regmap_update_bits(sai->regmap, SAI_CKR, mask, val); + rockchip_sai_fmt_create(sai, fmt); + } =20 - rockchip_sai_fmt_create(sai, fmt); + if (clk_gates) + regmap_update_bits(sai->regmap, SAI_XFER, + SAI_XFER_CLK_MASK | SAI_XFER_FSS_MASK, + clk_gates); + } =20 -err_xfer_unlock: - if (clk_gates) - regmap_update_bits(sai->regmap, SAI_XFER, - SAI_XFER_CLK_MASK | SAI_XFER_FSS_MASK, - clk_gates); - spin_unlock_irqrestore(&sai->xfer_lock, flags); -err_pm_put: pm_runtime_put(dai->dev); =20 return ret; @@ -564,7 +560,6 @@ static int rockchip_sai_hw_params(struct snd_pcm_substr= eam *substream, unsigned int ch_per_lane, slot_width; unsigned int val, fscr, reg; unsigned int lanes, req_lanes; - unsigned long flags; int ret =3D 0; =20 if (!rockchip_sai_stream_valid(substream, dai)) @@ -618,84 +613,88 @@ static int rockchip_sai_hw_params(struct snd_pcm_subs= tream *substream, val =3D SAI_XCR_VDW(32); break; default: - ret =3D -EINVAL; - goto err_pm_put; + pm_runtime_put(sai->dev); + return -EINVAL; } =20 val |=3D SAI_XCR_CSR(lanes); =20 - spin_lock_irqsave(&sai->xfer_lock, flags); - - regmap_update_bits(sai->regmap, reg, SAI_XCR_VDW_MASK | SAI_XCR_CSR_MASK,= val); - - if (!sai->is_tdm) - regmap_update_bits(sai->regmap, reg, SAI_XCR_SBW_MASK, - SAI_XCR_SBW(params_physical_width(params))); + scoped_guard(spinlock_irqsave, &sai->xfer_lock) { =20 - regmap_read(sai->regmap, reg, &val); + regmap_update_bits(sai->regmap, reg, SAI_XCR_VDW_MASK | SAI_XCR_CSR_MASK= , val); =20 - slot_width =3D SAI_XCR_SBW_V(val); - ch_per_lane =3D params_channels(params) / lanes; + if (!sai->is_tdm) + regmap_update_bits(sai->regmap, reg, SAI_XCR_SBW_MASK, + SAI_XCR_SBW(params_physical_width(params))); =20 - regmap_update_bits(sai->regmap, reg, SAI_XCR_SNB_MASK, - SAI_XCR_SNB(ch_per_lane)); + regmap_read(sai->regmap, reg, &val); =20 - fscr =3D SAI_FSCR_FW(sai->fw_ratio * slot_width * ch_per_lane); - - switch (sai->fpw) { - case FPW_ONE_BCLK_WIDTH: - fscr |=3D SAI_FSCR_FPW(1); - break; - case FPW_ONE_SLOT_WIDTH: - fscr |=3D SAI_FSCR_FPW(slot_width); - break; - case FPW_HALF_FRAME_WIDTH: - fscr |=3D SAI_FSCR_FPW(sai->fw_ratio * slot_width * ch_per_lane / 2); - break; - default: - dev_err(sai->dev, "Invalid Frame Pulse Width %d\n", sai->fpw); - ret =3D -EINVAL; - goto err_xfer_unlock; - } + slot_width =3D SAI_XCR_SBW_V(val); + ch_per_lane =3D params_channels(params) / lanes; =20 - regmap_update_bits(sai->regmap, SAI_FSCR, - SAI_FSCR_FW_MASK | SAI_FSCR_FPW_MASK, fscr); + regmap_update_bits(sai->regmap, reg, SAI_XCR_SNB_MASK, + SAI_XCR_SNB(ch_per_lane)); =20 - if (sai->is_master_mode) { - bclk_rate =3D sai->fw_ratio * slot_width * ch_per_lane * params_rate(par= ams); - ret =3D clk_set_rate(sai->mclk, sai->mclk_rate); - if (ret) { - dev_err(sai->dev, "Failed to set mclk to %u: %pe\n", - sai->mclk_rate, ERR_PTR(ret)); - goto err_xfer_unlock; - } + fscr =3D SAI_FSCR_FW(sai->fw_ratio * slot_width * ch_per_lane); =20 - mclk_rate =3D clk_get_rate(sai->mclk); - if (mclk_rate < bclk_rate) { - dev_err(sai->dev, "Mismatch mclk: %u, at least %u\n", - mclk_rate, bclk_rate); + switch (sai->fpw) { + case FPW_ONE_BCLK_WIDTH: + fscr |=3D SAI_FSCR_FPW(1); + break; + case FPW_ONE_SLOT_WIDTH: + fscr |=3D SAI_FSCR_FPW(slot_width); + break; + case FPW_HALF_FRAME_WIDTH: + fscr |=3D SAI_FSCR_FPW(sai->fw_ratio * slot_width * ch_per_lane / 2); + break; + default: + dev_err(sai->dev, "Invalid Frame Pulse Width %d\n", sai->fpw); ret =3D -EINVAL; - goto err_xfer_unlock; + break; } =20 - div_bclk =3D DIV_ROUND_CLOSEST(mclk_rate, bclk_rate); - mclk_req_rate =3D bclk_rate * div_bclk; - - if (mclk_rate < mclk_req_rate - CLK_SHIFT_RATE_HZ_MAX || - mclk_rate > mclk_req_rate + CLK_SHIFT_RATE_HZ_MAX) { - dev_err(sai->dev, "Mismatch mclk: %u, expected %u (+/- %dHz)\n", - mclk_rate, mclk_req_rate, CLK_SHIFT_RATE_HZ_MAX); - ret =3D -EINVAL; - goto err_xfer_unlock; + if (ret =3D=3D 0) { + regmap_update_bits(sai->regmap, SAI_FSCR, + SAI_FSCR_FW_MASK | SAI_FSCR_FPW_MASK, fscr); + + if (sai->is_master_mode) { + bclk_rate =3D sai->fw_ratio * slot_width * + ch_per_lane * params_rate(params); + ret =3D clk_set_rate(sai->mclk, sai->mclk_rate); + if (ret) + dev_err(sai->dev, "Failed to set mclk to %u: %pe\n", + sai->mclk_rate, ERR_PTR(ret)); + else { + mclk_rate =3D clk_get_rate(sai->mclk); + if (mclk_rate < bclk_rate) { + dev_err(sai->dev, "Mismatch mclk: %u, at least %u\n", + mclk_rate, bclk_rate); + ret =3D -EINVAL; + } else { + + div_bclk =3D DIV_ROUND_CLOSEST(mclk_rate, bclk_rate); + mclk_req_rate =3D bclk_rate * div_bclk; + + if (mclk_rate < + mclk_req_rate - CLK_SHIFT_RATE_HZ_MAX || + mclk_rate > + mclk_req_rate + CLK_SHIFT_RATE_HZ_MAX) { + dev_err(sai->dev, + "Mismatch mclk: %u, expected %u (+/- %dHz)\n", + mclk_rate, mclk_req_rate, + CLK_SHIFT_RATE_HZ_MAX); + ret =3D -EINVAL; + } else + regmap_update_bits(sai->regmap, + SAI_CKR, + SAI_CKR_MDIV_MASK, + SAI_CKR_MDIV(div_bclk)); + } + } + } } - - regmap_update_bits(sai->regmap, SAI_CKR, SAI_CKR_MDIV_MASK, - SAI_CKR_MDIV(div_bclk)); } =20 -err_xfer_unlock: - spin_unlock_irqrestore(&sai->xfer_lock, flags); -err_pm_put: pm_runtime_put(sai->dev); =20 return ret; @@ -705,7 +704,6 @@ static int rockchip_sai_prepare(struct snd_pcm_substrea= m *substream, struct snd_soc_dai *dai) { struct rk_sai_dev *sai =3D snd_soc_dai_get_drvdata(dai); - unsigned long flags; =20 if (!rockchip_sai_stream_valid(substream, dai)) return 0; @@ -726,13 +724,12 @@ static int rockchip_sai_prepare(struct snd_pcm_substr= eam *substream, * udelay falls short. */ udelay(20); - spin_lock_irqsave(&sai->xfer_lock, flags); - regmap_update_bits(sai->regmap, SAI_XFER, - SAI_XFER_CLK_MASK | - SAI_XFER_FSS_MASK, - SAI_XFER_CLK_EN | - SAI_XFER_FSS_EN); - spin_unlock_irqrestore(&sai->xfer_lock, flags); + scoped_guard(spinlock_irqsave, &sai->xfer_lock) + regmap_update_bits(sai->regmap, SAI_XFER, + SAI_XFER_CLK_MASK | + SAI_XFER_FSS_MASK, + SAI_XFER_CLK_EN | + SAI_XFER_FSS_EN); } =20 rockchip_sai_fsync_lost_detect(sai, 1); @@ -915,7 +912,6 @@ static int rockchip_sai_set_tdm_slot(struct snd_soc_dai= *dai, int slots, int slot_width) { struct rk_sai_dev *sai =3D snd_soc_dai_get_drvdata(dai); - unsigned long flags; unsigned int clk_gates; int sw =3D slot_width; =20 @@ -931,16 +927,16 @@ static int rockchip_sai_set_tdm_slot(struct snd_soc_d= ai *dai, return -EINVAL; =20 pm_runtime_get_sync(dai->dev); - spin_lock_irqsave(&sai->xfer_lock, flags); - rockchip_sai_xfer_clk_stop_and_wait(sai, &clk_gates); - regmap_update_bits(sai->regmap, SAI_TXCR, SAI_XCR_SBW_MASK, - SAI_XCR_SBW(sw)); - regmap_update_bits(sai->regmap, SAI_RXCR, SAI_XCR_SBW_MASK, - SAI_XCR_SBW(sw)); - regmap_update_bits(sai->regmap, SAI_XFER, - SAI_XFER_CLK_MASK | SAI_XFER_FSS_MASK, - clk_gates); - spin_unlock_irqrestore(&sai->xfer_lock, flags); + scoped_guard(spinlock_irqsave, &sai->xfer_lock) { + rockchip_sai_xfer_clk_stop_and_wait(sai, &clk_gates); + regmap_update_bits(sai->regmap, SAI_TXCR, SAI_XCR_SBW_MASK, + SAI_XCR_SBW(sw)); + regmap_update_bits(sai->regmap, SAI_RXCR, SAI_XCR_SBW_MASK, + SAI_XCR_SBW(sw)); + regmap_update_bits(sai->regmap, SAI_XFER, + SAI_XFER_CLK_MASK | SAI_XFER_FSS_MASK, + clk_gates); + } pm_runtime_put(dai->dev); =20 return 0; --=20 2.43.0