From nobody Mon Jun 8 06:35:46 2026 Received: from smtpbguseast1.qq.com (smtpbguseast1.qq.com [54.204.34.129]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C1F93F44FA for ; Wed, 3 Jun 2026 03:37:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=54.204.34.129 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780457844; cv=none; b=ocslC4iqKvzEMwNhDx9yp14W00YdJ3PyQam7hIAv4PlBMXEhJ0n/6El/oSDKHKDE8HPG7f30DV4yG0tddCjHcjD0DF9+bLRerrFataU6kbizTd/aRwQkq0hFCoj1V2UEZarmSPI/jozbbzvPbPdJMCZ7fYMcH8dgcoIokfR0clM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780457844; c=relaxed/simple; bh=YiaZXOI2ZGs0aILBSYHru05Mh195xGoCIM/aLbA3D0Y=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=QcOr4inbuPCIWeAeCqV3055kn8/IbaYjmTDlt0I69BvFQKF/BttIZRPeOj+QnD4xhoaqabk74UKr+lfkbavHPOkJRQaD6ShXGNBT7m+r2eQWnE4XVcs3Pre+m5Phau/MgcGFTwdAO+8Onoi99BMuX2+LpMXI9UN3aPNsXmkD6MU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=airkyi.com; spf=pass smtp.mailfrom=airkyi.com; dkim=pass (1024-bit key) header.d=airkyi.com header.i=@airkyi.com header.b=mxWcYVI6; arc=none smtp.client-ip=54.204.34.129 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=airkyi.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=airkyi.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=airkyi.com header.i=@airkyi.com header.b="mxWcYVI6" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=airkyi.com; s=altu2504; t=1780457747; bh=SZJVak88/aC7UTVK2wwbeD1rPLF/qNGzBGGJ5rAWfSg=; h=From:To:Subject:Date:Message-Id; b=mxWcYVI620l/6x+AdUfkE00+luazpSOUF8CzhhSvSpoglnYq3cO/9aogVbe2Suy5n cPqptjNBS5tEY8CSvb7N+CB4IFDYLY3Kjy09HskYownsqS7qa+PK8UJniHqDQFowTl poMn0S+JMFfV2QRd8nITuzMoGbfLUww6WrBThQX8= X-QQ-mid: zesmtpsz3t1780457744t40a9fe0e X-QQ-Originating-IP: PQ/u+gWD46vcVDfQQRGeC38c+LI/83M6xwchE1O5Lik= Received: from DESKTOP-8BT1A2O.localdomain ( [58.22.7.114]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 03 Jun 2026 11:35:41 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 6389778551223950337 From: Chaoyi Chen To: Sandy Huang , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Guochun Huang Cc: dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Chaoyi Chen Subject: [PATCH v2 1/3] drm/rockchip: dsi: Add maximum per lane bit rate calculation Date: Wed, 3 Jun 2026 11:35:30 +0800 Message-Id: <20260603033532.164-2-kernel@airkyi.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20260603033532.164-1-kernel@airkyi.com> References: <20260603033532.164-1-kernel@airkyi.com> X-QQ-SENDSIZE: 520 Feedback-ID: zesmtpsz:airkyi.com:qybglogicsvrgz:qybglogicsvrgz6b-0 X-QQ-XMAILINFO: MCg5+ArSTX6cI8MT6PFu0yKBnZg7NNmzMhqB5fcT0Ih+hPtX+3PAoGHn Uh2QfOyjF8VCqpCni/HY8bt0EzY4wNu3HxXF71jPkEvz9BzMmAnIoNw2iE+G/JhH9BbvHRI fxl2mXWyGEDguCVrwBT0rv7t3IeBdfQ8/caQdYice7EkurIh7Zc+Wu1sGvimuIxOXu5WY3D cZyiBqWulXnxjz2DC5lY5bAU6Z7FHloUWLkJZNubtxiK3MYCOScPboSwiUcLOppt5EVcgBY NeY6+t7m/wTkqbTlUbLmVX9YUjBvgEmY0Ou81CvhmA0W8niIlfkizyEAGKYFeCNtd8C4KpZ 78oUewjiRH/jR6nXnOpHJijFquyJqYgNooqxaSwlZxHInncqUT8sq67voPnJmIalL2fszpv je9U595Z+DHhRiPU+b+SVZqyTX/5wudhMXIsE1m/oRF0Nkm4HsV/qvPIWfLhUceoh0lnSEF etZ3jI3v9hZ2WozUAsgIopwOAPryn+EIO1Bp9RQePOozBFYZ4aypdZglYXtrhK/LA6LfnMs IpXLg5kF/6n1fQlG1SyoVU3FxrCPHVKWg4/+sg1zCcZXWDonppEb2pTCLt7eV+yorDtn7WF fFaKyv6f5YmznWS4qqpt6suYymgL+Em1NpwwXHGeQncMwNq5nAmkL7cvS21uRN5t4qfzfwo 4N5uTn3E/wgGxzcgVdnFqR+R2jj2Ls7yn/suk/AtWRFK4vA09k3UHvFkVuzNuo6PsPUfJEH aU/DG5kMkEJSvY/2o6OrA8LS2QDb8S00uO4Nw6vEAV5HHA4s8wbE/EF9Uqt9GUp72KFW881 mn6b4VH4Xn2axhcM1yhMRFofNZSu2dyn8m7A6MSwx4GV2O+0+wZy/qZvtK7dnTUYEHy4Ktj ooMMJlYDlq3fhmww1VPRVivc2/IxleJ7DbaahE/YTGRJwFAHNx6GJPL1L4P6pjRIfEP7uNX VT94hIE+HMg4gG6zeu7XU4rUOQ13tBMOFn85H3MsilkJ2WZEWPwKDc+ApqkXPA1gAlvryjK NNmjSGIA== X-QQ-XMRINFO: NyFYKkN4Ny6FuXrnB5Ye7Aabb3ujjtK+gg== X-QQ-RECHKSPAM: 0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Chaoyi Chen Different chips have varying support for the maximum bit rate per lane. Add calculation for the maximum per lane bit rate for various chip platforms. Signed-off-by: Chaoyi Chen --- Changes in v2: - Fix the unit conversion for max_mbps. - Split the lane rate calculation into a separate patch. --- drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/= drm/rockchip/dw-mipi-dsi-rockchip.c index 3547d91b25d3..1060abec9f29 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c @@ -268,6 +268,7 @@ struct rockchip_dw_dsi_chip_data { =20 unsigned int flags; unsigned int max_data_lanes; + unsigned long max_bit_rate_per_lane; }; =20 struct dw_mipi_dsi_rockchip { @@ -565,7 +566,7 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct= drm_display_mode *mode, int bpp; unsigned long mpclk, tmp; unsigned int target_mbps =3D 1000; - unsigned int max_mbps =3D dppa_map[ARRAY_SIZE(dppa_map) - 1].max_mbps; + unsigned int max_mbps; unsigned long best_freq =3D 0; unsigned long fvco_min, fvco_max, fin, fout; unsigned int min_prediv, max_prediv; @@ -573,6 +574,7 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct= drm_display_mode *mode, unsigned long _fbdiv, best_fbdiv; unsigned long min_delta =3D ULONG_MAX; =20 + max_mbps =3D dsi->cdata->max_bit_rate_per_lane / USEC_PER_SEC; dsi->format =3D format; bpp =3D mipi_dsi_pixel_format_to_bpp(dsi->format); if (bpp < 0) { @@ -1503,6 +1505,7 @@ static const struct rockchip_dw_dsi_chip_data px30_ch= ip_data[] =3D { PX30_DSI_FORCETXSTOPMODE), 0), =20 .max_data_lanes =3D 4, + .max_bit_rate_per_lane =3D 1000000000UL, }, { /* sentinel */ } }; @@ -1515,6 +1518,7 @@ static const struct rockchip_dw_dsi_chip_data rk3128_= chip_data[] =3D { RK3128_DSI_FORCERXMODE | RK3128_DSI_FORCETXSTOPMODE), 0), .max_data_lanes =3D 4, + .max_bit_rate_per_lane =3D 1000000000UL, }, { /* sentinel */ } }; @@ -1527,6 +1531,7 @@ static const struct rockchip_dw_dsi_chip_data rk3288_= chip_data[] =3D { .lcdsel_lit =3D FIELD_PREP_WM16_CONST(RK3288_DSI0_LCDC_SEL, 1), =20 .max_data_lanes =3D 4, + .max_bit_rate_per_lane =3D 1500000000UL, }, { .reg =3D 0xff964000, @@ -1535,6 +1540,7 @@ static const struct rockchip_dw_dsi_chip_data rk3288_= chip_data[] =3D { .lcdsel_lit =3D FIELD_PREP_WM16_CONST(RK3288_DSI1_LCDC_SEL, 1), =20 .max_data_lanes =3D 4, + .max_bit_rate_per_lane =3D 1500000000UL, }, { /* sentinel */ } }; @@ -1547,6 +1553,7 @@ static const struct rockchip_dw_dsi_chip_data rk3368_= chip_data[] =3D { RK3368_DSI_FORCETXSTOPMODE | RK3368_DSI_FORCERXMODE), 0), .max_data_lanes =3D 4, + .max_bit_rate_per_lane =3D 1500000000UL, }, { /* sentinel */ } }; @@ -1634,6 +1641,7 @@ static const struct rockchip_dw_dsi_chip_data rk3399_= chip_data[] =3D { =20 .flags =3D DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK, .max_data_lanes =3D 4, + .max_bit_rate_per_lane =3D 1500000000UL, }, { .reg =3D 0xff968000, @@ -1658,6 +1666,7 @@ static const struct rockchip_dw_dsi_chip_data rk3399_= chip_data[] =3D { =20 .flags =3D DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK, .max_data_lanes =3D 4, + .max_bit_rate_per_lane =3D 1500000000UL, =20 .dphy_rx_init =3D rk3399_dphy_tx1rx1_init, .dphy_rx_power_on =3D rk3399_dphy_tx1rx1_power_on, @@ -1674,6 +1683,7 @@ static const struct rockchip_dw_dsi_chip_data rk3506_= chip_data[] =3D { FIELD_PREP_WM16_CONST(RK3506_DSI_FORCERXMODE, 0) | FIELD_PREP_WM16_CONST(RK3506_DSI_FORCETXSTOPMODE, 0)), .max_data_lanes =3D 2, + .max_bit_rate_per_lane =3D 1500000000UL, }, { /* sentinel */ } }; @@ -1687,6 +1697,7 @@ static const struct rockchip_dw_dsi_chip_data rk3568_= chip_data[] =3D { FIELD_PREP_WM16_CONST(RK3568_DSI0_TURNDISABLE, 0) | FIELD_PREP_WM16_CONST(RK3568_DSI0_FORCERXMODE, 0)), .max_data_lanes =3D 4, + .max_bit_rate_per_lane =3D 1200000000UL, }, { .reg =3D 0xfe070000, @@ -1696,6 +1707,7 @@ static const struct rockchip_dw_dsi_chip_data rk3568_= chip_data[] =3D { FIELD_PREP_WM16_CONST(RK3568_DSI1_TURNDISABLE, 0) | FIELD_PREP_WM16_CONST(RK3568_DSI1_FORCERXMODE, 0)), .max_data_lanes =3D 4, + .max_bit_rate_per_lane =3D 1200000000UL, }, { /* sentinel */ } }; @@ -1708,6 +1720,7 @@ static const struct rockchip_dw_dsi_chip_data rv1126_= chip_data[] =3D { FIELD_PREP_WM16_CONST(RV1126_DSI_FORCERXMODE, 0) | FIELD_PREP_WM16_CONST(RV1126_DSI_FORCETXSTOPMODE, 0)), .max_data_lanes =3D 4, + .max_bit_rate_per_lane =3D 1000000000UL, }, { /* sentinel */ } }; --=20 2.53.0 From nobody Mon Jun 8 06:35:46 2026 Received: from smtpbgsg1.qq.com (smtpbgsg1.qq.com [54.254.200.92]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8DBE93F5BDF for ; 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charset="utf-8" From: Chaoyi Chen Currently, there are generally two types of DPHY for Rockchip. One is the DPHY used by RK3288/RK3399, whose timing is described by Table A-3 High-Speed Transition Times in the databook. The other is the DPHY used by PX30 and its successors. If its timing is still described using RK3288/RK3399, it may not perform correctly on some DSI panel. Add dphy_get_timing for different D-PHY types to adapt to timing differences. The configuration details are as follows: - RK3288/RK3399: Select the corresponding entry from the timing table based on the data rate. - PX30 and later platforms: Use a fixed timing configuration. Signed-off-by: Chaoyi Chen --- Changes in v2: - Add more comment about timing config. --- .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 45 ++++++++++++++++++- 1 file changed, 43 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/= drm/rockchip/dw-mipi-dsi-rockchip.c index 1060abec9f29..e64dfc327891 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c @@ -247,6 +247,7 @@ enum { BIASEXTR_127_7, }; =20 +struct dw_mipi_dsi_rockchip; struct rockchip_dw_dsi_chip_data { u32 reg; =20 @@ -262,6 +263,9 @@ struct rockchip_dw_dsi_chip_data { u32 lanecfg2_grf_reg; u32 lanecfg2; =20 + int (*dphy_get_timing)(struct dw_mipi_dsi_rockchip *dsi, unsigned int lan= e_mbps, + struct dw_mipi_dsi_dphy_timing *timing); + int (*dphy_rx_init)(struct phy *phy); int (*dphy_rx_power_on)(struct phy *phy); int (*dphy_rx_power_off)(struct phy *phy); @@ -721,8 +725,9 @@ static struct hstt hstt_table[] =3D { }; =20 static int -dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps, - struct dw_mipi_dsi_dphy_timing *timing) +dw_mipi_dsi_phy_rk3288_get_timing(struct dw_mipi_dsi_rockchip *dsi, + unsigned int lane_mbps, + struct dw_mipi_dsi_dphy_timing *timing) { int i; =20 @@ -738,6 +743,32 @@ dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned i= nt lane_mbps, return 0; } =20 +static const struct dw_mipi_dsi_dphy_timing dphy_timing_px30 =3D { + .clk_lp2hs =3D 0x40, + .clk_hs2lp =3D 0x40, + .data_lp2hs =3D 0x10, + .data_hs2lp =3D 0x14, +}; + +static int +dw_mipi_dsi_phy_px30_get_timing(struct dw_mipi_dsi_rockchip *dsi, + unsigned int lane_mbps, + struct dw_mipi_dsi_dphy_timing *timing) +{ + *timing =3D dphy_timing_px30; + + return 0; +} + +static int +dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps, + struct dw_mipi_dsi_dphy_timing *timing) +{ + struct dw_mipi_dsi_rockchip *dsi =3D priv_data; + + return dsi->cdata->dphy_get_timing(dsi, lane_mbps, timing); +} + static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops =3D { .init =3D dw_mipi_dsi_phy_init, .power_on =3D dw_mipi_dsi_phy_power_on, @@ -1506,6 +1537,7 @@ static const struct rockchip_dw_dsi_chip_data px30_ch= ip_data[] =3D { =20 .max_data_lanes =3D 4, .max_bit_rate_per_lane =3D 1000000000UL, + .dphy_get_timing =3D dw_mipi_dsi_phy_px30_get_timing, }, { /* sentinel */ } }; @@ -1519,6 +1551,7 @@ static const struct rockchip_dw_dsi_chip_data rk3128_= chip_data[] =3D { RK3128_DSI_FORCETXSTOPMODE), 0), .max_data_lanes =3D 4, .max_bit_rate_per_lane =3D 1000000000UL, + .dphy_get_timing =3D dw_mipi_dsi_phy_px30_get_timing, }, { /* sentinel */ } }; @@ -1532,6 +1565,7 @@ static const struct rockchip_dw_dsi_chip_data rk3288_= chip_data[] =3D { =20 .max_data_lanes =3D 4, .max_bit_rate_per_lane =3D 1500000000UL, + .dphy_get_timing =3D dw_mipi_dsi_phy_rk3288_get_timing, }, { .reg =3D 0xff964000, @@ -1541,6 +1575,7 @@ static const struct rockchip_dw_dsi_chip_data rk3288_= chip_data[] =3D { =20 .max_data_lanes =3D 4, .max_bit_rate_per_lane =3D 1500000000UL, + .dphy_get_timing =3D dw_mipi_dsi_phy_rk3288_get_timing, }, { /* sentinel */ } }; @@ -1554,6 +1589,7 @@ static const struct rockchip_dw_dsi_chip_data rk3368_= chip_data[] =3D { RK3368_DSI_FORCERXMODE), 0), .max_data_lanes =3D 4, .max_bit_rate_per_lane =3D 1500000000UL, + .dphy_get_timing =3D dw_mipi_dsi_phy_px30_get_timing, }, { /* sentinel */ } }; @@ -1642,6 +1678,7 @@ static const struct rockchip_dw_dsi_chip_data rk3399_= chip_data[] =3D { .flags =3D DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK, .max_data_lanes =3D 4, .max_bit_rate_per_lane =3D 1500000000UL, + .dphy_get_timing =3D dw_mipi_dsi_phy_rk3288_get_timing, }, { .reg =3D 0xff968000, @@ -1671,6 +1708,7 @@ static const struct rockchip_dw_dsi_chip_data rk3399_= chip_data[] =3D { .dphy_rx_init =3D rk3399_dphy_tx1rx1_init, .dphy_rx_power_on =3D rk3399_dphy_tx1rx1_power_on, .dphy_rx_power_off =3D rk3399_dphy_tx1rx1_power_off, + .dphy_get_timing =3D dw_mipi_dsi_phy_rk3288_get_timing, }, { /* sentinel */ } }; @@ -1698,6 +1736,7 @@ static const struct rockchip_dw_dsi_chip_data rk3568_= chip_data[] =3D { FIELD_PREP_WM16_CONST(RK3568_DSI0_FORCERXMODE, 0)), .max_data_lanes =3D 4, .max_bit_rate_per_lane =3D 1200000000UL, + .dphy_get_timing =3D dw_mipi_dsi_phy_px30_get_timing, }, { .reg =3D 0xfe070000, @@ -1708,6 +1747,7 @@ static const struct rockchip_dw_dsi_chip_data rk3568_= chip_data[] =3D { FIELD_PREP_WM16_CONST(RK3568_DSI1_FORCERXMODE, 0)), .max_data_lanes =3D 4, .max_bit_rate_per_lane =3D 1200000000UL, + .dphy_get_timing =3D dw_mipi_dsi_phy_px30_get_timing, }, { /* sentinel */ } }; @@ -1721,6 +1761,7 @@ static const struct rockchip_dw_dsi_chip_data rv1126_= chip_data[] =3D { FIELD_PREP_WM16_CONST(RV1126_DSI_FORCETXSTOPMODE, 0)), .max_data_lanes =3D 4, .max_bit_rate_per_lane =3D 1000000000UL, + .dphy_get_timing =3D dw_mipi_dsi_phy_px30_get_timing, }, { /* sentinel */ } }; --=20 2.53.0 From nobody Mon Jun 8 06:35:46 2026 Received: from smtpbgau1.qq.com (smtpbgau1.qq.com [54.206.16.166]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 441433F412A for ; Wed, 3 Jun 2026 03:37:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=54.206.16.166 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780457845; cv=none; b=TRgQ+qp2d7mn9cek2pl6FK7CoG/2w2pUbWv2pmvNC9+y8m+V/HYQdD8tm6nKUqts3ivHquRveQ8pO2mLeYmEplYZxothaPOggnjoovwMp6ILmQJbORwH+WjlQHFuaM1v69yH6t0TrWawvEW8fjcgOqfX2D6M3GG10juo8kHJasA= ARC-Message-Signature: i=1; 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charset="utf-8" From: Chaoyi Chen The lane rate is calculated as follows: Lane_Rate =3D Pixel_Clk * BPP / lanes * Overhead The overhead factor is set to 1/0.8, equivalent to a 25% overhead. Now let's consider the case of RGB888 (BPP24) with a pclk of 148.5MHz. The lane rate equals 148.5M * 24 / 4 * 1.25 =3D 1113.75 Mbps. However, this is beyond the capability of certain platforms limited to a 1Gbps lane rate. On the other hand, we have observed that some DSI panel actually perform worse with higher overhead. So we are considering relaxing the bandwidth margin requirements. According to the downstream test results, adopting 1/0.9 seems to be a sound approach, corresponding to an overhead of about 11%. Signed-off-by: Chaoyi Chen --- drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/= drm/rockchip/dw-mipi-dsi-rockchip.c index e64dfc327891..8af9d6934d27 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c @@ -590,8 +590,8 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct= drm_display_mode *mode, =20 mpclk =3D DIV_ROUND_UP(mode->clock, MSEC_PER_SEC); if (mpclk) { - /* take 1 / 0.8, since mbps must big than bandwidth of RGB */ - tmp =3D mpclk * (bpp / lanes) * 10 / 8; + /* take 1 / 0.9, since mbps must big than bandwidth of RGB */ + tmp =3D mpclk * (bpp / lanes) * 10 / 9; if (tmp < max_mbps) target_mbps =3D tmp; else @@ -601,7 +601,7 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct= drm_display_mode *mode, =20 /* for external phy only a the mipi_dphy_config is necessary */ if (dsi->phy) { - phy_mipi_dphy_get_default_config(mode->clock * 1000 * 10 / 8, + phy_mipi_dphy_get_default_config(mode->clock * 1000 * 10 / 9, bpp, lanes, &dsi->phy_opts.mipi_dphy); dsi->lane_mbps =3D target_mbps; --=20 2.53.0