From nobody Mon Jun 8 06:36:45 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E2BA3FC5D0; Wed, 3 Jun 2026 06:59:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780469944; cv=none; b=h2Zzx8hezFqDwAaaU1OH7qiGDWaVtUXiuToZeb+NV+buepRY1M00kXyNdYYKxsigtAU8CneyIhp5wvAPF4nstAj9HrqJqmtcD+1tuzXmYT3J3BohJwM2eTWDsb2recg7QSnSrpJPUoXda248FK0PiHIXzN7ZU7x57hNAMszu8GA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780469944; c=relaxed/simple; bh=3oS3mTiggystwLzZeuZZyOrTtEuaq/6Ip6uXuOoIUWw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=E237cQqP9z88UCbjxt6OKDtfmkaHH5g+Yps80I2oUcB+kMZmLYLRAULeHeJ0b1UNN1Pg2HSBfVaT7v6IwSqHpfb9H+eE+OTQ2kSgTlmOoMdK2sVLEHpBAlxhE164byEaLMq4vfodIkf1Z1pYNF4CF9J0cMMqwYME8G+Aws9IQ0w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=OXHDFjme; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="OXHDFjme" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1780469941; x=1812005941; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=3oS3mTiggystwLzZeuZZyOrTtEuaq/6Ip6uXuOoIUWw=; b=OXHDFjmemFe2kaupROKo+mDSLGKJUtp13OoUfI8ioR2ct4suLYHlW648 9B/ot9ghXCfOQprlIqcvyKlBtkwUB3QnlaFXRwo3a8Yt9V95s7SATsbrG N7yoUbB1115k0BRUISmjmsSrnYiTVBy2CCFeQv3qxJjy/LIOkLzQK/zRE uzqkk7oUV38EhLwbipSzkeGxI705WVqsANoyxqtPL8XfO+E2w7VtXoBe8 utrziJrwObTLw0J2jwUCMxs72YJUl0qbBSJESMv14szqLups9v13VxkjM gOlAqLdRPbkVGlJ+KfI60XzCAxhWni5yPOVR+FL9OPaoK3HRmibbv3Evz g==; X-CSE-ConnectionGUID: p0u978ZNRcyiWJJtvm1DhA== X-CSE-MsgGUID: 3fpl0hH/QiSZVXKck2RSEA== X-IronPort-AV: E=Sophos;i="6.24,184,1774335600"; d="scan'208";a="57701323" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 02 Jun 2026 23:58:54 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Tue, 2 Jun 2026 23:58:54 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 2 Jun 2026 23:58:50 -0700 From: Balakrishnan Sambath Date: Wed, 3 Jun 2026 12:28:44 +0530 Subject: [PATCH v6 01/12] media: microchip-isc: fix SBGGR10 Bayer pattern Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260603-microchip-isc-fixes-v6-1-8c3d7474a768@microchip.com> References: <20260603-microchip-isc-fixes-v6-0-8c3d7474a768@microchip.com> In-Reply-To: <20260603-microchip-isc-fixes-v6-0-8c3d7474a768@microchip.com> To: Eugen Hristev , Mauro Carvalho Chehab , Hans Verkuil CC: Laurent Pinchart , Kieran Bingham , Sakari Ailus , Balamanikandan Gunasundar , , , , "Balakrishnan Sambath" X-Mailer: b4 0.14.3 SBGGR10 was mapped to ISC_BAY_CFG_RGRG instead of ISC_BAY_CFG_BGBG, causing red/blue channel swap. Fixes: 91b4e487b0c6 ("media: microchip: add ISC driver as Microchip ISC") Cc: stable@vger.kernel.org Signed-off-by: Balakrishnan Sambath Reviewed-by: Eugen Hristev --- drivers/media/platform/microchip/microchip-sama5d2-isc.c | 2 +- drivers/media/platform/microchip/microchip-sama7g5-isc.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/microchip/microchip-sama5d2-isc.c b/dri= vers/media/platform/microchip/microchip-sama5d2-isc.c index 66d3d7891991..0ddff1e7b0a0 100644 --- a/drivers/media/platform/microchip/microchip-sama5d2-isc.c +++ b/drivers/media/platform/microchip/microchip-sama5d2-isc.c @@ -147,7 +147,7 @@ static struct isc_format sama5d2_formats_list[] =3D { .fourcc =3D V4L2_PIX_FMT_SBGGR10, .mbus_code =3D MEDIA_BUS_FMT_SBGGR10_1X10, .pfe_cfg0_bps =3D ISC_PFG_CFG0_BPS_TEN, - .cfa_baycfg =3D ISC_BAY_CFG_RGRG, + .cfa_baycfg =3D ISC_BAY_CFG_BGBG, }, { .fourcc =3D V4L2_PIX_FMT_SGBRG10, diff --git a/drivers/media/platform/microchip/microchip-sama7g5-isc.c b/dri= vers/media/platform/microchip/microchip-sama7g5-isc.c index b0302dfc3278..ca23e8adecbd 100644 --- a/drivers/media/platform/microchip/microchip-sama7g5-isc.c +++ b/drivers/media/platform/microchip/microchip-sama7g5-isc.c @@ -156,7 +156,7 @@ static struct isc_format sama7g5_formats_list[] =3D { .fourcc =3D V4L2_PIX_FMT_SBGGR10, .mbus_code =3D MEDIA_BUS_FMT_SBGGR10_1X10, .pfe_cfg0_bps =3D ISC_PFG_CFG0_BPS_TEN, - .cfa_baycfg =3D ISC_BAY_CFG_RGRG, + .cfa_baycfg =3D ISC_BAY_CFG_BGBG, }, { .fourcc =3D V4L2_PIX_FMT_SGBRG10, --=20 2.34.1 From nobody Mon Jun 8 06:36:45 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 848053FBEA7; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260603-microchip-isc-fixes-v6-2-8c3d7474a768@microchip.com> References: <20260603-microchip-isc-fixes-v6-0-8c3d7474a768@microchip.com> In-Reply-To: <20260603-microchip-isc-fixes-v6-0-8c3d7474a768@microchip.com> To: Eugen Hristev , Mauro Carvalho Chehab , Hans Verkuil CC: Laurent Pinchart , Kieran Bingham , Sakari Ailus , Balamanikandan Gunasundar , , , , "Balakrishnan Sambath" X-Mailer: b4 0.14.3 ISC_WB_O_* and ISC_WB_G_* pack two 13-bit fields per register. Sign extension from negative offsets corrupts the upper field. Mask both fields to 13 bits before packing. Fixes: 91b4e487b0c6 ("media: microchip: add ISC driver as Microchip ISC") Cc: stable@vger.kernel.org Signed-off-by: Balakrishnan Sambath --- .../media/platform/microchip/microchip-isc-base.c | 21 +++++++++++++----= ---- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/media/platform/microchip/microchip-isc-base.c b/driver= s/media/platform/microchip/microchip-isc-base.c index a7cdc743fda7..45b94f1e89d8 100644 --- a/drivers/media/platform/microchip/microchip-isc-base.c +++ b/drivers/media/platform/microchip/microchip-isc-base.c @@ -61,18 +61,23 @@ static inline void isc_update_awb_ctrls(struct isc_devi= ce *isc) =20 /* In here we set our actual hw pipeline config */ =20 + /* + * Mask offset fields to 13 bits. Sign extension of negative s32 + * values would otherwise corrupt the adjacent field. + */ regmap_write(isc->regmap, ISC_WB_O_RGR, - ((ctrls->offset[ISC_HIS_CFG_MODE_R])) | - ((ctrls->offset[ISC_HIS_CFG_MODE_GR]) << 16)); + ((u32)ctrls->offset[ISC_HIS_CFG_MODE_R] & GENMASK(12, 0)) | + (((u32)ctrls->offset[ISC_HIS_CFG_MODE_GR] & GENMASK(12, 0)) << 16)); regmap_write(isc->regmap, ISC_WB_O_BGB, - ((ctrls->offset[ISC_HIS_CFG_MODE_B])) | - ((ctrls->offset[ISC_HIS_CFG_MODE_GB]) << 16)); + ((u32)ctrls->offset[ISC_HIS_CFG_MODE_B] & GENMASK(12, 0)) | + (((u32)ctrls->offset[ISC_HIS_CFG_MODE_GB] & GENMASK(12, 0)) << 16)); + /* Gains are 13-bit unsigned fields [12:0] and [28:16] */ regmap_write(isc->regmap, ISC_WB_G_RGR, - ctrls->gain[ISC_HIS_CFG_MODE_R] | - (ctrls->gain[ISC_HIS_CFG_MODE_GR] << 16)); + (ctrls->gain[ISC_HIS_CFG_MODE_R] & GENMASK(12, 0)) | + ((ctrls->gain[ISC_HIS_CFG_MODE_GR] & GENMASK(12, 0)) << 16)); regmap_write(isc->regmap, ISC_WB_G_BGB, - ctrls->gain[ISC_HIS_CFG_MODE_B] | - (ctrls->gain[ISC_HIS_CFG_MODE_GB] << 16)); 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Tue, 2 Jun 2026 23:59:04 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 2 Jun 2026 23:59:00 -0700 From: Balakrishnan Sambath Date: Wed, 3 Jun 2026 12:28:46 +0530 Subject: [PATCH v6 03/12] media: microchip-isc: fix race condition on stream stop Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260603-microchip-isc-fixes-v6-3-8c3d7474a768@microchip.com> References: <20260603-microchip-isc-fixes-v6-0-8c3d7474a768@microchip.com> In-Reply-To: <20260603-microchip-isc-fixes-v6-0-8c3d7474a768@microchip.com> To: Eugen Hristev , Mauro Carvalho Chehab , Hans Verkuil CC: Laurent Pinchart , Kieran Bingham , Sakari Ailus , Balamanikandan Gunasundar , , , , "Balakrishnan Sambath" X-Mailer: b4 0.14.3 Disable histogram and drain AWB work queue before releasing DMA buffers to prevent use-after-free if histogram IRQ fires during stream stop. Fixes: 91b4e487b0c6 ("media: microchip: add ISC driver as Microchip ISC") Cc: stable@vger.kernel.org Signed-off-by: Balakrishnan Sambath --- drivers/media/platform/microchip/microchip-isc-base.c | 19 +++++++++++++++= ++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/microchip/microchip-isc-base.c b/driver= s/media/platform/microchip/microchip-isc-base.c index 45b94f1e89d8..b19c5a63b4bd 100644 --- a/drivers/media/platform/microchip/microchip-isc-base.c +++ b/drivers/media/platform/microchip/microchip-isc-base.c @@ -427,6 +427,14 @@ static void isc_stop_streaming(struct vb2_queue *vq) =20 mutex_unlock(&isc->awb_mutex); =20 + /* + * Disable the histogram so the ISR stops firing HISREQ, then drain + * any work that was already queued before returning. This must happen + * after releasing awb_mutex because isc_awb_work also takes it. + */ + isc_set_histogram(isc, false); + cancel_work_sync(&isc->awb_work); + /* Disable DMA interrupt */ regmap_write(isc->regmap, ISC_INTDIS, ISC_INT_DDONE); =20 @@ -1519,10 +1527,17 @@ static int isc_s_awb_ctrl(struct v4l2_ctrl *ctrl) } mutex_unlock(&isc->awb_mutex); =20 - /* if we have autowhitebalance on, start histogram procedure */ + /* + * If AWB auto mode is requested and we are streaming RAW, + * start the histogram procedure, but only if it is not + * already running. Repeated enable requests would reset + * hist_id, preventing the 4-channel Bayer cycle from + * completing. + */ if (ctrls->awb =3D=3D ISC_WB_AUTO && vb2_is_streaming(&isc->vb2_vidq) && - ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code)) + ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code) && + ctrls->hist_stat !=3D HIST_ENABLED) isc_set_histogram(isc, true); =20 /* --=20 2.34.1 From nobody Mon Jun 8 06:36:45 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E8E63FCB3E; Wed, 3 Jun 2026 06:59:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780469951; cv=none; b=r2bDUa3bRLKjSFI6xCflOjnDKOh3UJwE60MJQgX5AkBc5+SyUcddEDQRDYUaVWWU2TBRw9dn43sW/HuFxMPWzI+NYV1ehPI4fNyBF4oPTl0D53elY0agypf1SVAV+sYm8ItwoMDRBbpt6QwD57OHf51WRtdV0H8+jA2PGJa29Ng= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780469951; c=relaxed/simple; bh=nN9+zsfRheHiwR0iNWCgcstHm1IznAMW4+4pvqexfH0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=futMeRbOltoIdXQsEb9fZPwTvZHpA9C3NRupkjCzm3M4O8BdmBEtMe4smETrbj0tB3wVm8hLJg0ylLtOjNulvFaWkfz1AtSP5NbLjYyXwV/shJSyT2WtoTA6z3fnq0Mf3hZEoP9rQNvNHGPOnUEtZZsuTtuR6tchXVrxHX6SSqA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=NM59DDRw; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="NM59DDRw" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1780469950; x=1812005950; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=nN9+zsfRheHiwR0iNWCgcstHm1IznAMW4+4pvqexfH0=; b=NM59DDRw+clQwKA73wcK5GBNY+NU1Pdd6DzvntSZ2lVI0oiJC6IU91/S jT9TcJ6WNzPwnDhPvqKGfyH2vyL1o9a+K4hv8NkdyZDQZP/feEPF7EZJN TlzOdPlJCMWYTAjVi5LJvNjyYJ+oYGiync8I25QF6Go8/8meyb1VQdFRA +0QaSv4lOrfHIk7B6mBtKxuEatYLbPZrcwWW7cgYIt8CF9fohw5wCKZQ1 0UooWS5oaaCWYBUASLMWwcVixal7j29pTEplOlWZssVofqDkGy7Dtqc0S u1IgMgiZh8u6JwgAyTVBRmc7bN7QbWJpS4R51vWvdDyd+2OsldOgtamlg A==; X-CSE-ConnectionGUID: uJUwXwksQCSkwNeOf6LMgQ== X-CSE-MsgGUID: allv64AaQBOwW7opxLFwag== X-IronPort-AV: E=Sophos;i="6.24,184,1774335600"; d="scan'208";a="58510248" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 02 Jun 2026 23:59:09 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Tue, 2 Jun 2026 23:59:08 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 2 Jun 2026 23:59:04 -0700 From: Balakrishnan Sambath Date: Wed, 3 Jun 2026 12:28:47 +0530 Subject: [PATCH v6 04/12] media: microchip-isc: fix PM runtime leak in AWB work handler Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260603-microchip-isc-fixes-v6-4-8c3d7474a768@microchip.com> References: <20260603-microchip-isc-fixes-v6-0-8c3d7474a768@microchip.com> In-Reply-To: <20260603-microchip-isc-fixes-v6-0-8c3d7474a768@microchip.com> To: Eugen Hristev , Mauro Carvalho Chehab , Hans Verkuil CC: Laurent Pinchart , Kieran Bingham , Sakari Ailus , Balamanikandan Gunasundar , , , , "Balakrishnan Sambath" X-Mailer: b4 0.14.3 Early return when streaming stops skips pm_runtime_put_sync(), leaking the reference and preventing runtime suspend. Fixes: 91b4e487b0c6 ("media: microchip: add ISC driver as Microchip ISC") Cc: stable@vger.kernel.org Signed-off-by: Balakrishnan Sambath Reviewed-by: Eugen Hristev --- drivers/media/platform/microchip/microchip-isc-base.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/microchip/microchip-isc-base.c b/driver= s/media/platform/microchip/microchip-isc-base.c index b19c5a63b4bd..f61a5d5a3e04 100644 --- a/drivers/media/platform/microchip/microchip-isc-base.c +++ b/drivers/media/platform/microchip/microchip-isc-base.c @@ -1429,7 +1429,7 @@ static void isc_awb_work(struct work_struct *w) /* streaming is not active anymore */ if (isc->stop) { mutex_unlock(&isc->awb_mutex); - return; + goto out_pm_put; } =20 isc_update_profile(isc); @@ -1440,6 +1440,7 @@ static void isc_awb_work(struct work_struct *w) if (ctrls->awb) regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_HISREQ); =20 +out_pm_put: pm_runtime_put_sync(isc->dev); } =20 --=20 2.34.1 From nobody Mon Jun 8 06:36:45 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 880D0400E07; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260603-microchip-isc-fixes-v6-5-8c3d7474a768@microchip.com> References: <20260603-microchip-isc-fixes-v6-0-8c3d7474a768@microchip.com> In-Reply-To: <20260603-microchip-isc-fixes-v6-0-8c3d7474a768@microchip.com> To: Eugen Hristev , Mauro Carvalho Chehab , Hans Verkuil CC: Laurent Pinchart , Kieran Bingham , Sakari Ailus , Balamanikandan Gunasundar , , , , "Balakrishnan Sambath" X-Mailer: b4 0.14.3 Document the driver topology, supported formats, controls, the AWB algorithm, the gamma table layout, and the Microchip-specific custom controls exposed via atmel-isc-media.h. Signed-off-by: Balakrishnan Sambath --- .../userspace-api/media/drivers/index.rst | 1 + .../userspace-api/media/drivers/microchip-isc.rst | 69 ++++++++++++++++++= ++++ MAINTAINERS | 1 + 3 files changed, 71 insertions(+) diff --git a/Documentation/userspace-api/media/drivers/index.rst b/Document= ation/userspace-api/media/drivers/index.rst index 02967c9b18d6..65ef6ba3523e 100644 --- a/Documentation/userspace-api/media/drivers/index.rst +++ b/Documentation/userspace-api/media/drivers/index.rst @@ -34,6 +34,7 @@ For more details see the file COPYING in the source distr= ibution of Linux. imx-uapi mali-c55 max2175 + microchip-isc npcm-video omap3isp-uapi thp7312 diff --git a/Documentation/userspace-api/media/drivers/microchip-isc.rst b/= Documentation/userspace-api/media/drivers/microchip-isc.rst new file mode 100644 index 000000000000..69c7672e122a --- /dev/null +++ b/Documentation/userspace-api/media/drivers/microchip-isc.rst @@ -0,0 +1,69 @@ +.. SPDX-License-Identifier: GPL-2.0 + +Microchip ISC/XISC Driver +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + +The Image Sensor Controller (ISC) on SAMA5D2 and eXtended ISC (XISC) on +SAMA7G5/SAM9X7 provide camera capture with hardware image processing. + +Supported Hardware +------------------ + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +SoC Controller Max Resolution Interface Hue/Saturation +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +SAMA5D2 ISC 2592x1944 12-bit parallel No +SAMA7G5 XISC 3264x2464 12-bit + CSI-2 Yes +SAM9X7 XISC 2560x1920 12-bit + CSI-2 Yes +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +SAM9X7 shares the XISC pipeline with SAMA7G5 but has a smaller internal +line buffer, limiting horizontal resolution to 2560 pixels. + +Controls +-------- + +Standard V4L2 controls: + +* ``V4L2_CID_BRIGHTNESS``: -1024..1023, default 0 +* ``V4L2_CID_CONTRAST``: -2048..2047. Default differs per SoC: + SAMA7G5/SAM9X7 use 16, SAMA5D2 uses 256. +* ``V4L2_CID_GAMMA``: 0..2 selects a preset curve. Indices differ + per SoC: SAMA7G5/SAM9X7 use 0=3D1/2.4, 1=3D1/2.2 (default), 2=3D1/1.8; + SAMA5D2 uses 0=3D1/1.8, 1=3D1/2.0, 2=3D1/2.2 (default). +* ``V4L2_CID_AUTO_WHITE_BALANCE``: Enable kernel Grey World AWB +* ``V4L2_CID_DO_WHITE_BALANCE``: Trigger one-shot AWB + +SAMA7G5/SAM9X7 add: + +* ``V4L2_CID_HUE``: -180..180 degrees +* ``V4L2_CID_SATURATION``: 0..127, default 16 (Q4 fixed-point, 16 =3D 1.0x) + +Custom controls (defined in ``atmel-isc-media.h``): + +* ``ISC_CID_R_GAIN``, ``ISC_CID_B_GAIN``, ``ISC_CID_GR_GAIN``, + ``ISC_CID_GB_GAIN``: WB gains, 0..8191, Q2.9 (512 =3D 1.0x) +* ``ISC_CID_R_OFFSET``, ``ISC_CID_B_OFFSET``, ``ISC_CID_GR_OFFSET``, + ``ISC_CID_GB_OFFSET``: WB offsets, -4096..4095 + +Pipeline +-------- + +Pipeline modules: DPC -> WB -> CFA -> CC -> GAM -> CSC -> CBHS/CBC -> SUB + +* DPC: Defective Pixel Correction (XISC only), black level subtraction + to sensor bit depth, green disparity correction +* WB: White Balance gains/offsets +* CFA: Color Filter Array interpolation (demosaic) +* CC: Color Correction matrix +* GAM: Gamma correction (preset) +* CSC: Color Space Conversion (RGB to YCbCr) +* CBHS: Contrast/Brightness/Hue/Saturation (XISC only), operates on YCbCr +* CBC: Contrast/Brightness (ISC only), operates on YCbCr +* SUB: Chroma subsampling (4:2:2, 4:2:0) + +Pipeline usage depends on input and output formats: + +* Raw Bayer input, RGB output: DPC, WB, CFA, CC, GAM +* Raw Bayer input, YUV output: Full pipeline including CSC, CBHS/CBC, SUB +* Non-RAW input (YUV/RGB sensor): Pipeline bypassed diff --git a/MAINTAINERS b/MAINTAINERS index e08767323763..d4aa7e86e2bd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17057,6 +17057,7 @@ L: linux-media@vger.kernel.org S: Supported F: Documentation/devicetree/bindings/media/atmel,isc.yaml F: Documentation/devicetree/bindings/media/microchip,xisc.yaml +F: Documentation/userspace-api/media/drivers/microchip-isc.rst F: drivers/media/platform/microchip/microchip-isc* F: drivers/media/platform/microchip/microchip-sama*-isc* F: drivers/staging/media/deprecated/atmel/atmel-isc* --=20 2.34.1 From nobody Mon Jun 8 06:36:45 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 552AB4028C4; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260603-microchip-isc-fixes-v6-6-8c3d7474a768@microchip.com> References: <20260603-microchip-isc-fixes-v6-0-8c3d7474a768@microchip.com> In-Reply-To: <20260603-microchip-isc-fixes-v6-0-8c3d7474a768@microchip.com> To: Eugen Hristev , Mauro Carvalho Chehab , Hans Verkuil CC: Laurent Pinchart , Kieran Bingham , Sakari Ailus , Balamanikandan Gunasundar , , , , "Balakrishnan Sambath" X-Mailer: b4 0.14.3 SAM9X7 XISC uses the same image processing pipeline as SAMA7G5 but has a smaller internal line buffer. The reduced RAM constrains the maximum horizontal resolution to 2560 pixels (compared to 3264 on SAMA7G5), resulting in a maximum capture resolution of 2560x1920. Co-developed-by: Balamanikandan Gunasundar Signed-off-by: Balamanikandan Gunasundar Signed-off-by: Balakrishnan Sambath --- drivers/media/platform/microchip/microchip-sama7g5-isc.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/microchip/microchip-sama7g5-isc.c b/dri= vers/media/platform/microchip/microchip-sama7g5-isc.c index ca23e8adecbd..4119cfe12cdf 100644 --- a/drivers/media/platform/microchip/microchip-sama7g5-isc.c +++ b/drivers/media/platform/microchip/microchip-sama7g5-isc.c @@ -55,6 +55,9 @@ #define ISC_SAMA7G5_MAX_SUPPORT_WIDTH 3264 #define ISC_SAMA7G5_MAX_SUPPORT_HEIGHT 2464 =20 +#define ISC_SAM9X7_MAX_SUPPORT_WIDTH 2560 +#define ISC_SAM9X7_MAX_SUPPORT_HEIGHT 1920 + #define ISC_SAMA7G5_PIPELINE \ (WB_ENABLE | CFA_ENABLE | CC_ENABLE | GAM_ENABLES | CSC_ENABLE | \ CBC_ENABLE | SUB422_ENABLE | SUB420_ENABLE) @@ -432,8 +435,13 @@ static int microchip_xisc_probe(struct platform_device= *pdev) isc->gamma_table =3D isc_sama7g5_gamma_table; isc->gamma_max =3D 0; =20 - isc->max_width =3D ISC_SAMA7G5_MAX_SUPPORT_WIDTH; - isc->max_height =3D ISC_SAMA7G5_MAX_SUPPORT_HEIGHT; + if (of_machine_is_compatible("microchip,sam9x7")) { + isc->max_width =3D ISC_SAM9X7_MAX_SUPPORT_WIDTH; + isc->max_height =3D ISC_SAM9X7_MAX_SUPPORT_HEIGHT; + } else { + isc->max_width =3D ISC_SAMA7G5_MAX_SUPPORT_WIDTH; + isc->max_height =3D ISC_SAMA7G5_MAX_SUPPORT_HEIGHT; + } =20 isc->config_dpc =3D isc_sama7g5_config_dpc; isc->config_csc =3D isc_sama7g5_config_csc; --=20 2.34.1 From nobody Mon Jun 8 06:36:45 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E9583FB7FC; Wed, 3 Jun 2026 06:59:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780469965; 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02 Jun 2026 23:59:23 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Tue, 2 Jun 2026 23:59:23 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 2 Jun 2026 23:59:19 -0700 From: Balakrishnan Sambath Date: Wed, 3 Jun 2026 12:28:50 +0530 Subject: [PATCH v6 07/12] media: microchip-isc: configure DPC and pipeline for SAMA7G5 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260603-microchip-isc-fixes-v6-7-8c3d7474a768@microchip.com> References: <20260603-microchip-isc-fixes-v6-0-8c3d7474a768@microchip.com> In-Reply-To: <20260603-microchip-isc-fixes-v6-0-8c3d7474a768@microchip.com> To: Eugen Hristev , Mauro Carvalho Chehab , Hans Verkuil CC: Laurent Pinchart , Kieran Bingham , Sakari Ailus , Balamanikandan Gunasundar , , , , "Balakrishnan Sambath" X-Mailer: b4 0.14.3 Enable DPC black level and green disparity correction for raw Bayer to RGB conversion. Bypass the pipeline for raw Bayer output so software ISPs (libcamera) receive unmodified sensor data. Rename CBC_ENABLE to CBHS_ENABLE to match the SAMA7G5 block name; SAMA5D2's CBC sub-block uses the same bitmap bit. Co-developed-by: Balamanikandan Gunasundar Signed-off-by: Balamanikandan Gunasundar Signed-off-by: Balakrishnan Sambath --- drivers/media/platform/microchip/microchip-isc-base.c | 15 ++++++------= --- drivers/media/platform/microchip/microchip-isc.h | 2 +- drivers/media/platform/microchip/microchip-sama5d2-isc.c | 2 +- drivers/media/platform/microchip/microchip-sama7g5-isc.c | 5 +++-- 4 files changed, 11 insertions(+), 13 deletions(-) diff --git a/drivers/media/platform/microchip/microchip-isc-base.c b/driver= s/media/platform/microchip/microchip-isc-base.c index f61a5d5a3e04..ff920019fe37 100644 --- a/drivers/media/platform/microchip/microchip-isc-base.c +++ b/drivers/media/platform/microchip/microchip-isc-base.c @@ -800,7 +800,7 @@ static int isc_try_configure_pipeline(struct isc_device= *isc) if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { isc->try_config.bits_pipeline =3D CFA_ENABLE | WB_ENABLE | GAM_ENABLES | DPC_BLCENABLE | - CC_ENABLE; + DPC_GDCENABLE | CC_ENABLE; } else { isc->try_config.bits_pipeline =3D 0x0; } @@ -810,7 +810,7 @@ static int isc_try_configure_pipeline(struct isc_device= *isc) if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { isc->try_config.bits_pipeline =3D CFA_ENABLE | CSC_ENABLE | GAM_ENABLES | WB_ENABLE | - SUB420_ENABLE | SUB422_ENABLE | CBC_ENABLE | + SUB420_ENABLE | SUB422_ENABLE | CBHS_ENABLE | DPC_BLCENABLE; } else { isc->try_config.bits_pipeline =3D 0x0; @@ -821,7 +821,7 @@ static int isc_try_configure_pipeline(struct isc_device= *isc) if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { isc->try_config.bits_pipeline =3D CFA_ENABLE | CSC_ENABLE | WB_ENABLE | GAM_ENABLES | - SUB422_ENABLE | CBC_ENABLE | DPC_BLCENABLE; + SUB422_ENABLE | CBHS_ENABLE | DPC_BLCENABLE; } else { isc->try_config.bits_pipeline =3D 0x0; } @@ -833,7 +833,7 @@ static int isc_try_configure_pipeline(struct isc_device= *isc) if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { isc->try_config.bits_pipeline =3D CFA_ENABLE | CSC_ENABLE | WB_ENABLE | GAM_ENABLES | - SUB422_ENABLE | CBC_ENABLE | DPC_BLCENABLE; + SUB422_ENABLE | CBHS_ENABLE | DPC_BLCENABLE; } else { isc->try_config.bits_pipeline =3D 0x0; } @@ -844,16 +844,13 @@ static int isc_try_configure_pipeline(struct isc_devi= ce *isc) if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { isc->try_config.bits_pipeline =3D CFA_ENABLE | CSC_ENABLE | WB_ENABLE | GAM_ENABLES | - CBC_ENABLE | DPC_BLCENABLE; + CBHS_ENABLE | DPC_BLCENABLE; } else { isc->try_config.bits_pipeline =3D 0x0; } break; default: - if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) - isc->try_config.bits_pipeline =3D WB_ENABLE | DPC_BLCENABLE; - else - isc->try_config.bits_pipeline =3D 0x0; + isc->try_config.bits_pipeline =3D 0x0; } =20 /* Tune the pipeline to product specific */ diff --git a/drivers/media/platform/microchip/microchip-isc.h b/drivers/med= ia/platform/microchip/microchip-isc.h index ad4e98a1dd8f..a943b072f6be 100644 --- a/drivers/media/platform/microchip/microchip-isc.h +++ b/drivers/media/platform/microchip/microchip-isc.h @@ -88,7 +88,7 @@ struct isc_format { #define GAM_RENABLE BIT(9) #define VHXS_ENABLE BIT(10) #define CSC_ENABLE BIT(11) -#define CBC_ENABLE BIT(12) +#define CBHS_ENABLE BIT(12) #define SUB422_ENABLE BIT(13) #define SUB420_ENABLE BIT(14) =20 diff --git a/drivers/media/platform/microchip/microchip-sama5d2-isc.c b/dri= vers/media/platform/microchip/microchip-sama5d2-isc.c index 0ddff1e7b0a0..71609a93358a 100644 --- a/drivers/media/platform/microchip/microchip-sama5d2-isc.c +++ b/drivers/media/platform/microchip/microchip-sama5d2-isc.c @@ -54,7 +54,7 @@ =20 #define ISC_SAMA5D2_PIPELINE \ (WB_ENABLE | CFA_ENABLE | CC_ENABLE | GAM_ENABLES | CSC_ENABLE | \ - CBC_ENABLE | SUB422_ENABLE | SUB420_ENABLE) + CBHS_ENABLE | SUB422_ENABLE | SUB420_ENABLE) =20 /* This is a list of the formats that the ISC can *output* */ static const struct isc_format sama5d2_controller_formats[] =3D { diff --git a/drivers/media/platform/microchip/microchip-sama7g5-isc.c b/dri= vers/media/platform/microchip/microchip-sama7g5-isc.c index 4119cfe12cdf..287fc76da479 100644 --- a/drivers/media/platform/microchip/microchip-sama7g5-isc.c +++ b/drivers/media/platform/microchip/microchip-sama7g5-isc.c @@ -59,8 +59,9 @@ #define ISC_SAM9X7_MAX_SUPPORT_HEIGHT 1920 =20 #define ISC_SAMA7G5_PIPELINE \ - (WB_ENABLE | CFA_ENABLE | CC_ENABLE | GAM_ENABLES | CSC_ENABLE | \ - CBC_ENABLE | SUB422_ENABLE | SUB420_ENABLE) + (DPC_GDCENABLE | DPC_BLCENABLE | \ + WB_ENABLE | CFA_ENABLE | CC_ENABLE | GAM_ENABLES | CSC_ENABLE | \ + CBHS_ENABLE | SUB422_ENABLE | SUB420_ENABLE) =20 /* This is a list of the formats that the ISC can *output* */ static const struct isc_format sama7g5_controller_formats[] =3D { --=20 2.34.1 From nobody Mon Jun 8 06:36:45 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A65D3F6614; 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X-CSE-ConnectionGUID: ODQ1mTl1QfmHVo+OD6Pyrg== X-CSE-MsgGUID: nLDel/tWTDy5OSJC94Sw8g== X-IronPort-AV: E=Sophos;i="6.24,184,1774335600"; d="scan'208";a="58510261" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jun 2026 23:59:29 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.87.71) by chn-vm-ex3.mchp-main.com (10.10.87.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.41; Tue, 2 Jun 2026 23:59:28 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 2 Jun 2026 23:59:24 -0700 From: Balakrishnan Sambath Date: Wed, 3 Jun 2026 12:28:51 +0530 Subject: [PATCH v6 08/12] media: microchip-isc: add gamma 1.8 and 2.4 correction curves Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260603-microchip-isc-fixes-v6-8-8c3d7474a768@microchip.com> References: <20260603-microchip-isc-fixes-v6-0-8c3d7474a768@microchip.com> In-Reply-To: <20260603-microchip-isc-fixes-v6-0-8c3d7474a768@microchip.com> To: Eugen Hristev , Mauro Carvalho Chehab , Hans Verkuil CC: Laurent Pinchart , Kieran Bingham , Sakari Ailus , Balamanikandan Gunasundar , , , , "Balakrishnan Sambath" X-Mailer: b4 0.14.3 Display profiles for older macOS content (gamma 1.8) and HDR pipelines (gamma 2.4) need curves not covered by the existing sRGB 2.2 default. Add the two extra curves to the SAMA7G5 table so userspace can pick a curve matching the target display profile. The two SoCs put gamma 1/2.2 at different indices in their tables (SAMA5D2 at index 2, SAMA7G5 at index 1), so introduce a gamma_default field on struct isc_device and let each platform set it. The SAMA5D2 default of index 2 matches the historical behaviour. Co-developed-by: Balamanikandan Gunasundar Signed-off-by: Balamanikandan Gunasundar Signed-off-by: Balakrishnan Sambath --- .../media/platform/microchip/microchip-isc-base.c | 2 +- drivers/media/platform/microchip/microchip-isc.h | 1 + .../platform/microchip/microchip-sama5d2-isc.c | 2 + .../platform/microchip/microchip-sama7g5-isc.c | 56 ++++++++++++++++--= ---- 4 files changed, 46 insertions(+), 15 deletions(-) diff --git a/drivers/media/platform/microchip/microchip-isc-base.c b/driver= s/media/platform/microchip/microchip-isc-base.c index ff920019fe37..04187127070d 100644 --- a/drivers/media/platform/microchip/microchip-isc-base.c +++ b/drivers/media/platform/microchip/microchip-isc-base.c @@ -1648,7 +1648,7 @@ static int isc_ctrl_init(struct isc_device *isc) =20 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -1024, 1023, 1, 0); v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, isc->gamma_max, 1, - isc->gamma_max); + isc->gamma_default); isc->awb_ctrl =3D v4l2_ctrl_new_std(hdl, &isc_awb_ops, V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1); diff --git a/drivers/media/platform/microchip/microchip-isc.h b/drivers/med= ia/platform/microchip/microchip-isc.h index a943b072f6be..2282ef7dd596 100644 --- a/drivers/media/platform/microchip/microchip-isc.h +++ b/drivers/media/platform/microchip/microchip-isc.h @@ -342,6 +342,7 @@ struct isc_device { /* pointer to the defined gamma table */ const u32 (*gamma_table)[GAMMA_ENTRIES]; u32 gamma_max; + u32 gamma_default; =20 u32 max_width; u32 max_height; diff --git a/drivers/media/platform/microchip/microchip-sama5d2-isc.c b/dri= vers/media/platform/microchip/microchip-sama5d2-isc.c index 71609a93358a..9fa8413c74c7 100644 --- a/drivers/media/platform/microchip/microchip-sama5d2-isc.c +++ b/drivers/media/platform/microchip/microchip-sama5d2-isc.c @@ -442,6 +442,8 @@ static int microchip_isc_probe(struct platform_device *= pdev) =20 isc->gamma_table =3D isc_sama5d2_gamma_table; isc->gamma_max =3D 2; + /* Index 2 in the SAMA5D2 table is gamma 1/2.2 (sRGB). */ + isc->gamma_default =3D 2; =20 isc->max_width =3D ISC_SAMA5D2_MAX_SUPPORT_WIDTH; isc->max_height =3D ISC_SAMA5D2_MAX_SUPPORT_HEIGHT; diff --git a/drivers/media/platform/microchip/microchip-sama7g5-isc.c b/dri= vers/media/platform/microchip/microchip-sama7g5-isc.c index 287fc76da479..ac21fe1dade0 100644 --- a/drivers/media/platform/microchip/microchip-sama7g5-isc.c +++ b/drivers/media/platform/microchip/microchip-sama7g5-isc.c @@ -320,21 +320,47 @@ static void isc_sama7g5_adapt_pipeline(struct isc_dev= ice *isc) isc->try_config.bits_pipeline &=3D ISC_SAMA7G5_PIPELINE; } =20 -/* Gamma table with gamma 1/2.2 */ +/* Gamma tables with gamma values 0.42, 0.45(Default), 0.56 */ static const u32 isc_sama7g5_gamma_table[][GAMMA_ENTRIES] =3D { - /* index 0 --> gamma bipartite */ + /* index 0 --> gamma bipartite 1/2.4(=3D0.42) */ { - 0x980, 0x4c0320, 0x650260, 0x7801e0, 0x8701a0, 0x940180, - 0xa00160, 0xab0120, 0xb40120, 0xbd0120, 0xc60100, 0xce0100, - 0xd600e0, 0xdd00e0, 0xe400e0, 0xeb00c0, 0xf100c0, 0xf700c0, - 0xfd00c0, 0x10300a0, 0x10800c0, 0x10e00a0, 0x11300a0, 0x11800a0, - 0x11d00a0, 0x12200a0, 0x12700a0, 0x12c0080, 0x13000a0, 0x1350080, - 0x13900a0, 0x13e0080, 0x1420076, 0x17d0062, 0x1ae0054, 0x1d8004a, - 0x1fd0044, 0x21f003e, 0x23e003a, 0x25b0036, 0x2760032, 0x28f0030, - 0x2a7002e, 0x2be002c, 0x2d4002c, 0x2ea0028, 0x2fe0028, 0x3120026, - 0x3250024, 0x3370024, 0x3490022, 0x35a0022, 0x36b0020, 0x37b0020, - 0x38b0020, 0x39b001e, 0x3aa001e, 0x3b9001c, 0x3c7001c, 0x3d5001c, - 0x3e3001c, 0x3f1001c, 0x3ff001a, 0x40c001a }, + 0x940, 0x4b0310, 0x630250, 0x7601d0, 0x840190, 0x910170, + 0x9d0150, 0xa80110, 0xb10110, 0xba0110, 0xc300f0, 0xcb00f0, + 0xd300e0, 0xda00e0, 0xe100c0, 0xe800c0, 0xee00c0, 0xf400c0, + 0xfa00a0, 0x10000a0, 0x10500a0, 0x10b00a0, 0x11000a0, 0x11500a0, + 0x11a0080, 0x11f0080, 0x1240080, 0x1290080, 0x12e0080, 0x1330070, + 0x1380070, 0x13c0070, 0x1410070, 0x17a0060, 0x1aa0052, 0x1d40046, + 0x1f90042, 0x21b003c, 0x23a0038, 0x2570034, 0x2720030, 0x28b002e, + 0x2a3002c, 0x2ba002a, 0x2d0002a, 0x2e60028, 0x2fa0026, 0x30e0026, + 0x3210024, 0x3330022, 0x3450022, 0x3560020, 0x3670020, 0x3770020, + 0x387001e, 0x396001e, 0x3a5001c, 0x3b3001c, 0x3c1001c, 0x3cf001a, + 0x3dd001a, 0x3eb0018, 0x3f90018, 0x4070016 }, + /* index 1 --> gamma bipartite 1/2.2(=3D0.45) */ + { + 0x980, 0x4c0320, 0x650260, 0x7801e0, 0x8701a0, 0x940180, + 0xa00160, 0xab0120, 0xb40120, 0xbd0120, 0xc60100, 0xce0100, + 0xd600e0, 0xdd00e0, 0xe400e0, 0xeb00c0, 0xf100c0, 0xf700c0, + 0xfd00c0, 0x10300a0, 0x10800c0, 0x10e00a0, 0x11300a0, 0x11800a0, + 0x11d00a0, 0x12200a0, 0x12700a0, 0x12c0080, 0x13000a0, 0x1350080, + 0x13900a0, 0x13e0080, 0x1420076, 0x17d0062, 0x1ae0054, 0x1d8004a, + 0x1fd0044, 0x21f003e, 0x23e003a, 0x25b0036, 0x2760032, 0x28f0030, + 0x2a7002e, 0x2be002c, 0x2d4002c, 0x2ea0028, 0x2fe0028, 0x3120026, + 0x3250024, 0x3370024, 0x3490022, 0x35a0022, 0x36b0020, 0x37b0020, + 0x38b0020, 0x39b001e, 0x3aa001e, 0x3b9001c, 0x3c7001c, 0x3d5001c, + 0x3e3001c, 0x3f1001c, 0x3ff001a, 0x40c001a }, + /* index 2 --> gamma bipartite 1/1.8(=3D0.56) */ + { + 0xa62, 0x4f0350, 0x680280, 0x7e0200, 0x8d01c0, 0x9a01a0, + 0xa50180, 0xb00140, 0xb90140, 0xc20120, 0xcb0120, 0xd30100, + 0xdb0100, 0xe300e0, 0xea00e0, 0xf100e0, 0xf700c0, 0xfd00c0, + 0x10300c0, 0x10900a0, 0x10e00a0, 0x11400a0, 0x11900a0, 0x11e00a0, + 0x12300a0, 0x12800a0, 0x12d0080, 0x1320080, 0x1370080, 0x13c0080, + 0x1410080, 0x1460080, 0x14a0070, 0x1830060, 0x1b40052, 0x1df0048, + 0x2040042, 0x2250040, 0x2440038, 0x2600036, 0x27b0032, 0x2940030, + 0x2ac002e, 0x2c4002c, 0x2da002a, 0x2f0002a, 0x3050028, 0x3190026, + 0x32c0026, 0x33e0024, 0x3500024, 0x3610022, 0x3720020, 0x3820020, + 0x3920020, 0x3a2001e, 0x3b1001e, 0x3c0001c, 0x3ce001c, 0x3dc001c, + 0x3ea001a, 0x3f8001a, 0x4060018, 0x4130018 }, }; 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Tue, 2 Jun 2026 23:59:33 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 2 Jun 2026 23:59:29 -0700 From: Balakrishnan Sambath Date: Wed, 3 Jun 2026 12:28:52 +0530 Subject: [PATCH v6 09/12] media: microchip-isc: add SAMA7G5 hue and saturation controls Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260603-microchip-isc-fixes-v6-9-8c3d7474a768@microchip.com> References: <20260603-microchip-isc-fixes-v6-0-8c3d7474a768@microchip.com> In-Reply-To: <20260603-microchip-isc-fixes-v6-0-8c3d7474a768@microchip.com> To: Eugen Hristev , Mauro Carvalho Chehab , Hans Verkuil CC: Laurent Pinchart , Kieran Bingham , Sakari Ailus , Balamanikandan Gunasundar , , , , "Balakrishnan Sambath" X-Mailer: b4 0.14.3 The CBHS (Contrast/Brightness/Hue/Saturation) block on SAMA7G5 operates in YCbCr space; expose hue and saturation as V4L2 controls. Hue and saturation act on chroma, so they are active only when the output format is YUV. The SAMA5D2 has only the CBC block (no hue/saturation), so the controls are gated on a new has_cbhs flag. Saturation uses the Q4 fixed-point range 0..127 with default 16 (1.0x) directly matching the CBHS_SAT register field. The control state is initialised to neutral at probe so the first config_cbc() write after streaming starts does not produce a grayscale image. Co-developed-by: Balamanikandan Gunasundar Signed-off-by: Balamanikandan Gunasundar Signed-off-by: Balakrishnan Sambath --- .../media/platform/microchip/microchip-isc-base.c | 70 ++++++++++++++++++= +++- .../media/platform/microchip/microchip-isc-regs.h | 11 ++-- drivers/media/platform/microchip/microchip-isc.h | 7 +++ .../platform/microchip/microchip-sama5d2-isc.c | 3 +- .../platform/microchip/microchip-sama7g5-isc.c | 9 +-- 5 files changed, 90 insertions(+), 10 deletions(-) diff --git a/drivers/media/platform/microchip/microchip-isc-base.c b/driver= s/media/platform/microchip/microchip-isc-base.c index 04187127070d..3a941757906a 100644 --- a/drivers/media/platform/microchip/microchip-isc-base.c +++ b/drivers/media/platform/microchip/microchip-isc-base.c @@ -859,6 +859,46 @@ static int isc_try_configure_pipeline(struct isc_devic= e *isc) return 0; } =20 +static bool isc_format_is_yuv(u32 fourcc) +{ + switch (fourcc) { + case V4L2_PIX_FMT_YUV420: + case V4L2_PIX_FMT_YUV422P: + case V4L2_PIX_FMT_YUYV: + case V4L2_PIX_FMT_UYVY: + case V4L2_PIX_FMT_VYUY: + return true; + default: + return false; + } +} + +/* + * isc_update_cbhs_ctrls() - Activate/deactivate CBHS controls + * + * Called from isc_set_fmt(), isc_link_validate(), and isc_ctrl_init(). + * At isc_ctrl_init() time isc->config.bits_pipeline is zero (no format + * has been negotiated yet), so all CBHS controls are initially marked + * inactive. They become active once a format that includes CBHS in the + * pipeline is configured via VIDIOC_S_FMT or link validation. Hue and + * saturation operate in YCbCr space, so they activate only when the + * output format is YUV. + */ +static void isc_update_cbhs_ctrls(struct isc_device *isc) +{ + bool cbhs_active =3D isc->config.bits_pipeline & CBHS_ENABLE; + bool chroma_active =3D cbhs_active && isc_format_is_yuv(isc->config.fourc= c); + + if (isc->brightness_ctrl) + v4l2_ctrl_activate(isc->brightness_ctrl, cbhs_active); + if (isc->contrast_ctrl) + v4l2_ctrl_activate(isc->contrast_ctrl, cbhs_active); + if (isc->hue_ctrl) + v4l2_ctrl_activate(isc->hue_ctrl, chroma_active); + if (isc->saturation_ctrl) + v4l2_ctrl_activate(isc->saturation_ctrl, chroma_active); +} + static int isc_try_fmt(struct isc_device *isc, struct v4l2_format *f) { struct v4l2_pix_format *pixfmt =3D &f->fmt.pix; @@ -902,6 +942,7 @@ static int isc_set_fmt(struct isc_device *isc, struct v= 4l2_format *f) /* make the try configuration active */ isc->config =3D isc->try_config; isc->fmt =3D isc->try_fmt; + isc_update_cbhs_ctrls(isc); =20 dev_dbg(isc->dev, "ISC set_fmt to %.4s @%dx%d\n", (char *)&f->fmt.pix.pixelformat, @@ -989,6 +1030,7 @@ static int isc_link_validate(struct media_link *link) return ret; =20 isc->config =3D isc->try_config; + isc_update_cbhs_ctrls(isc); =20 dev_dbg(isc->dev, "New ISC configuration in place\n"); =20 @@ -1457,6 +1499,14 @@ static int isc_s_ctrl(struct v4l2_ctrl *ctrl) case V4L2_CID_CONTRAST: ctrls->contrast =3D ctrl->val & ISC_CBC_CONTRAST_MASK; break; + case V4L2_CID_HUE: + if (isc->has_cbhs) + ctrls->hue =3D ctrl->val & ISC_CBHS_HUE_MASK; + break; + case V4L2_CID_SATURATION: + if (isc->has_cbhs) + ctrls->saturation =3D ctrl->val & ISC_CBHS_SAT_MASK; + break; case V4L2_CID_GAMMA: ctrls->gamma_index =3D ctrl->val; break; @@ -1646,7 +1696,24 @@ static int isc_ctrl_init(struct isc_device *isc) =20 ctrls->brightness =3D 0; =20 - v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -1024, 1023, 1, 0); + isc->brightness_ctrl =3D v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, + -1024, 1023, 1, 0); + if (isc->has_cbhs) { + /* + * CBHS_HUE is a signed 9-bit value in degrees. + * CBHS_SAT is Q4 unsigned 7-bit, 16 =3D 1.0x. + * Initialize the kernel-side state to neutral here so the + * first config_cbc() call after streaming starts does not + * write zero (grayscale) to the hardware. + */ + ctrls->hue =3D 0; + ctrls->saturation =3D 16; + isc->hue_ctrl =3D v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HUE, + -180, 180, 1, 0); + isc->saturation_ctrl =3D v4l2_ctrl_new_std(hdl, ops, + V4L2_CID_SATURATION, + 0, 127, 1, 16); + } v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, isc->gamma_max, 1, isc->gamma_default); isc->awb_ctrl =3D v4l2_ctrl_new_std(hdl, &isc_awb_ops, @@ -1665,6 +1732,7 @@ static int isc_ctrl_init(struct isc_device *isc) } =20 v4l2_ctrl_activate(isc->do_wb_ctrl, false); + isc_update_cbhs_ctrls(isc); =20 isc->r_gain_ctrl =3D v4l2_ctrl_new_custom(hdl, &isc_r_gain_ctrl, NULL); isc->b_gain_ctrl =3D v4l2_ctrl_new_custom(hdl, &isc_b_gain_ctrl, NULL); diff --git a/drivers/media/platform/microchip/microchip-isc-regs.h b/driver= s/media/platform/microchip/microchip-isc-regs.h index e77e1d9a1db8..7f5c2e50e74b 100644 --- a/drivers/media/platform/microchip/microchip-isc-regs.h +++ b/drivers/media/platform/microchip/microchip-isc-regs.h @@ -268,10 +268,13 @@ #define ISC_CBC_CONTRAST 0x000003c0 #define ISC_CBC_CONTRAST_MASK GENMASK(11, 0) =20 -/* Hue Register */ -#define ISC_CBCHS_HUE 0x4e0 -/* Saturation Register */ -#define ISC_CBCHS_SAT 0x4e4 +/* Hue Register: signed 9-bit two's complement, covers -180 to +180 degree= s */ +#define ISC_CBHS_HUE 0x4e0 +#define ISC_CBHS_HUE_MASK GENMASK(8, 0) + +/* Saturation Register: unsigned Q4 fixed-point (1.0 =3D 16, V4L2 range 0.= .127) */ +#define ISC_CBHS_SAT 0x4e4 +#define ISC_CBHS_SAT_MASK GENMASK(6, 0) =20 /* Offset for SUB422 register specific to sama5d2 product */ #define ISC_SAMA5D2_SUB422_OFFSET 0 diff --git a/drivers/media/platform/microchip/microchip-isc.h b/drivers/med= ia/platform/microchip/microchip-isc.h index 2282ef7dd596..1ecefe990f00 100644 --- a/drivers/media/platform/microchip/microchip-isc.h +++ b/drivers/media/platform/microchip/microchip-isc.h @@ -139,6 +139,8 @@ struct isc_ctrls { =20 u32 brightness; u32 contrast; + u32 hue; + u32 saturation; u8 gamma_index; #define ISC_WB_NONE 0 #define ISC_WB_AUTO 1 @@ -336,6 +338,10 @@ struct isc_device { struct v4l2_ctrl *b_off_ctrl; struct v4l2_ctrl *gr_off_ctrl; struct v4l2_ctrl *gb_off_ctrl; + struct v4l2_ctrl *brightness_ctrl; + struct v4l2_ctrl *contrast_ctrl; + struct v4l2_ctrl *hue_ctrl; + struct v4l2_ctrl *saturation_ctrl; }; =20 #define GAMMA_ENTRIES 64 @@ -343,6 +349,7 @@ struct isc_device { const u32 (*gamma_table)[GAMMA_ENTRIES]; u32 gamma_max; u32 gamma_default; + bool has_cbhs; =20 u32 max_width; u32 max_height; diff --git a/drivers/media/platform/microchip/microchip-sama5d2-isc.c b/dri= vers/media/platform/microchip/microchip-sama5d2-isc.c index 9fa8413c74c7..4b8279fba560 100644 --- a/drivers/media/platform/microchip/microchip-sama5d2-isc.c +++ b/drivers/media/platform/microchip/microchip-sama5d2-isc.c @@ -264,7 +264,8 @@ static void isc_sama5d2_config_ctrls(struct isc_device = *isc, =20 ctrls->contrast =3D 256; =20 - v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 256); + isc->contrast_ctrl =3D v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, + -2048, 2047, 1, 256); } =20 static void isc_sama5d2_config_dpc(struct isc_device *isc) diff --git a/drivers/media/platform/microchip/microchip-sama7g5-isc.c b/dri= vers/media/platform/microchip/microchip-sama7g5-isc.c index ac21fe1dade0..e6ccdd465805 100644 --- a/drivers/media/platform/microchip/microchip-sama7g5-isc.c +++ b/drivers/media/platform/microchip/microchip-sama7g5-isc.c @@ -257,9 +257,8 @@ static void isc_sama7g5_config_cbc(struct isc_device *i= sc) /* Configure what is set via v4l2 ctrls */ regmap_write(regmap, ISC_CBC_BRIGHT + isc->offsets.cbc, isc->ctrls.bright= ness); regmap_write(regmap, ISC_CBC_CONTRAST + isc->offsets.cbc, isc->ctrls.cont= rast); - /* Configure Hue and Saturation as neutral midpoint */ - regmap_write(regmap, ISC_CBCHS_HUE, 0); - regmap_write(regmap, ISC_CBCHS_SAT, (1 << 4)); + regmap_write(regmap, ISC_CBHS_HUE, isc->ctrls.hue); + regmap_write(regmap, ISC_CBHS_SAT, isc->ctrls.saturation); } =20 static void isc_sama7g5_config_cc(struct isc_device *isc) @@ -283,7 +282,8 @@ static void isc_sama7g5_config_ctrls(struct isc_device = *isc, =20 ctrls->contrast =3D 16; =20 - v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 16); + isc->contrast_ctrl =3D v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, + -2048, 2047, 1, 16); } =20 static void isc_sama7g5_config_dpc(struct isc_device *isc) @@ -463,6 +463,7 @@ static int microchip_xisc_probe(struct platform_device = *pdev) isc->gamma_max =3D 2; /* Index 1 in the SAMA7G5 table is gamma 1/2.2 (sRGB). */ isc->gamma_default =3D 1; + isc->has_cbhs =3D true; =20 if (of_machine_is_compatible("microchip,sam9x7")) { isc->max_width =3D ISC_SAM9X7_MAX_SUPPORT_WIDTH; --=20 2.34.1 From nobody Mon Jun 8 06:36:45 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D888409131; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260603-microchip-isc-fixes-v6-10-8c3d7474a768@microchip.com> References: <20260603-microchip-isc-fixes-v6-0-8c3d7474a768@microchip.com> In-Reply-To: <20260603-microchip-isc-fixes-v6-0-8c3d7474a768@microchip.com> To: Eugen Hristev , Mauro Carvalho Chehab , Hans Verkuil CC: Laurent Pinchart , Kieran Bingham , Sakari Ailus , Balamanikandan Gunasundar , , , , "Balakrishnan Sambath" X-Mailer: b4 0.14.3 Bright highlights dominate the unweighted pixel-count average and bias grey-world estimates toward overexposed regions. Replace pixel counts with intensity-weighted averages and add 2% outlier rejection at the histogram tails so saturated highlights and the noise floor do not dominate the gain calculation. Also reset the new per-channel histogram statistics in isc_reset_awb_ctrls() so a fresh streaming session does not feed the first AWB cycle with stale values from a previous session. Co-developed-by: Balamanikandan Gunasundar Signed-off-by: Balamanikandan Gunasundar Signed-off-by: Balakrishnan Sambath --- .../media/platform/microchip/microchip-isc-base.c | 180 +++++++++++++++--= ---- drivers/media/platform/microchip/microchip-isc.h | 2 + 2 files changed, 134 insertions(+), 48 deletions(-) diff --git a/drivers/media/platform/microchip/microchip-isc-base.c b/driver= s/media/platform/microchip/microchip-isc-base.c index 3a941757906a..6ebbb8adea45 100644 --- a/drivers/media/platform/microchip/microchip-isc-base.c +++ b/drivers/media/platform/microchip/microchip-isc-base.c @@ -39,6 +39,12 @@ (((mbus_code) =3D=3D MEDIA_BUS_FMT_Y10_1X10) | \ (((mbus_code) =3D=3D MEDIA_BUS_FMT_Y8_1X8))) =20 +/* 4.0 in Q9 fixed-point: cap grey-world correction at 4x. */ +#define ISC_AWB_GW_GAIN_MAX (4u << 9) + +/* Outlier rejection: skip darkest/brightest 2% of histogram. */ +#define ISC_AWB_OUTLIER_DIV 50 + static inline void isc_update_v4l2_ctrls(struct isc_device *isc) { struct isc_ctrls *ctrls =3D &isc->ctrls; @@ -82,14 +88,24 @@ static inline void isc_update_awb_ctrls(struct isc_devi= ce *isc) =20 static inline void isc_reset_awb_ctrls(struct isc_device *isc) { + struct isc_ctrls *ctrls =3D &isc->ctrls; unsigned int c; =20 for (c =3D ISC_HIS_CFG_MODE_GR; c <=3D ISC_HIS_CFG_MODE_B; c++) { /* gains have a fixed point at 9 decimals */ - isc->ctrls.gain[c] =3D 1 << 9; + ctrls->gain[c] =3D 1 << 9; /* offsets are in 2's complements */ - isc->ctrls.offset[c] =3D 0; + ctrls->offset[c] =3D 0; } + + /* + * Reset histogram statistics so the first AWB cycle of a new + * streaming session does not feed isc_wb_update with stale + * values left over from a previous session. + */ + memset(ctrls->channel_avg, 0, sizeof(ctrls->channel_avg)); + memset(ctrls->total_pixels, 0, sizeof(ctrls->total_pixels)); + memset(ctrls->hist_minmax, 0, sizeof(ctrls->hist_minmax)); } =20 static int isc_queue_setup(struct vb2_queue *vq, @@ -1276,6 +1292,11 @@ static void isc_hist_count(struct isc_device *isc, u= 32 *min, u32 *max) u32 *hist_count =3D &ctrls->hist_count[ctrls->hist_id]; u32 *hist_entry =3D &ctrls->hist_entry[0]; u32 i; + u32 total_pixels; + u32 dark_threshold, bright_threshold; + u32 cumulative; + u64 weighted_sum; + u32 pixel_count; =20 *min =3D 0; *max =3D HIST_ENTRIES; @@ -1283,44 +1304,98 @@ static void isc_hist_count(struct isc_device *isc, = u32 *min, u32 *max) regmap_bulk_read(regmap, ISC_HIS_ENTRY + isc->offsets.his_entry, hist_entry, HIST_ENTRIES); =20 - *hist_count =3D 0; - /* - * we deliberately ignore the end of the histogram, - * the most white pixels - */ + /* Calculate total pixels */ + total_pixels =3D 0; + for (i =3D 0; i < HIST_ENTRIES; i++) + total_pixels +=3D hist_entry[i]; + + /* Handle empty histogram case */ + if (total_pixels =3D=3D 0) { + *hist_count =3D 0; + ctrls->channel_avg[ctrls->hist_id] =3D 256; /* Default middle value */ + ctrls->total_pixels[ctrls->hist_id] =3D 0; + *min =3D 1; + *max =3D HIST_ENTRIES - 1; + dev_dbg(isc->dev, + "isc wb: no pixels in histogram for channel %u\n", + ctrls->hist_id); + return; + } + + /* Outlier rejection: skip darkest/brightest 2% of histogram */ + dark_threshold =3D total_pixels / ISC_AWB_OUTLIER_DIV; + bright_threshold =3D total_pixels / ISC_AWB_OUTLIER_DIV; + cumulative =3D 0; + + /* Find effective minimum (skip dark noise) */ + *min =3D 1; for (i =3D 1; i < HIST_ENTRIES; i++) { - if (*hist_entry && !*min) + cumulative +=3D hist_entry[i]; + if (cumulative > dark_threshold) { *min =3D i; - if (*hist_entry) + break; + } + } + + /* Find effective maximum (skip bright saturation) */ + cumulative =3D 0; + *max =3D HIST_ENTRIES - 1; + for (i =3D HIST_ENTRIES - 1; i > *min; i--) { + cumulative +=3D hist_entry[i]; + if (cumulative > bright_threshold) { *max =3D i; - *hist_count +=3D i * (*hist_entry++); + break; + } } =20 - if (!*min) - *min =3D 1; + /* Ensure reasonable range */ + if (*max <=3D *min) { + *min =3D HIST_ENTRIES / 4; + *max =3D (HIST_ENTRIES * 3) / 4; + } + + /* Calculate both pixel count and weighted average for useful range */ + *hist_count =3D 0; + weighted_sum =3D 0; + + for (i =3D *min; i <=3D *max; i++) { + pixel_count =3D hist_entry[i]; + *hist_count +=3D pixel_count; + weighted_sum +=3D (u64)i * pixel_count; + } =20 - dev_dbg(isc->dev, "isc wb: hist_id %u, hist_count %u", - ctrls->hist_id, *hist_count); + /* Store total useful pixels for this channel */ + ctrls->total_pixels[ctrls->hist_id] =3D *hist_count; + + if (*hist_count > 0) + ctrls->channel_avg[ctrls->hist_id] =3D + div64_u64(weighted_sum, *hist_count); + else + ctrls->channel_avg[ctrls->hist_id] =3D 256; + + dev_dbg(isc->dev, + "isc wb: hist_id %u, avg %u, count %u, range [%u,%u], total %u\n", + ctrls->hist_id, ctrls->channel_avg[ctrls->hist_id], + *hist_count, *min, *max, total_pixels); } =20 static void isc_wb_update(struct isc_ctrls *ctrls) { struct isc_device *isc =3D container_of(ctrls, struct isc_device, ctrls); - u32 *hist_count =3D &ctrls->hist_count[0]; u32 c, offset[4]; u64 avg =3D 0; - /* We compute two gains, stretch gain and grey world gain */ - u32 s_gain[4], gw_gain[4]; + u32 gain, gw_gain, s_gain; + u32 min_pixels; + u32 frame_pixels; =20 /* * According to Grey World, we need to set gains for R/B to normalize * them towards the green channel. - * Thus we want to keep Green as fixed and adjust only Red/Blue - * Compute the average of the both green channels first + * Thus we want to keep Green as fixed and adjust only Red/Blue. + * Compute the average of the both green channels first. */ - avg =3D (u64)hist_count[ISC_HIS_CFG_MODE_GR] + - (u64)hist_count[ISC_HIS_CFG_MODE_GB]; - avg >>=3D 1; + avg =3D (ctrls->channel_avg[ISC_HIS_CFG_MODE_GR] + + ctrls->channel_avg[ISC_HIS_CFG_MODE_GB]) >> 1; =20 dev_dbg(isc->dev, "isc wb: green components average %llu\n", avg); =20 @@ -1328,7 +1403,23 @@ static void isc_wb_update(struct isc_ctrls *ctrls) if (!avg) return; =20 + /* + * Require a minimum pixel count for both black-level offset and + * grey-world gain: 1/64 of the frame area, which equals ~6.25% of + * one Bayer channel's expected pixel count. This scales with sensor + * resolution and prevents noise-dominated histograms (from very small + * crops or a nearly-empty frame) from producing wild corrections. + * A floor of 64 ensures the guard is non-zero for tiny crops. + */ + frame_pixels =3D isc->fmt.fmt.pix.width * isc->fmt.fmt.pix.height; + min_pixels =3D frame_pixels ? max(frame_pixels >> 6, 64u) : 64u; + for (c =3D ISC_HIS_CFG_MODE_GR; c <=3D ISC_HIS_CFG_MODE_B; c++) { + u32 hist_min =3D ctrls->hist_minmax[c][HIST_MIN_INDEX]; + u32 hist_max =3D ctrls->hist_minmax[c][HIST_MAX_INDEX]; + u32 channel_avg =3D ctrls->channel_avg[c]; + u32 total_pixels =3D ctrls->total_pixels[c]; + /* * the color offset is the minimum value of the histogram. * we stretch this color to the full range by substracting @@ -1354,40 +1445,33 @@ static void isc_wb_update(struct isc_ctrls *ctrls) ctrls->offset[c] =3D -ctrls->offset[c]; =20 /* - * the stretch gain is the total number of histogram bins - * divided by the actual range of color component (Max - Min) - * If we compute gain like this, the actual color component - * will be stretched to the full histogram. - * We need to shift 9 bits for precision, we have 9 bits for - * decimals + * Stretch gain: scale the histogram range [hist_min, hist_max] + * to the full 512-bin span. Result is in Q9 fixed-point + * (1.0 =3D 512). */ - s_gain[c] =3D (HIST_ENTRIES << 9) / - (ctrls->hist_minmax[c][HIST_MAX_INDEX] - - ctrls->hist_minmax[c][HIST_MIN_INDEX] + 1); + s_gain =3D (HIST_ENTRIES << 9) / (hist_max - hist_min + 1); =20 /* - * Now we have to compute the gain w.r.t. the average. - * Add/lose gain to the component towards the average. - * If it happens that the component is zero, use the - * fixed point value : 1.0 gain. + * Grey-world gain: scale each channel towards the green + * average. Require a minimum pixel count so noise-dominated + * channels do not produce wild corrections. */ - if (hist_count[c]) - gw_gain[c] =3D div_u64(avg << 9, hist_count[c]); + if (channel_avg > 0 && total_pixels >=3D min_pixels) + gw_gain =3D div64_u64((avg << 9), channel_avg); else - gw_gain[c] =3D 1 << 9; + gw_gain =3D 1 << 9; =20 - dev_dbg(isc->dev, - "isc wb: component %d, s_gain %u, gw_gain %u\n", - c, s_gain[c], gw_gain[c]); - /* multiply both gains and adjust for decimals */ - ctrls->gain[c] =3D s_gain[c] * gw_gain[c]; - ctrls->gain[c] >>=3D 9; + /* Cap grey-world correction at 4x to avoid over-amplification. */ + gw_gain =3D min_t(u32, gw_gain, ISC_AWB_GW_GAIN_MAX); =20 - /* make sure we are not out of range */ - ctrls->gain[c] =3D clamp_val(ctrls->gain[c], 0, GENMASK(12, 0)); + /* Combine stretch and grey-world gains; result stays in Q9. */ + gain =3D (s_gain * gw_gain) >> 9; =20 - dev_dbg(isc->dev, "isc wb: component %d, final gain %u\n", - c, ctrls->gain[c]); + ctrls->gain[c] =3D clamp_val(gain, 0, GENMASK(12, 0)); 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Signed-off-by: Balakrishnan Sambath --- drivers/media/platform/microchip/microchip-isc-base.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/microchip/microchip-isc-base.c b/driver= s/media/platform/microchip/microchip-isc-base.c index 6ebbb8adea45..621d90afe730 100644 --- a/drivers/media/platform/microchip/microchip-isc-base.c +++ b/drivers/media/platform/microchip/microchip-isc-base.c @@ -1467,11 +1467,20 @@ static void isc_wb_update(struct isc_ctrls *ctrls) /* Combine stretch and grey-world gains; result stays in Q9. */ gain =3D (s_gain * gw_gain) >> 9; =20 - ctrls->gain[c] =3D clamp_val(gain, 0, GENMASK(12, 0)); + /* + * Smooth gain updates with an exponential weighted average + * to suppress per-frame flicker: + * gain =3D (3 * gain_old + gain_new) / 4 (alpha =3D 0.25) + * Clamp to the hardware register width to prevent unbounded + * accumulation under degenerate (near-empty histogram) inputs. + */ + ctrls->gain[c] =3D (3 * ctrls->gain[c] + gain) / 4; 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Tue, 2 Jun 2026 23:59:47 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 2 Jun 2026 23:59:43 -0700 From: Balakrishnan Sambath Date: Wed, 3 Jun 2026 12:28:55 +0530 Subject: [PATCH v6 12/12] media: microchip-isc: scale DPC black level to sensor bit depth Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260603-microchip-isc-fixes-v6-12-8c3d7474a768@microchip.com> References: <20260603-microchip-isc-fixes-v6-0-8c3d7474a768@microchip.com> In-Reply-To: <20260603-microchip-isc-fixes-v6-0-8c3d7474a768@microchip.com> To: Eugen Hristev , Mauro Carvalho Chehab , Hans Verkuil CC: Laurent Pinchart , Kieran Bingham , Sakari Ailus , Balamanikandan Gunasundar , , , , "Balakrishnan Sambath" X-Mailer: b4 0.14.3 The DPC_BLCFG black level register expects counts in the sensor's native bit depth. The previous fixed 10-bit value (64 counts) under- corrects 12-bit sensors and over-corrects 8-bit ones, producing an incorrect black point. Scale the nominal 10-bit value to match the 8/10/12-bit sensor bus width derived from pfe_cfg0_bps. Co-developed-by: Balamanikandan Gunasundar Signed-off-by: Balamanikandan Gunasundar Signed-off-by: Balakrishnan Sambath --- .../media/platform/microchip/microchip-sama7g5-isc.c | 19 +++++++++++++++= +++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/microchip/microchip-sama7g5-isc.c b/dri= vers/media/platform/microchip/microchip-sama7g5-isc.c index e6ccdd465805..a57bc022aeb6 100644 --- a/drivers/media/platform/microchip/microchip-sama7g5-isc.c +++ b/drivers/media/platform/microchip/microchip-sama7g5-isc.c @@ -26,6 +26,7 @@ * HIS: Histogram module performs statistic counters on the frames */ =20 +#include #include #include #include @@ -290,9 +291,25 @@ static void isc_sama7g5_config_dpc(struct isc_device *= isc) { u32 bay_cfg =3D isc->config.sd_format->cfa_baycfg; struct regmap *regmap =3D isc->regmap; + u32 bps, bloff; + + /* + * Scale the nominal 10-bit black level offset (64 counts) to the + * actual sensor bus width. + * ISC_PFE_CFG0_BPS encodes 12 - bit_depth in bits[30:28]: + * BPS_EIGHT =3D 4 -> 8-bit -> bloff =3D 64 >> 2 =3D 16 + * BPS_TEN =3D 2 -> 10-bit -> bloff =3D 64 + * BPS_TWELVE =3D 0 -> 12-bit -> bloff =3D min(64 << 2, 255) =3D 255 + * The BLOFF hardware field is 8-bit so values are clamped to 255. + */ + bps =3D FIELD_GET(ISC_PFE_CFG0_BPS_MASK, isc->config.sd_format->pfe_cfg0_= bps); + if (bps >=3D 2) + bloff =3D 64u >> (bps - 2); + else + bloff =3D min(64u << (2 - bps), 255u); =20 regmap_update_bits(regmap, ISC_DPC_CFG, ISC_DPC_CFG_BLOFF_MASK, - (64 << ISC_DPC_CFG_BLOFF_SHIFT)); + (bloff << ISC_DPC_CFG_BLOFF_SHIFT)); regmap_update_bits(regmap, ISC_DPC_CFG, ISC_DPC_CFG_BAYCFG_MASK, (bay_cfg << ISC_DPC_CFG_BAYCFG_SHIFT)); } --=20 2.34.1