From nobody Mon Jun 8 07:24:55 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 67F3C13D51E; Wed, 3 Jun 2026 12:04:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780488244; cv=none; b=lKHqdF4MxPSvrP5WL3lt1VZOdGlJY70DkZUUeYNZaBHuGNDsPblWHB+50v5YCi0och4e/Q+c36Sha9kv5FdVJwg/XwbHe8220UkWKu9armsHfgG8hH8HFi/2Zz3agiarPi5fDMKlP71k0tHrTSNHTjZodfTjoHzEfwfsx0X5Xcc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780488244; c=relaxed/simple; bh=VZG0I1D2cmTSAxxtOtAqkd6FDbng/ubSj7swUVF8kKk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=SC15hDlNX0PXLWAkZVCO4M3Ex67XwyVzTqxty1QXTo/qTy1tR46NPDGYScnX2uv+NXnuc0eQl4SgQlOdcQ2kwXj1deDK0zhJ0EqatDO6ZhqBx5rXRF0JTcrqWhJTU6X0CBh876RroptucvZPThIVhS/y6aoAukWHINy/qXtM3+A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DQjVVlPR; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DQjVVlPR" Received: by smtp.kernel.org (Postfix) with ESMTPS id 1A511C2BCC7; Wed, 3 Jun 2026 12:04:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1780488244; bh=VZG0I1D2cmTSAxxtOtAqkd6FDbng/ubSj7swUVF8kKk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=DQjVVlPRvbei95AIVSiO6yMvINKeBpt7EHiEfHac7NdvCvjeTHFfCfs9sJXLSHEtr udeVpuWeE3HPTdY6u2PjR63ar2EfK1EuWr1612n45vqzKOGhbYB4fHHCTFVfTVg0zk INdBhq329bTQdEV7FnEtMSh7KmASuTH51TvrpbZ211r36aWi/glXmb82GJmIshNXvi Xx22t1yxzKihEv5ISWoIEsVcBEDI9yIxDamhz9TbZ5Uiah8WnuMzRmoPvCWKCfKGxp 2uNPE7kuW61B9028qD8mtH5hphWVfBG486hiuIKOkW/nVALykLOwhyXumbrPg2q378 q4L3gJShVyj5A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F195CD6E55; Wed, 3 Jun 2026 12:04:04 +0000 (UTC) From: Jian Hu via B4 Relay Date: Wed, 03 Jun 2026 20:03:56 +0800 Subject: [PATCH v2 1/2] dt-bindings: clock: Add Amlogic A9 peripherals clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260603-a9_peripherals-v2-1-ee1b8c0a1e6c@amlogic.com> References: <20260603-a9_peripherals-v2-0-ee1b8c0a1e6c@amlogic.com> In-Reply-To: <20260603-a9_peripherals-v2-0-ee1b8c0a1e6c@amlogic.com> To: Neil Armstrong , Jerome Brunet , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Xianwei Zhao , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jian Hu X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780488242; l=17396; i=jian.hu@amlogic.com; s=20260415; h=from:subject:message-id; bh=3+nZdtpVuIG2pNvaSBLNTrrkBWvIMfywajdhWp1+a54=; b=8CP3hWvt8Sb4hMVwGcK0Pn0CxdAKi1nNoV29rCQuOewz/R5t5RBMQgxASPuYCN8m+8kg3P/kU ueONxZy/O/GCb9Sd6lPlZIKom6EmOiUl8qewFnLgDZcYAxiTzPQRN19 X-Developer-Key: i=jian.hu@amlogic.com; a=ed25519; pk=zHUE+rNtH9z+Sb8au1/elWknjFQmy5QDVkBoxleuOIA= X-Endpoint-Received: by B4 Relay for jian.hu@amlogic.com/20260415 with auth_id=735 X-Original-From: Jian Hu Reply-To: jian.hu@amlogic.com From: Jian Hu Add the peripherals clock controller dt-bindings for the Amlogic A9 SoC family. Signed-off-by: Jian Hu Acked-by: Conor Dooley --- .../clock/amlogic,a9-peripherals-clkc.yaml | 160 ++++++++++ .../clock/amlogic,a9-peripherals-clkc.h | 352 +++++++++++++++++= ++++ 2 files changed, 512 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/amlogic,a9-peripherals= -clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a9-peripherals= -clkc.yaml new file mode 100644 index 000000000000..1d0abbaa85b8 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,a9-peripherals-clkc.y= aml @@ -0,0 +1,160 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2026 Amlogic, Inc. All rights reserved +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,a9-peripherals-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic A9 Series Peripherals Clock Controller + +maintainers: + - Neil Armstrong + - Jerome Brunet + - Jian Hu + - Xianwei Zhao + +properties: + compatible: + const: amlogic,a9-peripherals-clkc + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + clocks: + minItems: 26 + items: + - description: input oscillator + - description: input fclk div 2 + - description: input fclk div 3 + - description: input fclk div 4 + - description: input fclk div 5 + - description: input fclk div 7 + - description: input fclk div 2p5 + - description: input sys clk + - description: input gp1 pll + - description: input gp2 pll + - description: input sys pll div 16 + - description: input cpu clk div 16 + - description: input a78 clk div 16 + - description: input dsu clk div 16 + - description: input rtc clk + - description: input gp0 pll + - description: input hifi0 pll + - description: input hifi1 pll + - description: input mclk0 pll + - description: input mclk1 pll + - description: input video1 pll + - description: input video2 pll + - description: input hdmi out2 clk + - description: input hdmi pixel clk + - description: input pixel0 pll + - description: input pixel1 pll + - description: external input rmii oscillator (optional) + + clock-names: + minItems: 26 + items: + - const: xtal + - const: fdiv2 + - const: fdiv3 + - const: fdiv4 + - const: fdiv5 + - const: fdiv7 + - const: fdiv2p5 + - const: sys + - const: gp1 + - const: gp2 + - const: sysplldiv16 + - const: cpudiv16 + - const: a78div16 + - const: dsudiv16 + - const: rtc + - const: gp0 + - const: hifi0 + - const: hifi1 + - const: mclk0 + - const: mclk1 + - const: vid1 + - const: vid2 + - const: hdmiout2 + - const: hdmipix + - const: pix0 + - const: pix1 + - const: ext_rmii + +required: + - compatible + - reg + - '#clock-cells' + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + clock-controller@200 { + compatible =3D "amlogic,a9-peripherals-clkc"; + reg =3D <0x0 0x200 0x0 0x2f8>; + #clock-cells =3D <1>; + clocks =3D <&xtal>, + <&scmi_clk 10>, + <&scmi_clk 12>, + <&scmi_clk 14>, + <&scmi_clk 16>, + <&scmi_clk 18>, + <&scmi_clk 20>, + <&scmi_clk 21>, + <&scmi_clk 33>, + <&scmi_clk 34>, + <&scmi_clk 35>, + <&scmi_clk 36>, + <&scmi_clk 37>, + <&scmi_clk 38>, + <&scmi_clk 40>, + <&gp0 3>, + <&hifi0 3>, + <&hifi1 3>, + <&mclk0 3>, + <&mclk1 3>, + <&vid1>, + <&vid2>, + <&hdmitx 10>, + <&hdmitx 11>, + <&pix0>, + <&pix1>; + clock-names =3D "xtal", + "fdiv2", + "fdiv3", + "fdiv4", + "fdiv5", + "fdiv7", + "fdiv2p5", + "sys", + "gp1", + "gp2", + "sysplldiv16", + "cpudiv16", + "a78div16", + "dsudiv16", + "rtc", + "gp0", + "hifi0", + "hifi1", + "mclk0", + "mclk1", + "vid1", + "vid2", + "hdmiout2", + "hdmipix", + "pix0", + "pix1"; + }; + }; diff --git a/include/dt-bindings/clock/amlogic,a9-peripherals-clkc.h b/incl= ude/dt-bindings/clock/amlogic,a9-peripherals-clkc.h new file mode 100644 index 000000000000..bca69771d728 --- /dev/null +++ b/include/dt-bindings/clock/amlogic,a9-peripherals-clkc.h @@ -0,0 +1,352 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2026 Amlogic, Inc. All rights reserved. + */ + +#ifndef __AMLOGIC_A9_PERIPHERALS_CLKC_H +#define __AMLOGIC_A9_PERIPHERALS_CLKC_H + +#define CLKID_SYS_AM_AXI 0 +#define CLKID_SYS_DOS 1 +#define CLKID_SYS_MIPI_DSI 2 +#define CLKID_SYS_ETH_PHY 3 +#define CLKID_SYS_AMFC 4 +#define CLKID_SYS_MALI 5 +#define CLKID_SYS_NNA 6 +#define CLKID_SYS_ETH_AXI 7 +#define CLKID_SYS_DP_APB 8 +#define CLKID_SYS_EDPTX_APB 9 +#define CLKID_SYS_U3HSG 10 +#define CLKID_SYS_AUCPU 11 +#define CLKID_SYS_GLB 12 +#define CLKID_SYS_COMBO_DPHY_APB 13 +#define CLKID_SYS_HDMIRX_APB 14 +#define CLKID_SYS_HDMIRX_PCLK 15 +#define CLKID_SYS_MIPI_DSI_PHY 16 +#define CLKID_SYS_CAN0 17 +#define CLKID_SYS_CAN1 18 +#define CLKID_SYS_SD_EMMC_A 19 +#define CLKID_SYS_SD_EMMC_B 20 +#define CLKID_SYS_SD_EMMC_C 21 +#define CLKID_SYS_SC 22 +#define CLKID_SYS_ACODEC 23 +#define CLKID_SYS_MIPI_ISP 24 +#define CLKID_SYS_MSR 25 +#define CLKID_SYS_AUDIO 26 +#define CLKID_SYS_MIPI_DSI_B 27 +#define CLKID_SYS_MIPI_DSI1_PHY 28 +#define CLKID_SYS_ETH 29 +#define CLKID_SYS_ETH_1G_MAC 30 +#define CLKID_SYS_UART_A 31 +#define CLKID_SYS_UART_F 32 +#define CLKID_SYS_TS_A55 33 +#define CLKID_SYS_ETH_1G_AXI 34 +#define CLKID_SYS_TS_DOS 35 +#define CLKID_SYS_U3DRD_B 36 +#define CLKID_SYS_TS_CORE 37 +#define CLKID_SYS_TS_PLL 38 +#define CLKID_SYS_CSI_DIG_CLKIN 39 +#define CLKID_SYS_CVE 40 +#define CLKID_SYS_GE2D 41 +#define CLKID_SYS_SPISG 42 +#define CLKID_SYS_U3DRD_1 43 +#define CLKID_SYS_U2H 44 +#define CLKID_SYS_PCIE_MAC_A 45 +#define CLKID_SYS_U3DRD_A 46 +#define CLKID_SYS_U2DRD 47 +#define CLKID_SYS_PCIE_PHY 48 +#define CLKID_SYS_PCIE_MAC_B 49 +#define CLKID_SYS_PERIPH 50 +#define CLKID_SYS_PIO 51 +#define CLKID_SYS_I3C 52 +#define CLKID_SYS_I2C_M_E 53 +#define CLKID_SYS_I2C_M_F 54 +#define CLKID_SYS_HDMITX_APB 55 +#define CLKID_SYS_I2C_M_I 56 +#define CLKID_SYS_I2C_M_G 57 +#define CLKID_SYS_I2C_M_H 58 +#define CLKID_SYS_HDMI20_AES 59 +#define CLKID_SYS_CSI2_HOST 60 +#define CLKID_SYS_CSI2_ADAPT 61 +#define CLKID_SYS_DSPA 62 +#define CLKID_SYS_PP_DMA 63 +#define CLKID_SYS_PP_WRAPPER 64 +#define CLKID_SYS_VPU_INTR 65 +#define CLKID_SYS_CSI2_PHY 66 +#define CLKID_SYS_SARADC 67 +#define CLKID_SYS_PWM_J 68 +#define CLKID_SYS_PWM_I 69 +#define CLKID_SYS_PWM_H 70 +#define CLKID_SYS_PWM_N 71 +#define CLKID_SYS_PWM_M 72 +#define CLKID_SYS_PWM_L 73 +#define CLKID_SYS_PWM_K 74 +#define CLKID_SD_EMMC_A_SEL 75 +#define CLKID_SD_EMMC_A_DIV 76 +#define CLKID_SD_EMMC_A 77 +#define CLKID_SD_EMMC_B_SEL 78 +#define CLKID_SD_EMMC_B_DIV 79 +#define CLKID_SD_EMMC_B 80 +#define CLKID_SD_EMMC_C_SEL 81 +#define CLKID_SD_EMMC_C_DIV 82 +#define CLKID_SD_EMMC_C 83 +#define CLKID_PWM_H_SEL 84 +#define CLKID_PWM_H_DIV 85 +#define CLKID_PWM_H 86 +#define CLKID_PWM_I_SEL 87 +#define CLKID_PWM_I_DIV 88 +#define CLKID_PWM_I 89 +#define CLKID_PWM_J_SEL 90 +#define CLKID_PWM_J_DIV 91 +#define CLKID_PWM_J 92 +#define CLKID_PWM_K_SEL 93 +#define CLKID_PWM_K_DIV 94 +#define CLKID_PWM_K 95 +#define CLKID_PWM_L_SEL 96 +#define CLKID_PWM_L_DIV 97 +#define CLKID_PWM_L 98 +#define CLKID_PWM_M_SEL 99 +#define CLKID_PWM_M_DIV 100 +#define CLKID_PWM_M 101 +#define CLKID_PWM_N_SEL 102 +#define CLKID_PWM_N_DIV 103 +#define CLKID_PWM_N 104 +#define CLKID_SPISG_SEL 105 +#define CLKID_SPISG_DIV 106 +#define CLKID_SPISG 107 +#define CLKID_SPISG1_SEL 108 +#define CLKID_SPISG1_DIV 109 +#define CLKID_SPISG1 110 +#define CLKID_SPISG2_SEL 111 +#define CLKID_SPISG2_DIV 112 +#define CLKID_SPISG2 113 +#define CLKID_SARADC_SEL 114 +#define CLKID_SARADC_DIV 115 +#define CLKID_SARADC 116 +#define CLKID_AMFC_SEL 117 +#define CLKID_AMFC_DIV 118 +#define CLKID_AMFC 119 +#define CLKID_NNA_SEL 120 +#define CLKID_NNA_DIV 121 +#define CLKID_NNA 122 +#define CLKID_USB_250M_SEL 123 +#define CLKID_USB_250M_DIV 124 +#define CLKID_USB_250M 125 +#define CLKID_USB_48M_PRE_SEL 126 +#define CLKID_USB_48M_PRE_DIV 127 +#define CLKID_USB_48M_PRE 128 +#define CLKID_PCIE_TL_SEL 129 +#define CLKID_PCIE_TL_DIV 130 +#define CLKID_PCIE_TL 131 +#define CLKID_PCIE1_TL_SEL 132 +#define CLKID_PCIE1_TL_DIV 133 +#define CLKID_PCIE1_TL 134 +#define CLKID_CMPR_SEL 135 +#define CLKID_CMPR_DIV 136 +#define CLKID_CMPR 137 +#define CLKID_DEWARPA_SEL 138 +#define CLKID_DEWARPA_DIV 139 +#define CLKID_DEWARPA 140 +#define CLKID_SC_PRE_SEL 141 +#define CLKID_SC_PRE_DIV 142 +#define CLKID_SC_PRE 143 +#define CLKID_SC 144 +#define CLKID_DPTX_APB2_SEL 145 +#define CLKID_DPTX_APB2_DIV 146 +#define CLKID_DPTX_APB2 147 +#define CLKID_DPTX_AUD_SEL 148 +#define CLKID_DPTX_AUD_DIV 149 +#define CLKID_DPTX_AUD 150 +#define CLKID_ISP_SEL 151 +#define CLKID_ISP_DIV 152 +#define CLKID_ISP 153 +#define CLKID_CVE_SEL 154 +#define CLKID_CVE_DIV 155 +#define CLKID_CVE 156 +#define CLKID_VGE_SEL 157 +#define CLKID_VGE_DIV 158 +#define CLKID_VGE 159 +#define CLKID_PP_SEL 160 +#define CLKID_PP_DIV 161 +#define CLKID_PP 162 +#define CLKID_GLB_SEL 163 +#define CLKID_GLB_DIV 164 +#define CLKID_GLB 165 +#define CLKID_USB_48M_DUALDIV_IN 166 +#define CLKID_USB_48M_DUALDIV_DIV 167 +#define CLKID_USB_48M_DUALDIV_SEL 168 +#define CLKID_USB_48M_DUALDIV 169 +#define CLKID_USB_48M 170 +#define CLKID_CAN_PE_SEL 171 +#define CLKID_CAN_PE_DIV 172 +#define CLKID_CAN_PE 173 +#define CLKID_CAN1_PE_SEL 174 +#define CLKID_CAN1_PE_DIV 175 +#define CLKID_CAN1_PE 176 +#define CLKID_CAN_FILTER_SEL 177 +#define CLKID_CAN_FILTER_DIV 178 +#define CLKID_CAN_FILTER 179 +#define CLKID_CAN1_FILTER_SEL 180 +#define CLKID_CAN1_FILTER_DIV 181 +#define CLKID_CAN1_FILTER 182 +#define CLKID_I3C_SEL 183 +#define CLKID_I3C_DIV 184 +#define CLKID_I3C 185 +#define CLKID_TS_DIV 186 +#define CLKID_TS 187 +#define CLKID_ETH_125M_DIV 188 +#define CLKID_ETH_125M 189 +#define CLKID_ETH_RMII_SEL 190 +#define CLKID_ETH_RMII_DIV 191 +#define CLKID_ETH_RMII 192 +#define CLKID_GEN_SEL 193 +#define CLKID_GEN_DIV 194 +#define CLKID_GEN 195 +#define CLKID_CLK24M_IN 196 +#define CLKID_CLK12_24M 197 +#define CLKID_MALI_0_SEL 198 +#define CLKID_MALI_0_DIV 199 +#define CLKID_MALI_0 200 +#define CLKID_MALI_1_SEL 201 +#define CLKID_MALI_1_DIV 202 +#define CLKID_MALI_1 203 +#define CLKID_MALI 204 +#define CLKID_MALI_STACK_0_SEL 205 +#define CLKID_MALI_STACK_0_DIV 206 +#define CLKID_MALI_STACK_0 207 +#define CLKID_MALI_STACK_1_SEL 208 +#define CLKID_MALI_STACK_1_DIV 209 +#define CLKID_MALI_STACK_1 210 +#define CLKID_MALI_STACK 211 +#define CLKID_DSPA_0_SEL 212 +#define CLKID_DSPA_0_DIV 213 +#define CLKID_DSPA_0 214 +#define CLKID_DSPA_1_SEL 215 +#define CLKID_DSPA_1_DIV 216 +#define CLKID_DSPA_1 217 +#define CLKID_DSPA 218 +#define CLKID_HEVCF_0_SEL 219 +#define CLKID_HEVCF_0_DIV 220 +#define CLKID_HEVCF_0 221 +#define CLKID_HEVCF_1_SEL 222 +#define CLKID_HEVCF_1_DIV 223 +#define CLKID_HEVCF_1 224 +#define CLKID_HEVCF 225 +#define CLKID_HCODEC_0_SEL 226 +#define CLKID_HCODEC_0_DIV 227 +#define CLKID_HCODEC_0 228 +#define CLKID_HCODEC_1_SEL 229 +#define CLKID_HCODEC_1_DIV 230 +#define CLKID_HCODEC_1 231 +#define CLKID_HCODEC 232 +#define CLKID_VPU_0_SEL 233 +#define CLKID_VPU_0_DIV 234 +#define CLKID_VPU_0 235 +#define CLKID_VPU_1_SEL 236 +#define CLKID_VPU_1_DIV 237 +#define CLKID_VPU_1 238 +#define CLKID_VPU 239 +#define CLKID_VAPB_0_SEL 240 +#define CLKID_VAPB_0_DIV 241 +#define CLKID_VAPB_0 242 +#define CLKID_VAPB_1_SEL 243 +#define CLKID_VAPB_1_DIV 244 +#define CLKID_VAPB_1 245 +#define CLKID_VAPB 246 +#define CLKID_GE2D 247 +#define CLKID_VPU_CLKB_TMP_SEL 248 +#define CLKID_VPU_CLKB_TMP_DIV 249 +#define CLKID_VPU_CLKB_TMP 250 +#define CLKID_VPU_CLKB_DIV 251 +#define CLKID_VPU_CLKB 252 +#define CLKID_HDMITX_SYS_SEL 253 +#define CLKID_HDMITX_SYS_DIV 254 +#define CLKID_HDMITX_SYS 255 +#define CLKID_HDMITX_PRIF_SEL 256 +#define CLKID_HDMITX_PRIF_DIV 257 +#define CLKID_HDMITX_PRIF 258 +#define CLKID_HDMITX_200M_SEL 259 +#define CLKID_HDMITX_200M_DIV 260 +#define CLKID_HDMITX_200M 261 +#define CLKID_HDMITX_AUD_SEL 262 +#define CLKID_HDMITX_AUD_DIV 263 +#define CLKID_HDMITX_AUD 264 +#define CLKID_HDMIRX_5M_SEL 265 +#define CLKID_HDMIRX_5M_DIV 266 +#define CLKID_HDMIRX_5M 267 +#define CLKID_HDMIRX_2M_SEL 268 +#define CLKID_HDMIRX_2M_DIV 269 +#define CLKID_HDMIRX_2M 270 +#define CLKID_HDMIRX_CFG_SEL 271 +#define CLKID_HDMIRX_CFG_DIV 272 +#define CLKID_HDMIRX_CFG 273 +#define CLKID_HDMIRX_HDCP2X_SEL 274 +#define CLKID_HDMIRX_HDCP2X_DIV 275 +#define CLKID_HDMIRX_HDCP2X 276 +#define CLKID_HDMIRX_ACR_REF_SEL 277 +#define CLKID_HDMIRX_ACR_REF_DIV 278 +#define CLKID_HDMIRX_ACR_REF 279 +#define CLKID_HDMIRX_METER_SEL 280 +#define CLKID_HDMIRX_METER_DIV 281 +#define CLKID_HDMIRX_METER 282 +#define CLKID_VID_LOCK_SEL 283 +#define CLKID_VID_LOCK_DIV 284 +#define CLKID_VID_LOCK 285 +#define CLKID_VDIN_MEAS_SEL 286 +#define CLKID_VDIN_MEAS_DIV 287 +#define CLKID_VDIN_MEAS 288 +#define CLKID_VID_PLL_DIV 289 +#define CLKID_VID_PLL_SEL 290 +#define CLKID_VID_PLL 291 +#define CLKID_VID_PLL_VCLK 292 +#define CLKID_VCLK_SEL 293 +#define CLKID_VCLK_IN 294 +#define CLKID_VCLK_DIV 295 +#define CLKID_VCLK 296 +#define CLKID_VCLK_DIV1_EN 297 +#define CLKID_VCLK_DIV2_EN 298 +#define CLKID_VCLK_DIV2 299 +#define CLKID_VCLK_DIV4_EN 300 +#define CLKID_VCLK_DIV4 301 +#define CLKID_VCLK_DIV6_EN 302 +#define CLKID_VCLK_DIV6 303 +#define CLKID_VCLK_DIV12_EN 304 +#define CLKID_VCLK_DIV12 305 +#define CLKID_VCLK2_SEL 306 +#define CLKID_VCLK2_IN 307 +#define CLKID_VCLK2_DIV 308 +#define CLKID_VCLK2 309 +#define CLKID_VCLK2_DIV1_EN 310 +#define CLKID_VCLK2_DIV2_EN 311 +#define CLKID_VCLK2_DIV2 312 +#define CLKID_VCLK2_DIV4_EN 313 +#define CLKID_VCLK2_DIV4 314 +#define CLKID_VCLK2_DIV6_EN 315 +#define CLKID_VCLK2_DIV6 316 +#define CLKID_VCLK2_DIV12_EN 317 +#define CLKID_VCLK2_DIV12 318 +#define CLKID_VDAC_SEL 319 +#define CLKID_VDAC 320 +#define CLKID_ENC_SEL 321 +#define CLKID_ENC 322 +#define CLKID_ENC1_SEL 323 +#define CLKID_ENC1 324 +#define CLKID_HDMITX_PIXEL_SEL 325 +#define CLKID_HDMITX_PIXEL 326 +#define CLKID_HDMITX_FE_SEL 327 +#define CLKID_HDMITX_FE 328 +#define CLKID_HDMITX1_PIXEL_SEL 329 +#define CLKID_HDMITX1_PIXEL 330 +#define CLKID_HDMITX1_FE_SEL 331 +#define CLKID_HDMITX1_FE 332 +#define CLKID_CSI_PHY_SEL 333 +#define CLKID_CSI_PHY_DIV 334 +#define CLKID_CSI_PHY 335 +#define CLKID_DSI_MEAS_SEL 336 +#define CLKID_DSI_MEAS_DIV 337 +#define CLKID_DSI_MEAS 338 +#define CLKID_DSI_B_MEAS_SEL 339 +#define CLKID_DSI_B_MEAS_DIV 340 +#define CLKID_DSI_B_MEAS 341 + +#endif /* __AMLOGIC_A9_PERIPHERALS_CLKC_H */ --=20 2.47.1 From nobody Mon Jun 8 07:24:55 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68080395DB9; Wed, 3 Jun 2026 12:04:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780488244; cv=none; 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List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260603-a9_peripherals-v2-2-ee1b8c0a1e6c@amlogic.com> References: <20260603-a9_peripherals-v2-0-ee1b8c0a1e6c@amlogic.com> In-Reply-To: <20260603-a9_peripherals-v2-0-ee1b8c0a1e6c@amlogic.com> To: Neil Armstrong , Jerome Brunet , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Xianwei Zhao , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jian Hu X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780488242; l=68750; i=jian.hu@amlogic.com; s=20260415; h=from:subject:message-id; bh=BJXeUsILMenQEdkE+Yd7t5czgRjDotBdwYUANojtZps=; b=klo/Djm48vEHdL6idb4unY2I+FBdkhRmTAo9W/ZsAjyePks7zapRqSgxL3BQ2nZytBYD66M2C Z1cEmN2o6q2CHoFtAu4e9RDuanGJUnPtUiUgJ6Wqc/F0+LpyaCDp1sn X-Developer-Key: i=jian.hu@amlogic.com; a=ed25519; pk=zHUE+rNtH9z+Sb8au1/elWknjFQmy5QDVkBoxleuOIA= X-Endpoint-Received: by B4 Relay for jian.hu@amlogic.com/20260415 with auth_id=735 X-Original-From: Jian Hu Reply-To: jian.hu@amlogic.com From: Jian Hu Add the peripherals clock controller driver for the Amlogic A9 SoC family. Signed-off-by: Jian Hu --- drivers/clk/meson/Kconfig | 15 + drivers/clk/meson/Makefile | 1 + drivers/clk/meson/a9-peripherals.c | 1927 ++++++++++++++++++++++++++++++++= ++++ 3 files changed, 1943 insertions(+) diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index cf8cf3f9e4ee..42c06c294096 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -132,6 +132,21 @@ config COMMON_CLK_A1_PERIPHERALS device, A1 SoC Family. Say Y if you want A1 Peripherals clock controller to work. =20 +config COMMON_CLK_A9_PERIPHERALS + tristate "Amlogic A9 SoC peripherals clock controller support" + depends on ARM64 + default ARCH_MESON || COMPILE_TEST + select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_MESON_CLKC_UTILS + select COMMON_CLK_MESON_DUALDIV + select COMMON_CLK_MESON_VID_PLL_DIV + imply COMMON_CLK_SCMI + imply COMMON_CLK_A9_PLL + help + Support for the peripherals clock controller on Amlogic A311Y3 based + device, AKA A9. Peripherals are required by most peripheral to operate. + Say Y if you want A9 peripherals clock controller to work. + config COMMON_CLK_C3_PLL tristate "Amlogic C3 PLL clock controller" depends on ARM64 diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index c6719694a242..bccd9ace9201 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_COMMON_CLK_AXG) +=3D axg.o axg-aoclk.o obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) +=3D axg-audio.o obj-$(CONFIG_COMMON_CLK_A1_PLL) +=3D a1-pll.o obj-$(CONFIG_COMMON_CLK_A1_PERIPHERALS) +=3D a1-peripherals.o +obj-$(CONFIG_COMMON_CLK_A9_PERIPHERALS) +=3D a9-peripherals.o obj-$(CONFIG_COMMON_CLK_C3_PLL) +=3D c3-pll.o obj-$(CONFIG_COMMON_CLK_C3_PERIPHERALS) +=3D c3-peripherals.o obj-$(CONFIG_COMMON_CLK_GXBB) +=3D gxbb.o gxbb-aoclk.o diff --git a/drivers/clk/meson/a9-peripherals.c b/drivers/clk/meson/a9-peri= pherals.c new file mode 100644 index 000000000000..4ce351618a86 --- /dev/null +++ b/drivers/clk/meson/a9-peripherals.c @@ -0,0 +1,1927 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +/* + * Copyright (C) 2026 Amlogic, Inc. All rights reserved + */ + +#include +#include +#include +#include "clk-regmap.h" +#include "clk-dualdiv.h" +#include "meson-clkc-utils.h" +#include "vid-pll-div.h" + +#define SYS_CLK_EN0_REG0 0x30 +#define SYS_CLK_EN0_REG1 0x34 +#define SYS_CLK_EN0_REG2 0x38 +#define SYS_CLK_EN0_REG3 0x3c +#define SD_EMMC_CLK_CTRL0 0x90 +#define SD_EMMC_CLK_CTRL1 0x94 +#define PWM_CLK_H_CTRL 0xbc +#define PWM_CLK_I_CTRL 0xc0 +#define PWM_CLK_J_CTRL 0xc4 +#define PWM_CLK_K_CTRL 0xc8 +#define PWM_CLK_L_CTRL 0xcc +#define PWM_CLK_M_CTRL 0xd0 +#define PWM_CLK_N_CTRL 0xd4 +#define SPISG_CLK_CTRL 0x100 +#define SPISG_CLK_CTRL1 0x104 +#define SAR_CLK_CTRL 0x150 +#define AMFC_CLK_CTRL 0x154 +#define NNA_CLK_CTRL 0x15c +#define USB_CLK_CTRL 0x160 +#define PCIE_TL_CLK_CTRL 0x164 +#define CMPR_CLK_CTRL 0x168 +#define DEWARP_CLK_CTRL 0x16c +#define SC_CLK_CTRL 0x170 +#define DPTX_CLK_CTRL 0x178 +#define ISP_CLK_CTRL 0x17c +#define CVE_CLK_CTRL 0x180 +#define PP_CLK_CTRL 0x184 +#define GLB_CLK_CTRL 0x188 +#define USB_CLK_CTRL0 0x18c +#define USB_CLK_CTRL1 0x190 +#define CAN_CLK_CTRL 0x194 +#define CAN_CLK_CTRL1 0x198 +#define I3C_CLK_CTRL 0x19c +#define TS_CLK_CTRL 0x1a0 +#define ETH_CLK_CTRL 0x1a4 +#define GEN_CLK_CTRL 0x1a8 +#define CLK12_24_CTRL 0x1ac +#define MALI_CLK_CTRL 0x200 +#define MALI_STACK_CLK_CTRL 0x204 +#define DSPA_CLK_CTRL 0x220 +#define HEVCF_CLK_CTRL 0x240 +#define HCODEC_CLK_CTRL 0x244 +#define VPU_CLK_CTRL 0x260 +#define VAPB_CLK_CTRL 0x268 +#define VPU_CLKB_CTRL 0x280 +#define HDMI_CLK_CTRL 0x284 +#define HTX_CLK_CTRL 0x28c +#define HTX_CLK_CTRL1 0x290 +#define HRX_CLK_CTRL 0x294 +#define HRX_CLK_CTRL1 0x298 +#define HRX_CLK_CTRL2 0x29c +#define HRX_CLK_CTRL3 0x2a0 +#define VID_LOCK_CLK_CTRL 0x2a4 +#define VDIN_MEAS_CLK_CTRL 0x2a8 +#define VID_PLL_CLK_DIV 0x2b0 +#define VID_CLK_CTRL 0x2c0 +#define VID_CLK_CTRL2 0x2c4 +#define VID_CLK_DIV 0x2c8 +#define VIID_CLK_DIV 0x2cc +#define VIID_CLK_CTRL 0x2d0 +#define MIPI_CSI_PHY_CLK_CTRL 0x2e0 +#define DSI_MEAS_CLK_CTRL 0x2f4 + +#define A9_COMP_SEL(_name, _reg, _shift, _mask, _pdata, _table) \ + MESON_COMP_SEL(a9_, _name, _reg, _shift, _mask, _pdata, _table, 0, 0) + +#define A9_COMP_DIV(_name, _reg, _shift, _width) \ + MESON_COMP_DIV(a9_, _name, _reg, _shift, _width, 0, CLK_SET_RATE_PARENT) + +#define A9_COMP_GATE(_name, _reg, _bit, _iflags) \ + MESON_COMP_GATE(a9_, _name, _reg, _bit, CLK_SET_RATE_PARENT | (_iflags)) + +static const struct clk_parent_data a9_sys_pclk_parents =3D { .fw_name =3D= "sys" }; + +#define A9_SYS_PCLK(_name, _reg, _bit) \ + MESON_PCLK(a9_##_name, _reg, _bit, &a9_sys_pclk_parents, 0) + +static A9_SYS_PCLK(sys_am_axi, SYS_CLK_EN0_REG0, 0); +static A9_SYS_PCLK(sys_dos, SYS_CLK_EN0_REG0, 1); +static A9_SYS_PCLK(sys_mipi_dsi, SYS_CLK_EN0_REG0, 3); +static A9_SYS_PCLK(sys_eth_phy, SYS_CLK_EN0_REG0, 4); +static A9_SYS_PCLK(sys_amfc, SYS_CLK_EN0_REG0, 5); +static A9_SYS_PCLK(sys_mali, SYS_CLK_EN0_REG0, 6); +static A9_SYS_PCLK(sys_nna, SYS_CLK_EN0_REG0, 7); +static A9_SYS_PCLK(sys_eth_axi, SYS_CLK_EN0_REG0, 8); +static A9_SYS_PCLK(sys_dp_apb, SYS_CLK_EN0_REG0, 9); +static A9_SYS_PCLK(sys_edptx_apb, SYS_CLK_EN0_REG0, 10); +static A9_SYS_PCLK(sys_u3hsg, SYS_CLK_EN0_REG0, 11); +static A9_SYS_PCLK(sys_aucpu, SYS_CLK_EN0_REG0, 14); +static A9_SYS_PCLK(sys_glb, SYS_CLK_EN0_REG0, 15); +static A9_SYS_PCLK(sys_combo_dphy_apb, SYS_CLK_EN0_REG0, 17); +static A9_SYS_PCLK(sys_hdmirx_apb, SYS_CLK_EN0_REG0, 18); +static A9_SYS_PCLK(sys_hdmirx_pclk, SYS_CLK_EN0_REG0, 19); +static A9_SYS_PCLK(sys_mipi_dsi_phy, SYS_CLK_EN0_REG0, 20); +static A9_SYS_PCLK(sys_can0, SYS_CLK_EN0_REG0, 21); +static A9_SYS_PCLK(sys_can1, SYS_CLK_EN0_REG0, 22); +static A9_SYS_PCLK(sys_sd_emmc_a, SYS_CLK_EN0_REG0, 24); +static A9_SYS_PCLK(sys_sd_emmc_b, SYS_CLK_EN0_REG0, 25); +static A9_SYS_PCLK(sys_sd_emmc_c, SYS_CLK_EN0_REG0, 26); +static A9_SYS_PCLK(sys_sc, SYS_CLK_EN0_REG0, 27); +static A9_SYS_PCLK(sys_acodec, SYS_CLK_EN0_REG0, 28); +static A9_SYS_PCLK(sys_mipi_isp, SYS_CLK_EN0_REG0, 29); +static A9_SYS_PCLK(sys_msr, SYS_CLK_EN0_REG0, 30); +static A9_SYS_PCLK(sys_audio, SYS_CLK_EN0_REG1, 0); +static A9_SYS_PCLK(sys_mipi_dsi_b, SYS_CLK_EN0_REG1, 1); +static A9_SYS_PCLK(sys_mipi_dsi1_phy, SYS_CLK_EN0_REG1, 2); +static A9_SYS_PCLK(sys_eth, SYS_CLK_EN0_REG1, 3); +static A9_SYS_PCLK(sys_eth_1g_mac, SYS_CLK_EN0_REG1, 4); +static A9_SYS_PCLK(sys_uart_a, SYS_CLK_EN0_REG1, 5); +static A9_SYS_PCLK(sys_uart_f, SYS_CLK_EN0_REG1, 10); +static A9_SYS_PCLK(sys_ts_a55, SYS_CLK_EN0_REG1, 11); +static A9_SYS_PCLK(sys_eth_1g_axi, SYS_CLK_EN0_REG1, 12); +static A9_SYS_PCLK(sys_ts_dos, SYS_CLK_EN0_REG1, 13); +static A9_SYS_PCLK(sys_u3drd_b, SYS_CLK_EN0_REG1, 14); +static A9_SYS_PCLK(sys_ts_core, SYS_CLK_EN0_REG1, 15); +static A9_SYS_PCLK(sys_ts_pll, SYS_CLK_EN0_REG1, 16); +static A9_SYS_PCLK(sys_csi_dig_clkin, SYS_CLK_EN0_REG1, 18); +static A9_SYS_PCLK(sys_cve, SYS_CLK_EN0_REG1, 19); +static A9_SYS_PCLK(sys_ge2d, SYS_CLK_EN0_REG1, 20); +static A9_SYS_PCLK(sys_spisg, SYS_CLK_EN0_REG1, 21); +static A9_SYS_PCLK(sys_u3drd_1, SYS_CLK_EN0_REG1, 22); +static A9_SYS_PCLK(sys_u2h, SYS_CLK_EN0_REG1, 23); +static A9_SYS_PCLK(sys_pcie_mac_a, SYS_CLK_EN0_REG1, 24); +static A9_SYS_PCLK(sys_u3drd_a, SYS_CLK_EN0_REG1, 25); +static A9_SYS_PCLK(sys_u2drd, SYS_CLK_EN0_REG1, 26); +static A9_SYS_PCLK(sys_pcie_phy, SYS_CLK_EN0_REG1, 27); +static A9_SYS_PCLK(sys_pcie_mac_b, SYS_CLK_EN0_REG1, 28); +static A9_SYS_PCLK(sys_periph, SYS_CLK_EN0_REG1, 29); +static A9_SYS_PCLK(sys_pio, SYS_CLK_EN0_REG2, 0); +static A9_SYS_PCLK(sys_i3c, SYS_CLK_EN0_REG2, 1); +static A9_SYS_PCLK(sys_i2c_m_e, SYS_CLK_EN0_REG2, 2); +static A9_SYS_PCLK(sys_i2c_m_f, SYS_CLK_EN0_REG2, 3); +static A9_SYS_PCLK(sys_hdmitx_apb, SYS_CLK_EN0_REG2, 4); +static A9_SYS_PCLK(sys_i2c_m_i, SYS_CLK_EN0_REG2, 5); +static A9_SYS_PCLK(sys_i2c_m_g, SYS_CLK_EN0_REG2, 6); +static A9_SYS_PCLK(sys_i2c_m_h, SYS_CLK_EN0_REG2, 7); +static A9_SYS_PCLK(sys_hdmi20_aes, SYS_CLK_EN0_REG2, 9); +static A9_SYS_PCLK(sys_csi2_host, SYS_CLK_EN0_REG2, 16); +static A9_SYS_PCLK(sys_csi2_adapt, SYS_CLK_EN0_REG2, 17); +static A9_SYS_PCLK(sys_dspa, SYS_CLK_EN0_REG2, 21); +static A9_SYS_PCLK(sys_pp_dma, SYS_CLK_EN0_REG2, 22); +static A9_SYS_PCLK(sys_pp_wrapper, SYS_CLK_EN0_REG2, 23); +static A9_SYS_PCLK(sys_vpu_intr, SYS_CLK_EN0_REG2, 25); +static A9_SYS_PCLK(sys_csi2_phy, SYS_CLK_EN0_REG2, 27); +static A9_SYS_PCLK(sys_saradc, SYS_CLK_EN0_REG2, 28); +static A9_SYS_PCLK(sys_pwm_j, SYS_CLK_EN0_REG2, 30); +static A9_SYS_PCLK(sys_pwm_i, SYS_CLK_EN0_REG2, 31); +static A9_SYS_PCLK(sys_pwm_h, SYS_CLK_EN0_REG3, 0); +static A9_SYS_PCLK(sys_pwm_n, SYS_CLK_EN0_REG3, 8); +static A9_SYS_PCLK(sys_pwm_m, SYS_CLK_EN0_REG3, 9); +static A9_SYS_PCLK(sys_pwm_l, SYS_CLK_EN0_REG3, 10); +static A9_SYS_PCLK(sys_pwm_k, SYS_CLK_EN0_REG3, 11); + +/* Channel 5 is unconnected. */ +static u32 a9_sd_emmc_parents_val_table[] =3D { 0, 1, 2, 3, 4, 6, 7 }; +static const struct clk_parent_data a9_sd_emmc_parents[] =3D { + { .fw_name =3D "xtal", }, + { .fw_name =3D "fdiv2", }, + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "hifi0", }, + { .fw_name =3D "fdiv2p5", }, + { .fw_name =3D "gp1", }, + { .fw_name =3D "gp0", } +}; + +static A9_COMP_SEL(sd_emmc_a, SD_EMMC_CLK_CTRL0, 9, 0x7, a9_sd_emmc_parent= s, + a9_sd_emmc_parents_val_table); +static A9_COMP_DIV(sd_emmc_a, SD_EMMC_CLK_CTRL0, 0, 7); +static A9_COMP_GATE(sd_emmc_a, SD_EMMC_CLK_CTRL0, 8, 0); + +static A9_COMP_SEL(sd_emmc_b, SD_EMMC_CLK_CTRL0, 25, 0x7, a9_sd_emmc_paren= ts, + a9_sd_emmc_parents_val_table); +static A9_COMP_DIV(sd_emmc_b, SD_EMMC_CLK_CTRL0, 16, 7); +static A9_COMP_GATE(sd_emmc_b, SD_EMMC_CLK_CTRL0, 24, 0); + +static A9_COMP_SEL(sd_emmc_c, SD_EMMC_CLK_CTRL1, 9, 0x7, a9_sd_emmc_parent= s, + a9_sd_emmc_parents_val_table); +static A9_COMP_DIV(sd_emmc_c, SD_EMMC_CLK_CTRL1, 0, 7); +static A9_COMP_GATE(sd_emmc_c, SD_EMMC_CLK_CTRL1, 8, 0); + +static const struct clk_parent_data a9_pwm_parents[] =3D { + { .fw_name =3D "xtal", }, + { .fw_name =3D "fdiv5", }, + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "fdiv3", } +}; + +static A9_COMP_SEL(pwm_h, PWM_CLK_H_CTRL, 9, 0x7, a9_pwm_parents, NULL); +static A9_COMP_DIV(pwm_h, PWM_CLK_H_CTRL, 0, 8); +static A9_COMP_GATE(pwm_h, PWM_CLK_H_CTRL, 8, 0); + +static A9_COMP_SEL(pwm_i, PWM_CLK_I_CTRL, 9, 0x7, a9_pwm_parents, NULL); +static A9_COMP_DIV(pwm_i, PWM_CLK_I_CTRL, 0, 8); +static A9_COMP_GATE(pwm_i, PWM_CLK_I_CTRL, 8, 0); + +static A9_COMP_SEL(pwm_j, PWM_CLK_J_CTRL, 9, 0x7, a9_pwm_parents, NULL); +static A9_COMP_DIV(pwm_j, PWM_CLK_J_CTRL, 0, 8); +static A9_COMP_GATE(pwm_j, PWM_CLK_J_CTRL, 8, 0); + +static A9_COMP_SEL(pwm_k, PWM_CLK_K_CTRL, 9, 0x7, a9_pwm_parents, NULL); +static A9_COMP_DIV(pwm_k, PWM_CLK_K_CTRL, 0, 8); +static A9_COMP_GATE(pwm_k, PWM_CLK_K_CTRL, 8, 0); + +static A9_COMP_SEL(pwm_l, PWM_CLK_L_CTRL, 9, 0x7, a9_pwm_parents, NULL); +static A9_COMP_DIV(pwm_l, PWM_CLK_L_CTRL, 0, 8); +static A9_COMP_GATE(pwm_l, PWM_CLK_L_CTRL, 8, 0); + +static A9_COMP_SEL(pwm_m, PWM_CLK_M_CTRL, 9, 0x7, a9_pwm_parents, NULL); +static A9_COMP_DIV(pwm_m, PWM_CLK_M_CTRL, 0, 8); +static A9_COMP_GATE(pwm_m, PWM_CLK_M_CTRL, 8, 0); + +static A9_COMP_SEL(pwm_n, PWM_CLK_N_CTRL, 9, 0x7, a9_pwm_parents, NULL); +static A9_COMP_DIV(pwm_n, PWM_CLK_N_CTRL, 0, 8); +static A9_COMP_GATE(pwm_n, PWM_CLK_N_CTRL, 8, 0); + +static const struct clk_parent_data a9_spisg_parents[] =3D { + { .fw_name =3D "xtal", }, + { .fw_name =3D "sys", }, + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "fdiv2", }, + { .fw_name =3D "fdiv5", }, + { .fw_name =3D "fdiv7", }, + { .fw_name =3D "gp0", } +}; + +static A9_COMP_SEL(spisg, SPISG_CLK_CTRL, 9, 0x7, a9_spisg_parents, NULL); +static A9_COMP_DIV(spisg, SPISG_CLK_CTRL, 0, 6); +static A9_COMP_GATE(spisg, SPISG_CLK_CTRL, 8, 0); + +static A9_COMP_SEL(spisg1, SPISG_CLK_CTRL, 25, 0x7, a9_spisg_parents, NULL= ); +static A9_COMP_DIV(spisg1, SPISG_CLK_CTRL, 16, 6); +static A9_COMP_GATE(spisg1, SPISG_CLK_CTRL, 24, 0); + +static A9_COMP_SEL(spisg2, SPISG_CLK_CTRL1, 9, 0x7, a9_spisg_parents, NULL= ); +static A9_COMP_DIV(spisg2, SPISG_CLK_CTRL1, 0, 6); +static A9_COMP_GATE(spisg2, SPISG_CLK_CTRL1, 8, 0); + +static const struct clk_parent_data a9_saradc_parents[] =3D { + { .fw_name =3D "xtal", }, + { .fw_name =3D "sys", } +}; + +static A9_COMP_SEL(saradc, SAR_CLK_CTRL, 9, 0x7, a9_saradc_parents, NULL); +static A9_COMP_DIV(saradc, SAR_CLK_CTRL, 0, 8); +static A9_COMP_GATE(saradc, SAR_CLK_CTRL, 8, 0); + +static const struct clk_parent_data a9_amfc_parents[] =3D { + { .fw_name =3D "xtal", }, + { .fw_name =3D "sys", }, + { .fw_name =3D "fdiv2", }, + { .fw_name =3D "fdiv2p5", }, + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "fdiv5", }, + { .fw_name =3D "fdiv7", } +}; + +static A9_COMP_SEL(amfc, AMFC_CLK_CTRL, 9, 0x7, a9_amfc_parents, NULL); +static A9_COMP_DIV(amfc, AMFC_CLK_CTRL, 0, 6); +static A9_COMP_GATE(amfc, AMFC_CLK_CTRL, 8, 0); + +static const struct clk_parent_data a9_nna_parents[] =3D { + { .fw_name =3D "xtal", }, + { .fw_name =3D "fdiv2p5", }, + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "fdiv5", }, + { .fw_name =3D "fdiv2", }, + { .fw_name =3D "gp2", }, + { .fw_name =3D "hifi0", } +}; + +static A9_COMP_SEL(nna, NNA_CLK_CTRL, 9, 0x7, a9_nna_parents, NULL); +static A9_COMP_DIV(nna, NNA_CLK_CTRL, 0, 7); +static A9_COMP_GATE(nna, NNA_CLK_CTRL, 8, 0); + +/* Channel 5 and 6 are unconnected. */ +static u32 a9_usb_250m_parents_val_table[] =3D { 0, 1, 2, 3, 4, 7 }; +static const struct clk_parent_data a9_usb_250m_parents[] =3D { + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "fdiv5", }, + { .fw_name =3D "fdiv2", }, + { .fw_name =3D "fdiv7", }, + { .fw_name =3D "fdiv2p5", } +}; + +static A9_COMP_SEL(usb_250m, USB_CLK_CTRL, 9, 0x7, a9_usb_250m_parents, + a9_usb_250m_parents_val_table); +static A9_COMP_DIV(usb_250m, USB_CLK_CTRL, 0, 7); +static A9_COMP_GATE(usb_250m, USB_CLK_CTRL, 8, 0); + +static const struct clk_parent_data a9_usb_48m_pre_parents[] =3D { + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "fdiv5", }, + { .fw_name =3D "fdiv2", }, + { .fw_name =3D "fdiv7", }, + { .fw_name =3D "fdiv2p5", } +}; + +static A9_COMP_SEL(usb_48m_pre, USB_CLK_CTRL, 25, 0x7, a9_usb_48m_pre_pare= nts, + NULL); +static A9_COMP_DIV(usb_48m_pre, USB_CLK_CTRL, 16, 7); +static A9_COMP_GATE(usb_48m_pre, USB_CLK_CTRL, 24, 0); + +static const struct clk_parent_data a9_pcie_tl_parents[] =3D { + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "fdiv5", }, + { .fw_name =3D "fdiv2", }, + { .fw_name =3D "fdiv2p5", }, + { .fw_name =3D "gp0", }, + { .fw_name =3D "sys", }, + { .fw_name =3D "xtal", } +}; + +static A9_COMP_SEL(pcie_tl, PCIE_TL_CLK_CTRL, 9, 0x7, a9_pcie_tl_parents, + NULL); +static A9_COMP_DIV(pcie_tl, PCIE_TL_CLK_CTRL, 0, 7); +static A9_COMP_GATE(pcie_tl, PCIE_TL_CLK_CTRL, 8, 0); + +static A9_COMP_SEL(pcie1_tl, PCIE_TL_CLK_CTRL, 25, 0x7, a9_pcie_tl_parents, + NULL); +static A9_COMP_DIV(pcie1_tl, PCIE_TL_CLK_CTRL, 16, 7); +static A9_COMP_GATE(pcie1_tl, PCIE_TL_CLK_CTRL, 24, 0); + +static const struct clk_parent_data a9_cmpr_parents[] =3D { + { .fw_name =3D "xtal", }, + { .fw_name =3D "fdiv2p5", }, + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "fdiv5", }, + { .fw_name =3D "fdiv7", }, + { .fw_name =3D "hifi0", }, + { .fw_name =3D "gp1", } +}; + +static A9_COMP_SEL(cmpr, CMPR_CLK_CTRL, 25, 0x7, a9_cmpr_parents, NULL); +static A9_COMP_DIV(cmpr, CMPR_CLK_CTRL, 16, 7); +static A9_COMP_GATE(cmpr, CMPR_CLK_CTRL, 24, 0); + +static const struct clk_parent_data a9_dewarpa_parents[] =3D { + { .fw_name =3D "fdiv2p5", }, + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "fdiv5", }, + { .fw_name =3D "fdiv7", }, + { .fw_name =3D "gp0", }, + { .fw_name =3D "hifi0", }, + { .fw_name =3D "gp1", } +}; + +static A9_COMP_SEL(dewarpa, DEWARP_CLK_CTRL, 9, 0x7, a9_dewarpa_parents, N= ULL); +static A9_COMP_DIV(dewarpa, DEWARP_CLK_CTRL, 0, 7); +static A9_COMP_GATE(dewarpa, DEWARP_CLK_CTRL, 8, 0); + +static const struct clk_parent_data a9_sc_parents[] =3D { + { .fw_name =3D "fdiv2", }, + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "fdiv5", }, + { .fw_name =3D "xtal", } +}; + +static A9_COMP_SEL(sc_pre, SC_CLK_CTRL, 9, 0x7, a9_sc_parents, NULL); +static A9_COMP_DIV(sc_pre, SC_CLK_CTRL, 0, 8); +static A9_COMP_GATE(sc_pre, SC_CLK_CTRL, 8, 0); + +static struct clk_regmap a9_sc =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D SC_CLK_CTRL, + .shift =3D 16, + .width =3D 4, + }, + .hw.init =3D CLK_HW_INIT_HW("sc", &a9_sc_pre.hw, + &clk_regmap_divider_ops, CLK_SET_RATE_PARENT), +}; + +static const struct clk_parent_data a9_dptx_apb2_parents[] =3D { + { .fw_name =3D "xtal", }, + { .fw_name =3D "sys", }, + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "fdiv5", } +}; + +static A9_COMP_SEL(dptx_apb2, DPTX_CLK_CTRL, 9, 0x7, a9_dptx_apb2_parents,= NULL); +static A9_COMP_DIV(dptx_apb2, DPTX_CLK_CTRL, 0, 7); +static A9_COMP_GATE(dptx_apb2, DPTX_CLK_CTRL, 8, 0); + +static const struct clk_parent_data a9_dptx_aud_parents[] =3D { + { .fw_name =3D "xtal", }, + { .fw_name =3D "sys", }, + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "fdiv4", } +}; + +static A9_COMP_SEL(dptx_aud, DPTX_CLK_CTRL, 25, 0x7, a9_dptx_aud_parents, = NULL); +static A9_COMP_DIV(dptx_aud, DPTX_CLK_CTRL, 16, 7); +static A9_COMP_GATE(dptx_aud, DPTX_CLK_CTRL, 24, 0); + +static const struct clk_parent_data a9_isp_parents[] =3D { + { .fw_name =3D "fdiv2p5", }, + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "fdiv5", }, + { .fw_name =3D "gp0", }, + { .fw_name =3D "hifi0", }, + { .fw_name =3D "fdiv2", }, + { .fw_name =3D "xtal", } +}; + +static A9_COMP_SEL(isp, ISP_CLK_CTRL, 9, 0x7, a9_isp_parents, NULL); +static A9_COMP_DIV(isp, ISP_CLK_CTRL, 0, 7); +static A9_COMP_GATE(isp, ISP_CLK_CTRL, 8, 0); + +static const struct clk_parent_data a9_cve_vge_parents[] =3D { + { .fw_name =3D "xtal", }, + { .fw_name =3D "fdiv2p5", }, + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "hifi0", }, + { .fw_name =3D "fdiv5", }, + { .fw_name =3D "gp0", }, + { .fw_name =3D "rtc", } +}; + +static A9_COMP_SEL(cve, CVE_CLK_CTRL, 9, 0x7, a9_cve_vge_parents, NULL); +static A9_COMP_DIV(cve, CVE_CLK_CTRL, 0, 7); +static A9_COMP_GATE(cve, CVE_CLK_CTRL, 8, 0); + +static A9_COMP_SEL(vge, CVE_CLK_CTRL, 25, 0x7, a9_cve_vge_parents, NULL); +static A9_COMP_DIV(vge, CVE_CLK_CTRL, 16, 7); +static A9_COMP_GATE(vge, CVE_CLK_CTRL, 24, 0); + +static const struct clk_parent_data a9_pp_parents[] =3D { + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "fdiv5", }, + { .fw_name =3D "fdiv2", }, + { .fw_name =3D "fdiv2p5", }, + { .fw_name =3D "gp0", }, + { .fw_name =3D "sys", }, + { .fw_name =3D "xtal", } +}; + +static A9_COMP_SEL(pp, PP_CLK_CTRL, 9, 0x7, a9_pp_parents, NULL); +static A9_COMP_DIV(pp, PP_CLK_CTRL, 0, 6); +static A9_COMP_GATE(pp, PP_CLK_CTRL, 8, 0); + +/* Channel 6 is unconnected. */ +static u32 a9_glb_parents_val_table[] =3D { 0, 1, 2, 3, 4, 5, 7 }; +static struct clk_regmap a9_dspa; + +static const struct clk_parent_data a9_glb_parents[] =3D { + { .fw_name =3D "xtal", }, + { .hw =3D &a9_dspa.hw }, + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "fdiv5", }, + { .hw =3D &a9_isp.hw }, + { .fw_name =3D "rtc", } +}; + +static A9_COMP_SEL(glb, GLB_CLK_CTRL, 9, 0x7, a9_glb_parents, + a9_glb_parents_val_table); +static A9_COMP_DIV(glb, GLB_CLK_CTRL, 0, 7); +static A9_COMP_GATE(glb, GLB_CLK_CTRL, 8, 0); + +static struct clk_regmap a9_usb_48m_dualdiv_in =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D USB_CLK_CTRL, + .bit_idx =3D 31, + }, + .hw.init =3D CLK_HW_INIT_HW("usb_48m_dualdiv_in", &a9_usb_48m_pre.hw, + &clk_regmap_gate_ops, 0), +}; + +static const struct meson_clk_dualdiv_param a9_usb_48m_dualdiv_div_table[]= =3D { + { 733, 732, 8, 11, 1 }, + { /* sentinel */ } +}; + +static struct clk_regmap a9_usb_48m_dualdiv_div =3D { + .data =3D &(struct meson_clk_dualdiv_data) { + .n1 =3D { + .reg_off =3D USB_CLK_CTRL0, + .shift =3D 0, + .width =3D 12, + }, + .n2 =3D { + .reg_off =3D USB_CLK_CTRL0, + .shift =3D 12, + .width =3D 12, + }, + .m1 =3D { + .reg_off =3D USB_CLK_CTRL1, + .shift =3D 0, + .width =3D 12, + }, + .m2 =3D { + .reg_off =3D USB_CLK_CTRL1, + .shift =3D 12, + .width =3D 12, + }, + .dual =3D { + .reg_off =3D USB_CLK_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .table =3D a9_usb_48m_dualdiv_div_table, + }, + .hw.init =3D CLK_HW_INIT_HW("usb_48m_dualdiv_div", &a9_usb_48m_dualdiv_in= .hw, + &meson_clk_dualdiv_ops, 0), +}; + +static struct clk_regmap a9_usb_48m_dualdiv_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D USB_CLK_CTRL1, + .mask =3D 0x1, + .shift =3D 24, + }, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("usb_48m_dualdiv_sel", + ((const struct clk_hw *[]) { + &a9_usb_48m_dualdiv_in.hw, + &a9_usb_48m_dualdiv_div.hw, + }), &clk_regmap_mux_ops, CLK_SET_RATE_PARENT), +}; + +static struct clk_regmap a9_usb_48m_dualdiv =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D USB_CLK_CTRL0, + .bit_idx =3D 30, + }, + .hw.init =3D CLK_HW_INIT_HW("usb_48m_dualdiv", &a9_usb_48m_dualdiv_sel.hw, + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT), +}; + +static struct clk_regmap a9_usb_48m =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D USB_CLK_CTRL1, + .mask =3D 0x3, + .shift =3D 30, + }, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("usb_48m", + ((const struct clk_hw *[]) { + &a9_usb_48m_pre.hw, + &a9_usb_48m_dualdiv.hw, + }), &clk_regmap_mux_ops, CLK_SET_RATE_PARENT), +}; + +/* Channel 3 is unconnected. */ +static u32 a9_can_pe_parents_val_table[] =3D { 0, 1, 3 }; +static const struct clk_parent_data a9_can_pe_parents[] =3D { + { .fw_name =3D "sys", }, + { .fw_name =3D "xtal", }, + { .fw_name =3D "fdiv5", } +}; + +static A9_COMP_SEL(can_pe, CAN_CLK_CTRL, 9, 0x7, a9_can_pe_parents, + a9_can_pe_parents_val_table); +static A9_COMP_DIV(can_pe, CAN_CLK_CTRL, 0, 7); +static A9_COMP_GATE(can_pe, CAN_CLK_CTRL, 8, 0); + +static A9_COMP_SEL(can1_pe, CAN_CLK_CTRL, 25, 0x7, a9_can_pe_parents, + a9_can_pe_parents_val_table); +static A9_COMP_DIV(can1_pe, CAN_CLK_CTRL, 16, 7); +static A9_COMP_GATE(can1_pe, CAN_CLK_CTRL, 24, 0); + +static const struct clk_parent_data a9_can_filter_parents[] =3D { + { .fw_name =3D "sys", }, + { .fw_name =3D "xtal", }, + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "fdiv5", } +}; + +static A9_COMP_SEL(can_filter, CAN_CLK_CTRL1, 9, 0x7, a9_can_filter_parent= s, + NULL); +static A9_COMP_DIV(can_filter, CAN_CLK_CTRL1, 0, 7); +static A9_COMP_GATE(can_filter, CAN_CLK_CTRL1, 8, 0); + +static A9_COMP_SEL(can1_filter, CAN_CLK_CTRL1, 25, 0x7, a9_can_filter_pare= nts, + NULL); +static A9_COMP_DIV(can1_filter, CAN_CLK_CTRL1, 16, 7); +static A9_COMP_GATE(can1_filter, CAN_CLK_CTRL1, 24, 0); + +static const struct clk_parent_data a9_i3c_parents[] =3D { + { .fw_name =3D "sys", }, + { .fw_name =3D "xtal", }, + { .fw_name =3D "fdiv5", } +}; + +static A9_COMP_SEL(i3c, I3C_CLK_CTRL, 9, 0x7, a9_i3c_parents, NULL); +static A9_COMP_DIV(i3c, I3C_CLK_CTRL, 0, 8); +static A9_COMP_GATE(i3c, I3C_CLK_CTRL, 8, 0); + +static struct clk_regmap a9_ts_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D TS_CLK_CTRL, + .shift =3D 0, + .width =3D 8, + }, + .hw.init =3D CLK_HW_INIT_FW_NAME("ts_div", "xtal", + &clk_regmap_divider_ops, 0), +}; + +static struct clk_regmap a9_ts =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D TS_CLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D CLK_HW_INIT_HW("ts", &a9_ts_div.hw, + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT), +}; + +static struct clk_fixed_factor a9_eth_125m_div =3D { + .mult =3D 1, + .div =3D 8, + .hw.init =3D CLK_HW_INIT_FW_NAME("eth_125m_div", "fdiv2", + &clk_fixed_factor_ops, 0), +}; + +static struct clk_regmap a9_eth_125m =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D ETH_CLK_CTRL, + .bit_idx =3D 7, + }, + .hw.init =3D CLK_HW_INIT_HW("eth_125m", &a9_eth_125m_div.hw, + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT), +}; + +/* + * Channel 1, 2, 3, 4, 5 and 6 are unconnected, + * ext_rmii connects external PAD. Do not automatically reparent. + */ +static u32 a9_eth_rmii_parents_val_table[] =3D { 0, 7 }; +static const struct clk_parent_data a9_eth_rmii_parents[] =3D { + { .fw_name =3D "fdiv2", }, + { .fw_name =3D "ext_rmii", } +}; + +static struct clk_regmap a9_eth_rmii_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D ETH_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 9, + .table =3D a9_eth_rmii_parents_val_table, + }, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("eth_rmii_sel", + a9_eth_rmii_parents, + &clk_regmap_mux_ops, CLK_SET_RATE_NO_REPARENT), +}; + +static struct clk_regmap a9_eth_rmii_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D ETH_CLK_CTRL, + .shift =3D 0, + .width =3D 7, + }, + .hw.init =3D CLK_HW_INIT_HW("eth_rmii_div", &a9_eth_rmii_sel.hw, + &clk_regmap_divider_ops, CLK_SET_RATE_PARENT), +}; + +static struct clk_regmap a9_eth_rmii =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D ETH_CLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D CLK_HW_INIT_HW("eth_rmii", &a9_eth_rmii_div.hw, + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT), +}; + +/* + * Channel 3(ddr_dpll_pt_clk) is manged by the DDR module; + * channel 12(msr_clk) is manged by clock measures module. + * channel 16(audio_dac1_clk) is manged by audio module. + * Channel 10, 11, 13, 14 are not connected. + */ +static u32 a9_gen_parents_val_table[] =3D { 0, 1, 2, 4, 5, 6, 7, 8, 9, 15,= 17, 18, + 19, 20, 21, 22, 23, 24, 25, 26}; +static struct clk_regmap a9_vid_pll; + +static const struct clk_parent_data a9_gen_parents[] =3D { + { .fw_name =3D "xtal" }, + { .fw_name =3D "rtc" }, + { .fw_name =3D "sysplldiv16" }, + { .hw =3D &a9_vid_pll.hw }, + { .fw_name =3D "gp0" }, + { .fw_name =3D "hifi1" }, + { .fw_name =3D "hifi0" }, + { .fw_name =3D "gp1" }, + { .fw_name =3D "gp2" }, + { .fw_name =3D "dsudiv16" }, + { .fw_name =3D "cpudiv16" }, + { .fw_name =3D "a78div16" }, + { .fw_name =3D "fdiv2" }, + { .fw_name =3D "fdiv2p5" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "fdiv4" }, + { .fw_name =3D "fdiv5" }, + { .fw_name =3D "fdiv7" }, + { .fw_name =3D "mclk0" }, + { .fw_name =3D "mclk1" } +}; + +static A9_COMP_SEL(gen, GEN_CLK_CTRL, 12, 0x1f, a9_gen_parents, + a9_gen_parents_val_table); +static A9_COMP_DIV(gen, GEN_CLK_CTRL, 0, 12); +static A9_COMP_GATE(gen, GEN_CLK_CTRL, 11, 0); + +static struct clk_regmap a9_24m_in =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLK12_24_CTRL, + .bit_idx =3D 11, + }, + .hw.init =3D CLK_HW_INIT_FW_NAME("24m_in", "xtal", + &clk_regmap_gate_ops, 0), +}; + +static struct clk_regmap a9_12_24m =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLK12_24_CTRL, + .shift =3D 10, + .width =3D 1, + }, + .hw.init =3D CLK_HW_INIT_HW("12_24m", &a9_24m_in.hw, + &clk_regmap_divider_ops, 0), +}; + +static const struct clk_parent_data a9_mali_parents[] =3D { + { .fw_name =3D "xtal", }, + { .fw_name =3D "gp1", }, + { .fw_name =3D "fdiv2", }, + { .fw_name =3D "fdiv2p5", }, + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "fdiv5", }, + { .fw_name =3D "fdiv7", } +}; + +static A9_COMP_SEL(mali_0, MALI_CLK_CTRL, 9, 0x7, a9_mali_parents, NULL); +static A9_COMP_DIV(mali_0, MALI_CLK_CTRL, 0, 7); +static A9_COMP_GATE(mali_0, MALI_CLK_CTRL, 8, CLK_SET_RATE_GATE); + +static A9_COMP_SEL(mali_1, MALI_CLK_CTRL, 25, 0x7, a9_mali_parents, NULL); +static A9_COMP_DIV(mali_1, MALI_CLK_CTRL, 16, 7); +static A9_COMP_GATE(mali_1, MALI_CLK_CTRL, 24, CLK_SET_RATE_GATE); + +static struct clk_regmap a9_mali =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D MALI_CLK_CTRL, + .mask =3D 0x1, + .shift =3D 31, + }, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("mali", + ((const struct clk_hw *[]) { + &a9_mali_0.hw, + &a9_mali_1.hw, + }), &clk_regmap_mux_ops, CLK_SET_RATE_PARENT), +}; + +static A9_COMP_SEL(mali_stack_0, MALI_STACK_CLK_CTRL, 9, 0x7, a9_mali_pare= nts, + NULL); +static A9_COMP_DIV(mali_stack_0, MALI_STACK_CLK_CTRL, 0, 7); +static A9_COMP_GATE(mali_stack_0, MALI_STACK_CLK_CTRL, 8, CLK_SET_RATE_GAT= E); + +static A9_COMP_SEL(mali_stack_1, MALI_STACK_CLK_CTRL, 25, 0x7, a9_mali_par= ents, + NULL); +static A9_COMP_DIV(mali_stack_1, MALI_STACK_CLK_CTRL, 16, 7); +static A9_COMP_GATE(mali_stack_1, MALI_STACK_CLK_CTRL, 24, CLK_SET_RATE_GA= TE); + +static struct clk_regmap a9_mali_stack =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D MALI_STACK_CLK_CTRL, + .mask =3D 0x1, + .shift =3D 31, + }, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("mali_stack", + ((const struct clk_hw *[]) { + &a9_mali_stack_0.hw, + &a9_mali_stack_1.hw, + }), &clk_regmap_mux_ops, CLK_SET_RATE_PARENT), +}; + +static const struct clk_parent_data a9_dspa_parents[] =3D { + { .fw_name =3D "xtal", }, + { .fw_name =3D "fdiv2p5", }, + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "fdiv5", }, + { .fw_name =3D "gp2", }, + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "hifi0", }, + { .fw_name =3D "rtc", } +}; + +static A9_COMP_SEL(dspa_0, DSPA_CLK_CTRL, 9, 0x7, a9_dspa_parents, NULL); +static A9_COMP_DIV(dspa_0, DSPA_CLK_CTRL, 0, 7); +static A9_COMP_GATE(dspa_0, DSPA_CLK_CTRL, 8, CLK_SET_RATE_GATE); + +static A9_COMP_SEL(dspa_1, DSPA_CLK_CTRL, 25, 0x7, a9_dspa_parents, NULL); +static A9_COMP_DIV(dspa_1, DSPA_CLK_CTRL, 16, 7); +static A9_COMP_GATE(dspa_1, DSPA_CLK_CTRL, 24, CLK_SET_RATE_GATE); + +static struct clk_regmap a9_dspa =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D DSPA_CLK_CTRL, + .mask =3D 0x1, + .shift =3D 31, + }, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("dspa", + ((const struct clk_hw *[]) { + &a9_dspa_0.hw, + &a9_dspa_1.hw, + }), &clk_regmap_mux_ops, CLK_SET_RATE_PARENT), +}; + +static const struct clk_parent_data a9_hevcf_parents[] =3D { + { .fw_name =3D "fdiv2p5", }, + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "fdiv5", }, + { .fw_name =3D "fdiv7", }, + { .fw_name =3D "hifi0", }, + { .fw_name =3D "gp1", }, + { .fw_name =3D "xtal", } +}; + +static A9_COMP_SEL(hevcf_0, HEVCF_CLK_CTRL, 9, 0x7, a9_hevcf_parents, NULL= ); +static A9_COMP_DIV(hevcf_0, HEVCF_CLK_CTRL, 0, 7); +static A9_COMP_GATE(hevcf_0, HEVCF_CLK_CTRL, 8, CLK_SET_RATE_GATE); + +static A9_COMP_SEL(hevcf_1, HEVCF_CLK_CTRL, 25, 0x7, a9_hevcf_parents, NUL= L); +static A9_COMP_DIV(hevcf_1, HEVCF_CLK_CTRL, 16, 7); +static A9_COMP_GATE(hevcf_1, HEVCF_CLK_CTRL, 24, CLK_SET_RATE_GATE); + +static struct clk_regmap a9_hevcf =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D HEVCF_CLK_CTRL, + .mask =3D 0x1, + .shift =3D 31, + }, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("hevcf", + ((const struct clk_hw *[]) { + &a9_hevcf_0.hw, + &a9_hevcf_1.hw, + }), &clk_regmap_mux_ops, CLK_SET_RATE_PARENT), +}; + +static const struct clk_parent_data a9_hcodec_parents[] =3D { + { .fw_name =3D "fdiv2p5", }, + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "fdiv5", }, + { .fw_name =3D "fdiv7", }, + { .fw_name =3D "hifi0", }, + { .fw_name =3D "gp0", }, + { .fw_name =3D "xtal", } +}; + +static A9_COMP_SEL(hcodec_0, HCODEC_CLK_CTRL, 9, 0x7, a9_hcodec_parents, N= ULL); +static A9_COMP_DIV(hcodec_0, HCODEC_CLK_CTRL, 0, 7); +static A9_COMP_GATE(hcodec_0, HCODEC_CLK_CTRL, 8, CLK_SET_RATE_GATE); + +static A9_COMP_SEL(hcodec_1, HCODEC_CLK_CTRL, 25, 0x7, a9_hcodec_parents, = NULL); +static A9_COMP_DIV(hcodec_1, HCODEC_CLK_CTRL, 16, 7); +static A9_COMP_GATE(hcodec_1, HCODEC_CLK_CTRL, 24, CLK_SET_RATE_GATE); + +static struct clk_regmap a9_hcodec =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D HCODEC_CLK_CTRL, + .mask =3D 0x1, + .shift =3D 31, + }, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("hcodec", + ((const struct clk_hw *[]) { + &a9_hcodec_0.hw, + &a9_hcodec_1.hw, + }), &clk_regmap_mux_ops, CLK_SET_RATE_PARENT), +}; + +static const struct clk_parent_data a9_vpu_parents[] =3D { + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "fdiv5", }, + { .fw_name =3D "vid1", }, + { .fw_name =3D "fdiv2", }, + { .hw =3D &a9_vid_pll.hw }, + { .fw_name =3D "vid2", }, + { .fw_name =3D "gp1", } +}; + +static A9_COMP_SEL(vpu_0, VPU_CLK_CTRL, 9, 0x7, a9_vpu_parents, NULL); +static A9_COMP_DIV(vpu_0, VPU_CLK_CTRL, 0, 7); +static A9_COMP_GATE(vpu_0, VPU_CLK_CTRL, 8, CLK_SET_RATE_GATE); + +static A9_COMP_SEL(vpu_1, VPU_CLK_CTRL, 25, 0x7, a9_vpu_parents, NULL); +static A9_COMP_DIV(vpu_1, VPU_CLK_CTRL, 16, 7); +static A9_COMP_GATE(vpu_1, VPU_CLK_CTRL, 24, CLK_SET_RATE_GATE); + +static struct clk_regmap a9_vpu =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D VPU_CLK_CTRL, + .mask =3D 0x1, + .shift =3D 31, + }, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("vpu", + ((const struct clk_hw *[]) { + &a9_vpu_0.hw, + &a9_vpu_1.hw, + }), &clk_regmap_mux_ops, CLK_SET_RATE_PARENT), +}; + +static const struct clk_parent_data a9_vapb_parents[] =3D { + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "fdiv5", }, + { .fw_name =3D "fdiv7", }, + { .fw_name =3D "fdiv2", }, + { .hw =3D &a9_vid_pll.hw }, + { .fw_name =3D "hifi0", }, + { .fw_name =3D "fdiv2p5", } +}; + +static A9_COMP_SEL(vapb_0, VAPB_CLK_CTRL, 9, 0x7, a9_vapb_parents, NULL); +static A9_COMP_DIV(vapb_0, VAPB_CLK_CTRL, 0, 7); +static A9_COMP_GATE(vapb_0, VAPB_CLK_CTRL, 8, CLK_SET_RATE_GATE); + +static A9_COMP_SEL(vapb_1, VAPB_CLK_CTRL, 25, 0x7, a9_vapb_parents, NULL); +static A9_COMP_DIV(vapb_1, VAPB_CLK_CTRL, 16, 7); +static A9_COMP_GATE(vapb_1, VAPB_CLK_CTRL, 24, CLK_SET_RATE_GATE); + +static struct clk_regmap a9_vapb =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D VAPB_CLK_CTRL, + .mask =3D 0x1, + .shift =3D 31, + }, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("vapb", + ((const struct clk_hw *[]) { + &a9_vapb_0.hw, + &a9_vapb_1.hw, + }), &clk_regmap_mux_ops, CLK_SET_RATE_PARENT), +}; + +static struct clk_regmap a9_ge2d =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D VAPB_CLK_CTRL, + .bit_idx =3D 30, + }, + .hw.init =3D CLK_HW_INIT_HW("ge2d", &a9_vapb.hw, + &clk_regmap_gate_ops, 0), +}; + +static const struct clk_parent_data a9_vpu_clkb_tmp_parents[] =3D { + { .hw =3D &a9_vpu.hw }, + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "fdiv5", }, + { .fw_name =3D "fdiv7", } +}; + +static A9_COMP_SEL(vpu_clkb_tmp, VPU_CLKB_CTRL, 25, 0x7, a9_vpu_clkb_tmp_p= arents, + NULL); +static A9_COMP_DIV(vpu_clkb_tmp, VPU_CLKB_CTRL, 16, 4); +static A9_COMP_GATE(vpu_clkb_tmp, VPU_CLKB_CTRL, 24, 0); + +static struct clk_regmap a9_vpu_clkb_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D VPU_CLKB_CTRL, + .shift =3D 0, + .width =3D 8, + }, + .hw.init =3D CLK_HW_INIT_HW("vpu_clkb_div", &a9_vpu_clkb_tmp.hw, + &clk_regmap_divider_ops, 0), +}; + +static struct clk_regmap a9_vpu_clkb =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D VPU_CLKB_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D CLK_HW_INIT_HW("vpu_clkb", &a9_vpu_clkb_div.hw, + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT), +}; + +static const struct clk_parent_data a9_hdmi_parents[] =3D { + { .fw_name =3D "xtal", }, + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "fdiv5", } +}; + +static A9_COMP_SEL(hdmitx_sys, HDMI_CLK_CTRL, 9, 0x7, a9_hdmi_parents, NUL= L); +static A9_COMP_DIV(hdmitx_sys, HDMI_CLK_CTRL, 0, 7); +static A9_COMP_GATE(hdmitx_sys, HDMI_CLK_CTRL, 8, 0); + +static A9_COMP_SEL(hdmitx_prif, HTX_CLK_CTRL, 9, 0x7, a9_hdmi_parents, NUL= L); +static A9_COMP_DIV(hdmitx_prif, HTX_CLK_CTRL, 0, 7); +static A9_COMP_GATE(hdmitx_prif, HTX_CLK_CTRL, 8, 0); + +static A9_COMP_SEL(hdmitx_200m, HTX_CLK_CTRL, 25, 0x7, a9_hdmi_parents, NU= LL); +static A9_COMP_DIV(hdmitx_200m, HTX_CLK_CTRL, 16, 7); +static A9_COMP_GATE(hdmitx_200m, HTX_CLK_CTRL, 24, 0); + +static A9_COMP_SEL(hdmitx_aud, HTX_CLK_CTRL1, 9, 0x7, a9_hdmi_parents, NUL= L); +static A9_COMP_DIV(hdmitx_aud, HTX_CLK_CTRL1, 0, 7); +static A9_COMP_GATE(hdmitx_aud, HTX_CLK_CTRL1, 8, 0); + +static A9_COMP_SEL(hdmirx_5m, HRX_CLK_CTRL, 9, 0x7, a9_hdmi_parents, + NULL); +static A9_COMP_DIV(hdmirx_5m, HRX_CLK_CTRL, 0, 7); +static A9_COMP_GATE(hdmirx_5m, HRX_CLK_CTRL, 8, 0); + +static A9_COMP_SEL(hdmirx_2m, HRX_CLK_CTRL, 25, 0x7, a9_hdmi_parents, + NULL); +static A9_COMP_DIV(hdmirx_2m, HRX_CLK_CTRL, 16, 7); +static A9_COMP_GATE(hdmirx_2m, HRX_CLK_CTRL, 24, 0); + +static A9_COMP_SEL(hdmirx_cfg, HRX_CLK_CTRL1, 9, 0x7, a9_hdmi_parents, + NULL); +static A9_COMP_DIV(hdmirx_cfg, HRX_CLK_CTRL1, 0, 7); +static A9_COMP_GATE(hdmirx_cfg, HRX_CLK_CTRL1, 8, 0); + +static A9_COMP_SEL(hdmirx_hdcp2x, HRX_CLK_CTRL1, 25, 0x7, a9_hdmi_parents, + NULL); +static A9_COMP_DIV(hdmirx_hdcp2x, HRX_CLK_CTRL1, 16, 7); +static A9_COMP_GATE(hdmirx_hdcp2x, HRX_CLK_CTRL1, 24, 0); + +static A9_COMP_SEL(hdmirx_acr_ref, HRX_CLK_CTRL2, 25, 0x7, a9_hdmi_parents, + NULL); +static A9_COMP_DIV(hdmirx_acr_ref, HRX_CLK_CTRL2, 16, 7); +static A9_COMP_GATE(hdmirx_acr_ref, HRX_CLK_CTRL2, 24, 0); + +static A9_COMP_SEL(hdmirx_meter, HRX_CLK_CTRL3, 9, 0x7, a9_hdmi_parents, + NULL); +static A9_COMP_DIV(hdmirx_meter, HRX_CLK_CTRL3, 0, 7); +static A9_COMP_GATE(hdmirx_meter, HRX_CLK_CTRL3, 8, 0); + +static struct clk_regmap a9_enc, a9_enc1; + +static const struct clk_parent_data a9_vid_lock_parents[] =3D { + { .fw_name =3D "xtal", }, + { .hw =3D &a9_enc.hw }, + { .hw =3D &a9_enc1.hw } +}; + +static A9_COMP_SEL(vid_lock, VID_LOCK_CLK_CTRL, 9, 0x7, a9_vid_lock_parent= s, + NULL); +static A9_COMP_DIV(vid_lock, VID_LOCK_CLK_CTRL, 0, 7); +static A9_COMP_GATE(vid_lock, VID_LOCK_CLK_CTRL, 8, 0); + +static const struct clk_parent_data a9_vdin_meas_parents[] =3D { + { .fw_name =3D "xtal", }, + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "fdiv5", } +}; + +static A9_COMP_SEL(vdin_meas, VDIN_MEAS_CLK_CTRL, 9, 0x7, a9_vdin_meas_par= ents, + NULL); +static A9_COMP_DIV(vdin_meas, VDIN_MEAS_CLK_CTRL, 0, 7); +static A9_COMP_GATE(vdin_meas, VDIN_MEAS_CLK_CTRL, 8, 0); + +static struct clk_regmap a9_vid_pll_div =3D { + .data =3D &(struct meson_vid_pll_div_data){ + .val =3D { + .reg_off =3D VID_PLL_CLK_DIV, + .shift =3D 0, + .width =3D 15, + }, + .sel =3D { + .reg_off =3D VID_PLL_CLK_DIV, + .shift =3D 16, + .width =3D 2, + }, + }, + .hw.init =3D CLK_HW_INIT_FW_NAME("vid_pll_div", "hdmiout2", + &meson_vid_pll_div_ro_ops, 0), +}; + +static struct clk_regmap a9_vid_pll_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D VID_PLL_CLK_DIV, + .mask =3D 0x1, + .shift =3D 18, + }, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("vid_pll_sel", + ((const struct clk_parent_data []) { + { .hw =3D &a9_vid_pll_div.hw }, + { .fw_name =3D "hdmiout2" } + }), &clk_regmap_mux_ops, CLK_SET_RATE_PARENT), +}; + +static struct clk_regmap a9_vid_pll =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D VID_PLL_CLK_DIV, + .bit_idx =3D 19, + }, + .hw.init =3D CLK_HW_INIT_HW("vid_pll", &a9_vid_pll_sel.hw, + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT), +}; + +static struct clk_regmap a9_vid_pll_vclk =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D HDMI_CLK_CTRL, + .mask =3D 0x1, + .shift =3D 15, + }, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("vid_pll_vclk", + ((const struct clk_parent_data []) { + { .hw =3D &a9_vid_pll.hw }, + { .fw_name =3D "hdmipix" } + }), &clk_regmap_mux_ops, 0), +}; + +static const struct clk_parent_data a9_vclk_parents[] =3D { + { .hw =3D &a9_vid_pll_vclk.hw }, + { .fw_name =3D "pix0", }, + { .fw_name =3D "vid1", }, + { .fw_name =3D "pix1", }, + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "fdiv5", }, + { .fw_name =3D "vid2", } +}; + +static struct clk_regmap a9_vclk_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D VID_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 16, + }, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("vclk_sel", a9_vclk_parents, + &clk_regmap_mux_ops, 0), +}; + +static struct clk_regmap a9_vclk_in =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D VID_CLK_DIV, + .bit_idx =3D 16, + }, + .hw.init =3D CLK_HW_INIT_HW("vclk_in", &a9_vclk_sel.hw, + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT), +}; + +static struct clk_regmap a9_vclk_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D VID_CLK_DIV, + .shift =3D 0, + .width =3D 8, + }, + .hw.init =3D CLK_HW_INIT_HW("vclk_div", &a9_vclk_in.hw, + &clk_regmap_divider_ops, CLK_SET_RATE_PARENT), +}; + +static struct clk_regmap a9_vclk =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D VID_CLK_CTRL, + .bit_idx =3D 19, + }, + .hw.init =3D CLK_HW_INIT_HW("vclk", &a9_vclk_div.hw, + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT), +}; + +static struct clk_regmap a9_vclk_div1_en =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D VID_CLK_CTRL, + .bit_idx =3D 0, + }, + .hw.init =3D CLK_HW_INIT_HW("vclk_div1_en", &a9_vclk.hw, + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT), +}; + +static struct clk_regmap a9_vclk_div2_en =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D VID_CLK_CTRL, + .bit_idx =3D 1, + }, + .hw.init =3D CLK_HW_INIT_HW("vclk_div2_en", &a9_vclk.hw, + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT), +}; + +static struct clk_fixed_factor a9_vclk_div2 =3D { + .mult =3D 1, + .div =3D 2, + .hw.init =3D CLK_HW_INIT_HW("vclk_div2", &a9_vclk_div2_en.hw, + &clk_fixed_factor_ops, CLK_SET_RATE_PARENT), +}; + +static struct clk_regmap a9_vclk_div4_en =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D VID_CLK_CTRL, + .bit_idx =3D 2, + }, + .hw.init =3D CLK_HW_INIT_HW("vclk_div4_en", &a9_vclk.hw, + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT), +}; + +static struct clk_fixed_factor a9_vclk_div4 =3D { + .mult =3D 1, + .div =3D 4, + .hw.init =3D CLK_HW_INIT_HW("vclk_div4", &a9_vclk_div4_en.hw, + &clk_fixed_factor_ops, CLK_SET_RATE_PARENT), +}; + +static struct clk_regmap a9_vclk_div6_en =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D VID_CLK_CTRL, + .bit_idx =3D 3, + }, + .hw.init =3D CLK_HW_INIT_HW("vclk_div6_en", &a9_vclk.hw, + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT), +}; + +static struct clk_fixed_factor a9_vclk_div6 =3D { + .mult =3D 1, + .div =3D 6, + .hw.init =3D CLK_HW_INIT_HW("vclk_div6", &a9_vclk_div6_en.hw, + &clk_fixed_factor_ops, CLK_SET_RATE_PARENT), +}; + +static struct clk_regmap a9_vclk_div12_en =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D VID_CLK_CTRL, + .bit_idx =3D 4, + }, + .hw.init =3D CLK_HW_INIT_HW("vclk_div12_en", &a9_vclk.hw, + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT), +}; + +static struct clk_fixed_factor a9_vclk_div12 =3D { + .mult =3D 1, + .div =3D 12, + .hw.init =3D CLK_HW_INIT_HW("vclk_div12", &a9_vclk_div12_en.hw, + &clk_fixed_factor_ops, CLK_SET_RATE_PARENT), +}; + +static struct clk_regmap a9_vclk2_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D VIID_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 16, + }, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("vclk2_sel", a9_vclk_parents, + &clk_regmap_mux_ops, 0), +}; + +static struct clk_regmap a9_vclk2_in =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D VIID_CLK_DIV, + .bit_idx =3D 16, + }, + .hw.init =3D CLK_HW_INIT_HW("vclk2_in", &a9_vclk2_sel.hw, + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT), +}; + +static struct clk_regmap a9_vclk2_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D VIID_CLK_DIV, + .shift =3D 0, + .width =3D 8, + }, + .hw.init =3D CLK_HW_INIT_HW("vclk2_div", &a9_vclk2_in.hw, + &clk_regmap_divider_ops, CLK_SET_RATE_PARENT), +}; + +static struct clk_regmap a9_vclk2 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D VIID_CLK_CTRL, + .bit_idx =3D 19, + }, + .hw.init =3D CLK_HW_INIT_HW("vclk2", &a9_vclk2_div.hw, + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT), +}; + +static struct clk_regmap a9_vclk2_div1_en =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D VIID_CLK_CTRL, + .bit_idx =3D 0, + }, + .hw.init =3D CLK_HW_INIT_HW("vclk2_div1_en", &a9_vclk2.hw, + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT), +}; + +static struct clk_regmap a9_vclk2_div2_en =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D VIID_CLK_CTRL, + .bit_idx =3D 1, + }, + .hw.init =3D CLK_HW_INIT_HW("vclk2_div2_en", &a9_vclk2.hw, + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT), +}; + +static struct clk_fixed_factor a9_vclk2_div2 =3D { + .mult =3D 1, + .div =3D 2, + .hw.init =3D CLK_HW_INIT_HW("vclk2_div2", &a9_vclk2_div2_en.hw, + &clk_fixed_factor_ops, CLK_SET_RATE_PARENT), +}; + +static struct clk_regmap a9_vclk2_div4_en =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D VIID_CLK_CTRL, + .bit_idx =3D 2, + }, + .hw.init =3D CLK_HW_INIT_HW("vclk2_div4_en", &a9_vclk2.hw, + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT), +}; + +static struct clk_fixed_factor a9_vclk2_div4 =3D { + .mult =3D 1, + .div =3D 4, + .hw.init =3D CLK_HW_INIT_HW("vclk2_div4", &a9_vclk2_div4_en.hw, + &clk_fixed_factor_ops, CLK_SET_RATE_PARENT), +}; + +static struct clk_regmap a9_vclk2_div6_en =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D VIID_CLK_CTRL, + .bit_idx =3D 3, + }, + .hw.init =3D CLK_HW_INIT_HW("vclk2_div6_en", &a9_vclk2.hw, + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT), +}; + +static struct clk_fixed_factor a9_vclk2_div6 =3D { + .mult =3D 1, + .div =3D 6, + .hw.init =3D CLK_HW_INIT_HW("vclk2_div6", &a9_vclk2_div6_en.hw, + &clk_fixed_factor_ops, CLK_SET_RATE_PARENT), +}; + +static struct clk_regmap a9_vclk2_div12_en =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D VIID_CLK_CTRL, + .bit_idx =3D 4, + }, + .hw.init =3D CLK_HW_INIT_HW("vclk2_div12_en", &a9_vclk2.hw, + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT), +}; + +static struct clk_fixed_factor a9_vclk2_div12 =3D { + .mult =3D 1, + .div =3D 12, + .hw.init =3D CLK_HW_INIT_HW("vclk2_div12", &a9_vclk2_div12_en.hw, + &clk_fixed_factor_ops, CLK_SET_RATE_PARENT), +}; + +/* Channel 5, 6 and 7 are unconnected */ +static u32 a9_vid_parents_val_table[] =3D { 0, 1, 2, 3, 4, 8, 9, 10, 11, 1= 2 }; +static const struct clk_hw *a9_vid_parents[] =3D { + &a9_vclk_div1_en.hw, + &a9_vclk_div2.hw, + &a9_vclk_div4.hw, + &a9_vclk_div6.hw, + &a9_vclk_div12.hw, + &a9_vclk2_div1_en.hw, + &a9_vclk2_div2.hw, + &a9_vclk2_div4.hw, + &a9_vclk2_div6.hw, + &a9_vclk2_div12.hw +}; + +static struct clk_regmap a9_vdac_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D VIID_CLK_DIV, + .mask =3D 0xf, + .shift =3D 28, + .table =3D a9_vid_parents_val_table, + }, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("vdac_sel", a9_vid_parents + , &clk_regmap_mux_ops, 0), +}; + +static struct clk_regmap a9_vdac =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D VID_CLK_CTRL2, + .bit_idx =3D 4, + }, + .hw.init =3D CLK_HW_INIT_HW("vdac", &a9_vdac_sel.hw, + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT), +}; + +static struct clk_regmap a9_enc_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D VIID_CLK_DIV, + .mask =3D 0xf, + .shift =3D 12, + .table =3D a9_vid_parents_val_table, + }, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("enc_sel", a9_vid_parents + , &clk_regmap_mux_ops, 0), +}; + +static struct clk_regmap a9_enc =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D VID_CLK_CTRL2, + .bit_idx =3D 10, + }, + .hw.init =3D CLK_HW_INIT_HW("enc", &a9_enc_sel.hw, + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT), +}; + +static struct clk_regmap a9_enc1_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D VIID_CLK_DIV, + .mask =3D 0xf, + .shift =3D 8, + .table =3D a9_vid_parents_val_table, + }, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("enc1_sel", a9_vid_parents + , &clk_regmap_mux_ops, 0), +}; + +static struct clk_regmap a9_enc1 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D VID_CLK_CTRL2, + .bit_idx =3D 11, + }, + .hw.init =3D CLK_HW_INIT_HW("enc1", &a9_enc1_sel.hw, + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT), +}; + +static struct clk_regmap a9_hdmitx_pixel_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D HDMI_CLK_CTRL, + .mask =3D 0xf, + .shift =3D 16, + .table =3D a9_vid_parents_val_table, + }, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("hdmitx_pixel_sel", a9_vid_parents + , &clk_regmap_mux_ops, 0), +}; + +static struct clk_regmap a9_hdmitx_pixel =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D VID_CLK_CTRL2, + .bit_idx =3D 5, + }, + .hw.init =3D CLK_HW_INIT_HW("hdmitx_pixel", &a9_hdmitx_pixel_sel.hw, + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT), +}; + +static struct clk_regmap a9_hdmitx_fe_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D HDMI_CLK_CTRL, + .mask =3D 0xf, + .shift =3D 20, + .table =3D a9_vid_parents_val_table, + }, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("hdmitx_fe_sel", a9_vid_parents + , &clk_regmap_mux_ops, 0), +}; + +static struct clk_regmap a9_hdmitx_fe =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D VID_CLK_CTRL2, + .bit_idx =3D 9, + }, + .hw.init =3D CLK_HW_INIT_HW("hdmitx_fe", &a9_hdmitx_fe_sel.hw, + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT), +}; + +static struct clk_regmap a9_hdmitx1_pixel_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D HDMI_CLK_CTRL, + .mask =3D 0xf, + .shift =3D 24, + .table =3D a9_vid_parents_val_table, + }, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("hdmitx1_pixel_sel", a9_vid_parents + , &clk_regmap_mux_ops, 0), +}; + +static struct clk_regmap a9_hdmitx1_pixel =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D VID_CLK_CTRL2, + .bit_idx =3D 12, + }, + .hw.init =3D CLK_HW_INIT_HW("hdmitx1_pixel", &a9_hdmitx_pixel_sel.hw, + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT), +}; + +static struct clk_regmap a9_hdmitx1_fe_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D HDMI_CLK_CTRL, + .mask =3D 0xf, + .shift =3D 28, + .table =3D a9_vid_parents_val_table, + }, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("hdmitx1_fe_sel", a9_vid_parents + , &clk_regmap_mux_ops, 0), +}; + +static struct clk_regmap a9_hdmitx1_fe =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D VID_CLK_CTRL2, + .bit_idx =3D 13, + }, + .hw.init =3D CLK_HW_INIT_HW("hdmitx1_fe", &a9_hdmitx1_fe_sel.hw, + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT), +}; + +static const struct clk_parent_data a9_csi_phy_parents[] =3D { + { .fw_name =3D "fdiv2p5", }, + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "fdiv5", }, + { .fw_name =3D "gp0", }, + { .fw_name =3D "hifi0", }, + { .fw_name =3D "fdiv2", }, + { .fw_name =3D "xtal", } +}; + +static A9_COMP_SEL(csi_phy, MIPI_CSI_PHY_CLK_CTRL, 9, 0x7, + a9_csi_phy_parents, NULL); +static A9_COMP_DIV(csi_phy, MIPI_CSI_PHY_CLK_CTRL, 0, 7); +static A9_COMP_GATE(csi_phy, MIPI_CSI_PHY_CLK_CTRL, 8, 0); + +static const struct clk_parent_data a9_dsi_meas_parents[] =3D { + { .fw_name =3D "xtal", }, + { .fw_name =3D "fdiv4", }, + { .fw_name =3D "fdiv3", }, + { .fw_name =3D "fdiv5", }, + { .hw =3D &a9_vid_pll.hw }, + { .fw_name =3D "gp0", }, + { .fw_name =3D "vid1", }, + { .fw_name =3D "vid2", } +}; + +static A9_COMP_SEL(dsi_meas, DSI_MEAS_CLK_CTRL, 9, 0x7, + a9_dsi_meas_parents, NULL); +static A9_COMP_DIV(dsi_meas, DSI_MEAS_CLK_CTRL, 0, 7); +static A9_COMP_GATE(dsi_meas, DSI_MEAS_CLK_CTRL, 8, 0); + +static A9_COMP_SEL(dsi_b_meas, DSI_MEAS_CLK_CTRL, 25, 0x7, + a9_dsi_meas_parents, NULL); +static A9_COMP_DIV(dsi_b_meas, DSI_MEAS_CLK_CTRL, 16, 7); +static A9_COMP_GATE(dsi_b_meas, DSI_MEAS_CLK_CTRL, 24, 0); + +static struct clk_hw *a9_peripherals_hw_clks[] =3D { + [CLKID_SYS_AM_AXI] =3D &a9_sys_am_axi.hw, + [CLKID_SYS_DOS] =3D &a9_sys_dos.hw, + [CLKID_SYS_MIPI_DSI] =3D &a9_sys_mipi_dsi.hw, + [CLKID_SYS_ETH_PHY] =3D &a9_sys_eth_phy.hw, + [CLKID_SYS_AMFC] =3D &a9_sys_amfc.hw, + [CLKID_SYS_MALI] =3D &a9_sys_mali.hw, + [CLKID_SYS_NNA] =3D &a9_sys_nna.hw, + [CLKID_SYS_ETH_AXI] =3D &a9_sys_eth_axi.hw, + [CLKID_SYS_DP_APB] =3D &a9_sys_dp_apb.hw, + [CLKID_SYS_EDPTX_APB] =3D &a9_sys_edptx_apb.hw, + [CLKID_SYS_U3HSG] =3D &a9_sys_u3hsg.hw, + [CLKID_SYS_AUCPU] =3D &a9_sys_aucpu.hw, + [CLKID_SYS_GLB] =3D &a9_sys_glb.hw, + [CLKID_SYS_COMBO_DPHY_APB] =3D &a9_sys_combo_dphy_apb.hw, + [CLKID_SYS_HDMIRX_APB] =3D &a9_sys_hdmirx_apb.hw, + [CLKID_SYS_HDMIRX_PCLK] =3D &a9_sys_hdmirx_pclk.hw, + [CLKID_SYS_MIPI_DSI_PHY] =3D &a9_sys_mipi_dsi_phy.hw, + [CLKID_SYS_CAN0] =3D &a9_sys_can0.hw, + [CLKID_SYS_CAN1] =3D &a9_sys_can1.hw, + [CLKID_SYS_SD_EMMC_A] =3D &a9_sys_sd_emmc_a.hw, + [CLKID_SYS_SD_EMMC_B] =3D &a9_sys_sd_emmc_b.hw, + [CLKID_SYS_SD_EMMC_C] =3D &a9_sys_sd_emmc_c.hw, + [CLKID_SYS_SC] =3D &a9_sys_sc.hw, + [CLKID_SYS_ACODEC] =3D &a9_sys_acodec.hw, + [CLKID_SYS_MIPI_ISP] =3D &a9_sys_mipi_isp.hw, + [CLKID_SYS_MSR] =3D &a9_sys_msr.hw, + [CLKID_SYS_AUDIO] =3D &a9_sys_audio.hw, + [CLKID_SYS_MIPI_DSI_B] =3D &a9_sys_mipi_dsi_b.hw, + [CLKID_SYS_MIPI_DSI1_PHY] =3D &a9_sys_mipi_dsi1_phy.hw, + [CLKID_SYS_ETH] =3D &a9_sys_eth.hw, + [CLKID_SYS_ETH_1G_MAC] =3D &a9_sys_eth_1g_mac.hw, + [CLKID_SYS_UART_A] =3D &a9_sys_uart_a.hw, + [CLKID_SYS_UART_F] =3D &a9_sys_uart_f.hw, + [CLKID_SYS_TS_A55] =3D &a9_sys_ts_a55.hw, + [CLKID_SYS_ETH_1G_AXI] =3D &a9_sys_eth_1g_axi.hw, + [CLKID_SYS_TS_DOS] =3D &a9_sys_ts_dos.hw, + [CLKID_SYS_U3DRD_B] =3D &a9_sys_u3drd_b.hw, + [CLKID_SYS_TS_CORE] =3D &a9_sys_ts_core.hw, + [CLKID_SYS_TS_PLL] =3D &a9_sys_ts_pll.hw, + [CLKID_SYS_CSI_DIG_CLKIN] =3D &a9_sys_csi_dig_clkin.hw, + [CLKID_SYS_CVE] =3D &a9_sys_cve.hw, + [CLKID_SYS_GE2D] =3D &a9_sys_ge2d.hw, + [CLKID_SYS_SPISG] =3D &a9_sys_spisg.hw, + [CLKID_SYS_U3DRD_1] =3D &a9_sys_u3drd_1.hw, + [CLKID_SYS_U2H] =3D &a9_sys_u2h.hw, + [CLKID_SYS_PCIE_MAC_A] =3D &a9_sys_pcie_mac_a.hw, + [CLKID_SYS_U3DRD_A] =3D &a9_sys_u3drd_a.hw, + [CLKID_SYS_U2DRD] =3D &a9_sys_u2drd.hw, + [CLKID_SYS_PCIE_PHY] =3D &a9_sys_pcie_phy.hw, + [CLKID_SYS_PCIE_MAC_B] =3D &a9_sys_pcie_mac_b.hw, + [CLKID_SYS_PERIPH] =3D &a9_sys_periph.hw, + [CLKID_SYS_PIO] =3D &a9_sys_pio.hw, + [CLKID_SYS_I3C] =3D &a9_sys_i3c.hw, + [CLKID_SYS_I2C_M_E] =3D &a9_sys_i2c_m_e.hw, + [CLKID_SYS_I2C_M_F] =3D &a9_sys_i2c_m_f.hw, + [CLKID_SYS_HDMITX_APB] =3D &a9_sys_hdmitx_apb.hw, + [CLKID_SYS_I2C_M_I] =3D &a9_sys_i2c_m_i.hw, + [CLKID_SYS_I2C_M_G] =3D &a9_sys_i2c_m_g.hw, + [CLKID_SYS_I2C_M_H] =3D &a9_sys_i2c_m_h.hw, + [CLKID_SYS_HDMI20_AES] =3D &a9_sys_hdmi20_aes.hw, + [CLKID_SYS_CSI2_HOST] =3D &a9_sys_csi2_host.hw, + [CLKID_SYS_CSI2_ADAPT] =3D &a9_sys_csi2_adapt.hw, + [CLKID_SYS_DSPA] =3D &a9_sys_dspa.hw, + [CLKID_SYS_PP_DMA] =3D &a9_sys_pp_dma.hw, + [CLKID_SYS_PP_WRAPPER] =3D &a9_sys_pp_wrapper.hw, + [CLKID_SYS_VPU_INTR] =3D &a9_sys_vpu_intr.hw, + [CLKID_SYS_CSI2_PHY] =3D &a9_sys_csi2_phy.hw, + [CLKID_SYS_SARADC] =3D &a9_sys_saradc.hw, + [CLKID_SYS_PWM_J] =3D &a9_sys_pwm_j.hw, + [CLKID_SYS_PWM_I] =3D &a9_sys_pwm_i.hw, + [CLKID_SYS_PWM_H] =3D &a9_sys_pwm_h.hw, + [CLKID_SYS_PWM_N] =3D &a9_sys_pwm_n.hw, + [CLKID_SYS_PWM_M] =3D &a9_sys_pwm_m.hw, + [CLKID_SYS_PWM_L] =3D &a9_sys_pwm_l.hw, + [CLKID_SYS_PWM_K] =3D &a9_sys_pwm_k.hw, + [CLKID_SD_EMMC_A_SEL] =3D &a9_sd_emmc_a_sel.hw, + [CLKID_SD_EMMC_A_DIV] =3D &a9_sd_emmc_a_div.hw, + [CLKID_SD_EMMC_A] =3D &a9_sd_emmc_a.hw, + [CLKID_SD_EMMC_B_SEL] =3D &a9_sd_emmc_b_sel.hw, + [CLKID_SD_EMMC_B_DIV] =3D &a9_sd_emmc_b_div.hw, + [CLKID_SD_EMMC_B] =3D &a9_sd_emmc_b.hw, + [CLKID_SD_EMMC_C_SEL] =3D &a9_sd_emmc_c_sel.hw, + [CLKID_SD_EMMC_C_DIV] =3D &a9_sd_emmc_c_div.hw, + [CLKID_SD_EMMC_C] =3D &a9_sd_emmc_c.hw, + [CLKID_PWM_H_SEL] =3D &a9_pwm_h_sel.hw, + [CLKID_PWM_H_DIV] =3D &a9_pwm_h_div.hw, + [CLKID_PWM_H] =3D &a9_pwm_h.hw, + [CLKID_PWM_I_SEL] =3D &a9_pwm_i_sel.hw, + [CLKID_PWM_I_DIV] =3D &a9_pwm_i_div.hw, + [CLKID_PWM_I] =3D &a9_pwm_i.hw, + [CLKID_PWM_J_SEL] =3D &a9_pwm_j_sel.hw, + [CLKID_PWM_J_DIV] =3D &a9_pwm_j_div.hw, + [CLKID_PWM_J] =3D &a9_pwm_j.hw, + [CLKID_PWM_K_SEL] =3D &a9_pwm_k_sel.hw, + [CLKID_PWM_K_DIV] =3D &a9_pwm_k_div.hw, + [CLKID_PWM_K] =3D &a9_pwm_k.hw, + [CLKID_PWM_L_SEL] =3D &a9_pwm_l_sel.hw, + [CLKID_PWM_L_DIV] =3D &a9_pwm_l_div.hw, + [CLKID_PWM_L] =3D &a9_pwm_l.hw, + [CLKID_PWM_M_SEL] =3D &a9_pwm_m_sel.hw, + [CLKID_PWM_M_DIV] =3D &a9_pwm_m_div.hw, + [CLKID_PWM_M] =3D &a9_pwm_m.hw, + [CLKID_PWM_N_SEL] =3D &a9_pwm_n_sel.hw, + [CLKID_PWM_N_DIV] =3D &a9_pwm_n_div.hw, + [CLKID_PWM_N] =3D &a9_pwm_n.hw, + [CLKID_SPISG_SEL] =3D &a9_spisg_sel.hw, + [CLKID_SPISG_DIV] =3D &a9_spisg_div.hw, + [CLKID_SPISG] =3D &a9_spisg.hw, + [CLKID_SPISG1_SEL] =3D &a9_spisg1_sel.hw, + [CLKID_SPISG1_DIV] =3D &a9_spisg1_div.hw, + [CLKID_SPISG1] =3D &a9_spisg1.hw, + [CLKID_SPISG2_SEL] =3D &a9_spisg2_sel.hw, + [CLKID_SPISG2_DIV] =3D &a9_spisg2_div.hw, + [CLKID_SPISG2] =3D &a9_spisg2.hw, + [CLKID_SARADC_SEL] =3D &a9_saradc_sel.hw, + [CLKID_SARADC_DIV] =3D &a9_saradc_div.hw, + [CLKID_SARADC] =3D &a9_saradc.hw, + [CLKID_AMFC_SEL] =3D &a9_amfc_sel.hw, + [CLKID_AMFC_DIV] =3D &a9_amfc_div.hw, + [CLKID_AMFC] =3D &a9_amfc.hw, + [CLKID_NNA_SEL] =3D &a9_nna_sel.hw, + [CLKID_NNA_DIV] =3D &a9_nna_div.hw, + [CLKID_NNA] =3D &a9_nna.hw, + [CLKID_USB_250M_SEL] =3D &a9_usb_250m_sel.hw, + [CLKID_USB_250M_DIV] =3D &a9_usb_250m_div.hw, + [CLKID_USB_250M] =3D &a9_usb_250m.hw, + [CLKID_USB_48M_PRE_SEL] =3D &a9_usb_48m_pre_sel.hw, + [CLKID_USB_48M_PRE_DIV] =3D &a9_usb_48m_pre_div.hw, + [CLKID_USB_48M_PRE] =3D &a9_usb_48m_pre.hw, + [CLKID_PCIE_TL_SEL] =3D &a9_pcie_tl_sel.hw, + [CLKID_PCIE_TL_DIV] =3D &a9_pcie_tl_div.hw, + [CLKID_PCIE_TL] =3D &a9_pcie_tl.hw, + [CLKID_PCIE1_TL_SEL] =3D &a9_pcie1_tl_sel.hw, + [CLKID_PCIE1_TL_DIV] =3D &a9_pcie1_tl_div.hw, + [CLKID_PCIE1_TL] =3D &a9_pcie1_tl.hw, + [CLKID_CMPR_SEL] =3D &a9_cmpr_sel.hw, + [CLKID_CMPR_DIV] =3D &a9_cmpr_div.hw, + [CLKID_CMPR] =3D &a9_cmpr.hw, + [CLKID_DEWARPA_SEL] =3D &a9_dewarpa_sel.hw, + [CLKID_DEWARPA_DIV] =3D &a9_dewarpa_div.hw, + [CLKID_DEWARPA] =3D &a9_dewarpa.hw, + [CLKID_SC_PRE_SEL] =3D &a9_sc_pre_sel.hw, + [CLKID_SC_PRE_DIV] =3D &a9_sc_pre_div.hw, + [CLKID_SC_PRE] =3D &a9_sc_pre.hw, + [CLKID_SC] =3D &a9_sc.hw, + [CLKID_DPTX_APB2_SEL] =3D &a9_dptx_apb2_sel.hw, + [CLKID_DPTX_APB2_DIV] =3D &a9_dptx_apb2_div.hw, + [CLKID_DPTX_APB2] =3D &a9_dptx_apb2.hw, + [CLKID_DPTX_AUD_SEL] =3D &a9_dptx_aud_sel.hw, + [CLKID_DPTX_AUD_DIV] =3D &a9_dptx_aud_div.hw, + [CLKID_DPTX_AUD] =3D &a9_dptx_aud.hw, + [CLKID_ISP_SEL] =3D &a9_isp_sel.hw, + [CLKID_ISP_DIV] =3D &a9_isp_div.hw, + [CLKID_ISP] =3D &a9_isp.hw, + [CLKID_CVE_SEL] =3D &a9_cve_sel.hw, + [CLKID_CVE_DIV] =3D &a9_cve_div.hw, + [CLKID_CVE] =3D &a9_cve.hw, + [CLKID_VGE_SEL] =3D &a9_vge_sel.hw, + [CLKID_VGE_DIV] =3D &a9_vge_div.hw, + [CLKID_VGE] =3D &a9_vge.hw, + [CLKID_PP_SEL] =3D &a9_pp_sel.hw, + [CLKID_PP_DIV] =3D &a9_pp_div.hw, + [CLKID_PP] =3D &a9_pp.hw, + [CLKID_GLB_SEL] =3D &a9_glb_sel.hw, + [CLKID_GLB_DIV] =3D &a9_glb_div.hw, + [CLKID_GLB] =3D &a9_glb.hw, + [CLKID_USB_48M_DUALDIV_IN] =3D &a9_usb_48m_dualdiv_in.hw, + [CLKID_USB_48M_DUALDIV_DIV] =3D &a9_usb_48m_dualdiv_div.hw, + [CLKID_USB_48M_DUALDIV_SEL] =3D &a9_usb_48m_dualdiv_sel.hw, + [CLKID_USB_48M_DUALDIV] =3D &a9_usb_48m_dualdiv.hw, + [CLKID_USB_48M] =3D &a9_usb_48m.hw, + [CLKID_CAN_PE_SEL] =3D &a9_can_pe_sel.hw, + [CLKID_CAN_PE_DIV] =3D &a9_can_pe_div.hw, + [CLKID_CAN_PE] =3D &a9_can_pe.hw, + [CLKID_CAN1_PE_SEL] =3D &a9_can1_pe_sel.hw, + [CLKID_CAN1_PE_DIV] =3D &a9_can1_pe_div.hw, + [CLKID_CAN1_PE] =3D &a9_can1_pe.hw, + [CLKID_CAN_FILTER_SEL] =3D &a9_can_filter_sel.hw, + [CLKID_CAN_FILTER_DIV] =3D &a9_can_filter_div.hw, + [CLKID_CAN_FILTER] =3D &a9_can_filter.hw, + [CLKID_CAN1_FILTER_SEL] =3D &a9_can1_filter_sel.hw, + [CLKID_CAN1_FILTER_DIV] =3D &a9_can1_filter_div.hw, + [CLKID_CAN1_FILTER] =3D &a9_can1_filter.hw, + [CLKID_I3C_SEL] =3D &a9_i3c_sel.hw, + [CLKID_I3C_DIV] =3D &a9_i3c_div.hw, + [CLKID_I3C] =3D &a9_i3c.hw, + [CLKID_TS_DIV] =3D &a9_ts_div.hw, + [CLKID_TS] =3D &a9_ts.hw, + [CLKID_ETH_125M_DIV] =3D &a9_eth_125m_div.hw, + [CLKID_ETH_125M] =3D &a9_eth_125m.hw, + [CLKID_ETH_RMII_SEL] =3D &a9_eth_rmii_sel.hw, + [CLKID_ETH_RMII_DIV] =3D &a9_eth_rmii_div.hw, + [CLKID_ETH_RMII] =3D &a9_eth_rmii.hw, + [CLKID_GEN_SEL] =3D &a9_gen_sel.hw, + [CLKID_GEN_DIV] =3D &a9_gen_div.hw, + [CLKID_GEN] =3D &a9_gen.hw, + [CLKID_CLK24M_IN] =3D &a9_24m_in.hw, + [CLKID_CLK12_24M] =3D &a9_12_24m.hw, + [CLKID_MALI_0_SEL] =3D &a9_mali_0_sel.hw, + [CLKID_MALI_0_DIV] =3D &a9_mali_0_div.hw, + [CLKID_MALI_0] =3D &a9_mali_0.hw, + [CLKID_MALI_1_SEL] =3D &a9_mali_1_sel.hw, + [CLKID_MALI_1_DIV] =3D &a9_mali_1_div.hw, + [CLKID_MALI_1] =3D &a9_mali_1.hw, + [CLKID_MALI] =3D &a9_mali.hw, + [CLKID_MALI_STACK_0_SEL] =3D &a9_mali_stack_0_sel.hw, + [CLKID_MALI_STACK_0_DIV] =3D &a9_mali_stack_0_div.hw, + [CLKID_MALI_STACK_0] =3D &a9_mali_stack_0.hw, + [CLKID_MALI_STACK_1_SEL] =3D &a9_mali_stack_1_sel.hw, + [CLKID_MALI_STACK_1_DIV] =3D &a9_mali_stack_1_div.hw, + [CLKID_MALI_STACK_1] =3D &a9_mali_stack_1.hw, + [CLKID_MALI_STACK] =3D &a9_mali_stack.hw, + [CLKID_DSPA_0_SEL] =3D &a9_dspa_0_sel.hw, + [CLKID_DSPA_0_DIV] =3D &a9_dspa_0_div.hw, + [CLKID_DSPA_0] =3D &a9_dspa_0.hw, + [CLKID_DSPA_1_SEL] =3D &a9_dspa_1_sel.hw, + [CLKID_DSPA_1_DIV] =3D &a9_dspa_1_div.hw, + [CLKID_DSPA_1] =3D &a9_dspa_1.hw, + [CLKID_DSPA] =3D &a9_dspa.hw, + [CLKID_HEVCF_0_SEL] =3D &a9_hevcf_0_sel.hw, + [CLKID_HEVCF_0_DIV] =3D &a9_hevcf_0_div.hw, + [CLKID_HEVCF_0] =3D &a9_hevcf_0.hw, + [CLKID_HEVCF_1_SEL] =3D &a9_hevcf_1_sel.hw, + [CLKID_HEVCF_1_DIV] =3D &a9_hevcf_1_div.hw, + [CLKID_HEVCF_1] =3D &a9_hevcf_1.hw, + [CLKID_HEVCF] =3D &a9_hevcf.hw, + [CLKID_HCODEC_0_SEL] =3D &a9_hcodec_0_sel.hw, + [CLKID_HCODEC_0_DIV] =3D &a9_hcodec_0_div.hw, + [CLKID_HCODEC_0] =3D &a9_hcodec_0.hw, + [CLKID_HCODEC_1_SEL] =3D &a9_hcodec_1_sel.hw, + [CLKID_HCODEC_1_DIV] =3D &a9_hcodec_1_div.hw, + [CLKID_HCODEC_1] =3D &a9_hcodec_1.hw, + [CLKID_HCODEC] =3D &a9_hcodec.hw, + [CLKID_VPU_0_SEL] =3D &a9_vpu_0_sel.hw, + [CLKID_VPU_0_DIV] =3D &a9_vpu_0_div.hw, + [CLKID_VPU_0] =3D &a9_vpu_0.hw, + [CLKID_VPU_1_SEL] =3D &a9_vpu_1_sel.hw, + [CLKID_VPU_1_DIV] =3D &a9_vpu_1_div.hw, + [CLKID_VPU_1] =3D &a9_vpu_1.hw, + [CLKID_VPU] =3D &a9_vpu.hw, + [CLKID_VAPB_0_SEL] =3D &a9_vapb_0_sel.hw, + [CLKID_VAPB_0_DIV] =3D &a9_vapb_0_div.hw, + [CLKID_VAPB_0] =3D &a9_vapb_0.hw, + [CLKID_VAPB_1_SEL] =3D &a9_vapb_1_sel.hw, + [CLKID_VAPB_1_DIV] =3D &a9_vapb_1_div.hw, + [CLKID_VAPB_1] =3D &a9_vapb_1.hw, + [CLKID_VAPB] =3D &a9_vapb.hw, + [CLKID_GE2D] =3D &a9_ge2d.hw, + [CLKID_VPU_CLKB_TMP_SEL] =3D &a9_vpu_clkb_tmp_sel.hw, + [CLKID_VPU_CLKB_TMP_DIV] =3D &a9_vpu_clkb_tmp_div.hw, + [CLKID_VPU_CLKB_TMP] =3D &a9_vpu_clkb_tmp.hw, + [CLKID_VPU_CLKB_DIV] =3D &a9_vpu_clkb_div.hw, + [CLKID_VPU_CLKB] =3D &a9_vpu_clkb.hw, + [CLKID_HDMITX_SYS_SEL] =3D &a9_hdmitx_sys_sel.hw, + [CLKID_HDMITX_SYS_DIV] =3D &a9_hdmitx_sys_div.hw, + [CLKID_HDMITX_SYS] =3D &a9_hdmitx_sys.hw, + [CLKID_HDMITX_PRIF_SEL] =3D &a9_hdmitx_prif_sel.hw, + [CLKID_HDMITX_PRIF_DIV] =3D &a9_hdmitx_prif_div.hw, + [CLKID_HDMITX_PRIF] =3D &a9_hdmitx_prif.hw, + [CLKID_HDMITX_200M_SEL] =3D &a9_hdmitx_200m_sel.hw, + [CLKID_HDMITX_200M_DIV] =3D &a9_hdmitx_200m_div.hw, + [CLKID_HDMITX_200M] =3D &a9_hdmitx_200m.hw, + [CLKID_HDMITX_AUD_SEL] =3D &a9_hdmitx_aud_sel.hw, + [CLKID_HDMITX_AUD_DIV] =3D &a9_hdmitx_aud_div.hw, + [CLKID_HDMITX_AUD] =3D &a9_hdmitx_aud.hw, + [CLKID_HDMIRX_5M_SEL] =3D &a9_hdmirx_5m_sel.hw, + [CLKID_HDMIRX_5M_DIV] =3D &a9_hdmirx_5m_div.hw, + [CLKID_HDMIRX_5M] =3D &a9_hdmirx_5m.hw, + [CLKID_HDMIRX_2M_SEL] =3D &a9_hdmirx_2m_sel.hw, + [CLKID_HDMIRX_2M_DIV] =3D &a9_hdmirx_2m_div.hw, + [CLKID_HDMIRX_2M] =3D &a9_hdmirx_2m.hw, + [CLKID_HDMIRX_CFG_SEL] =3D &a9_hdmirx_cfg_sel.hw, + [CLKID_HDMIRX_CFG_DIV] =3D &a9_hdmirx_cfg_div.hw, + [CLKID_HDMIRX_CFG] =3D &a9_hdmirx_cfg.hw, + [CLKID_HDMIRX_HDCP2X_SEL] =3D &a9_hdmirx_hdcp2x_sel.hw, + [CLKID_HDMIRX_HDCP2X_DIV] =3D &a9_hdmirx_hdcp2x_div.hw, + [CLKID_HDMIRX_HDCP2X] =3D &a9_hdmirx_hdcp2x.hw, + [CLKID_HDMIRX_ACR_REF_SEL] =3D &a9_hdmirx_acr_ref_sel.hw, + [CLKID_HDMIRX_ACR_REF_DIV] =3D &a9_hdmirx_acr_ref_div.hw, + [CLKID_HDMIRX_ACR_REF] =3D &a9_hdmirx_acr_ref.hw, + [CLKID_HDMIRX_METER_SEL] =3D &a9_hdmirx_meter_sel.hw, + [CLKID_HDMIRX_METER_DIV] =3D &a9_hdmirx_meter_div.hw, + [CLKID_HDMIRX_METER] =3D &a9_hdmirx_meter.hw, + [CLKID_VID_LOCK_SEL] =3D &a9_vid_lock_sel.hw, + [CLKID_VID_LOCK_DIV] =3D &a9_vid_lock_div.hw, + [CLKID_VID_LOCK] =3D &a9_vid_lock.hw, + [CLKID_VDIN_MEAS_SEL] =3D &a9_vdin_meas_sel.hw, + [CLKID_VDIN_MEAS_DIV] =3D &a9_vdin_meas_div.hw, + [CLKID_VDIN_MEAS] =3D &a9_vdin_meas.hw, + [CLKID_VID_PLL_DIV] =3D &a9_vid_pll_div.hw, + [CLKID_VID_PLL_SEL] =3D &a9_vid_pll_sel.hw, + [CLKID_VID_PLL] =3D &a9_vid_pll.hw, + [CLKID_VID_PLL_VCLK] =3D &a9_vid_pll_vclk.hw, + [CLKID_VCLK_SEL] =3D &a9_vclk_sel.hw, + [CLKID_VCLK_IN] =3D &a9_vclk_in.hw, + [CLKID_VCLK_DIV] =3D &a9_vclk_div.hw, + [CLKID_VCLK] =3D &a9_vclk.hw, + [CLKID_VCLK_DIV1_EN] =3D &a9_vclk_div1_en.hw, + [CLKID_VCLK_DIV2_EN] =3D &a9_vclk_div2_en.hw, + [CLKID_VCLK_DIV2] =3D &a9_vclk_div2.hw, + [CLKID_VCLK_DIV4_EN] =3D &a9_vclk_div4_en.hw, + [CLKID_VCLK_DIV4] =3D &a9_vclk_div4.hw, + [CLKID_VCLK_DIV6_EN] =3D &a9_vclk_div6_en.hw, + [CLKID_VCLK_DIV6] =3D &a9_vclk_div6.hw, + [CLKID_VCLK_DIV12_EN] =3D &a9_vclk_div12_en.hw, + [CLKID_VCLK_DIV12] =3D &a9_vclk_div12.hw, + [CLKID_VCLK2_SEL] =3D &a9_vclk2_sel.hw, + [CLKID_VCLK2_IN] =3D &a9_vclk2_in.hw, + [CLKID_VCLK2_DIV] =3D &a9_vclk2_div.hw, + [CLKID_VCLK2] =3D &a9_vclk2.hw, + [CLKID_VCLK2_DIV1_EN] =3D &a9_vclk2_div1_en.hw, + [CLKID_VCLK2_DIV2_EN] =3D &a9_vclk2_div2_en.hw, + [CLKID_VCLK2_DIV2] =3D &a9_vclk2_div2.hw, + [CLKID_VCLK2_DIV4_EN] =3D &a9_vclk2_div4_en.hw, + [CLKID_VCLK2_DIV4] =3D &a9_vclk2_div4.hw, + [CLKID_VCLK2_DIV6_EN] =3D &a9_vclk2_div6_en.hw, + [CLKID_VCLK2_DIV6] =3D &a9_vclk2_div6.hw, + [CLKID_VCLK2_DIV12_EN] =3D &a9_vclk2_div12_en.hw, + [CLKID_VCLK2_DIV12] =3D &a9_vclk2_div12.hw, + [CLKID_VDAC_SEL] =3D &a9_vdac_sel.hw, + [CLKID_VDAC] =3D &a9_vdac.hw, + [CLKID_ENC_SEL] =3D &a9_enc_sel.hw, + [CLKID_ENC] =3D &a9_enc.hw, + [CLKID_ENC1_SEL] =3D &a9_enc1_sel.hw, + [CLKID_ENC1] =3D &a9_enc1.hw, + [CLKID_HDMITX_PIXEL_SEL] =3D &a9_hdmitx_pixel_sel.hw, + [CLKID_HDMITX_PIXEL] =3D &a9_hdmitx_pixel.hw, + [CLKID_HDMITX_FE_SEL] =3D &a9_hdmitx_fe_sel.hw, + [CLKID_HDMITX_FE] =3D &a9_hdmitx_fe.hw, + [CLKID_HDMITX1_PIXEL_SEL] =3D &a9_hdmitx1_pixel_sel.hw, + [CLKID_HDMITX1_PIXEL] =3D &a9_hdmitx1_pixel.hw, + [CLKID_HDMITX1_FE_SEL] =3D &a9_hdmitx1_fe_sel.hw, + [CLKID_HDMITX1_FE] =3D &a9_hdmitx1_fe.hw, + [CLKID_CSI_PHY_SEL] =3D &a9_csi_phy_sel.hw, + [CLKID_CSI_PHY_DIV] =3D &a9_csi_phy_div.hw, + [CLKID_CSI_PHY] =3D &a9_csi_phy.hw, + [CLKID_DSI_MEAS_SEL] =3D &a9_dsi_meas_sel.hw, + [CLKID_DSI_MEAS_DIV] =3D &a9_dsi_meas_div.hw, + [CLKID_DSI_MEAS] =3D &a9_dsi_meas.hw, + [CLKID_DSI_B_MEAS_SEL] =3D &a9_dsi_b_meas_sel.hw, + [CLKID_DSI_B_MEAS_DIV] =3D &a9_dsi_b_meas_div.hw, + [CLKID_DSI_B_MEAS] =3D &a9_dsi_b_meas.hw, +}; + +static const struct meson_clkc_data a9_peripherals_clkc_data =3D { + .hw_clks =3D { + .hws =3D a9_peripherals_hw_clks, + .num =3D ARRAY_SIZE(a9_peripherals_hw_clks), + }, +}; + +static const struct of_device_id a9_peripherals_clkc_match_table[] =3D { + { + .compatible =3D "amlogic,a9-peripherals-clkc", + .data =3D &a9_peripherals_clkc_data, + }, + { /* sentinel */ } +}; + +MODULE_DEVICE_TABLE(of, a9_peripherals_clkc_match_table); + +static struct platform_driver a9_peripherals_clkc_driver =3D { + .probe =3D meson_clkc_mmio_probe, + .driver =3D { + .name =3D "a9-peripherals-clkc", + .of_match_table =3D a9_peripherals_clkc_match_table, + }, +}; +module_platform_driver(a9_peripherals_clkc_driver); + +MODULE_DESCRIPTION("Amlogic A9 Peripherals Clock Controller driver"); +MODULE_AUTHOR("Jian Hu "); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("CLK_MESON"); --=20 2.47.1