From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Hi all, This patch series adds PCIe support to the Renesas RZ/V2H SoC and enables PCIe on the RZ/V2H EVK. The first patch adds the necessary device tree nodes for the PCIe controller, while the second patch enables the PCIe slot on the EVK. Note, the driver and binding patches have been posted separately [0]. [0] https://lore.kernel.org/all/20260602195019.1798126-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ Cheers, Prabhakar Lad Prabhakar (2): arm64: dts: renesas: r9a09g057: Add PCIe nodes arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable PCIe arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 140 ++++++++++++++++++ .../dts/renesas/r9a09g057h44-rzv2h-evk.dts | 18 +++ 2 files changed, 158 insertions(+) -- 2.54.0 From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Add PCIe nodes to Renesas RZ/V2H(P) ("R9A09G057") SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 140 +++++++++++++++++++++ 1 file changed, 140 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index XXXXXXX..XXXXXXX 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -XXX,XX +XXX,XX @@ rsci9: serial@12803000 { status = "disabled"; }; + pcie0: pcie@13400000 { + compatible = "renesas,r9a09g057-pcie"; + reg = <0 0x13400000 0 0x10000>; + ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x8000000>, + <0x43000000 4 0x40000000 4 0x40000000 6 0x00000000>; + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 4 0x00000000>; + bus-range = <0x0 0xff>; + interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "serr", "serr_cor", "serr_nonfatal", + "serr_fatal", "axi_err", "inta", + "intb", "intc", "intd", "msi", + "link_bandwidth", "pm_pme", "dma", + "pcie_evt", "msg", "all", + "link_equalization_request", + "turn_off_event", "pmu_poweroff", + "d3_event_f0", "d3_event_f1", + "cfg_pmcsr_writeclear_f0", + "cfg_pmcsr_writeclear_f1"; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0 0 0 0 0>, /* INTA */ + <0 0 0 2 &pcie0 0 0 0 1>, /* INTB */ + <0 0 0 3 &pcie0 0 0 0 2>, /* INTC */ + <0 0 0 4 &pcie0 0 0 0 3>; /* INTD */ + clocks = <&cpg CPG_MOD 0xc4>, <&cpg CPG_MOD 0xc5>; + clock-names = "aclk", "pmu"; + resets = <&cpg 0xb2>; + reset-names = "aresetn"; + power-domains = <&cpg>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + num-lanes = <2>; + renesas,sysc = <&sys 0>; + status = "disabled"; + + pcie_port0: pcie@0,0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + ranges; + device_type = "pci"; + vendor-id = <0x1912>; + device-id = <0x003b>; + #address-cells = <3>; + #size-cells = <2>; + }; + }; + + pcie1: pcie@13410000 { + compatible = "renesas,r9a09g057-pcie"; + reg = <0 0x13410000 0 0x10000>; + ranges = <0x02000000 0 0x38000000 0 0x38000000 0 0x8000000>, + <0x43000000 0xa 0x40000000 0xa 0x40000000 5 0xc0000000>; + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 4 0x00000000>; + bus-range = <0x0 0xff>; + interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 826 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 829 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 815 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 827 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 828 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 830 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "serr", "serr_cor", "serr_nonfatal", + "serr_fatal", "axi_err", "inta", + "intb", "intc", "intd", "msi", + "link_bandwidth", "pm_pme", "dma", + "pcie_evt", "msg", "all", + "link_equalization_request", + "turn_off_event", "pmu_poweroff", + "d3_event_f0", "d3_event_f1", + "cfg_pmcsr_writeclear_f0", + "cfg_pmcsr_writeclear_f1"; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1 0 0 0 0>, /* INTA */ + <0 0 0 2 &pcie1 0 0 0 1>, /* INTB */ + <0 0 0 3 &pcie1 0 0 0 2>, /* INTC */ + <0 0 0 4 &pcie1 0 0 0 3>; /* INTD */ + clocks = <&cpg CPG_MOD 0xc4>, <&cpg CPG_MOD 0xc5>; + clock-names = "aclk", "pmu"; + resets = <&cpg 0xb2>; + reset-names = "aresetn"; + power-domains = <&cpg>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + num-lanes = <2>; + renesas,sysc = <&sys 1>; + status = "disabled"; + + pcie_port1: pcie@0,0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + ranges; + device_type = "pci"; + vendor-id = <0x1912>; + device-id = <0x003b>; + #address-cells = <3>; + #size-cells = <2>; + }; + }; + i2c0: i2c@14400400 { compatible = "renesas,riic-r9a09g057"; reg = <0 0x14400400 0 0x400>; -- 2.54.0 From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Enable the PCIE1 slot which is connected to PCIe0 channel. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- .../dts/renesas/r9a09g057h44-rzv2h-evk.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts index XXXXXXX..XXXXXXX 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts @@ -XXX,XX +XXX,XX @@ &ostm7 { status = "okay"; }; +&pcie0 { + pinctrl-0 = <&pcie0_pins>; + pinctrl-names = "default"; + num-lanes = <4>; + status = "okay"; +}; + +&pcie_port0 { + clocks = <&versa3 5>; + clock-names = "ref"; +}; + &pinctrl { eth0_pins: eth0 { pins = "ET0_TXC_TXCLK"; @@ -XXX,XX +XXX,XX @@ i2c8_pins: i2c8 { <RZV2H_PORT_PINMUX(0, 7, 1)>; /* I2C8_SCL */ }; + pcie0_pins: pcie { + pins = "PCIE0_RSTOUTB"; + slew-rate = <0>; + renesas,output-impedance = <2>; + }; + scif_pins: scif { pins = "SCIF_TXD", "SCIF_RXD"; renesas,output-impedance = <1>; -- 2.54.0 From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Hi all, This patch series adds PCIe support to the Renesas RZ/V2H SoC and enables PCIe on the RZ/V2H EVK. The first patch adds the necessary device tree nodes for the PCIe controller, while the second patch enables the PCIe slot on the RZ/V2H EVK. v1->v2: - Formatted the ranges property so that the new line entries are aligned. - Corrected the flag values for dma-ranges property for pcie0/1 nodes. - Renamed the node name from pcie to pcie0. v1: https://lore.kernel.org/all/20260602204707.1920839-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ Note, the driver and binding patches have landed in linux-next. Cheers, Prabhakar Lad Prabhakar (2): arm64: dts: renesas: r9a09g057: Add PCIe nodes arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable PCIe arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 140 ++++++++++++++++++ .../dts/renesas/r9a09g057h44-rzv2h-evk.dts | 18 +++ 2 files changed, 158 insertions(+) -- 2.54.0 From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Add PCIe nodes to Renesas RZ/V2H(P) ("R9A09G057") SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- v1->v2: - Formatted the ranges property so that the new line entries are aligned. - Corrected the flag values for dma-ranges property for pcie0/1 nodes. --- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 140 +++++++++++++++++++++ 1 file changed, 140 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index XXXXXXX..XXXXXXX 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -XXX,XX +XXX,XX @@ rsci9: serial@12803000 { status = "disabled"; }; + pcie0: pcie@13400000 { + compatible = "renesas,r9a09g057-pcie"; + reg = <0 0x13400000 0 0x10000>; + ranges = <0x02000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>, + <0x43000000 0x4 0x40000000 0x4 0x40000000 0x6 0x00000000>; + dma-ranges = <0x43000000 0x0 0x40000000 0x0 0x40000000 0x4 0x00000000>; + bus-range = <0x0 0xff>; + interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "serr", "serr_cor", "serr_nonfatal", + "serr_fatal", "axi_err", "inta", + "intb", "intc", "intd", "msi", + "link_bandwidth", "pm_pme", "dma", + "pcie_evt", "msg", "all", + "link_equalization_request", + "turn_off_event", "pmu_poweroff", + "d3_event_f0", "d3_event_f1", + "cfg_pmcsr_writeclear_f0", + "cfg_pmcsr_writeclear_f1"; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0 0 0 0 0>, /* INTA */ + <0 0 0 2 &pcie0 0 0 0 1>, /* INTB */ + <0 0 0 3 &pcie0 0 0 0 2>, /* INTC */ + <0 0 0 4 &pcie0 0 0 0 3>; /* INTD */ + clocks = <&cpg CPG_MOD 0xc4>, <&cpg CPG_MOD 0xc5>; + clock-names = "aclk", "pmu"; + resets = <&cpg 0xb2>; + reset-names = "aresetn"; + power-domains = <&cpg>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + num-lanes = <2>; + renesas,sysc = <&sys 0>; + status = "disabled"; + + pcie_port0: pcie@0,0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + ranges; + device_type = "pci"; + vendor-id = <0x1912>; + device-id = <0x003b>; + #address-cells = <3>; + #size-cells = <2>; + }; + }; + + pcie1: pcie@13410000 { + compatible = "renesas,r9a09g057-pcie"; + reg = <0 0x13410000 0 0x10000>; + ranges = <0x02000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>, + <0x43000000 0xa 0x40000000 0xa 0x40000000 0x5 0xc0000000>; + dma-ranges = <0x43000000 0x0 0x40000000 0x0 0x40000000 0x4 0x00000000>; + bus-range = <0x0 0xff>; + interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 826 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 829 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 815 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 827 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 828 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 830 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "serr", "serr_cor", "serr_nonfatal", + "serr_fatal", "axi_err", "inta", + "intb", "intc", "intd", "msi", + "link_bandwidth", "pm_pme", "dma", + "pcie_evt", "msg", "all", + "link_equalization_request", + "turn_off_event", "pmu_poweroff", + "d3_event_f0", "d3_event_f1", + "cfg_pmcsr_writeclear_f0", + "cfg_pmcsr_writeclear_f1"; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1 0 0 0 0>, /* INTA */ + <0 0 0 2 &pcie1 0 0 0 1>, /* INTB */ + <0 0 0 3 &pcie1 0 0 0 2>, /* INTC */ + <0 0 0 4 &pcie1 0 0 0 3>; /* INTD */ + clocks = <&cpg CPG_MOD 0xc4>, <&cpg CPG_MOD 0xc5>; + clock-names = "aclk", "pmu"; + resets = <&cpg 0xb2>; + reset-names = "aresetn"; + power-domains = <&cpg>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + num-lanes = <2>; + renesas,sysc = <&sys 1>; + status = "disabled"; + + pcie_port1: pcie@0,0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + ranges; + device_type = "pci"; + vendor-id = <0x1912>; + device-id = <0x003b>; + #address-cells = <3>; + #size-cells = <2>; + }; + }; + i2c0: i2c@14400400 { compatible = "renesas,riic-r9a09g057"; reg = <0 0x14400400 0 0x400>; -- 2.54.0 From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Enable the PCIE1 slot which is connected to PCIe0 channel. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- v1->v2: - Renamed the node name from pcie to pcie0. --- .../dts/renesas/r9a09g057h44-rzv2h-evk.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts index XXXXXXX..XXXXXXX 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts @@ -XXX,XX +XXX,XX @@ &ostm7 { status = "okay"; }; +&pcie0 { + pinctrl-0 = <&pcie0_pins>; + pinctrl-names = "default"; + num-lanes = <4>; + status = "okay"; +}; + +&pcie_port0 { + clocks = <&versa3 5>; + clock-names = "ref"; +}; + &pinctrl { eth0_pins: eth0 { pins = "ET0_TXC_TXCLK"; @@ -XXX,XX +XXX,XX @@ i2c8_pins: i2c8 { <RZV2H_PORT_PINMUX(0, 7, 1)>; /* I2C8_SCL */ }; + pcie0_pins: pcie0 { + pins = "PCIE0_RSTOUTB"; + slew-rate = <0>; + renesas,output-impedance = <2>; + }; + scif_pins: scif { pins = "SCIF_TXD", "SCIF_RXD"; renesas,output-impedance = <1>; -- 2.54.0