From nobody Mon Jun 8 04:19:39 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D179E360EC7; Tue, 2 Jun 2026 14:57:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780412278; cv=none; b=Ay0cMY0/Iu0QU2dijm41nx4WBzAJDerYWIJMZrJ9QcigLlGsoLkcs/Pereq4hx82pzrQv57y1fYs4x2pQGj2Mf1ks6ihpQ7MKc2QWFycUDuUzM/dJKLLYcQG/ynNdsTc/9qKT3Uy0FAkMGeO15GPNxz3UcHcMT2/BB0YGo8STx8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780412278; c=relaxed/simple; bh=vvAHYn1CzxqUSRrcLxh052MjySYP25gUrVIa6i4MTH8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=VvSkMLxeZmthaj0iK7PuVRngHFYueht6zbtArqOOXUhS63mAF/FXTaYnWUrVZj6cprK1QgwfoaulWbFRjofkYgrFjD9H0C+BuiuLDUU/tUKQ/XD/QDUcez5DAxgisi1YLp4EK43xc0Ch921E7xyCVg2a5xP2DnWCHpaF/WT9trw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=FHydV7Pu; arc=none smtp.client-ip=198.175.65.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="FHydV7Pu" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1780412277; x=1811948277; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vvAHYn1CzxqUSRrcLxh052MjySYP25gUrVIa6i4MTH8=; b=FHydV7Pu/lZzAsDpT09fdksIDPbtmpIcBe+bTojKjr7HzsqY/RRWh/Hb TQaYJx0WhNS6JhijycULf2rdv22uxZT4jRUp0T0jh/QVOcgKZAznmwSoi zcMDqWl3XuLhs0cAQoFLWtNM45wfGBmhY9rwkSNdfZxGVuh/RTPBJ33PC ZToC+Gmm/BijWgJ6WvcQINE8oYT1gbzVO7UZtjPRGbnls+yEHGH3rMk/w qHx9oE4qqKmBk1dVDIXQMMjA+0qSSO0t++u+w4AmICGB9dct9Eac4e1+o xInTHOyHMaCqt2GLiqoa79nfQaxLjxw3+k+KlrrJ3dWlZp3BxxlAn+PUc g==; X-CSE-ConnectionGUID: qWoFzrSQRTmdmcvIBSK43w== X-CSE-MsgGUID: wVNiCM7/SNOqqDPuYh0BFw== X-IronPort-AV: E=McAfee;i="6800,10657,11805"; a="103859980" X-IronPort-AV: E=Sophos;i="6.24,183,1774335600"; d="scan'208";a="103859980" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jun 2026 07:57:54 -0700 X-CSE-ConnectionGUID: Jy/m9/DIQFOh2OsjJ1frww== X-CSE-MsgGUID: cEDaIlJaRYSG6gF2L7Ghkw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,183,1774335600"; d="scan'208";a="243095619" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.29]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jun 2026 07:57:54 -0700 From: Zide Chen To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen Subject: [PATCH V3 1/7] perf/x86/intel/uncore: Fix discovery unit lookup for multi-die systems Date: Tue, 2 Jun 2026 07:49:02 -0700 Message-ID: <20260602144908.263680-2-zide.chen@intel.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260602144908.263680-1-zide.chen@intel.com> References: <20260602144908.263680-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In uncore_find_add_unit(), PMON units with the same unit ID may be added to the uncore discovery RB-tree for different dies. These units are distinguished by node->die. However, intel_generic_uncore_box_ctl() uses a fixed die ID of -1 when looking up the discovery unit, which may retrieve the wrong node on multi-die systems. Use box->dieid instead so the correct discovery unit is selected. No functional issue has been observed so far because currently supported platforms happen to use the same unit control register for such units. Remove WARN_ON_ONCE() because with the above change a NULL unit can be expected, e.g. when a CPU die is offline during uncore enumeration and the unit is not added to the RB-tree. In this case, intel_uncore_find_discovery_unit() returns NULL once the die becomes online, and it is expected that the PMU box is not functional for that die. Fixes: b1d9ea2e1ca4 ("perf/x86/uncore: Apply the unit control RB tree to MS= R uncore units") Reviewed-by: Dapeng Mi Signed-off-by: Zide Chen --- v2: - Remove WARN_ON_ONCE(). --- arch/x86/events/intel/uncore_discovery.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/intel/uncore_discovery.c b/arch/x86/events/int= el/uncore_discovery.c index 583cbd06b9b8..60e1200c4691 100644 --- a/arch/x86/events/intel/uncore_discovery.c +++ b/arch/x86/events/intel/uncore_discovery.c @@ -481,8 +481,8 @@ static u64 intel_generic_uncore_box_ctl(struct intel_un= core_box *box) struct intel_uncore_discovery_unit *unit; =20 unit =3D intel_uncore_find_discovery_unit(box->pmu->type->boxes, - -1, box->pmu->pmu_idx); - if (WARN_ON_ONCE(!unit)) + box->dieid, box->pmu->pmu_idx); + if (!unit) return 0; =20 return unit->addr; --=20 2.54.0 From nobody Mon Jun 8 04:19:39 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C96A364E9A; Tue, 2 Jun 2026 14:57:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780412279; cv=none; b=piE0c0jpA6ie6EOmUUyx4pmiM4yvOlYWE5kg4J/hbOdz7kusqPkldfD2h88vq/I4pkCdscVKuMkQD0Lhgueaqy3Z5tKnksnwMxisk32OlQJEDeZKZMvOrT9NbzBlV0pGOXmCZZRyiegbTJ+lcXA621knMdbzsuDztcYMuvsJvkw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780412279; c=relaxed/simple; bh=lYcsPORKnxuunMCgSU5k6nxHhMkq2G0Rqn+l+mBnbPU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=InFrxL8e6K61+8A3F5GOpwtV36VkQRHEUNmHjquyl+kSHViYvDsMIL7+ZGKyKUsMUcYnRQO77s5rhNwRedRItiYEG84zdnS5owmp2WPf8zCsnNplOMdzkPAg95mR7y3369vZ0TGVckoweF5aqjkY6dDNAMC30ojfMsto0b2omEI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=A6mxZc6N; arc=none smtp.client-ip=198.175.65.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="A6mxZc6N" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1780412279; x=1811948279; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lYcsPORKnxuunMCgSU5k6nxHhMkq2G0Rqn+l+mBnbPU=; b=A6mxZc6NZe0c41od09HXBlC2x8EM8kGLyMwL1i/VOYWOn+Q2k/0rpzBu VEETD7EHJJooo4NpexBIIJX+KM3ZOoG1/3BF8NZn6kgMKLtoAcc+em8Jl Vu+vYsi5j44UWfW+QrOdGfVCgoZeB1nttMF4NOR2+IrlCGCUAuhC2Iaq7 QNbnFmhmwTft8YuF/Z0+GQ9LpU93tDCfkM4fegyoyk/ANkJFgg4wvyg8p rnLjEqbJC1DDgADJIdpHloK6gLMvIsqxN3uk80hmTeTs5OM4Avl7EdWaW aZKWWGQhF8B2zdXh3oBMC/vPQ2cgO4gvf8w6FRwlNVzbbPfpXGA9r8kle g==; X-CSE-ConnectionGUID: KxkT3UhQRc6Yy54RNpVE+Q== X-CSE-MsgGUID: BuJn3hDvQVCYr56bpFPgng== X-IronPort-AV: E=McAfee;i="6800,10657,11805"; a="103859986" X-IronPort-AV: E=Sophos;i="6.24,183,1774335600"; d="scan'208";a="103859986" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jun 2026 07:57:55 -0700 X-CSE-ConnectionGUID: xVgZT30YQ3m+M8OoKw+XbQ== X-CSE-MsgGUID: gnu0XselQa2A9Nuc6b5HCQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,183,1774335600"; d="scan'208";a="243095621" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.29]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jun 2026 07:57:54 -0700 From: Zide Chen To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen Subject: [PATCH V3 2/7] perf/x86/intel/uncore: Guard against invalid box control address Date: Tue, 2 Jun 2026 07:49:03 -0700 Message-ID: <20260602144908.263680-3-zide.chen@intel.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260602144908.263680-1-zide.chen@intel.com> References: <20260602144908.263680-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Theoretically, intel_uncore_find_discovery_unit() could return NULL, e.g., when a CPU die is offline during uncore enumeration and its PMU units are not added to the discovery RB-tree. Guard against a NULL return value and the resulting invalid box control address (0) before accessing hardware. Reviewed-by: Dapeng Mi Signed-off-by: Zide Chen --- V2: - New patch. - Address pre-existing invalid box control address issue (Sashiko). --- arch/x86/events/intel/uncore_discovery.c | 33 +++++++++++++++++------- 1 file changed, 24 insertions(+), 9 deletions(-) diff --git a/arch/x86/events/intel/uncore_discovery.c b/arch/x86/events/int= el/uncore_discovery.c index 60e1200c4691..af7e80fee81f 100644 --- a/arch/x86/events/intel/uncore_discovery.c +++ b/arch/x86/events/intel/uncore_discovery.c @@ -490,17 +490,28 @@ static u64 intel_generic_uncore_box_ctl(struct intel_= uncore_box *box) =20 void intel_generic_uncore_msr_init_box(struct intel_uncore_box *box) { - wrmsrq(intel_generic_uncore_box_ctl(box), GENERIC_PMON_BOX_CTL_INT); + u64 box_ctl =3D intel_generic_uncore_box_ctl(box); + + if (!box_ctl) + return; + + wrmsrq(box_ctl, GENERIC_PMON_BOX_CTL_INT); } =20 void intel_generic_uncore_msr_disable_box(struct intel_uncore_box *box) { - wrmsrq(intel_generic_uncore_box_ctl(box), GENERIC_PMON_BOX_CTL_FRZ); + u64 box_ctl =3D intel_generic_uncore_box_ctl(box); + + if (box_ctl) + wrmsrq(box_ctl, GENERIC_PMON_BOX_CTL_FRZ); } =20 void intel_generic_uncore_msr_enable_box(struct intel_uncore_box *box) { - wrmsrq(intel_generic_uncore_box_ctl(box), 0); + u64 box_ctl =3D intel_generic_uncore_box_ctl(box); + + if (box_ctl) + wrmsrq(box_ctl, 0); } =20 static void intel_generic_uncore_msr_enable_event(struct intel_uncore_box = *box, @@ -549,6 +560,7 @@ bool intel_generic_uncore_assign_hw_event(struct perf_e= vent *event, =20 if (box->pci_dev) { box_ctl =3D UNCORE_DISCOVERY_PCI_BOX_CTRL(box_ctl); + hwc->config_base =3D box_ctl + uncore_pci_event_ctl(box, hwc->idx); hwc->event_base =3D box_ctl + uncore_pci_perf_ctr(box, hwc->idx); return true; @@ -567,27 +579,30 @@ static inline int intel_pci_uncore_box_ctl(struct int= el_uncore_box *box) =20 void intel_generic_uncore_pci_init_box(struct intel_uncore_box *box) { - struct pci_dev *pdev =3D box->pci_dev; int box_ctl =3D intel_pci_uncore_box_ctl(box); =20 + if (!box_ctl) + return; + __set_bit(UNCORE_BOX_FLAG_CTL_OFFS8, &box->flags); - pci_write_config_dword(pdev, box_ctl, GENERIC_PMON_BOX_CTL_INT); + pci_write_config_dword(box->pci_dev, box_ctl, GENERIC_PMON_BOX_CTL_INT); } =20 void intel_generic_uncore_pci_disable_box(struct intel_uncore_box *box) { - struct pci_dev *pdev =3D box->pci_dev; int box_ctl =3D intel_pci_uncore_box_ctl(box); =20 - pci_write_config_dword(pdev, box_ctl, GENERIC_PMON_BOX_CTL_FRZ); + if (box_ctl) + pci_write_config_dword(box->pci_dev, box_ctl, + GENERIC_PMON_BOX_CTL_FRZ); } =20 void intel_generic_uncore_pci_enable_box(struct intel_uncore_box *box) { - struct pci_dev *pdev =3D box->pci_dev; int box_ctl =3D intel_pci_uncore_box_ctl(box); =20 - pci_write_config_dword(pdev, box_ctl, 0); + if (box_ctl) + pci_write_config_dword(box->pci_dev, box_ctl, 0); } =20 static void intel_generic_uncore_pci_enable_event(struct intel_uncore_box = *box, --=20 2.54.0 From nobody Mon Jun 8 04:19:39 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9EE2E35B63D; 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a="103859991" X-IronPort-AV: E=Sophos;i="6.24,183,1774335600"; d="scan'208";a="103859991" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jun 2026 07:57:55 -0700 X-CSE-ConnectionGUID: W9JLQx9PRf+84Pgx0DxYTg== X-CSE-MsgGUID: UciWMnHvTWmx70k9qbKnxA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,183,1774335600"; d="scan'208";a="243095625" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.29]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jun 2026 07:57:54 -0700 From: Zide Chen To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen Subject: [PATCH V3 3/7] perf/x86/intel/uncore: Fix PCI device refcount leak in UPI discovery Date: Tue, 2 Jun 2026 07:49:04 -0700 Message-ID: <20260602144908.263680-4-zide.chen@intel.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260602144908.263680-1-zide.chen@intel.com> References: <20260602144908.263680-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" pci_get_domain_bus_and_slot() increments the reference count of the returned PCI device and therefore requires a matching pci_dev_put(). In skx_upi_topology_cb() and discover_upi_topology(), the lookup is performed inside a loop, but pci_dev_put() is only called once after the loop. As a result, references from all previous iterations are leaked. Move pci_dev_put(dev) into the if (dev) block immediately after upi_fill_topology() returns. Opportunistically, fix uninitialized variable in skx_upi_topology_cb(). Fixes: 4cfce57fa42d ("perf/x86/intel/uncore: Enable UPI topology discovery = for Skylake Server") Fixes: f680b6e6062e ("perf/x86/intel/uncore: Enable UPI topology discovery = for Icelake Server") Reviewed-by: Dapeng Mi Signed-off-by: Zide Chen --- arch/x86/events/intel/uncore_snbep.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/u= ncore_snbep.c index 215d33e260ed..c9ce206fcbb6 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -4261,7 +4261,7 @@ static int upi_fill_topology(struct pci_dev *dev, str= uct intel_uncore_topology * static int skx_upi_topology_cb(struct intel_uncore_type *type, int segment, int die, u64 cpu_bus_msr) { - int idx, ret; + int idx, ret =3D 0; struct intel_uncore_topology *upi; unsigned int devfn; struct pci_dev *dev =3D NULL; @@ -4274,12 +4274,12 @@ static int skx_upi_topology_cb(struct intel_uncore_= type *type, int segment, dev =3D pci_get_domain_bus_and_slot(segment, bus, devfn); if (dev) { ret =3D upi_fill_topology(dev, upi, idx); + pci_dev_put(dev); if (ret) break; } } =20 - pci_dev_put(dev); return ret; } =20 @@ -5499,6 +5499,7 @@ static int discover_upi_topology(struct intel_uncore_= type *type, int ubox_did, i devfn); if (dev) { ret =3D upi_fill_topology(dev, upi, idx); + pci_dev_put(dev); if (ret) goto err; } @@ -5506,7 +5507,6 @@ static int discover_upi_topology(struct intel_uncore_= type *type, int ubox_did, i } err: pci_dev_put(ubox); - pci_dev_put(dev); return ret; } =20 --=20 2.54.0 From nobody Mon Jun 8 04:19:39 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D6E5D3E8324; Tue, 2 Jun 2026 14:57:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780412281; 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02 Jun 2026 07:57:55 -0700 X-CSE-ConnectionGUID: JYOz9VHrSrqdfu0w+Gv+YQ== X-CSE-MsgGUID: zqwUxP+STFuStepAZAu9ow== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,183,1774335600"; d="scan'208";a="243095628" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.29]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jun 2026 07:57:54 -0700 From: Zide Chen To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , stable@vger.kernel.org Subject: [PATCH V3 4/7] perf/x86/intel/uncore: Defer ADL global PMON enable to enable_box() Date: Tue, 2 Jun 2026 07:49:05 -0700 Message-ID: <20260602144908.263680-5-zide.chen@intel.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260602144908.263680-1-zide.chen@intel.com> References: <20260602144908.263680-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On some Raptor Cove CPUs, enabling uncore PMON globally at driver init may increase power consumption even when no perf events are in use. Drop adl_uncore_msr_init_box() and defer programming the global control register to enable_box(), so it is only set when a box is actually used. IMC and IMC freerunning counters use a separate control path and are unaffected. Cc: stable@vger.kernel.org Fixes: 772ed05f3c5c ("perf/x86/intel/uncore: Add Alder Lake support") Reviewed-by: Dapeng Mi Signed-off-by: Zide Chen --- V3: - Add Fixes tag. (Dapeng) --- arch/x86/events/intel/uncore_snb.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/arch/x86/events/intel/uncore_snb.c b/arch/x86/events/intel/unc= ore_snb.c index 3dbc6bacbd9d..edddd4f9ab5f 100644 --- a/arch/x86/events/intel/uncore_snb.c +++ b/arch/x86/events/intel/uncore_snb.c @@ -563,12 +563,6 @@ void tgl_uncore_cpu_init(void) skl_uncore_msr_ops.init_box =3D rkl_uncore_msr_init_box; } =20 -static void adl_uncore_msr_init_box(struct intel_uncore_box *box) -{ - if (box->pmu->pmu_idx =3D=3D 0) - wrmsrq(ADL_UNC_PERF_GLOBAL_CTL, SNB_UNC_GLOBAL_CTL_EN); -} - static void adl_uncore_msr_enable_box(struct intel_uncore_box *box) { wrmsrq(ADL_UNC_PERF_GLOBAL_CTL, SNB_UNC_GLOBAL_CTL_EN); @@ -587,7 +581,6 @@ static void adl_uncore_msr_exit_box(struct intel_uncore= _box *box) } =20 static struct intel_uncore_ops adl_uncore_msr_ops =3D { - .init_box =3D adl_uncore_msr_init_box, .enable_box =3D adl_uncore_msr_enable_box, .disable_box =3D adl_uncore_msr_disable_box, .exit_box =3D adl_uncore_msr_exit_box, --=20 2.54.0 From nobody Mon Jun 8 04:19:39 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C373364E84; Tue, 2 Jun 2026 14:57:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780412279; cv=none; b=dmZymG2wQE6PN4t25/V3gFK95jcOwMmLukDXRYnz/z3JRQG/PyDj1mcDo9LNb/Ka9Vy+Q+FhjNXD8KY0ZuwxHAH37yHkx12NQa0EifgxIFL9Dm/pO8wD5DR1bPcKGNdZwmH6loBntOaT7QLC9vh2TfMzLuwIpou60rRwoJNcV+Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780412279; c=relaxed/simple; bh=YMuiNywvYbkwpmTegKp1vjKS9VWhDJSz9q6xitexl+s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Xof36BUX3rucVNrO6Taorc/chi1btx+wqDdzK3HsqqVDBLEofJh2eaui5ypxoQ7NGi+dOOQPSo5OUeko2mgPgZcdISZQitRnnvnsMsTqOLBIgj8wlIuPjZw6Ol2sB2FJOe2yufTR5pQScpJDZzRotscyHF/UbjaSwSzsIPCJMC4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=WTLxWncM; arc=none smtp.client-ip=198.175.65.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="WTLxWncM" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1780412279; x=1811948279; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YMuiNywvYbkwpmTegKp1vjKS9VWhDJSz9q6xitexl+s=; b=WTLxWncMqUhYuKHjTfQSqlrwipP7ak0yBgT9X02Yt2IvzHMr/iPzpGcj RbQxRWjJf845IWDd2/ymDvheZ9u2zc0mBqlIMnhk+JVVtVEE68GuuzJXj D6fzLh+8HQuXs3EcwbCFjFw2iwQBbdolhVX5U6eCUGUIXJdVNQHJ24xae 9yGNKZzM64RWMFasTZWHJcD1Bp6Xkyf8+3oS2/mylUR8eE5l9w87qPznp nZESy2Gajuz2jkU4+0wmRHWxlpS48IL0earQodZ5AfTBQrduBoFcA06dR sfUKo7zBrv1rokALCxN8mPP+hzMRlg6rmKqtA0iviWBZwmHWV0kBxKm1P w==; X-CSE-ConnectionGUID: FhDQjyitQNGqO9Gkl7ekTw== X-CSE-MsgGUID: oTAMxck7RD+0s1v60ui4eA== X-IronPort-AV: E=McAfee;i="6800,10657,11805"; a="103860003" X-IronPort-AV: E=Sophos;i="6.24,183,1774335600"; d="scan'208";a="103860003" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jun 2026 07:57:55 -0700 X-CSE-ConnectionGUID: ybo03O+kTJ+xKuLWVzKp4w== X-CSE-MsgGUID: by/pMh9HRYqcFB869tpO6Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,183,1774335600"; d="scan'208";a="243095631" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.29]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jun 2026 07:57:54 -0700 From: Zide Chen To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen Subject: [PATCH V3 5/7] perf/x86/intel/uncore: Move die_to_cpu() to uncore.c Date: Tue, 2 Jun 2026 07:49:06 -0700 Message-ID: <20260602144908.263680-6-zide.chen@intel.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260602144908.263680-1-zide.chen@intel.com> References: <20260602144908.263680-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move die_to_cpu() into uncore.c so it can be reused by the MSR initialization path, preparing for the introduction of an MSR global initialization callback. Move the cpus_read_{lock,unlock}() out of the API, in order to make it possible to be called when the lock is being held. Add the uncore_ prefix for consistency with other uncore APIs. Reviewed-by: Dapeng Mi Signed-off-by: Zide Chen --- V2: - Move cpus_read_{lock,unlock}() out of uncore_die_to_cpu() and rely on callers to manage the lock. (Sashiko) - Remove "No functional change intended" from the changelog. --- arch/x86/events/intel/uncore.c | 19 +++++++++++++++++++ arch/x86/events/intel/uncore.h | 1 + arch/x86/events/intel/uncore_snbep.c | 23 +++-------------------- 3 files changed, 23 insertions(+), 20 deletions(-) diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index e9cc1ba921c5..22256ded2d67 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -83,6 +83,25 @@ int uncore_device_to_die(struct pci_dev *dev) return -1; } =20 +/* + * Using cpus_read_lock() to ensure cpu is not going down between + * looking at cpu_online_mask. + * + * The lock must be held by the caller. + */ +int uncore_die_to_cpu(int die) +{ + int res =3D 0, cpu; + + for_each_online_cpu(cpu) { + if (topology_logical_die_id(cpu) =3D=3D die) { + res =3D cpu; + break; + } + } + return res; +} + static void uncore_free_pcibus_map(void) { struct pci2phy_map *map, *tmp; diff --git a/arch/x86/events/intel/uncore.h b/arch/x86/events/intel/uncore.h index c35918c01afa..94c68e3417b6 100644 --- a/arch/x86/events/intel/uncore.h +++ b/arch/x86/events/intel/uncore.h @@ -235,6 +235,7 @@ struct pci2phy_map *__find_pci2phy_map(int segment); int uncore_pcibus_to_dieid(struct pci_bus *bus); int uncore_die_to_segment(int die); int uncore_device_to_die(struct pci_dev *dev); +int uncore_die_to_cpu(int die); =20 ssize_t uncore_event_show(struct device *dev, struct device_attribute *attr, char *buf); diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/u= ncore_snbep.c index c9ce206fcbb6..772b78237424 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -3704,25 +3704,6 @@ static int skx_msr_cpu_bus_read(int cpu, u64 *topolo= gy) return 0; } =20 -static int die_to_cpu(int die) -{ - int res =3D 0, cpu, current_die; - /* - * Using cpus_read_lock() to ensure cpu is not going down between - * looking at cpu_online_mask. - */ - cpus_read_lock(); - for_each_online_cpu(cpu) { - current_die =3D topology_logical_die_id(cpu); - if (current_die =3D=3D die) { - res =3D cpu; - break; - } - } - cpus_read_unlock(); - return res; -} - enum { IIO_TOPOLOGY_TYPE, UPI_TOPOLOGY_TYPE, @@ -3794,8 +3775,9 @@ static int skx_pmu_get_topology(struct intel_uncore_t= ype *type, int die, ret =3D -EPERM; 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d="scan'208";a="243095634" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.29]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jun 2026 07:57:54 -0700 From: Zide Chen To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen Subject: [PATCH V3 6/7] perf/x86/intel/uncore: Fix uncore_die_to_cpu() for offline dies Date: Tue, 2 Jun 2026 07:49:07 -0700 Message-ID: <20260602144908.263680-7-zide.chen@intel.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260602144908.263680-1-zide.chen@intel.com> References: <20260602144908.263680-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" If the die is offline when uncore_die_to_cpu() is called, it silently returns 0, which is misleading. Return -1 in this case to indicate that all CPUs on the die are offline and the caller can take care of it accordingly. Opportunistically, replace -EPERM with -ENODEV, as -ENODEV is the appropriate error when no CPUs are online across all dies. Reviewed-by: Dapeng Mi Signed-off-by: Zide Chen --- arch/x86/events/intel/uncore.c | 2 +- arch/x86/events/intel/uncore_snbep.c | 9 +++++++-- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index 22256ded2d67..4b3a1fa5b41b 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -91,7 +91,7 @@ int uncore_device_to_die(struct pci_dev *dev) */ int uncore_die_to_cpu(int die) { - int res =3D 0, cpu; + int res =3D -1, cpu; =20 for_each_online_cpu(cpu) { if (topology_logical_die_id(cpu) =3D=3D die) { diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/u= ncore_snbep.c index 772b78237424..334dc384b5b9 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -3772,12 +3772,17 @@ static void pmu_free_topology(struct intel_uncore_t= ype *type) static int skx_pmu_get_topology(struct intel_uncore_type *type, int (*topology_cb)(struct intel_uncore_type*, int, int, u64)) { - int die, ret =3D -EPERM; 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d="scan'208";a="243095636" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.29]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jun 2026 07:57:54 -0700 From: Zide Chen To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen Subject: [PATCH V3 7/7] perf/x86/intel/uncore: Implement global init callback for GNR uncore Date: Tue, 2 Jun 2026 07:49:08 -0700 Message-ID: <20260602144908.263680-8-zide.chen@intel.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260602144908.263680-1-zide.chen@intel.com> References: <20260602144908.263680-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On Sierra Forest and Clearwater Forest, the FRZ_ALL bit in the global control register defaults to 0 at boot, but UBOX PMON units do not work until the global control register is explicitly written with 0 to trigger hardware initialization properly. Implement the generic uncore_msr_global_init() callback and add it to gnr_uncore_init[], which is shared by GNR, GRR, SRF, and CWF. Fixes: 632c4bf6d007 ("perf/x86/intel/uncore: Support Granite Rapids") Reviewed-by: Dapeng Mi Signed-off-by: Zide Chen --- v3: - Guard uncore_discovery_pci() with cpus_read_lock() to fix a theoretical race where CPUs could go offline between uncore_die_to_cpu() and wrmsrq_on_cpu(). (Sashiko) - Add Fixes tag. (Dapeng) v2: - Propagate return value of wrmsrq_on_cpu() to global_init(). --- arch/x86/events/intel/uncore.c | 13 ++++++++++++- arch/x86/events/intel/uncore.h | 2 +- arch/x86/events/intel/uncore_discovery.c | 9 +++++---- 3 files changed, 18 insertions(+), 6 deletions(-) diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index 4b3a1fa5b41b..7857959c6e82 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -1716,7 +1716,7 @@ static int __init uncore_mmio_init(void) return ret; } =20 -static int uncore_mmio_global_init(u64 ctl) +static int uncore_mmio_global_init(int die, u64 ctl) { void __iomem *io_addr; =20 @@ -1731,6 +1731,16 @@ static int uncore_mmio_global_init(u64 ctl) return 0; } =20 +static int uncore_msr_global_init(int die, u64 msr) +{ + int cpu =3D uncore_die_to_cpu(die); + + if (cpu =3D=3D -1) + return -ENODEV; + + return wrmsrq_on_cpu(cpu, msr, 0); +} + static const struct uncore_plat_init nhm_uncore_init __initconst =3D { .cpu_init =3D nhm_uncore_cpu_init, }; @@ -1871,6 +1881,7 @@ static const struct uncore_plat_init gnr_uncore_init = __initconst =3D { .domain[0].base_is_pci =3D true, .domain[0].discovery_base =3D UNCORE_DISCOVERY_TABLE_DEVICE, .domain[0].units_ignore =3D gnr_uncore_units_ignore, + .domain[0].global_init =3D uncore_msr_global_init, }; =20 static const struct uncore_plat_init dmr_uncore_init __initconst =3D { diff --git a/arch/x86/events/intel/uncore.h b/arch/x86/events/intel/uncore.h index 94c68e3417b6..c2e5ccb1d72c 100644 --- a/arch/x86/events/intel/uncore.h +++ b/arch/x86/events/intel/uncore.h @@ -53,7 +53,7 @@ struct uncore_discovery_domain { /* MSR address or PCI device used as the discovery base */ u32 discovery_base; bool base_is_pci; - int (*global_init)(u64 ctl); + int (*global_init)(int die, u64 ctl); =20 /* The units in the discovery table should be ignored. */ int *units_ignore; diff --git a/arch/x86/events/intel/uncore_discovery.c b/arch/x86/events/int= el/uncore_discovery.c index af7e80fee81f..e50776222256 100644 --- a/arch/x86/events/intel/uncore_discovery.c +++ b/arch/x86/events/intel/uncore_discovery.c @@ -287,7 +287,7 @@ static int __parse_discovery_table(struct uncore_discov= ery_domain *domain, if (!io_addr) return -ENOMEM; =20 - if (domain->global_init && domain->global_init(global.ctl)) { + if (domain->global_init && domain->global_init(die, global.ctl)) { ret =3D -ENODEV; goto out; } @@ -399,7 +399,6 @@ static bool uncore_discovery_msr(struct uncore_discover= y_domain *domain) if (!die_mask) return false; =20 - cpus_read_lock(); for_each_online_cpu(cpu) { die =3D topology_logical_die_id(cpu); if (__test_and_set_bit(die, die_mask)) @@ -414,8 +413,6 @@ static bool uncore_discovery_msr(struct uncore_discover= y_domain *domain) __parse_discovery_table(domain, base, die, &parsed); } =20 - cpus_read_unlock(); - kfree(die_mask); return parsed; } @@ -429,10 +426,14 @@ bool uncore_discovery(struct uncore_plat_init *init) for (i =3D 0; i < UNCORE_DISCOVERY_DOMAINS; i++) { domain =3D &init->domain[i]; if (domain->discovery_base) { + cpus_read_lock(); + if (!domain->base_is_pci) ret |=3D uncore_discovery_msr(domain); else ret |=3D uncore_discovery_pci(domain); + + cpus_read_unlock(); } } =20 --=20 2.54.0