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Tue, 2 Jun 2026 06:55:02 -0700 (PDT) From: To: CC: , , , , , , , , Sukhdeep Singh Subject: [PATCH net-next v4 1/12] net: atlantic: correct L3L4 filter flow_type masking and IPv6 handling Date: Tue, 2 Jun 2026 19:24:41 +0530 Message-ID: <20260602135452.516-2-sukhdeeps@marvell.com> X-Mailer: git-send-email 2.52.0.windows.1 In-Reply-To: <20260602135452.516-1-sukhdeeps@marvell.com> References: <20260602135452.516-1-sukhdeeps@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=GaInWwXL c=1 sm=1 tr=0 ts=6a1ee0bb cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=FelO9ux0wxsA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=TtqV-g6YmW1Jfm2GSLaY:22 a=M5GUcnROAAAA:8 a=7-RSyJf46AiWYYgqFwsA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-ORIG-GUID: ombZElfv7JOxUI0EOaCYUrgTgoSI-mtY X-Proofpoint-GUID: ombZElfv7JOxUI0EOaCYUrgTgoSI-mtY X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjAyMDEzMyBTYWx0ZWRfX1hFeJQS1gzUm h0KPqjH4bd9B7CZuyeX1QeOAAcRCv0GcfoSC3F5I+8GSSCtrwER3B6dF12a76GcGvL911NErDPV WJJ2VtAxTf+s0tnjFgVJY14YxDndjOO4khRu5sTZo1qUxDVkx8GlmNx6dLrS943E+gUU5Rdzduj RrVzQE0UCTcwefOmzDcoQgaA/TIy27YCa6KgVl70xKOo+u+EgmC2MwDhuxFbEMFUEHbJhEtjz2n n7ODVNU5fJ/P1WV/1c9tPUDwZR4XSKq95v0PirnwZ72rdhEbdMgUcfEL7/3kxEBVMm+rKLrfvWQ pyxNngbdBZSf8pFERNIWgldIqTJtqqbjWTa+ffSu4lZunGTmMF+1RZWrAfJknBw155TZFbXWUd1 f1lRkCbepj6x1N1VJptHXF/9aYyY2K5pfrLJxq423AwMZFU433x587eH8agPFbZjv9Ur6z0fN2I oQRLfX+7cUGIdvG2b3A== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-02_02,2026-05-28_03,2025-10-01_01 Content-Type: text/plain; charset="utf-8" From: Sukhdeep Singh Correct three issues in aq_set_data_fl3l4() required for the AQC113 PTP filter path introduced later in this series: 1. Mask FLOW_EXT from flow_type before the protocol switch statement. Flow types with FLOW_EXT set (e.g. TCP_V4_FLOW | FLOW_EXT) fall through to the default case and skip protocol comparison flags. 2. Extend the L3 address comparison check to cover all four IPv6 words. The original code only checked ip_src[0]/ip_dst[0] and required !is_ipv6, so CMP_SRC_ADDR_L3/CMP_DEST_ADDR_L3 were never set for IPv6 filters. 3. Use explicit flow type checks for port extraction instead of negating IP_USER_FLOW/IPV6_USER_FLOW. The old check did not mask FLOW_EXT, so IP_USER_FLOW | FLOW_EXT would incorrectly attempt port extraction. Use the actual flow type to pick the correct union member directly. Signed-off-by: Sukhdeep Singh --- .../ethernet/aquantia/atlantic/aq_filters.c | 33 ++++++++++--------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_filters.c b/drivers/= net/ethernet/aquantia/atlantic/aq_filters.c index e419c73b32ce..eef52f23166d 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_filters.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_filters.c @@ -472,6 +472,7 @@ static int aq_set_data_fl3l4(struct aq_nic_s *aq_nic, { struct aq_hw_rx_fltrs_s *rx_fltrs =3D aq_get_hw_rx_fltrs(aq_nic); const struct ethtool_rx_flow_spec *fsp =3D &aq_rx_fltr->aq_fsp; + u32 flow =3D fsp->flow_type & ~FLOW_EXT; =20 memset(data, 0, sizeof(*data)); =20 @@ -490,7 +491,7 @@ static int aq_set_data_fl3l4(struct aq_nic_s *aq_nic, =20 data->cmd |=3D HW_ATL_RX_ENABLE_FLTR_L3L4; =20 - switch (fsp->flow_type) { + switch (flow) { case TCP_V4_FLOW: case TCP_V6_FLOW: data->cmd |=3D HW_ATL_RX_ENABLE_CMP_PROT_L4; @@ -527,23 +528,23 @@ static int aq_set_data_fl3l4(struct aq_nic_s *aq_nic, } data->cmd |=3D HW_ATL_RX_ENABLE_L3_IPV6; } - if (fsp->flow_type !=3D IP_USER_FLOW && - fsp->flow_type !=3D IPV6_USER_FLOW) { - if (!data->is_ipv6) { - data->p_dst =3D - ntohs(fsp->h_u.tcp_ip4_spec.pdst); - data->p_src =3D - ntohs(fsp->h_u.tcp_ip4_spec.psrc); - } else { - data->p_dst =3D - ntohs(fsp->h_u.tcp_ip6_spec.pdst); - data->p_src =3D - ntohs(fsp->h_u.tcp_ip6_spec.psrc); - } + if (flow =3D=3D TCP_V4_FLOW || flow =3D=3D UDP_V4_FLOW || + flow =3D=3D SCTP_V4_FLOW) { + data->p_dst =3D ntohs(fsp->h_u.tcp_ip4_spec.pdst); + data->p_src =3D ntohs(fsp->h_u.tcp_ip4_spec.psrc); + } + if (flow =3D=3D TCP_V6_FLOW || flow =3D=3D UDP_V6_FLOW || + flow =3D=3D SCTP_V6_FLOW) { + data->p_dst =3D ntohs(fsp->h_u.tcp_ip6_spec.pdst); + data->p_src =3D ntohs(fsp->h_u.tcp_ip6_spec.psrc); } - if (data->ip_src[0] && !data->is_ipv6) + if (data->ip_src[0] || + (data->is_ipv6 && (data->ip_src[1] || data->ip_src[2] || + data->ip_src[3]))) data->cmd |=3D HW_ATL_RX_ENABLE_CMP_SRC_ADDR_L3; - if (data->ip_dst[0] && !data->is_ipv6) + if (data->ip_dst[0] || + (data->is_ipv6 && (data->ip_dst[1] || data->ip_dst[2] || + data->ip_dst[3]))) data->cmd |=3D HW_ATL_RX_ENABLE_CMP_DEST_ADDR_L3; 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charset="utf-8" From: Sukhdeep Singh Move active_ipv4/active_ipv6 bitmap updates from aq_set_data_fl3l4() into aq_add_del_fl3l4() after the hardware write succeeds. The bitmaps track which filter slots are actively programmed in hardware and must only be updated once the HW write is confirmed. The bitmap updates in aq_nic_reserve_filter() and aq_nic_release_filter() are intentionally retained: they guard the aq_check_approve_fl3l4() IPv4/IPv6 mixing validation for callers such as the AQC113 PTP path that program filters directly via hw_atl2_new_fl3l4_configure() without going through aq_add_del_fl3l4(). Signed-off-by: Sukhdeep Singh --- .../ethernet/aquantia/atlantic/aq_filters.c | 36 ++++++++++++------- 1 file changed, 23 insertions(+), 13 deletions(-) diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_filters.c b/drivers/= net/ethernet/aquantia/atlantic/aq_filters.c index eef52f23166d..150a0b1af26a 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_filters.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_filters.c @@ -479,15 +479,8 @@ static int aq_set_data_fl3l4(struct aq_nic_s *aq_nic, data->is_ipv6 =3D rx_fltrs->fl3l4.is_ipv6; data->location =3D HW_ATL_GET_REG_LOCATION_FL3L4(fsp->location); =20 - if (!add) { - if (!data->is_ipv6) - rx_fltrs->fl3l4.active_ipv4 &=3D ~BIT(data->location); - else - rx_fltrs->fl3l4.active_ipv6 &=3D - ~BIT((data->location) / 4); - + if (!add) return 0; - } =20 data->cmd |=3D HW_ATL_RX_ENABLE_FLTR_L3L4; =20 @@ -515,11 +508,9 @@ static int aq_set_data_fl3l4(struct aq_nic_s *aq_nic, ntohl(fsp->h_u.tcp_ip4_spec.ip4src); data->ip_dst[0] =3D ntohl(fsp->h_u.tcp_ip4_spec.ip4dst); - rx_fltrs->fl3l4.active_ipv4 |=3D BIT(data->location); } else { int i; =20 - rx_fltrs->fl3l4.active_ipv6 |=3D BIT((data->location) / 4); for (i =3D 0; i < HW_ATL_RX_CNT_REG_ADDR_IPV6; ++i) { data->ip_dst[i] =3D ntohl(fsp->h_u.tcp_ip6_spec.ip6dst[i]); @@ -574,16 +565,35 @@ static int aq_set_fl3l4(struct aq_hw_s *aq_hw, static int aq_add_del_fl3l4(struct aq_nic_s *aq_nic, struct aq_rx_filter *aq_rx_fltr, bool add) { + struct aq_hw_rx_fltrs_s *rx_fltrs =3D aq_get_hw_rx_fltrs(aq_nic); const struct aq_hw_ops *aq_hw_ops =3D aq_nic->aq_hw_ops; struct aq_hw_s *aq_hw =3D aq_nic->aq_hw; struct aq_rx_filter_l3l4 data; + int err; =20 if (unlikely(aq_rx_fltr->aq_fsp.location < AQ_RX_FIRST_LOC_FL3L4 || - aq_rx_fltr->aq_fsp.location > AQ_RX_LAST_LOC_FL3L4 || - aq_set_data_fl3l4(aq_nic, aq_rx_fltr, &data, add))) + aq_rx_fltr->aq_fsp.location > AQ_RX_LAST_LOC_FL3L4)) return -EINVAL; =20 - return aq_set_fl3l4(aq_hw, aq_hw_ops, &data); + aq_set_data_fl3l4(aq_nic, aq_rx_fltr, &data, add); + + err =3D aq_set_fl3l4(aq_hw, aq_hw_ops, &data); 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charset="utf-8" From: Sukhdeep Singh Refactor aq_set_data_fl3l4() to take an ethtool_rx_flow_spec pointer and an explicit HW register location instead of driver-internal structures (aq_nic_s, aq_rx_filter). This makes the function reusable for PTP filter setup which constructs flow specs independently. Key changes: - Add aq_is_ipv6_flow_type() helper to derive IPv6 status from the flow_type field, replacing the dependency on rx_fltrs->fl3l4.is_ipv6 shared state. - Change aq_set_data_fl3l4() signature to accept (fsp, data, location, add) and export it via aq_filters.h. - Update aq_add_del_fl3l4() to compute the HW register location and pass it explicitly. Signed-off-by: Sukhdeep Singh --- .../ethernet/aquantia/atlantic/aq_filters.c | 31 ++++++++++++++----- .../ethernet/aquantia/atlantic/aq_filters.h | 3 ++ 2 files changed, 26 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_filters.c b/drivers/= net/ethernet/aquantia/atlantic/aq_filters.c index 150a0b1af26a..4be7b629bfac 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_filters.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_filters.c @@ -181,6 +181,20 @@ aq_check_approve_fvlan(struct aq_nic_s *aq_nic, return 0; } =20 +static bool aq_is_ipv6_flow_type(const struct ethtool_rx_flow_spec *fsp) +{ + switch (fsp->flow_type & ~FLOW_EXT) { + case TCP_V6_FLOW: + case UDP_V6_FLOW: + case SCTP_V6_FLOW: + case IPV6_FLOW: + case IPV6_USER_FLOW: + return true; + default: + return false; + } +} + static int __must_check aq_check_filter(struct aq_nic_s *aq_nic, struct ethtool_rx_flow_spec *fsp) @@ -466,18 +480,16 @@ static int aq_add_del_fvlan(struct aq_nic_s *aq_nic, return aq_filters_vlans_update(aq_nic); } =20 -static int aq_set_data_fl3l4(struct aq_nic_s *aq_nic, - struct aq_rx_filter *aq_rx_fltr, - struct aq_rx_filter_l3l4 *data, bool add) +int aq_set_data_fl3l4(const struct ethtool_rx_flow_spec *fsp, + struct aq_rx_filter_l3l4 *data, + int location, bool add) { - struct aq_hw_rx_fltrs_s *rx_fltrs =3D aq_get_hw_rx_fltrs(aq_nic); - const struct ethtool_rx_flow_spec *fsp =3D &aq_rx_fltr->aq_fsp; u32 flow =3D fsp->flow_type & ~FLOW_EXT; =20 memset(data, 0, sizeof(*data)); =20 - data->is_ipv6 =3D rx_fltrs->fl3l4.is_ipv6; - data->location =3D HW_ATL_GET_REG_LOCATION_FL3L4(fsp->location); + data->is_ipv6 =3D aq_is_ipv6_flow_type(fsp); + data->location =3D location; =20 if (!add) return 0; @@ -569,13 +581,16 @@ static int aq_add_del_fl3l4(struct aq_nic_s *aq_nic, const struct aq_hw_ops *aq_hw_ops =3D aq_nic->aq_hw_ops; struct aq_hw_s *aq_hw =3D aq_nic->aq_hw; struct aq_rx_filter_l3l4 data; + int location; int err; =20 if (unlikely(aq_rx_fltr->aq_fsp.location < AQ_RX_FIRST_LOC_FL3L4 || aq_rx_fltr->aq_fsp.location > AQ_RX_LAST_LOC_FL3L4)) return -EINVAL; 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charset="utf-8" From: Sukhdeep Singh Add low-level hardware register definitions and accessor functions for AQC113 (Antigua) chip features: - L3/L4 filter command, tag, and address registers for IPv4/IPv6 - Ethertype filter tag registers - TSG (Time Stamp Generator) clock control, modification, and GPIO event generation/input timestamp registers - TX descriptor timestamp writeback, timestamp enable, and AVB enable registers - TX data/descriptor read request limit registers - TPB highest priority TC registers - PCIe extended tag enable register - RX descriptor timestamp request register - Action resolver section enable getter - GPIO special mode and TSG external GPIO TS input select Signed-off-by: Sukhdeep Singh --- .../aquantia/atlantic/hw_atl2/hw_atl2_llh.c | 322 ++++++++++++++++++ .../aquantia/atlantic/hw_atl2/hw_atl2_llh.h | 97 +++++- .../atlantic/hw_atl2/hw_atl2_llh_internal.h | 204 ++++++++++- 3 files changed, 617 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh.c b= /drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh.c index cd954b11d24a..2414e60b2028 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh.c @@ -7,6 +7,13 @@ #include "hw_atl2_llh_internal.h" #include "aq_hw_utils.h" =20 +u32 hw_atl2_phi_ext_tag_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg_bit(aq_hw, HW_ATL2_PHI_EXT_TAG_EN_ADR, + HW_ATL2_PHI_EXT_TAG_EN_MSK, + HW_ATL2_PHI_EXT_TAG_EN_SHIFT); +} + void hw_atl2_rpf_redirection_table2_select_set(struct aq_hw_s *aq_hw, u32 select) { @@ -66,6 +73,266 @@ void hw_atl2_rpf_vlan_flr_tag_set(struct aq_hw_s *aq_hw= , u32 tag, u32 filter) tag); } =20 +void hw_atl2_rpf_etht_flr_tag_set(struct aq_hw_s *aq_hw, u32 tag, u32 filt= er) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL2_RPF_ET_TAG_ADR(filter), + HW_ATL2_RPF_ET_TAG_MSK, + HW_ATL2_RPF_ET_TAG_SHIFT, tag); +} + +u32 hw_atl2_rpf_etht_flr_tag_get(struct aq_hw_s *aq_hw, u32 filter) +{ + return aq_hw_read_reg_bit(aq_hw, HW_ATL2_RPF_ET_TAG_ADR(filter), + HW_ATL2_RPF_ET_TAG_MSK, + HW_ATL2_RPF_ET_TAG_SHIFT); +} + +void hw_atl2_rpf_l3_v4_dest_addr_set(struct aq_hw_s *aq_hw, u32 filter, u3= 2 val) +{ + u32 addr_set =3D 6 + ((filter < 4) ? 0 : 1); + u32 dword =3D filter % 4; + + aq_hw_write_reg(aq_hw, HW_ATL2_RPF_L3_DA_DW_ADR(addr_set, dword), val); +} + +void hw_atl2_rpf_l3_v4_src_addr_set(struct aq_hw_s *aq_hw, u32 filter, u32= val) +{ + u32 addr_set =3D 6 + ((filter < 4) ? 0 : 1); + u32 dword =3D filter % 4; + + aq_hw_write_reg(aq_hw, HW_ATL2_RPF_L3_SA_DW_ADR(addr_set, dword), val); +} + +void hw_atl2_rpf_l3_v6_dest_addr_set(struct aq_hw_s *aq_hw, u8 location, + u32 *ipv6_dst) +{ + int i; + + for (i =3D 0; i < 4; ++i) + aq_hw_write_reg(aq_hw, + HW_ATL2_RPF_L3_DA_DW_ADR(location, 3 - i), + ipv6_dst[i]); +} + +void hw_atl2_rpf_l3_v6_src_addr_set(struct aq_hw_s *aq_hw, u8 location, + u32 *ipv6_src) +{ + int i; + + for (i =3D 0; i < 4; ++i) + aq_hw_write_reg(aq_hw, + HW_ATL2_RPF_L3_SA_DW_ADR(location, 3 - i), + ipv6_src[i]); +} + +void hw_atl2_rpf_l3_v4_cmd_set(struct aq_hw_s *aq_hw, u32 val, u32 filter) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL2_RPF_L3_V4_CMD_ADR(filter), + HW_ATL2_RPF_L3_V4_CMD_MSK, + HW_ATL2_RPF_L3_V4_CMD_SHIFT, val); +} + +void hw_atl2_rpf_l3_v6_cmd_set(struct aq_hw_s *aq_hw, u32 val, u32 filter) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL2_RPF_L3_V6_CMD_ADR(filter), + HW_ATL2_RPF_L3_V6_CMD_MSK, + HW_ATL2_RPF_L3_V6_CMD_SHIFT, val); +} + +void hw_atl2_rpf_l3_v6_v4_select_set(struct aq_hw_s *aq_hw, u32 val) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL2_RPF_L3_V6_V4_SELECT_ADR, + HW_ATL2_RPF_L3_V6_V4_SELECT_MSK, + HW_ATL2_RPF_L3_V6_V4_SELECT_SHIFT, val); +} + +void hw_atl2_rpf_l3_v4_tag_set(struct aq_hw_s *aq_hw, u32 val, u32 filter) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL2_RPF_L3_V4_TAG_ADR(filter), + HW_ATL2_RPF_L3_V4_TAG_MSK, + HW_ATL2_RPF_L3_V4_TAG_SHIFT, val); +} + +void hw_atl2_rpf_l3_v6_tag_set(struct aq_hw_s *aq_hw, u32 val, u32 filter) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL2_RPF_L3_V6_TAG_ADR(filter), + HW_ATL2_RPF_L3_V6_TAG_MSK, + HW_ATL2_RPF_L3_V6_TAG_SHIFT, val); +} + +void hw_atl2_rpf_l4_tag_set(struct aq_hw_s *aq_hw, u32 val, u32 filter) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL2_RPF_L4_TAG_ADR(filter), + HW_ATL2_RPF_L4_TAG_MSK, + HW_ATL2_RPF_L4_TAG_SHIFT, val); +} + +void hw_atl2_rpf_l4_cmd_set(struct aq_hw_s *aq_hw, u32 val, u32 filter) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL2_RPF_L4_CMD_ADR(filter), + HW_ATL2_RPF_L4_CMD_MSK, + HW_ATL2_RPF_L4_CMD_SHIFT, val); +} + +/* tsg */ +static void hw_atl2_clock_modif_value_set(struct aq_hw_s *aq_hw, + u32 clock_sel, u64 ns) +{ + aq_hw_write_reg64(aq_hw, + HW_ATL2_TSG_REG_ADR(clock_sel, CLOCK_MODIF_VAL_LSW), + ns); +} + +void hw_atl2_tsg_clock_en(struct aq_hw_s *aq_hw, + u32 clock_sel, u32 clock_enable) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL2_TSG_REG_ADR(clock_sel, CLOCK_CFG), + HW_ATL2_TSG_CLOCK_EN_MSK, + HW_ATL2_TSG_CLOCK_EN_SHIFT, + clock_enable); +} + +void hw_atl2_tsg_clock_reset(struct aq_hw_s *aq_hw, u32 clock_sel) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL2_TSG_REG_ADR(clock_sel, CLOCK_CFG), + HW_ATL2_TSG_SYNC_RESET_MSK, + HW_ATL2_TSG_SYNC_RESET_SHIFT, 1); + aq_hw_write_reg_bit(aq_hw, HW_ATL2_TSG_REG_ADR(clock_sel, CLOCK_CFG), + HW_ATL2_TSG_SYNC_RESET_MSK, + HW_ATL2_TSG_SYNC_RESET_SHIFT, 0); +} + +u64 hw_atl2_tsg_clock_read(struct aq_hw_s *aq_hw, u32 clock_sel) +{ + return aq_hw_read_reg64(aq_hw, + HW_ATL2_TSG_REG_ADR(clock_sel, + READ_CUR_NS_LSW)); +} + +void hw_atl2_tsg_clock_add(struct aq_hw_s *aq_hw, u32 clock_sel, u64 ns) +{ + hw_atl2_clock_modif_value_set(aq_hw, clock_sel, ns); + aq_hw_write_reg(aq_hw, + HW_ATL2_TSG_REG_ADR(clock_sel, CLOCK_MODIF_CTRL), + HW_ATL2_TSG_ADD_COUNTER_MSK); +} + +void hw_atl2_tsg_clock_sub(struct aq_hw_s *aq_hw, u32 clock_sel, u64 ns) +{ + hw_atl2_clock_modif_value_set(aq_hw, clock_sel, ns); + aq_hw_write_reg(aq_hw, + HW_ATL2_TSG_REG_ADR(clock_sel, CLOCK_MODIF_CTRL), + HW_ATL2_TSG_SUBTRACT_COUNTER_MSK); +} + +void hw_atl2_tsg_clock_increment_set(struct aq_hw_s *aq_hw, + u32 clock_sel, u32 ns, u32 fns) +{ + u32 nsfns =3D (ns & 0xff) | (fns & 0xffffff00); + + aq_hw_write_reg(aq_hw, + HW_ATL2_TSG_REG_ADR(clock_sel, CLOCK_INC_CFG), + nsfns); + aq_hw_write_reg(aq_hw, + HW_ATL2_TSG_REG_ADR(clock_sel, CLOCK_MODIF_CTRL), + HW_ATL2_TSG_LOAD_INC_CFG_MSK); +} + +void hw_atl2_tpb_tps_highest_priority_tc_enable_set(struct aq_hw_s *aq_hw, + u32 tps_highest_prio_tc_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL2_TPB_HIGHEST_PRIO_TC_EN_ADR, + HW_ATL2_TPB_HIGHEST_PRIO_TC_EN_MSK, + HW_ATL2_TPB_HIGHEST_PRIO_TC_EN_SHIFT, + tps_highest_prio_tc_en); +} + +void hw_atl2_tpb_tps_highest_priority_tc_set(struct aq_hw_s *aq_hw, + u32 tps_highest_prio_tc) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL2_TPB_HIGHEST_PRIO_TC_ADR, + HW_ATL2_TPB_HIGHEST_PRIO_TC_MSK, + HW_ATL2_TPB_HIGHEST_PRIO_TC_SHIFT, + tps_highest_prio_tc); +} + +void hw_atl2_tsg_gpio_isr_to_host_set(struct aq_hw_s *aq_hw, + int on, u32 clock_sel) +{ + aq_hw_write_reg_bit(aq_hw, + HW_ATL2_GLOBAL_HIGH_PRIO_INTERRUPT_1_MASK_ADR, + clock_sel =3D=3D 1 ? HW_ATL2_TSG_TSG1_GPIO_INTERRUPT_MSK : + HW_ATL2_TSG_TSG0_GPIO_INTERRUPT_MSK, + clock_sel =3D=3D 1 ? HW_ATL2_TSG_TSG1_GPIO_INTERRUPT_SHIFT : + HW_ATL2_TSG_TSG0_GPIO_INTERRUPT_SHIFT, + !!on); +} + +void hw_atl2_tsg_gpio_clear_status(struct aq_hw_s *aq_hw) +{ + aq_hw_read_reg(aq_hw, HW_ATL2_GLOBAL_INTERNAL_ALARMS_1_ADR); +} + +void hw_atl2_tsg_gpio_input_event_info_get(struct aq_hw_s *aq_hw, + u32 clock_sel, + u32 *event_count, + u64 *event_ts) +{ + if (event_count) + *event_count =3D aq_hw_read_reg(aq_hw, + HW_ATL2_TSG_REG_ADR(clock_sel, + EXT_CLK_COUNT)); + + if (event_ts) + *event_ts =3D aq_hw_read_reg64(aq_hw, + HW_ATL2_TSG_REG_ADR(clock_sel, + GPIO_EVENT_TS_LSW)); +} + +void hw_atl2_tsg_ptp_gpio_gen_pulse(struct aq_hw_s *aq_hw, u32 clk_sel, + u64 ts, u32 period, u32 hightime) +{ + u32 val =3D (HW_ATL2_TSG_GPIO_EVENT_MODE_SET_ON_TIME << + (HW_ATL2_TSG_GPIO_EVENT_MODE_SHIFT - + HW_ATL2_TSG_GPIO_OUTPUT_EN_SHIFT)) | + (HW_ATL2_TSG_GPIO_GEN_OUTPUT_EN_MSK) | + (HW_ATL2_TSG_GPIO_OUTPUT_EN_MSK); + + if (ts !=3D 0) { + aq_hw_write_reg64(aq_hw, + HW_ATL2_TSG_REG_ADR(clk_sel, + GPIO_EVENT_GEN_TS_LSW), + ts); + + aq_hw_write_reg64(aq_hw, + HW_ATL2_TSG_REG_ADR(clk_sel, + GPIO_EVENT_HIGH_TIME_LSW), + hightime); + + aq_hw_write_reg64(aq_hw, + HW_ATL2_TSG_REG_ADR(clk_sel, + GPIO_EVENT_LOW_TIME_LSW), + (period - hightime)); + } + + aq_hw_write_reg_bit(aq_hw, + HW_ATL2_TSG_REG_ADR(clk_sel, GPIO_EVENT_GEN_CFG), + HW_ATL2_TSG_GPIO_EVENT_MODE_MSK | + HW_ATL2_TSG_GPIO_OUTPUT_EN_MSK | + HW_ATL2_TSG_GPIO_GEN_OUTPUT_EN_MSK, + HW_ATL2_TSG_GPIO_OUTPUT_EN_SHIFT, + (!ts ? 0 : val)); +} + +void hw_atl2_rpf_rx_desc_timestamp_req_set(struct aq_hw_s *aq_hw, u32 requ= est, + u32 descriptor) +{ + aq_hw_write_reg_bit(aq_hw, + HW_ATL2_RPF_TIMESTAMP_REQ_DESCD_ADR(descriptor), + HW_ATL2_RPF_TIMESTAMP_REQ_DESCD_MSK, + HW_ATL2_RPF_TIMESTAMP_REQ_DESCD_SHIFT, request); +} + /* TX */ =20 void hw_atl2_tpb_tx_tc_q_rand_map_en_set(struct aq_hw_s *aq_hw, @@ -93,6 +360,30 @@ void hw_atl2_reg_tx_intr_moder_ctrl_set(struct aq_hw_s = *aq_hw, tx_intr_moderation_ctl); } =20 +void hw_atl2_tdm_tx_desc_timestamp_writeback_en_set(struct aq_hw_s *aq_hw, + u32 enable, u32 descriptor) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL2_TDM_DESCD_TS_WRB_EN_ADR(descriptor), + HW_ATL2_TDM_DESCD_TS_WRB_EN_MSK, + HW_ATL2_TDM_DESCD_TS_WRB_EN_SHIFT, enable); +} + +void hw_atl2_tdm_tx_desc_timestamp_en_set(struct aq_hw_s *aq_hw, u32 enabl= e, + u32 descriptor) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL2_TDM_DESCD_TS_EN_ADR(descriptor), + HW_ATL2_TDM_DESCD_TS_EN_MSK, + HW_ATL2_TDM_DESCD_TS_EN_SHIFT, enable); +} + +void hw_atl2_tdm_tx_desc_avb_en_set(struct aq_hw_s *aq_hw, u32 enable, + u32 descriptor) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL2_TDM_DESCD_AVB_EN_ADR(descriptor), + HW_ATL2_TDM_DESCD_AVB_EN_MSK, + HW_ATL2_TDM_DESCD_AVB_EN_SHIFT, enable); +} + void hw_atl2_tps_tx_pkt_shed_data_arb_mode_set(struct aq_hw_s *aq_hw, const u32 data_arb_mode) { @@ -122,6 +413,20 @@ void hw_atl2_tps_tx_pkt_shed_tc_data_weight_set(struct= aq_hw_s *aq_hw, weight); } =20 +void hw_atl2_tdm_tx_data_read_req_limit_set(struct aq_hw_s *aq_hw, u32 lim= it) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL2_TDM_TX_DATA_RD_REQ_LIMIT_ADR, + HW_ATL2_TDM_TX_DATA_RD_REQ_LIMIT_MSK, + HW_ATL2_TDM_TX_DATA_RD_REQ_LIMIT_SHIFT, limit); +} + +void hw_atl2_tdm_tx_desc_read_req_limit_set(struct aq_hw_s *aq_hw, u32 lim= it) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL2_TDM_TX_DESC_RD_REQ_LIMIT_ADR, + HW_ATL2_TDM_TX_DESC_RD_REQ_LIMIT_MSK, + HW_ATL2_TDM_TX_DESC_RD_REQ_LIMIT_SHIFT, limit); +} + u32 hw_atl2_get_hw_version(struct aq_hw_s *aq_hw) { return aq_hw_read_reg(aq_hw, HW_ATL2_FPGA_VER_ADR); @@ -164,6 +469,13 @@ void hw_atl2_rpf_act_rslvr_section_en_set(struct aq_hw= _s *aq_hw, u32 sections) sections); } =20 +u32 hw_atl2_rpf_act_rslvr_section_en_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg_bit(aq_hw, HW_ATL2_RPF_REC_TAB_EN_ADR, + HW_ATL2_RPF_REC_TAB_EN_MSK, + HW_ATL2_RPF_REC_TAB_EN_SHIFT); +} + void hw_atl2_mif_shared_buf_get(struct aq_hw_s *aq_hw, int offset, u32 *da= ta, int len) { @@ -232,3 +544,13 @@ void hw_atl2_mif_host_req_int_clr(struct aq_hw_s *aq_h= w, u32 val) return aq_hw_write_reg(aq_hw, HW_ATL2_MCP_HOST_REQ_INT_CLR_ADR, val); } + +void hw_atl2_gpio_special_mode_set(struct aq_hw_s *aq_hw, + u32 gpio_special_mode, + u32 pin) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL2_GPIO_PIN_SPEC_MODE_ADR(pin), + HW_ATL2_GPIO_PIN_SPEC_MODE_MSK, + HW_ATL2_GPIO_PIN_SPEC_MODE_SHIFT, + gpio_special_mode); +} diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh.h b= /drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh.h index 98c7a4621297..00dcc3e0184f 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh.h +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh.h @@ -10,6 +10,9 @@ =20 struct aq_hw_s; =20 +/* Get Enable usage of extended tags from 32-255. */ +u32 hw_atl2_phi_ext_tag_get(struct aq_hw_s *aq_hw); + /* Set TX Interrupt Moderation Control Register */ void hw_atl2_reg_tx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw, u32 tx_intr_moderation_ctl, @@ -19,7 +22,7 @@ void hw_atl2_reg_tx_intr_moder_ctrl_set(struct aq_hw_s *a= q_hw, void hw_atl2_rpf_redirection_table2_select_set(struct aq_hw_s *aq_hw, u32 select); =20 -/** Set RSS HASH type */ +/* Set RSS HASH type */ void hw_atl2_rpf_rss_hash_type_set(struct aq_hw_s *aq_hw, u32 rss_hash_typ= e); =20 /* set new RPF enable */ @@ -37,14 +40,91 @@ void hw_atl2_new_rpf_rss_redir_set(struct aq_hw_s *aq_h= w, u32 tc, u32 index, =20 /* Set VLAN filter tag */ void hw_atl2_rpf_vlan_flr_tag_set(struct aq_hw_s *aq_hw, u32 tag, u32 filt= er); +/* set ethertype filter tag */ +void hw_atl2_rpf_etht_flr_tag_set(struct aq_hw_s *aq_hw, u32 tag, u32 filt= er); + +/* get ethertype filter tag */ +u32 hw_atl2_rpf_etht_flr_tag_get(struct aq_hw_s *aq_hw, u32 filter); + +/* set L3 v4 dest address */ +void hw_atl2_rpf_l3_v4_dest_addr_set(struct aq_hw_s *aq_hw, + u32 filter, u32 val); + +/* set L3 v4 src address */ +void hw_atl2_rpf_l3_v4_src_addr_set(struct aq_hw_s *aq_hw, u32 filter, u32= val); + +/* set L3 v4 cmd */ +void hw_atl2_rpf_l3_v4_cmd_set(struct aq_hw_s *aq_hw, u32 val, u32 filter); + +/* set L3 v6 cmd */ +void hw_atl2_rpf_l3_v6_cmd_set(struct aq_hw_s *aq_hw, u32 val, u32 filter); + +/* set L3 v6 dest address */ +void hw_atl2_rpf_l3_v6_dest_addr_set(struct aq_hw_s *aq_hw, u8 location, + u32 *ipv6_dst); + +/* set L3 v6 src address */ +void hw_atl2_rpf_l3_v6_src_addr_set(struct aq_hw_s *aq_hw, u8 location, + u32 *ipv6_src); + +/* set L3 v6 v4 select */ +void hw_atl2_rpf_l3_v6_v4_select_set(struct aq_hw_s *aq_hw, u32 val); + +/* set L3 v4 tag */ +void hw_atl2_rpf_l3_v4_tag_set(struct aq_hw_s *aq_hw, u32 val, u32 filter); + +/* set L3 v6 tag */ +void hw_atl2_rpf_l3_v6_tag_set(struct aq_hw_s *aq_hw, u32 val, u32 filter); + +/* set L4 cmd */ +void hw_atl2_rpf_l4_cmd_set(struct aq_hw_s *aq_hw, u32 val, u32 filter); + +/* set L4 tag */ +void hw_atl2_rpf_l4_tag_set(struct aq_hw_s *aq_hw, u32 val, u32 filter); =20 /* set tx random TC-queue mapping enable bit */ void hw_atl2_tpb_tx_tc_q_rand_map_en_set(struct aq_hw_s *aq_hw, const u32 tc_q_rand_map_en); =20 +void hw_atl2_tpb_tps_highest_priority_tc_enable_set(struct aq_hw_s *aq_hw, + u32 tps_highest_prio_tc_en); + +void hw_atl2_tpb_tps_highest_priority_tc_set(struct aq_hw_s *aq_hw, + u32 tps_highest_prio_tc); + /* set tx buffer clock gate enable */ void hw_atl2_tpb_tx_buf_clk_gate_en_set(struct aq_hw_s *aq_hw, u32 clk_gat= e_en); =20 +/* tsg */ + +void hw_atl2_tsg_clock_en(struct aq_hw_s *aq_hw, u32 clock_sel, + u32 clock_enable); + +void hw_atl2_tsg_clock_reset(struct aq_hw_s *aq_hw, u32 clock_sel); +u64 hw_atl2_tsg_clock_read(struct aq_hw_s *aq_hw, u32 clock_sel); +void hw_atl2_tsg_clock_add(struct aq_hw_s *aq_hw, u32 clock_sel, + u64 ns); +void hw_atl2_tsg_clock_sub(struct aq_hw_s *aq_hw, u32 clock_sel, + u64 ns); +void hw_atl2_tsg_clock_increment_set(struct aq_hw_s *aq_hw, u32 clock_sel, + u32 ns, u32 fns); +void hw_atl2_tsg_gpio_isr_to_host_set(struct aq_hw_s *aq_hw, int on, + u32 clock_sel); +void hw_atl2_tsg_gpio_clear_status(struct aq_hw_s *aq_hw); +void hw_atl2_tsg_gpio_input_event_info_get(struct aq_hw_s *aq_hw, + u32 clock_sel, + u32 *event_count, + u64 *event_ts); +/* Set Rx Descriptor0 Timestamp request */ +void hw_atl2_rpf_rx_desc_timestamp_req_set(struct aq_hw_s *aq_hw, u32 requ= est, + u32 descriptor); +/* Set Tx Descriptor Timestamp writeback Enable */ +void hw_atl2_tdm_tx_desc_timestamp_writeback_en_set(struct aq_hw_s *aq_hw, + u32 enable, + u32 descriptor); +/* Set Tx Descriptor Timestamp enable */ +void hw_atl2_tdm_tx_desc_timestamp_en_set(struct aq_hw_s *aq_hw, u32 enabl= e, + u32 descriptor); void hw_atl2_tps_tx_pkt_shed_data_arb_mode_set(struct aq_hw_s *aq_hw, const u32 data_arb_mode); =20 @@ -57,6 +137,15 @@ void hw_atl2_tps_tx_pkt_shed_tc_data_max_credit_set(str= uct aq_hw_s *aq_hw, void hw_atl2_tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw, const u32 tc, const u32 weight); +/* Set Tx Descriptor AVB enable */ +void hw_atl2_tdm_tx_desc_avb_en_set(struct aq_hw_s *aq_hw, u32 enable, + u32 descriptor); +void hw_atl2_tsg_ptp_gpio_gen_pulse(struct aq_hw_s *aq_hw, u32 clk_sel, + u64 ts, u32 period, u32 hightime); + +void hw_atl2_tdm_tx_data_read_req_limit_set(struct aq_hw_s *aq_hw, u32 lim= it); + +void hw_atl2_tdm_tx_desc_read_req_limit_set(struct aq_hw_s *aq_hw, u32 lim= it); =20 u32 hw_atl2_get_hw_version(struct aq_hw_s *aq_hw); =20 @@ -69,6 +158,9 @@ void hw_atl2_rpf_act_rslvr_record_set(struct aq_hw_s *aq= _hw, u8 location, /* set enable action resolver section */ void hw_atl2_rpf_act_rslvr_section_en_set(struct aq_hw_s *aq_hw, u32 secti= ons); =20 +/* get enable action resolver section */ +u32 hw_atl2_rpf_act_rslvr_section_en_get(struct aq_hw_s *aq_hw); + /* get data from firmware shared input buffer */ void hw_atl2_mif_shared_buf_get(struct aq_hw_s *aq_hw, int offset, u32 *da= ta, int len); @@ -99,4 +191,7 @@ u32 hw_atl2_mif_host_req_int_get(struct aq_hw_s *aq_hw); /* clear host interrupt request */ void hw_atl2_mif_host_req_int_clr(struct aq_hw_s *aq_hw, u32 val); =20 +/* Set GPIO Special Mode */ +void hw_atl2_gpio_special_mode_set(struct aq_hw_s *aq_hw, + u32 gpio_special_mode, u32 pin); #endif /* HW_ATL2_LLH_H */ diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh_int= ernal.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh_intern= al.h index e34c5cda061e..9b9be3ef1332 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh_internal.h +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh_internal.h @@ -5,6 +5,11 @@ =20 #ifndef HW_ATL2_LLH_INTERNAL_H #define HW_ATL2_LLH_INTERNAL_H +/* RX timestamp_req_desc{D} [1:0] Bitfield Definitions + */ +#define HW_ATL2_RPF_TIMESTAMP_REQ_DESCD_ADR(descr) (0x00005B08 + (descr) *= 0x20) +#define HW_ATL2_RPF_TIMESTAMP_REQ_DESCD_MSK 0x00030000 +#define HW_ATL2_RPF_TIMESTAMP_REQ_DESCD_SHIFT 16 =20 /* RX pif_rpf_redir_2_en_i Bitfield Definitions * PORT=3D"pif_rpf_redir_2_en_i" @@ -114,7 +119,68 @@ #define HW_ATL2_RPF_VL_TAG_WIDTH 4 /* default value of bitfield vlan_req_tag0{f}[3:0] */ #define HW_ATL2_RPF_VL_TAG_DEFAULT 0x0 - +/* register address for bitfield etype_req_tag0{f}[2:0] */ +#define HW_ATL2_RPF_ET_TAG_ADR(filter) (0x00005340 + (filter) * 0x4) +/* bitmask for bitfield etype_req_tag0{f}[2:0] */ +#define HW_ATL2_RPF_ET_TAG_MSK 0x00000007 +/* lower bit position of bitfield etype_req_tag0{f}[2:0] */ +#define HW_ATL2_RPF_ET_TAG_SHIFT 0 +/* Lower bit position of bitfield l3_l4_act{F}[2:0] */ +#define HW_ATL2_RPF_L3_L4_ACTF_SHIFT 16 +/* Bitmask for bitfield l3_l4_rxq{F}[4:0] */ +#define HW_ATL2_RPF_L3_L4_RXQF_MSK 0x00001F00u +/* Lower bit position of bitfield l3_l4_rxq{F}[4:0] */ +#define HW_ATL2_RPF_L3_L4_RXQF_SHIFT 8 +/* Register address for bitfield rpf_l3_v6_sa{F}_dw{D}[1F:0] */ +#define HW_ATL2_RPF_L3_SA_DW_ADR(filter, dword) \ + (0x00006400u + (filter) * 0x10 + (dword) * 0x4) + +/* Register address for bitfield rpf_l3_v6_da{F}_dw{D}[1F:0] */ +#define HW_ATL2_RPF_L3_DA_DW_ADR(filter, dword) \ + (0x00006480u + (filter) * 0x10 + (dword) * 0x4) + +/* Register address for bitfield rpf_l3_cmd{F}[1F:0] */ +#define HW_ATL2_RPF_L3_V4_CMD_ADR(filter) (0x00006500u + (filter) * 0x4) +/* Bitmask for bitfield rpf_l3_cmd{F}[F:0] */ +#define HW_ATL2_RPF_L3_V4_CMD_MSK 0x0000FFFFu +/* Lower bit position of bitfield rpf_l3_cmd{F}[1F:0] */ +#define HW_ATL2_RPF_L3_V4_CMD_SHIFT 0 +/* Register address for bitfield rpf_l3_v6_cmd{F}[1F:0] */ +#define HW_ATL2_RPF_L3_V6_CMD_ADR(filter) (0x00006500u + (filter) * 0x4) +/* Bitmask for bitfield rpf_l3_v6_cmd{F}[F:0] */ +#define HW_ATL2_RPF_L3_V6_CMD_MSK 0xFF7F0000u +/* Lower bit position of bitfield rpf_l3_v6_cmd{F}[1F:0] */ +#define HW_ATL2_RPF_L3_V6_CMD_SHIFT 0 +/* Register address for bitfield rpf_l3_v6_cmd{F}[F:0] */ +#define HW_ATL2_RPF_L3_V6_V4_SELECT_ADR 0x00006500u +/* Bitmask for bitfield pif_rpf_l3_v6_v4_select*/ +#define HW_ATL2_RPF_L3_V6_V4_SELECT_MSK 0x00800000u +/* Lower bit position of bitfield pif_rpf_l3_v6_v4_select */ +#define HW_ATL2_RPF_L3_V6_V4_SELECT_SHIFT 23 +/* Register address for bitfield rpf_l3_v4_req_tag{F}[2:0] */ +#define HW_ATL2_RPF_L3_V4_TAG_ADR(filter) (0x00006500u + (filter) * 0x4) +/* Bitmask for bitfield rpf_l3_v4_req_tag{F}[2:0] */ +#define HW_ATL2_RPF_L3_V4_TAG_MSK 0x00000070u +/* Lower bit position of bitfield rpf_l3_v4_req_tag{F}[2:0] */ +#define HW_ATL2_RPF_L3_V4_TAG_SHIFT 4 +/* Register address for bitfield rpf_l3_v6_req_tag{F}[2:0] */ +#define HW_ATL2_RPF_L3_V6_TAG_ADR(filter) (0x00006500u + (filter) * 0x4) +/* Bitmask for bitfield rpf_l3_v6_req_tag{F}[2:0] */ +#define HW_ATL2_RPF_L3_V6_TAG_MSK 0x00700000 +/* Lower bit position of bitfield rpf_l3_v6_req_tag{F}[2:0] */ +#define HW_ATL2_RPF_L3_V6_TAG_SHIFT 20 +/* Register address for bitfield rpf_l4_cmd{F}[2:0] */ +#define HW_ATL2_RPF_L4_CMD_ADR(filter) (0x00006520u + (filter) * 0x4) +/* Bitmask for bitfield rpf_l4_cmd{F}[2:0] */ +#define HW_ATL2_RPF_L4_CMD_MSK 0x00000007u +/* Lower bit position of bitfield rpf_l4_cmd{F}[2:0] */ +#define HW_ATL2_RPF_L4_CMD_SHIFT 0 +/* Register address for bitfield rpf_l4_tag{F}[2:0] */ +#define HW_ATL2_RPF_L4_TAG_ADR(filter) (0x00006520u + (filter) * 0x4) +/* Bitmask for bitfield rpf_l4_tag{F}[2:0] */ +#define HW_ATL2_RPF_L4_TAG_MSK 0x00000070u +/* Lower bit position of bitfield rpf_l4_tag{F}[2:0] */ +#define HW_ATL2_RPF_L4_TAG_SHIFT 4 /* RX rx_q{Q}_tc_map[2:0] Bitfield Definitions * Preprocessor definitions for the bitfield "rx_q{Q}_tc_map[2:0]". * Parameter: Queue {Q} | bit-level stride | range [0, 31] @@ -131,7 +197,24 @@ #define HW_ATL2_RX_Q_TC_MAP_WIDTH 3 /* Default value of bitfield rx_q{Q}_tc_map[2:0] */ #define HW_ATL2_RX_Q_TC_MAP_DEFAULT 0x0 - +/* TX desc{D}_ts_wrb_en Bitfield Definitions + */ +#define HW_ATL2_TDM_DESCD_TS_WRB_EN_ADR(descriptor) \ + (0x00007C08 + (descriptor) * 0x40) +#define HW_ATL2_TDM_DESCD_TS_WRB_EN_MSK 0x00040000 +#define HW_ATL2_TDM_DESCD_TS_WRB_EN_SHIFT 18 +/* TX desc{D}_ts_en Bitfield Definitions + */ +#define HW_ATL2_TDM_DESCD_TS_EN_ADR(descriptor) \ + (0x00007C08 + (descriptor) * 0x40) +#define HW_ATL2_TDM_DESCD_TS_EN_MSK 0x00020000 +#define HW_ATL2_TDM_DESCD_TS_EN_SHIFT 17 +/* TX desc{D}_avb_en Bitfield Definitions + */ +#define HW_ATL2_TDM_DESCD_AVB_EN_ADR(descriptor) \ + (0x00007C08 + (descriptor) * 0x40) +#define HW_ATL2_TDM_DESCD_AVB_EN_MSK 0x00010000 +#define HW_ATL2_TDM_DESCD_AVB_EN_SHIFT 16 /* tx tx_tc_q_rand_map_en bitfield definitions * preprocessor definitions for the bitfield "tx_tc_q_rand_map_en". * port=3D"pif_tpb_tx_tc_q_rand_map_en_i" @@ -221,7 +304,18 @@ #define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_WIDTH 16 /* default value of bitfield data_tc{t}_credit_max[f:0] */ #define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_DEFAULT 0x0 - +/* register address for bitfield pif_tpb_highest_prio_tc_en */ +#define HW_ATL2_TPB_HIGHEST_PRIO_TC_EN_ADR 0x00007180 +/* bitmask for bitfield pif_tpb_highest_prio_tc_en */ +#define HW_ATL2_TPB_HIGHEST_PRIO_TC_EN_MSK 0x00000100 +/* lower bit position of bitfield pif_tpb_highest_prio_tc_en */ +#define HW_ATL2_TPB_HIGHEST_PRIO_TC_EN_SHIFT 8 +/* register address for bitfield pif_tpb_highest_prio_tc */ +#define HW_ATL2_TPB_HIGHEST_PRIO_TC_ADR 0x00007180 +/* bitmask for bitfield pif_tpb_highest_prio_tc */ +#define HW_ATL2_TPB_HIGHEST_PRIO_TC_MSK 0x00000007 +/* lower bit position of bitfield pif_tpb_highest_prio_tc */ +#define HW_ATL2_TPB_HIGHEST_PRIO_TC_SHIFT 0 /* tx data_tc{t}_weight[e:0] bitfield definitions * preprocessor definitions for the bitfield "data_tc{t}_weight[e:0]". * parameter: tc {t} | stride size 0x4 | range [0, 7] @@ -248,7 +342,87 @@ */ =20 #define HW_ATL2_TX_INTR_MODERATION_CTL_ADR(queue) (0x00007c28u + (queue) *= 0x40) - +/* TX tx_data_rd_req_limit[7:0] Bitfield Definitions + */ +#define HW_ATL2_TDM_TX_DATA_RD_REQ_LIMIT_ADR 0x00007B04 +#define HW_ATL2_TDM_TX_DATA_RD_REQ_LIMIT_MSK 0x0000FF00 +#define HW_ATL2_TDM_TX_DATA_RD_REQ_LIMIT_SHIFT 8 +/* TX tx_desc_rd_req_limit[4:0] Bitfield Definitions + */ +#define HW_ATL2_TDM_TX_DESC_RD_REQ_LIMIT_ADR 0x00007B04 +#define HW_ATL2_TDM_TX_DESC_RD_REQ_LIMIT_MSK 0x0000001F +#define HW_ATL2_TDM_TX_DESC_RD_REQ_LIMIT_SHIFT 0 +/* register address for bitfield uP Force Interrupt */ +#define HW_ATL2_GLB_CONTROL_2_ADR 0x00000404 +#define HW_ATL2_MIF_INTERRUPT_2_TO_ITR_MSK 0x00000100 +/* lower bit position of bitfield MIF Interrupt to ITR */ +#define HW_ATL2_MIF_INTERRUPT_TO_ITR_SHIFT 6 +#define HW_ATL2_EN_INTERRUPT_MIF2_TO_ITR_MSK 0x00001000 +/* lower bit position of bitfield Enable MIF Interrupt to ITR */ +#define HW_ATL2_EN_INTERRUPT_TO_ITR_SHIFT 0xA +#define HW_ATL2_GLOBAL_INTERNAL_ALARMS_1_ADR 0x00000924 +#define HW_ATL2_GLOBAL_HIGH_PRIO_INTERRUPT_1_MASK_ADR 0x00000964 +/* bitmask for bitfield TSG PTM GPIO interrupt */ +#define HW_ATL2_TSG_TSG1_GPIO_INTERRUPT_MSK 0x00000200 +/* lower bit position of bitfield TSG PTM GPIO interrupt */ +#define HW_ATL2_TSG_TSG1_GPIO_INTERRUPT_SHIFT 9 +/* bitmask for bitfield TSG0 GPIO interrupt */ +#define HW_ATL2_TSG_TSG0_GPIO_INTERRUPT_MSK 0x00000020 +/* lower bit position of bitfield TSG0 GPIO interrupt */ +#define HW_ATL2_TSG_TSG0_GPIO_INTERRUPT_SHIFT 5 +/* TSG registers */ +#define HW_ATL2_TSG_REG_ADR(clk, reg_name) \ + ((clk) =3D=3D 0 ? HW_ATL2_CLK0_##reg_name##_ADR :\ + HW_ATL2_CLK1_##reg_name##_ADR) + +#define HW_ATL2_CLK0_CLOCK_CFG_ADR 0x00000CA0u +#define HW_ATL2_CLK1_CLOCK_CFG_ADR 0x00000D50u +#define HW_ATL2_TSG_SYNC_RESET_MSK 0x00000001 +#define HW_ATL2_TSG_SYNC_RESET_SHIFT 0x00000000 +#define HW_ATL2_TSG_CLOCK_EN_MSK 0x00000002 +#define HW_ATL2_TSG_CLOCK_EN_SHIFT 0x00000001 +#define HW_ATL2_CLK0_CLOCK_MODIF_CTRL_ADR 0x00000CA4u +#define HW_ATL2_CLK1_CLOCK_MODIF_CTRL_ADR 0x00000D54u +#define HW_ATL2_TSG_SUBTRACT_COUNTER_MSK 0x00000002 +#define HW_ATL2_TSG_ADD_COUNTER_MSK 0x00000004 +#define HW_ATL2_TSG_LOAD_INC_CFG_MSK 0x00000008 +#define HW_ATL2_CLK0_CLOCK_MODIF_VAL_LSW_ADR 0x00000CA8u +#define HW_ATL2_CLK1_CLOCK_MODIF_VAL_LSW_ADR 0x00000D58u +#define HW_ATL2_CLK0_CLOCK_INC_CFG_ADR 0x00000CB0u +#define HW_ATL2_CLK1_CLOCK_INC_CFG_ADR 0x00000D60u +#define HW_ATL2_CLK0_READ_CUR_NS_LSW_ADR 0x00000CB8u +#define HW_ATL2_CLK1_READ_CUR_NS_LSW_ADR 0x00000D68u + +#define HW_ATL2_CLK0_GPIO_CFG_ADR 0x00000CC4u +#define HW_ATL2_CLK1_GPIO_CFG_ADR 0x00000D74u +#define HW_ATL2_TSG_GPIO_IN_MONITOR_EN_SHIFT 0x00000000 +#define HW_ATL2_TSG_GPIO_IN_MONITOR_EN_MSK 0x00000001 +#define HW_ATL2_TSG_GPIO_IN_MODE_SHIFT 0x00000001 +#define HW_ATL2_TSG_GPIO_IN_MODE_MSK 0x00000006 +#define HW_ATL2_TSG_GPIO_IN_MODE_POSEDGE 0x00000000 +#define HW_ATL2_CLK0_EXT_CLK_COUNT_ADR 0x00000CCCu +#define HW_ATL2_CLK1_EXT_CLK_COUNT_ADR 0x00000D7Cu +#define HW_ATL2_CLK0_GPIO_EVENT_TS_LSW_ADR 0x00000CD0u +#define HW_ATL2_CLK1_GPIO_EVENT_TS_LSW_ADR 0x00000D80u +#define HW_ATL2_CLK0_GPIO_EVENT_GEN_TS_LSW_ADR 0x00000CE0u +#define HW_ATL2_CLK1_GPIO_EVENT_GEN_TS_LSW_ADR 0x00000D90u +#define HW_ATL2_CLK0_GPIO_EVENT_GEN_CFG_ADR 0x00000CE8u +#define HW_ATL2_CLK1_GPIO_EVENT_GEN_CFG_ADR 0x00000D98u +#define HW_ATL2_TSG_GPIO_OUTPUT_EN_SHIFT 0x00000000 +#define HW_ATL2_TSG_GPIO_OUTPUT_EN_MSK 0x00000001 +#define HW_ATL2_TSG_GPIO_EVENT_MODE_SHIFT 0x00000001 +#define HW_ATL2_TSG_GPIO_EVENT_MODE_MSK 0x00000006 +#define HW_ATL2_TSG_GPIO_EVENT_MODE_SET_ON_TIME 0x00000003 +#define HW_ATL2_TSG_GPIO_GEN_OUTPUT_EN_MSK 0x00000008 +#define HW_ATL2_CLK0_GPIO_EVENT_HIGH_TIME_LSW_ADR 0x00000CF0u +#define HW_ATL2_CLK1_GPIO_EVENT_HIGH_TIME_LSW_ADR 0x00000DA0u +#define HW_ATL2_CLK0_GPIO_EVENT_LOW_TIME_LSW_ADR 0x00000CF8u +#define HW_ATL2_CLK1_GPIO_EVENT_LOW_TIME_LSW_ADR 0x00000DA8u +/* PCIE Extended tag enable Bitfield Definitions + */ +#define HW_ATL2_PHI_EXT_TAG_EN_ADR 0x00001000 +#define HW_ATL2_PHI_EXT_TAG_EN_MSK 0x00000020 +#define HW_ATL2_PHI_EXT_TAG_EN_SHIFT 5 /* Launch time control register */ #define HW_ATL2_LT_CTRL_ADR 0x00007a1c =20 @@ -387,5 +561,25 @@ #define HW_ATL2_MCP_HOST_REQ_INT_ADR 0x00000F00u #define HW_ATL2_MCP_HOST_REQ_INT_SET_ADR 0x00000F04u #define HW_ATL2_MCP_HOST_REQ_INT_CLR_ADR 0x00000F08u - +/* Register address for bitfield PTP EXT GPIO TS SEL */ +#define HW_ATL2_TSG0_EXT_GPIO_TS_INPUT_SEL_ADR 0x00003664 +/* Bitmask for bitfield PTP EXT GPIO TS SEL */ +#define HW_ATL2_TSG0_EXT_GPIO_TS_INPUT_SEL_MSK 0x00001F00 +/* Lower bit position of bitfield PTP EXT GPIO TS SEL */ +#define HW_ATL2_TSG0_EXT_GPIO_TS_INPUT_SEL_SHIFT 8 +/* Register address for bitfield TSG EXT GPIO TS SEL */ +#define HW_ATL2_TSG1_EXT_GPIO_TS_INPUT_SEL_ADR 0x00003660 +/* Bitmask for bitfield TSG EXT GPIO TS SEL */ +#define HW_ATL2_TSG1_EXT_GPIO_TS_INPUT_SEL_MSK 0x00001F00 +/* Lower bit position of bitfield TSG EXT GPIO TS SEL */ +#define HW_ATL2_TSG1_EXT_GPIO_TS_INPUT_SEL_SHIFT 8 +/* Register address for bitfield GPIO{P} Special Mode */ +#define HW_ATL2_GPIO_PIN_SPEC_MODE_ADR(pin) (0x00003698 + (pin) * 0x4) +/* Bitmask for bitfield GPIO{P} Special Mode */ +#define HW_ATL2_GPIO_PIN_SPEC_MODE_MSK 0x0000000C +/* Lower bit position of bitfield GPIO{P} Special Mode */ +#define HW_ATL2_GPIO_PIN_SPEC_MODE_SHIFT 2 +#define HW_ATL2_GPIO_PIN_SPEC_MODE_TSG1_EVENT_OUTPUT 0 +#define HW_ATL2_GPIO_PIN_SPEC_MODE_TSG0_EVENT_OUTPUT 2 +#define HW_ATL2_GPIO_PIN_SPEC_MODE_GPIO 3 #endif /* HW_ATL2_LLH_INTERNAL_H */ --=20 2.43.0 From nobody Mon Jun 8 04:24:32 2026 Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 05DBC3E9299; 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Tue, 02 Jun 2026 06:55:28 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.25; Tue, 2 Jun 2026 06:55:27 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.25 via Frontend Transport; Tue, 2 Jun 2026 06:55:27 -0700 Received: from BG-LT92649.marvell.com (unknown [10.193.71.86]) by maili.marvell.com (Postfix) with ESMTP id 18D733F7062; Tue, 2 Jun 2026 06:55:22 -0700 (PDT) From: To: CC: , , , , , , , , Sukhdeep Singh Subject: [PATCH net-next v4 5/12] net: atlantic: add AQC113 filter data structures and firmware query Date: Tue, 2 Jun 2026 19:24:45 +0530 Message-ID: <20260602135452.516-6-sukhdeeps@marvell.com> X-Mailer: git-send-email 2.52.0.windows.1 In-Reply-To: <20260602135452.516-1-sukhdeeps@marvell.com> References: <20260602135452.516-1-sukhdeeps@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=RMaD2Yi+ c=1 sm=1 tr=0 ts=6a1ee0d0 cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=FelO9ux0wxsA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=EAYMVhzMl8SCOHhVQcBL:22 a=M5GUcnROAAAA:8 a=C_pYv5bCH7riZfDLuocA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjAyMDEzMyBTYWx0ZWRfX4qOGqJrTaNDo ZHz160gQ2UlaZ9r32J32oi6LMVjOSP+towL+qAR79Le2O70DQhoK31pvK+50ZpuaGzSIHCsma7o 0oD6/gHrFE4lNbbN7/40IKpYs6rtv8Owt7/En9pBdBsg9w8eAUB/ATcnlfn2MJcm1Xtj0m1rQIG ln9ttub6ZfP9OeVWrcmjAoKzH0d5mXEXrIFFVhlrUJQTaJvAU7ga2gWlVk6YnKry4jAr+eIWdNK kP+saTTzVW4jN3SSsEFvH5c6DUnmKWLq1YugOltlkLE1YJ/qt8cbYoY6YKA2bJgEcVw1w3+1t1V yES5TGSu8cYd9f6HesZKwORK0kHJIyKSNCixk6SA4FChIF0p6Qtv5EsgZl/KZzk/u7Q4OGbBI3d N4+dwdoVmAAbOp1owf1D7QayAbKAHLtWMtzt2QeZjSFAY3wHgtnNIfIX82i1SOBR8wDoF7s/vHR 5L1yhOk78VNhEGyfotg== X-Proofpoint-ORIG-GUID: PFwUS2k11OwJU93LlcnjGW9P63h7F9vF X-Proofpoint-GUID: PFwUS2k11OwJU93LlcnjGW9P63h7F9vF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-02_02,2026-05-28_03,2025-10-01_01 Content-Type: text/plain; charset="utf-8" From: Sukhdeep Singh Add filter infrastructure for AQC113 hardware: - Define L3 (IPv4/IPv6), L4 (TCP/UDP/SCTP), and combined L3L4 filter structures with reference-counted sharing support. - Define tag policy structure for ethertype filter management. - Add RPF L3/L4 command bit definitions for filter programming. - Add filter count constants for L3L4, L3V4, L4, VLAN, and ethertype. - Extend hw_atl2_priv with filter arrays, base indices, and counts discovered from firmware. Query filter capabilities from firmware shared memory at init time to discover available L2/L3/L4/VLAN/ethertype filter resources and ART (Action Resolver Table) configuration. Add hardware register dump utility for AQC113 debug support. Signed-off-by: Sukhdeep Singh --- .../atlantic/hw_atl2/hw_atl2_internal.h | 63 +++++++++++++++ .../aquantia/atlantic/hw_atl2/hw_atl2_utils.c | 34 ++++++++ .../aquantia/atlantic/hw_atl2/hw_atl2_utils.h | 5 ++ .../atlantic/hw_atl2/hw_atl2_utils_fw.c | 77 +++++++++++++++++++ 4 files changed, 179 insertions(+) diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_interna= l.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_internal.h index 5a89bb8722f9..fc086d84fb91 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_internal.h +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_internal.h @@ -84,6 +84,18 @@ enum HW_ATL2_RPF_ART_INDEX { HW_ATL_VLAN_MAX_FILTERS, }; =20 +#define HW_ATL2_RPF_L3_CMD_EN BIT(0) +#define HW_ATL2_RPF_L3_CMD_SA_EN BIT(1) +#define HW_ATL2_RPF_L3_CMD_DA_EN BIT(2) +#define HW_ATL2_RPF_L3_CMD_PROTO_EN BIT(3) +#define HW_ATL2_RPF_L3_V6_CMD_EN BIT(0x10) +#define HW_ATL2_RPF_L3_V6_CMD_SA_EN BIT(0x11) +#define HW_ATL2_RPF_L3_V6_CMD_DA_EN BIT(0x12) +#define HW_ATL2_RPF_L3_V6_CMD_PROTO_EN BIT(0x13) +#define HW_ATL2_RPF_L4_CMD_EN BIT(0) +#define HW_ATL2_RPF_L4_CMD_DP_EN BIT(1) +#define HW_ATL2_RPF_L4_CMD_SP_EN BIT(2) + #define HW_ATL2_ACTION(ACTION, RSS, INDEX, VALID) \ ((((ACTION) & 0x3U) << 8) | \ (((RSS) & 0x1U) << 7) | \ @@ -94,6 +106,12 @@ enum HW_ATL2_RPF_ART_INDEX { #define HW_ATL2_ACTION_DISABLE HW_ATL2_ACTION(0, 0, 0, 0) #define HW_ATL2_ACTION_ASSIGN_QUEUE(QUEUE) HW_ATL2_ACTION(1, 0, (QUEUE), 1) #define HW_ATL2_ACTION_ASSIGN_TC(TC) HW_ATL2_ACTION(1, 1, (TC), 1) +#define HW_ATL2_RPF_L3L4_FILTERS 8 +#define HW_ATL2_RPF_L3V4_FILTERS 8 +#define HW_ATL2_RPF_L4_FILTERS 8 +#define HW_ATL2_RPF_VLAN_FILTERS 16 +#define HW_ATL2_RPF_ETYPE_FILTERS 16 +#define HW_ATL2_RPF_ETYPE_TAGS 7 =20 enum HW_ATL2_RPF_RSS_HASH_TYPE { HW_ATL2_RPF_RSS_HASH_TYPE_NONE =3D 0, @@ -119,9 +137,54 @@ enum HW_ATL2_RPF_RSS_HASH_TYPE { =20 #define HW_ATL_MCAST_FLT_ANY_TO_HOST 0x00010FFFU =20 +struct hw_atl2_l3_filter { + u8 proto; + u8 usage; + u32 cmd; + u32 srcip[4]; + u32 dstip[4]; +}; + +struct hw_atl2_l4_filter { + u8 usage; + u32 cmd; + u16 sport; + u16 dport; +}; + +struct hw_atl2_l3l4_filter { + s8 l3_index; + s8 l4_index; + u8 ipv6; +}; + +struct hw_atl2_tag_policy { + u16 action; + u16 usage; +}; + struct hw_atl2_priv { + struct hw_atl2_l3_filter l3_v4_filters[HW_ATL2_RPF_L3L4_FILTERS]; + struct hw_atl2_l3_filter l3_v6_filters[HW_ATL2_RPF_L3L4_FILTERS]; + struct hw_atl2_l4_filter l4_filters[HW_ATL2_RPF_L3L4_FILTERS]; + struct hw_atl2_l3l4_filter l3l4_filters[HW_ATL2_RPF_L3L4_FILTERS]; + struct hw_atl2_tag_policy etype_policy[HW_ATL2_RPF_ETYPE_FILTERS]; struct statistics_s last_stats; unsigned int art_base_index; + unsigned int art_count; + unsigned int l2_filters_base_index; + unsigned int l2_filter_count; + unsigned int etype_filter_base_index; + unsigned int etype_filter_count; + unsigned int etype_filter_tag_top; + unsigned int vlan_filter_base_index; + unsigned int vlan_filter_count; + unsigned int l3_v4_filter_base_index; + unsigned int l3_v4_filter_count; + unsigned int l3_v6_filter_base_index; + unsigned int l3_v6_filter_count; + unsigned int l4_filter_base_index; + unsigned int l4_filter_count; }; =20 #endif /* HW_ATL2_INTERNAL_H */ diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils.c= b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils.c index 0fe6257d9c08..ef549e172dd9 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils.c @@ -128,3 +128,37 @@ int hw_atl2_utils_soft_reset(struct aq_hw_s *self) err_exit: return err; } + +static const u32 hw_atl2_utils_hw_mac_regs[] =3D { + 0x00005580U, 0x00005590U, 0x000055B0U, 0x000055B4U, + 0x000055C0U, 0x00005B00U, 0x00005B04U, 0x00005B08U, + 0x00005B0CU, 0x00005B10U, 0x00005B14U, 0x00005B18U, + 0x00005B1CU, 0x00005B20U, 0x00005B24U, 0x00005B28U, + 0x00005B2CU, 0x00005B30U, 0x00005B34U, 0x00005B38U, + 0x00005B3CU, 0x00005B40U, 0x00005B44U, 0x00005B48U, + 0x00005B4CU, 0x00005B50U, 0x00005B54U, 0x00005B58U, + 0x00005B5CU, 0x00005B60U, 0x00005B64U, 0x00005B68U, + 0x00005B6CU, 0x00005B70U, 0x00005B74U, 0x00005B78U, + 0x00005B7CU, 0x00007C00U, 0x00007C04U, 0x00007C08U, + 0x00007C0CU, 0x00007C10U, 0x00007C14U, 0x00007C18U, + 0x00007C1CU, 0x00007C20U, 0x00007C40U, 0x00007C44U, + 0x00007C48U, 0x00007C4CU, 0x00007C50U, 0x00007C54U, + 0x00007C58U, 0x00007C5CU, 0x00007C60U, 0x00007C80U, + 0x00007C84U, 0x00007C88U, 0x00007C8CU, 0x00007C90U, + 0x00007C94U, 0x00007C98U, 0x00007C9CU, 0x00007CA0U, + 0x00007CC0U, 0x00007CC4U, 0x00007CC8U, 0x00007CCCU, + 0x00007CD0U, 0x00007CD4U, 0x00007CD8U, 0x00007CDCU, +}; + +int hw_atl2_utils_hw_get_regs(struct aq_hw_s *self, + const struct aq_hw_caps_s *aq_hw_caps, + u32 *regs_buff) +{ + unsigned int i; + + for (i =3D 0; i < min_t(u32, aq_hw_caps->mac_regs_count, + ARRAY_SIZE(hw_atl2_utils_hw_mac_regs)); i++) + regs_buff[i] =3D aq_hw_read_reg(self, + hw_atl2_utils_hw_mac_regs[i]); + return 0; +} diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils.h= b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils.h index 6bad64c77b87..c84955bc14ae 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils.h +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils.h @@ -626,10 +626,15 @@ int hw_atl2_utils_initfw(struct aq_hw_s *self, const = struct aq_fw_ops **fw_ops); =20 int hw_atl2_utils_soft_reset(struct aq_hw_s *self); =20 +int hw_atl2_utils_hw_get_regs(struct aq_hw_s *self, + const struct aq_hw_caps_s *aq_hw_caps, + u32 *regs_buff); + u32 hw_atl2_utils_get_fw_version(struct aq_hw_s *self); =20 int hw_atl2_utils_get_action_resolve_table_caps(struct aq_hw_s *self, u8 *base_index, u8 *count); +int hw_atl2_utils_get_filter_caps(struct aq_hw_s *self); =20 extern const struct aq_fw_ops aq_a2_fw_ops; =20 diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils_f= w.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils_fw.c index 7370e3f76b62..41b4745cf04f 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils_fw.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils_fw.c @@ -121,6 +121,10 @@ static int aq_a2_fw_init(struct aq_hw_s *self) u32 val; int err; =20 + err =3D hw_atl2_utils_get_filter_caps(self); + if (err) + return err; + hw_atl2_shared_buffer_get(self, link_control, link_control); link_control.mode =3D AQ_HOST_MODE_ACTIVE; hw_atl2_shared_buffer_write(self, link_control, link_control); @@ -606,6 +610,79 @@ u32 hw_atl2_utils_get_fw_version(struct aq_hw_s *self) version.bundle.build; } =20 +int hw_atl2_utils_get_filter_caps(struct aq_hw_s *self) +{ + struct hw_atl2_priv *priv =3D self->priv; + struct filter_caps_s filter_caps; + u32 tag_top; + int err; + u32 min_val; + + err =3D hw_atl2_shared_buffer_read_safe(self, filter_caps, &filter_caps); + if (err) + return err; + + priv->art_base_index =3D filter_caps.rslv_tbl_base_index * 8; + priv->art_count =3D filter_caps.rslv_tbl_count * 8; + if (priv->art_count =3D=3D 0) + priv->art_count =3D 128; + priv->l2_filters_base_index =3D filter_caps.l2_filters_base_index; + priv->l2_filter_count =3D filter_caps.l2_filter_count; + priv->etype_filter_base_index =3D filter_caps.ethertype_filter_base_index; + priv->etype_filter_count =3D filter_caps.ethertype_filter_count; + priv->etype_filter_tag_top =3D + (priv->etype_filter_count >=3D HW_ATL2_RPF_ETYPE_TAGS) ? + (HW_ATL2_RPF_ETYPE_TAGS) : (HW_ATL2_RPF_ETYPE_TAGS >> 1); + priv->vlan_filter_base_index =3D filter_caps.vlan_filter_base_index; + /* 0 - no tag, 1 - reserved for vlan-filter-offload filters */ + tag_top =3D + (filter_caps.vlan_filter_count =3D=3D HW_ATL2_RPF_VLAN_FILTERS) ? + (HW_ATL2_RPF_VLAN_FILTERS - 2) : + (HW_ATL2_RPF_VLAN_FILTERS / 2 - 2); + + if (filter_caps.vlan_filter_count > 2) + priv->vlan_filter_count =3D min_t(u32, + filter_caps.vlan_filter_count - 2, + tag_top); + else + priv->vlan_filter_count =3D 0; + + priv->l3_v4_filter_base_index =3D filter_caps.l3_ip4_filter_base_index; + if (priv->l3_v4_filter_base_index >=3D HW_ATL2_RPF_L3L4_FILTERS) { + priv->l3_v4_filter_base_index =3D 0; + priv->l3_v4_filter_count =3D 0; + } else { + min_val =3D HW_ATL2_RPF_L3L4_FILTERS - 1 - priv->l3_v4_filter_base_index; + priv->l3_v4_filter_count =3D min_t(u32, + filter_caps.l3_ip4_filter_count, + min_val); + } + + priv->l3_v6_filter_base_index =3D filter_caps.l3_ip6_filter_base_index; + if (priv->l3_v6_filter_base_index >=3D HW_ATL2_RPF_L3L4_FILTERS) { + priv->l3_v6_filter_base_index =3D 0; + priv->l3_v6_filter_count =3D 0; + } else { + min_val =3D HW_ATL2_RPF_L3L4_FILTERS - 1 - priv->l3_v6_filter_base_index; + priv->l3_v6_filter_count =3D min_t(u32, + filter_caps.l3_ip6_filter_count, + min_val); + } + + priv->l4_filter_base_index =3D filter_caps.l4_filter_base_index; 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charset="utf-8" From: Sukhdeep Singh Fix initialization issues in hw_atl2 to correctly support AQC113: - hw_atl2_hw_reset: replace unconditional priv memset with selective field clears so that l3l4_filters[].l3_index and l4_index can be initialized to -1 (not allocated) rather than 0; 0 is a valid filter index and would incorrectly appear as an occupied slot after a reset. - hw_atl2_hw_init_new_rx_filters: use firmware-reported ART section base and count (clamped to 16) instead of hardcoded 0xFFFF mask; enable simultaneous IPv4/IPv6 L3 filter mode (rpf_l3_v6_v4_select); tag the UC MAC slot using firmware-supplied l2_filters_base_index instead of hardcoded HW_ATL2_MAC_UC. - hw_atl2_hw_init_rx_path: enable only the firmware-assigned MAC slot (priv->l2_filters_base_index) instead of always slot 0. - Add hw_atl2_hw_mac_addr_set() that programs the MAC address into the firmware-assigned L2 filter slot. Wire into hw_atl2_ops replacing the A1 hw_atl_b0_hw_mac_addr_set; call it from hw_init. - Wire .hw_get_regs into hw_atl2_ops. Signed-off-by: Sukhdeep Singh --- .../aquantia/atlantic/hw_atl2/hw_atl2.c | 69 +++++++++++++++++-- .../atlantic/hw_atl2/hw_atl2_utils_fw.c | 2 + 2 files changed, 65 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.c b/dri= vers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.c index 0ce9caae8799..27a62fffbc29 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.c @@ -11,6 +11,7 @@ #include "hw_atl/hw_atl_utils.h" #include "hw_atl/hw_atl_llh.h" #include "hw_atl/hw_atl_llh_internal.h" +#include "hw_atl2.h" #include "hw_atl2_utils.h" #include "hw_atl2_llh.h" #include "hw_atl2_internal.h" @@ -95,12 +96,21 @@ static int hw_atl2_hw_reset(struct aq_hw_s *self) { struct hw_atl2_priv *priv =3D self->priv; int err; + int i; =20 err =3D hw_atl2_utils_soft_reset(self); if (err) return err; =20 - memset(priv, 0, sizeof(*priv)); + memset(&priv->last_stats, 0, sizeof(priv->last_stats)); + memset(priv->l3_v4_filters, 0, sizeof(priv->l3_v4_filters)); + memset(priv->l3_v6_filters, 0, sizeof(priv->l3_v6_filters)); + memset(priv->l4_filters, 0, sizeof(priv->l4_filters)); + memset(priv->etype_policy, 0, sizeof(priv->etype_policy)); + for (i =3D 0; i < HW_ATL2_RPF_L3L4_FILTERS; i++) { + priv->l3l4_filters[i].l3_index =3D -1; + priv->l3l4_filters[i].l4_index =3D -1; + } =20 self->aq_fw_ops->set_state(self, MPI_RESET); =20 @@ -380,6 +390,9 @@ static void hw_atl2_hw_init_new_rx_filters(struct aq_hw= _s *self) { u8 *prio_tc_map =3D self->aq_nic_cfg->prio_tc_map; struct hw_atl2_priv *priv =3D self->priv; + u32 art_first_sec, art_last_sec; + u32 art_sections; + u32 art_mask; u16 action; u8 index; int i; @@ -394,9 +407,20 @@ static void hw_atl2_hw_init_new_rx_filters(struct aq_h= w_s *self) * REC entry is used for further processing. If multiple entries match, * the lowest REC entry, Action field will be selected. */ - hw_atl2_rpf_act_rslvr_section_en_set(self, 0xFFFF); + art_last_sec =3D min_t(u32, + priv->art_base_index / 8 + priv->art_count / 8, + 16U); + art_first_sec =3D min_t(u32, priv->art_base_index / 8, 16U); + art_mask =3D (BIT(art_last_sec) - 1) - (BIT(art_first_sec) - 1); + if (!art_mask) { + /* ART base index is out of range, enabling all sections */ + art_mask =3D 0xFFFF; + } + art_sections =3D hw_atl2_rpf_act_rslvr_section_en_get(self) | art_mask; + hw_atl2_rpf_act_rslvr_section_en_set(self, art_sections); + hw_atl2_rpf_l3_v6_v4_select_set(self, 1); hw_atl2_rpfl2_uc_flr_tag_set(self, HW_ATL2_RPF_TAG_BASE_UC, - HW_ATL2_MAC_UC); + priv->l2_filters_base_index); hw_atl2_rpfl2_bc_flr_tag_set(self, HW_ATL2_RPF_TAG_BASE_UC); =20 /* FW reserves the beginning of ART, thus all driver entries must @@ -484,6 +508,7 @@ static int hw_atl2_act_rslvr_table_set(struct aq_hw_s *= self, u8 location, static int hw_atl2_hw_init_rx_path(struct aq_hw_s *self) { struct aq_nic_cfg_s *cfg =3D self->aq_nic_cfg; + struct hw_atl2_priv *priv =3D self->priv; int i; =20 /* Rx TC/RSS number config */ @@ -499,7 +524,9 @@ static int hw_atl2_hw_init_rx_path(struct aq_hw_s *self) =20 /* Multicast filters */ for (i =3D HW_ATL2_MAC_MAX; i--;) { - hw_atl_rpfl2_uc_flr_en_set(self, (i =3D=3D 0U) ? 1U : 0U, i); + hw_atl_rpfl2_uc_flr_en_set(self, + (i =3D=3D priv->l2_filters_base_index) ? + 1U : 0U, i); hw_atl_rpfl2unicast_flr_act_set(self, 1U, i); } =20 @@ -530,6 +557,35 @@ static int hw_atl2_hw_init_rx_path(struct aq_hw_s *sel= f) return aq_hw_err_from_flags(self); } =20 +static int hw_atl2_hw_mac_addr_set(struct aq_hw_s *self, const u8 *mac_add= r) +{ + struct hw_atl2_priv *priv =3D self->priv; + u32 location =3D priv->l2_filters_base_index; + unsigned int h; + unsigned int l; + int err; + + if (!mac_addr) { + err =3D -EINVAL; + goto err_exit; + } + h =3D (mac_addr[0] << 8) | (mac_addr[1]); + l =3D (mac_addr[2] << 24) | (mac_addr[3] << 16) | + (mac_addr[4] << 8) | mac_addr[5]; + + hw_atl_rpfl2_uc_flr_en_set(self, 0U, location); + hw_atl_rpfl2unicast_dest_addresslsw_set(self, l, location); + hw_atl_rpfl2unicast_dest_addressmsw_set(self, h, location); + hw_atl_rpfl2unicast_flr_act_set(self, 1U, location); + hw_atl2_rpfl2_uc_flr_tag_set(self, HW_ATL2_RPF_TAG_BASE_UC, location); + hw_atl_rpfl2_uc_flr_en_set(self, 1U, location); + + err =3D aq_hw_err_from_flags(self); + +err_exit: + return err; +} + static int hw_atl2_hw_init(struct aq_hw_s *self, const u8 *mac_addr) { static u32 aq_hw_atl2_igcr_table_[4][2] =3D { @@ -556,7 +612,7 @@ static int hw_atl2_hw_init(struct aq_hw_s *self, const = u8 *mac_addr) hw_atl2_hw_init_tx_path(self); hw_atl2_hw_init_rx_path(self); =20 - hw_atl_b0_hw_mac_addr_set(self, mac_addr); + hw_atl2_hw_mac_addr_set(self, mac_addr); =20 self->aq_fw_ops->set_link_speed(self, aq_nic_cfg->link_speed_msk); self->aq_fw_ops->set_state(self, MPI_INIT); @@ -825,7 +881,7 @@ static int hw_atl2_hw_vlan_ctrl(struct aq_hw_s *self, b= ool enable) const struct aq_hw_ops hw_atl2_ops =3D { .hw_soft_reset =3D hw_atl2_utils_soft_reset, .hw_prepare =3D hw_atl2_utils_initfw, - .hw_set_mac_address =3D hw_atl_b0_hw_mac_addr_set, + .hw_set_mac_address =3D hw_atl2_hw_mac_addr_set, .hw_init =3D hw_atl2_hw_init, .hw_reset =3D hw_atl2_hw_reset, .hw_start =3D hw_atl_b0_hw_start, @@ -855,6 +911,7 @@ const struct aq_hw_ops hw_atl2_ops =3D { .hw_rss_set =3D hw_atl2_hw_rss_set, .hw_rss_hash_set =3D hw_atl_b0_hw_rss_hash_set, .hw_tc_rate_limit_set =3D hw_atl2_hw_init_tx_tc_rate_limit, + .hw_get_regs =3D hw_atl2_utils_hw_get_regs, .hw_get_hw_stats =3D hw_atl2_utils_get_hw_stats, .hw_get_fw_version =3D hw_atl2_utils_get_fw_version, .hw_set_offload =3D hw_atl_b0_hw_offload_set, diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils_f= w.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils_fw.c index 3011c7cd5259..0f603a37218c 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils_fw.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils_fw.c @@ -627,6 +627,8 @@ int hw_atl2_utils_get_filter_caps(struct aq_hw_s *self) if (priv->art_count =3D=3D 0) priv->art_count =3D 128; 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charset="utf-8" From: Sukhdeep Singh Implement complete RX filter management for AQC113 hardware: - Add tag-based filter policy with reference-counted sharing (hw_atl2_filter_tag_get/put), allowing multiple filter rules to share the same L3 or L4 hardware filter when their match criteria are identical. - Implement L3 (IPv4/IPv6 source/destination address and protocol) filter find, get (program HW and increment refcount), and put (decrement refcount and clear HW when last user releases). - Implement L4 (TCP/UDP/SCTP source/destination port) filter management with the same find/get/put pattern. - Add combined L3L4 filter configuration (hw_atl2_new_fl3l4_configure) that translates legacy aq_rx_filter_l3l4 commands into AQC113 separate L3+L4 filter programming with Action Resolver Table (ART) entries. - Add L2 ethertype filter set/clear (hw_atl2_hw_fl2_set/clear) with tag-based ART integration. - Wire .hw_filter_l2_set, .hw_filter_l2_clear, .hw_filter_l3l4_set into hw_atl2_ops. Signed-off-by: Sukhdeep Singh --- .../aquantia/atlantic/hw_atl2/hw_atl2.c | 518 ++++++++++++++++++ 1 file changed, 518 insertions(+) diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.c b/dri= vers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.c index db0035fb04c7..a8ab27367dc1 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.c @@ -87,6 +87,38 @@ const struct aq_hw_caps_s hw_atl2_caps_aqc116c =3D { AQ_NIC_RATE_10M, }; =20 +/* Find tag with the same action or new free tag + * top - top inclusive tag value + * action - action for ActionResolverTable + */ +static int hw_atl2_filter_tag_get(struct hw_atl2_tag_policy *tags, + int top, u16 action) +{ + int i; + + for (i =3D 1; i <=3D top; i++) + if (tags[i].usage > 0 && tags[i].action =3D=3D action) { + tags[i].usage++; + return i; + } + + for (i =3D 1; i <=3D top; i++) + if (tags[i].usage =3D=3D 0) { + tags[i].usage =3D 1; + tags[i].action =3D action; + return i; + } + + return -1; +} + +static void hw_atl2_filter_tag_put(struct hw_atl2_tag_policy *tags, + int tag) +{ + if (tags[tag].usage > 0) + tags[tag].usage--; +} + static u32 hw_atl2_sem_act_rslvr_get(struct aq_hw_s *self) { return hw_atl_reg_glb_cpu_sem_get(self, HW_ATL2_FW_SM_ACT_RSLVR); @@ -819,6 +851,489 @@ static struct aq_stats_s *hw_atl2_utils_get_hw_stats(= struct aq_hw_s *self) return &self->curr_stats; } =20 +static bool hw_atl2_rxf_l3_is_equal(struct hw_atl2_l3_filter *f1, + struct hw_atl2_l3_filter *f2) +{ + if (f1->cmd !=3D f2->cmd) + return false; + + if (f1->cmd & HW_ATL2_RPF_L3_CMD_SA_EN) + if (f1->srcip[0] !=3D f2->srcip[0]) + return false; + + if (f1->cmd & HW_ATL2_RPF_L3_CMD_DA_EN) + if (f1->dstip[0] !=3D f2->dstip[0]) + return false; + + if (f1->cmd & (HW_ATL2_RPF_L3_CMD_PROTO_EN | + HW_ATL2_RPF_L3_V6_CMD_PROTO_EN)) + if (f1->proto !=3D f2->proto) + return false; + + if (f1->cmd & HW_ATL2_RPF_L3_V6_CMD_SA_EN) + if (memcmp(f1->srcip, f2->srcip, 16)) + return false; + + if (f1->cmd & HW_ATL2_RPF_L3_V6_CMD_DA_EN) + if (memcmp(f1->dstip, f2->dstip, 16)) + return false; + + return true; +} + +static int hw_atl2_new_fl3l4_find_l3(struct aq_hw_s *self, + struct hw_atl2_l3_filter *l3) +{ + struct hw_atl2_priv *priv =3D self->priv; + struct hw_atl2_l3_filter *l3_filters; + int i, first, last; + + if (l3->cmd & HW_ATL2_RPF_L3_V6_CMD_EN) { + l3_filters =3D priv->l3_v6_filters; + first =3D priv->l3_v6_filter_base_index; + last =3D priv->l3_v6_filter_base_index + + priv->l3_v6_filter_count; + } else { + l3_filters =3D priv->l3_v4_filters; + first =3D priv->l3_v4_filter_base_index; + last =3D priv->l3_v4_filter_base_index + + priv->l3_v4_filter_count; + } + for (i =3D first; i < last; i++) { + if (hw_atl2_rxf_l3_is_equal(&l3_filters[i], l3)) + return i; + } + + for (i =3D first; i < last; i++) { + u32 l3_enable_mask =3D HW_ATL2_RPF_L3_CMD_EN | + HW_ATL2_RPF_L3_V6_CMD_EN; + + if (!(l3_filters[i].cmd & l3_enable_mask)) + return i; + } + + return -ENOSPC; +} + +static void hw_atl2_rxf_l3_get(struct aq_hw_s *self, + struct hw_atl2_l3_filter *l3, int idx, + const struct hw_atl2_l3_filter *_l3) +{ + int i; + + l3->usage++; + if (l3->usage =3D=3D 1) { + l3->cmd =3D _l3->cmd; + for (i =3D 0; i < 4; i++) { + l3->srcip[i] =3D _l3->srcip[i]; + l3->dstip[i] =3D _l3->dstip[i]; + } + l3->proto =3D _l3->proto; + + if (l3->cmd & HW_ATL2_RPF_L3_CMD_EN) { + hw_atl2_rpf_l3_v4_cmd_set(self, l3->cmd, idx); + hw_atl2_rpf_l3_v4_tag_set(self, idx + 1, idx); + hw_atl2_rpf_l3_v4_dest_addr_set(self, + idx, + l3->dstip[0]); + hw_atl2_rpf_l3_v4_src_addr_set(self, + idx, + l3->srcip[0]); + } else { + hw_atl2_rpf_l3_v6_cmd_set(self, l3->cmd, idx); + hw_atl2_rpf_l3_v6_tag_set(self, idx + 1, idx); + hw_atl2_rpf_l3_v6_dest_addr_set(self, + idx, + l3->dstip); + hw_atl2_rpf_l3_v6_src_addr_set(self, + idx, + l3->srcip); + } + } +} + +static void hw_atl2_rxf_l3_put(struct aq_hw_s *self, + struct hw_atl2_l3_filter *l3, int idx) +{ + if (l3->usage) + l3->usage--; + + if (!l3->usage) { + if (l3->cmd & HW_ATL2_RPF_L3_V6_CMD_EN) + hw_atl2_rpf_l3_v6_cmd_set(self, 0, idx); + else + hw_atl2_rpf_l3_v4_cmd_set(self, 0, idx); + l3->cmd =3D 0; + } +} + +static bool hw_atl2_rxf_l4_is_equal(struct hw_atl2_l4_filter *f1, + struct hw_atl2_l4_filter *f2) +{ + if (f1->cmd !=3D f2->cmd) + return false; + + if (f1->cmd & HW_ATL2_RPF_L4_CMD_SP_EN) + if (f1->sport !=3D f2->sport) + return false; + + if (f1->cmd & HW_ATL2_RPF_L4_CMD_DP_EN) + if (f1->dport !=3D f2->dport) + return false; + + return true; +} + +static int hw_atl2_new_fl3l4_find_l4(struct aq_hw_s *self, + struct hw_atl2_l4_filter *l4) +{ + struct hw_atl2_priv *priv =3D self->priv; + int i, first, last; + + first =3D priv->l4_filter_base_index; + last =3D priv->l4_filter_base_index + priv->l4_filter_count; + + for (i =3D first; i < last; i++) + if (hw_atl2_rxf_l4_is_equal(&priv->l4_filters[i], l4)) + return i; + + for (i =3D first; i < last; i++) + if ((priv->l4_filters[i].cmd & HW_ATL2_RPF_L4_CMD_EN) =3D=3D 0) + return i; + + return -ENOSPC; +} + +static void hw_atl2_rxf_l4_put(struct aq_hw_s *self, + struct hw_atl2_l4_filter *l4, int idx) +{ + if (l4->usage) + l4->usage--; + + if (!l4->usage) { + l4->cmd =3D 0; + hw_atl2_rpf_l4_cmd_set(self, l4->cmd, idx); + } +} + +static void hw_atl2_rxf_l4_get(struct aq_hw_s *self, + struct hw_atl2_l4_filter *l4, int idx, + const struct hw_atl2_l4_filter *_l4) +{ + l4->usage++; + if (l4->usage =3D=3D 1) { + l4->cmd =3D _l4->cmd; + l4->sport =3D _l4->sport; + l4->dport =3D _l4->dport; + + hw_atl2_rpf_l4_cmd_set(self, l4->cmd, idx); + hw_atl2_rpf_l4_tag_set(self, idx + 1, idx); + hw_atl_rpf_l4_spd_set(self, l4->sport, idx); + hw_atl_rpf_l4_dpd_set(self, l4->dport, idx); + } +} + +static int hw_atl2_new_fl3l4_configure(struct aq_hw_s *self, + struct aq_rx_filter_l3l4 *data) +{ + struct hw_atl2_priv *priv =3D self->priv; + s8 old_l3_index =3D priv->l3l4_filters[data->location].l3_index; + s8 old_l4_index =3D priv->l3l4_filters[data->location].l4_index; + u8 old_ipv6 =3D priv->l3l4_filters[data->location].ipv6; + struct hw_atl2_l3_filter *l3_filters; + struct hw_atl2_l3_filter l3; + struct hw_atl2_l4_filter l4; + s8 l3_idx =3D -1; + s8 l4_idx =3D -1; + + if (!(data->cmd & HW_ATL_RX_ENABLE_FLTR_L3L4)) + return 0; + + memset(&l3, 0, sizeof(l3)); + memset(&l4, 0, sizeof(l4)); + + /* convert legacy filter to new */ + if (data->cmd & HW_ATL_RX_ENABLE_CMP_PROT_L4) { + l3.cmd |=3D data->is_ipv6 ? HW_ATL2_RPF_L3_V6_CMD_PROTO_EN : + HW_ATL2_RPF_L3_CMD_PROTO_EN; + l3.cmd |=3D data->is_ipv6 ? HW_ATL2_RPF_L3_V6_CMD_EN : + HW_ATL2_RPF_L3_CMD_EN; + switch (data->cmd & 0x7) { + case HW_ATL_RX_TCP: + l3.cmd |=3D IPPROTO_TCP << (data->is_ipv6 ? 0x18 : 8); + break; + case HW_ATL_RX_UDP: + l3.cmd |=3D IPPROTO_UDP << (data->is_ipv6 ? 0x18 : 8); + break; + case HW_ATL_RX_SCTP: + l3.cmd |=3D IPPROTO_SCTP << (data->is_ipv6 ? 0x18 : 8); + break; + case HW_ATL_RX_ICMP: + l3.cmd |=3D IPPROTO_ICMP << (data->is_ipv6 ? 0x18 : 8); + break; + } + } + + if (data->cmd & HW_ATL_RX_ENABLE_CMP_SRC_ADDR_L3) { + if (data->is_ipv6) { + l3.cmd |=3D HW_ATL2_RPF_L3_V6_CMD_SA_EN | + HW_ATL2_RPF_L3_V6_CMD_EN; + memcpy(l3.srcip, data->ip_src, sizeof(l3.srcip)); + } else { + l3.cmd |=3D HW_ATL2_RPF_L3_CMD_SA_EN | + HW_ATL2_RPF_L3_CMD_EN; + l3.srcip[0] =3D data->ip_src[0]; + } + } + if (data->cmd & HW_ATL_RX_ENABLE_CMP_DEST_ADDR_L3) { + if (data->is_ipv6) { + l3.cmd |=3D HW_ATL2_RPF_L3_V6_CMD_DA_EN | + HW_ATL2_RPF_L3_V6_CMD_EN; + memcpy(l3.dstip, data->ip_dst, sizeof(l3.dstip)); + } else { + l3.cmd |=3D HW_ATL2_RPF_L3_CMD_DA_EN | + HW_ATL2_RPF_L3_CMD_EN; + l3.dstip[0] =3D data->ip_dst[0]; + } + } + + if (data->cmd & HW_ATL_RX_ENABLE_CMP_DEST_PORT_L4) { + l4.cmd |=3D HW_ATL2_RPF_L4_CMD_DP_EN | HW_ATL2_RPF_L4_CMD_EN; + l4.dport =3D data->p_dst; + } + if (data->cmd & HW_ATL_RX_ENABLE_CMP_SRC_PORT_L4) { + l4.cmd |=3D HW_ATL2_RPF_L4_CMD_SP_EN | HW_ATL2_RPF_L4_CMD_EN; + l4.sport =3D data->p_src; + } + + /* find L3 and L4 filters */ + if (l3.cmd & (HW_ATL2_RPF_L3_CMD_EN | HW_ATL2_RPF_L3_V6_CMD_EN)) { + l3_idx =3D hw_atl2_new_fl3l4_find_l3(self, &l3); + if (l3_idx < 0) + return l3_idx; + + if (l3.cmd & HW_ATL2_RPF_L3_V6_CMD_EN) + l3_filters =3D priv->l3_v6_filters; + else + l3_filters =3D priv->l3_v4_filters; + + if (priv->l3l4_filters[data->location].l3_index !=3D l3_idx || + old_ipv6 !=3D !!(l3.cmd & HW_ATL2_RPF_L3_V6_CMD_EN)) + hw_atl2_rxf_l3_get(self, &l3_filters[l3_idx], + l3_idx, &l3); + } + + if (old_l3_index !=3D -1) { + if (old_ipv6) + l3_filters =3D priv->l3_v6_filters; + else + l3_filters =3D priv->l3_v4_filters; + + if (!(hw_atl2_rxf_l3_is_equal(&l3, + &l3_filters[old_l3_index]))) { + hw_atl2_rxf_l3_put(self, + &l3_filters[old_l3_index], + old_l3_index); + } + } + if (l3.cmd & HW_ATL2_RPF_L3_V6_CMD_EN) + priv->l3l4_filters[data->location].ipv6 =3D 1; + else + priv->l3l4_filters[data->location].ipv6 =3D 0; + priv->l3l4_filters[data->location].l3_index =3D l3_idx; + + if (l4.cmd & HW_ATL2_RPF_L4_CMD_EN) { + l4_idx =3D hw_atl2_new_fl3l4_find_l4(self, &l4); + if (l4_idx < 0) + return -EINVAL; + + if (priv->l3l4_filters[data->location].l4_index !=3D l4_idx) + hw_atl2_rxf_l4_get(self, &priv->l4_filters[l4_idx], + l4_idx, &l4); + } + + if (old_l4_index !=3D -1) { + if (!(hw_atl2_rxf_l4_is_equal(&priv->l4_filters[old_l4_index], + &l4))) { + hw_atl2_rxf_l4_put(self, + &priv->l4_filters[old_l4_index], + old_l4_index); + } + } + priv->l3l4_filters[data->location].l4_index =3D l4_idx; + + return 0; +} + +static int hw_atl2_hw_fl3l4_set(struct aq_hw_s *self, + struct aq_rx_filter_l3l4 *data) +{ + struct hw_atl2_priv *priv =3D self->priv; + struct hw_atl2_l3_filter *l3_filters; + struct hw_atl2_l3_filter *l3 =3D NULL; + struct hw_atl2_l4_filter *l4 =3D NULL; + u8 location =3D data->location; + u32 req_tag =3D 0; + u16 action =3D 0; + int l3_index; + int l4_index; + u32 mask =3D 0; + u8 index; + u8 ipv6; + int res; + + res =3D hw_atl2_new_fl3l4_configure(self, data); + if (res) + return res; + + l3_index =3D priv->l3l4_filters[location].l3_index; + l4_index =3D priv->l3l4_filters[location].l4_index; + ipv6 =3D priv->l3l4_filters[location].ipv6; + if (ipv6) + l3_filters =3D priv->l3_v6_filters; + else + l3_filters =3D priv->l3_v4_filters; + + if (!(data->cmd & HW_ATL_RX_ENABLE_FLTR_L3L4)) { + if (l3_index > -1) + hw_atl2_rxf_l3_put(self, &l3_filters[l3_index], + l3_index); + + if (l4_index > -1) + hw_atl2_rxf_l4_put(self, &priv->l4_filters[l4_index], + l4_index); + + priv->l3l4_filters[location].l3_index =3D -1; + priv->l3l4_filters[location].l4_index =3D -1; + index =3D priv->art_base_index + HW_ATL2_RPF_L3L4_USER_INDEX + + location; + hw_atl2_act_rslvr_table_set(self, index, 0, 0, + HW_ATL2_ACTION_DISABLE); + + return 0; + } + + if (l3_index !=3D -1) + l3 =3D &l3_filters[l3_index]; + if (l4_index !=3D -1) + l4 =3D &priv->l4_filters[l4_index]; + + if (l4 && (l4->cmd & HW_ATL2_RPF_L4_CMD_EN)) { + req_tag |=3D (l4_index + 1) << HW_ATL2_RPF_TAG_L4_OFFSET; + mask |=3D HW_ATL2_RPF_TAG_L4_MASK; + } + + if (l3) { + if (l3->cmd & HW_ATL2_RPF_L3_V6_CMD_EN) { + req_tag |=3D (l3_index + 1) << + HW_ATL2_RPF_TAG_L3_V6_OFFSET; + mask |=3D HW_ATL2_RPF_TAG_L3_V6_MASK; + } else { + req_tag |=3D (l3_index + 1) << + HW_ATL2_RPF_TAG_L3_V4_OFFSET; + mask |=3D HW_ATL2_RPF_TAG_L3_V4_MASK; + } + } + + if (data->cmd & (HW_ATL_RX_HOST << HW_ATL2_RPF_L3_L4_ACTF_SHIFT)) + action =3D HW_ATL2_ACTION_ASSIGN_QUEUE((data->cmd & + HW_ATL2_RPF_L3_L4_RXQF_MSK) >> + HW_ATL2_RPF_L3_L4_RXQF_SHIFT); + else + action =3D HW_ATL2_ACTION_DROP; + + index =3D priv->art_base_index + HW_ATL2_RPF_L3L4_USER_INDEX + location; + hw_atl2_act_rslvr_table_set(self, index, req_tag, mask, action); + return 0; +} + +static int hw_atl2_hw_fl2_set(struct aq_hw_s *self, + struct aq_rx_filter_l2 *data) +{ + struct hw_atl2_priv *priv =3D self->priv; + u32 mask =3D HW_ATL2_RPF_TAG_ET_MASK; + u32 req_tag =3D 0; + u16 action =3D 0; + u32 location; + u8 index; + int tag; + + location =3D priv->etype_filter_base_index + data->location; + + hw_atl_rpf_etht_flr_set(self, data->ethertype, location); + hw_atl_rpf_etht_user_priority_en_set(self, + !!data->user_priority_en, + location); + if (data->user_priority_en) { + hw_atl_rpf_etht_user_priority_set(self, + data->user_priority, + location); + req_tag |=3D data->user_priority << HW_ATL2_RPF_TAG_PCP_OFFSET; + mask |=3D HW_ATL2_RPF_TAG_PCP_MASK; + } + + if (data->queue < 0) { + hw_atl_rpf_etht_flr_act_set(self, 0U, location); + hw_atl_rpf_etht_rx_queue_en_set(self, 0U, location); + action =3D HW_ATL2_ACTION_DROP; + } else { + hw_atl_rpf_etht_flr_act_set(self, 1U, location); + hw_atl_rpf_etht_rx_queue_en_set(self, 1U, location); + hw_atl_rpf_etht_rx_queue_set(self, data->queue, location); + action =3D HW_ATL2_ACTION_ASSIGN_QUEUE(data->queue); + } + + tag =3D hw_atl2_filter_tag_get(priv->etype_policy, + priv->etype_filter_tag_top, + action); + + if (tag < 0) + return -ENOSPC; + + req_tag |=3D tag << HW_ATL2_RPF_TAG_ET_OFFSET; + hw_atl2_rpf_etht_flr_tag_set(self, tag, location); + index =3D priv->art_base_index + HW_ATL2_RPF_ET_PCP_USER_INDEX + + data->location; + hw_atl2_act_rslvr_table_set(self, index, req_tag, mask, action); + + hw_atl_rpf_etht_flr_en_set(self, 1U, location); + + return aq_hw_err_from_flags(self); +} + +static int hw_atl2_hw_fl2_clear(struct aq_hw_s *self, + struct aq_rx_filter_l2 *data) +{ + struct hw_atl2_priv *priv =3D self->priv; + u32 location; + u8 index; + u32 tag; + + location =3D priv->etype_filter_base_index + data->location; + hw_atl_rpf_etht_flr_en_set(self, 0U, location); + hw_atl_rpf_etht_flr_set(self, 0U, location); + hw_atl_rpf_etht_user_priority_en_set(self, 0U, location); + + index =3D priv->art_base_index + HW_ATL2_RPF_ET_PCP_USER_INDEX + + data->location; + hw_atl2_act_rslvr_table_set(self, index, 0, 0, + HW_ATL2_ACTION_DISABLE); + tag =3D hw_atl2_rpf_etht_flr_tag_get(self, location); + hw_atl2_filter_tag_put(priv->etype_policy, tag); + + return aq_hw_err_from_flags(self); +} + +/* + * Set VLAN filter table + * Configure VLAN filter table to accept (and assign the queue) traffic + * for the particular vlan ids. + * Note: use this function under vlan promisc mode not to lost the traffic + * + * param - aq_hw_s + * param - aq_rx_filter_vlan VLAN filter configuration + * return 0 - OK, <0 - error + */ static int hw_atl2_hw_vlan_set(struct aq_hw_s *self, struct aq_rx_filter_vlan *aq_vlans) { @@ -900,6 +1415,9 @@ const struct aq_hw_ops hw_atl2_ops =3D { .hw_ring_rx_init =3D hw_atl2_hw_ring_rx_init, .hw_ring_tx_init =3D hw_atl2_hw_ring_tx_init, .hw_packet_filter_set =3D hw_atl2_hw_packet_filter_set, + .hw_filter_l2_set =3D hw_atl2_hw_fl2_set, + .hw_filter_l2_clear =3D hw_atl2_hw_fl2_clear, + .hw_filter_l3l4_set =3D hw_atl2_hw_fl3l4_set, .hw_filter_vlan_set =3D hw_atl2_hw_vlan_set, .hw_filter_vlan_ctrl =3D hw_atl2_hw_vlan_ctrl, .hw_multicast_list_set =3D hw_atl2_hw_multicast_list_set, --=20 2.43.0 From nobody Mon Jun 8 04:24:32 2026 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 00DC52EAB82; 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Tue, 02 Jun 2026 06:55:43 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.25; Tue, 2 Jun 2026 06:55:42 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.25 via Frontend Transport; Tue, 2 Jun 2026 06:55:42 -0700 Received: from BG-LT92649.marvell.com (unknown [10.193.71.86]) by maili.marvell.com (Postfix) with ESMTP id 29F773F7062; Tue, 2 Jun 2026 06:55:37 -0700 (PDT) From: To: CC: , , , , , , , , Sukhdeep Singh Subject: [PATCH net-next v4 8/12] net: atlantic: add AQC113 PTP traffic class and TX path setup Date: Tue, 2 Jun 2026 19:24:48 +0530 Message-ID: <20260602135452.516-9-sukhdeeps@marvell.com> X-Mailer: git-send-email 2.52.0.windows.1 In-Reply-To: <20260602135452.516-1-sukhdeeps@marvell.com> References: <20260602135452.516-1-sukhdeeps@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjAyMDEzMyBTYWx0ZWRfX9Dx2meKTkk8r b/H9WmhcXRER3gpKhpt202PYuBAKEAqXbNgDEdHKNQXWgTqQoKNhdpp5tkEv8vftyu+h2P7hVZI xi6jl3raQVvzw7YkaIx1N7G/lc9ITnNfmyWJWyWxoOaFZFAjmf5EP89lN2jKTnSNxL6BH2zRPGm icNkaR0GY18XOlhk1UwAYmHEnwNR1UBR/N9kKrZBGdSxB36k6XweKXam2mugPsasiOidfHrF3HI cQ2zPYOHsWtSY8PJ9si5iaQGpf1hn0E5AymjZw1l87POYv3fENCr8gKEPjeUJrNSqxjwfufBWFs apIoW3oi98HEt4zquEIUBDa+zXql4JB/zP8vDQMJe1IALPgJqRvCmur2VrUvAboAMbIMT0V745H QJcKIr+53HjIgCwWCRLsaq7+5S8Wbog8VVnx8kEWwp9Qw+1+Qh6W2hjxiXpJQK8YZskhzMNkJ4l H5lUssF/Tm/3dA1Of+Q== X-Authority-Analysis: v=2.4 cv=cLjQdFeN c=1 sm=1 tr=0 ts=6a1ee0df cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=FelO9ux0wxsA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=QXcCYyLzdtTjyudCfB6f:22 a=M5GUcnROAAAA:8 a=Dpi8SI6RF_br7PiJ-gsA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-ORIG-GUID: rt8vqipLe_IDOGu1j-2IZSVci2bxZwad X-Proofpoint-GUID: rt8vqipLe_IDOGu1j-2IZSVci2bxZwad X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-02_02,2026-05-28_03,2025-10-01_01 Content-Type: text/plain; charset="utf-8" From: Sukhdeep Singh Add PTP traffic class (TC) buffer reservation and TX path improvements for AQC113: - Reserve dedicated TX and RX buffer space for PTP TC when PTP is enabled, reducing user TC buffers accordingly (TX: 8KB, RX: 16KB). - Configure PTP TC with no flow control and highest priority scheduling to ensure timely PTP packet transmission. TX path improvements: - Increase TX data and descriptor read-request limits when firmware has already enabled extended PCIe tag mode. Also simplify RSS queue calculation in hw_atl2_hw_rss_set() by extracting to a local variable and use unsigned types for loop variables to match their usage. Signed-off-by: Sukhdeep Singh --- .../aquantia/atlantic/hw_atl2/hw_atl2.c | 49 ++++++++++++++++--- .../atlantic/hw_atl2/hw_atl2_internal.h | 4 +- 2 files changed, 46 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.c b/dri= vers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.c index a8ab27367dc1..39d84576ca51 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.c @@ -151,6 +151,24 @@ static int hw_atl2_hw_reset(struct aq_hw_s *self) return err; } =20 +static int hw_atl2_tc_ptp_set(struct aq_hw_s *self) +{ + /* Init TC2 for PTP_TX */ + hw_atl_tpb_tx_pkt_buff_size_per_tc_set(self, HW_ATL2_PTP_TXBUF_SIZE, + AQ_HW_PTP_TC); + + /* Init TC2 for PTP_RX */ + hw_atl_rpb_rx_pkt_buff_size_per_tc_set(self, HW_ATL2_PTP_RXBUF_SIZE, + AQ_HW_PTP_TC); + + /* No flow control for PTP */ + hw_atl_rpb_rx_xoff_en_per_tc_set(self, 0U, AQ_HW_PTP_TC); + + hw_atl2_tpb_tps_highest_priority_tc_set(self, AQ_HW_PTP_TC); + + return aq_hw_err_from_flags(self); +} + static int hw_atl2_hw_queue_to_tc_map_set(struct aq_hw_s *self) { struct aq_nic_cfg_s *cfg =3D self->aq_nic_cfg; @@ -209,6 +227,11 @@ static int hw_atl2_hw_qos_set(struct aq_hw_s *self) unsigned int prio =3D 0U; u32 tc =3D 0U; =20 + if (cfg->is_ptp) { + tx_buff_size -=3D HW_ATL2_PTP_TXBUF_SIZE; + rx_buff_size -=3D HW_ATL2_PTP_RXBUF_SIZE; + } + /* TPS Descriptor rate init */ hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U); hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(self, 0xA); @@ -242,6 +265,9 @@ static int hw_atl2_hw_qos_set(struct aq_hw_s *self) hw_atl_b0_set_fc(self, self->aq_nic_cfg->fc.req, tc); } =20 + if (cfg->is_ptp) + hw_atl2_tc_ptp_set(self); + /* QoS 802.1p priority -> TC mapping */ for (prio =3D 0; prio < 8; ++prio) hw_atl_rpf_rpb_user_priority_tc_map_set(self, prio, @@ -259,8 +285,9 @@ static int hw_atl2_hw_rss_set(struct aq_hw_s *self, u8 *indirection_table =3D rss_params->indirection_table; const u32 num_tcs =3D aq_hw_num_tcs(self); u32 rpf_redir2_enable; - int tc; - int i; + u32 queue; + u32 tc; + u32 i; =20 rpf_redir2_enable =3D num_tcs > 4 ? 1 : 0; =20 @@ -268,10 +295,9 @@ static int hw_atl2_hw_rss_set(struct aq_hw_s *self, =20 for (i =3D HW_ATL2_RSS_REDIRECTION_MAX; i--;) { for (tc =3D 0; tc !=3D num_tcs; tc++) { - hw_atl2_new_rpf_rss_redir_set(self, tc, i, - tc * - aq_hw_q_per_tc(self) + - indirection_table[i]); + queue =3D tc * aq_hw_q_per_tc(self) + + indirection_table[i]; + hw_atl2_new_rpf_rss_redir_set(self, tc, i, queue); } } =20 @@ -415,9 +441,20 @@ static int hw_atl2_hw_init_tx_path(struct aq_hw_s *sel= f) =20 hw_atl2_tpb_tx_buf_clk_gate_en_set(self, 0U); =20 + if (hw_atl2_phi_ext_tag_get(self)) { + hw_atl2_tdm_tx_data_read_req_limit_set(self, 0x7F); + hw_atl2_tdm_tx_desc_read_req_limit_set(self, 0x0F); + } + return aq_hw_err_from_flags(self); } =20 +/* Initialise new rx filters + * L2 promisc OFF + * VLAN promisc OFF + * + * User priority to TC + */ static void hw_atl2_hw_init_new_rx_filters(struct aq_hw_s *self) { u8 *prio_tc_map =3D self->aq_nic_cfg->prio_tc_map; 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charset="utf-8" From: Sukhdeep Singh Extend the aq_hw_ops interface with new function pointers required for PTP support on AQC113: - enable_ptp: enable/disable PTP counter with clock selection - hw_ring_tx_ptp_get_ts: read TX timestamp from descriptor writeback - hw_tx_ptp_ring_init/hw_rx_ptp_ring_init: per-ring PTP initialization - hw_get_clk_sel: query active TSG clock selection Update existing hw_ops signatures to support AQC113 dual-clock architecture: - hw_gpio_pulse: add clk_sel and hightime parameters - hw_extts_gpio_enable: add channel parameter Add PTP-related hardware defines: - AQ_HW_TXD_CTL_TS_EN/TS_TSG0 for TX descriptor timestamp control - AQ2_HW_PTP_COUNTER_HZ for AQC113 TSG clock frequency - AQ_HW_PTP_IRQS for PTP interrupt vector accounting - PTP enable flags (L2/L4) and TSG clock selection constants Add request_ts and clk_sel bitfields to aq_ring_buff_s for per-packet TX timestamp request tracking. Update hw_atl_b0.c (AQC107) implementations: - Adapt gpio_pulse and extts_gpio_enable to new signatures - Add TX descriptor timestamp bits for AQC113 when ANTIGUA chip feature is detected Signed-off-by: Sukhdeep Singh --- .../net/ethernet/aquantia/atlantic/aq_hw.h | 34 +++++++++++++++++-- .../net/ethernet/aquantia/atlantic/aq_ptp.c | 4 +-- .../net/ethernet/aquantia/atlantic/aq_ring.h | 4 ++- .../aquantia/atlantic/hw_atl/hw_atl_b0.c | 15 ++++++-- 4 files changed, 48 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_hw.h b/drivers/net/e= thernet/aquantia/atlantic/aq_hw.h index 57ea59026a2c..0ba29b8f95ab 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_hw.h +++ b/drivers/net/ethernet/aquantia/atlantic/aq_hw.h @@ -19,6 +19,9 @@ #define AQ_HW_MAC_COUNTER_HZ 312500000ll #define AQ_HW_PHY_COUNTER_HZ 160000000ll =20 +#define AQ_HW_TXD_CTL_TS_EN 0x40000000U +#define AQ_HW_TXD_CTL_TS_TSG0 0x80000000U + enum aq_tc_mode { AQ_TC_MODE_INVALID =3D -1, AQ_TC_MODE_8TCS, @@ -38,6 +41,8 @@ enum aq_tc_mode { =20 #define AQ_FRAC_PER_NS 0x100000000LL =20 +#define AQ2_HW_PTP_COUNTER_HZ 156250000ll + /* Used for rate to Mbps conversion */ #define AQ_MBPS_DIVISOR 125000 /* 1000000 / 8 */ =20 @@ -109,6 +114,7 @@ struct aq_stats_s { #define AQ_HW_IRQ_MSIX 3U =20 #define AQ_HW_SERVICE_IRQS 1U +#define AQ_HW_PTP_IRQS 1U =20 #define AQ_HW_POWER_STATE_D0 0U #define AQ_HW_POWER_STATE_D3 3U @@ -157,6 +163,15 @@ enum aq_priv_flags { AQ_HW_LOOPBACK_PHYEXT_SYS, }; =20 +enum { + AQ_HW_PTP_DISABLE =3D 0, + AQ_HW_PTP_L2_ENABLE =3D BIT(1), + AQ_HW_PTP_L4_ENABLE =3D BIT(2), +}; + +#define ATL_TSG_CLOCK_SEL_0 0 +#define ATL_TSG_CLOCK_SEL_1 1 + #define AQ_HW_LOOPBACK_MASK (BIT(AQ_HW_LOOPBACK_DMA_SYS) |\ BIT(AQ_HW_LOOPBACK_PKT_SYS) |\ BIT(AQ_HW_LOOPBACK_DMA_NET) |\ @@ -198,6 +213,7 @@ struct aq_hw_s { u32 rpc_tid; struct hw_atl_utils_fw_rpc rpc; s64 ptp_clk_offset; + s8 clk_select; u16 phy_id; void *priv; }; @@ -323,11 +339,15 @@ struct aq_hw_ops { =20 int (*hw_ts_to_sys_clock)(struct aq_hw_s *self, u64 ts, u64 *time); =20 - int (*hw_gpio_pulse)(struct aq_hw_s *self, u32 index, u64 start, - u32 period); + int (*hw_gpio_pulse)(struct aq_hw_s *self, u32 index, + u32 clk_sel, u64 start, + u32 period, u32 hightime); =20 int (*hw_extts_gpio_enable)(struct aq_hw_s *self, u32 index, - u32 enable); + u32 channel, int enable); + + void (*enable_ptp)(struct aq_hw_s *self, unsigned int param, + int enable); =20 int (*hw_get_sync_ts)(struct aq_hw_s *self, u64 *ts); =20 @@ -337,6 +357,14 @@ struct aq_hw_ops { int (*extract_hwts)(struct aq_hw_s *self, u8 *p, unsigned int len, u64 *timestamp); =20 + u64 (*hw_ring_tx_ptp_get_ts)(struct aq_ring_s *ring); + + int (*hw_tx_ptp_ring_init)(struct aq_hw_s *self, + struct aq_ring_s *aq_ring); + int (*hw_rx_ptp_ring_init)(struct aq_hw_s *self, + struct aq_ring_s *aq_ring); + u32 (*hw_get_clk_sel)(struct aq_hw_s *self); + int (*hw_set_fc)(struct aq_hw_s *self, u32 fc, u32 tc); =20 int (*hw_set_loopback)(struct aq_hw_s *self, u32 mode, bool enable); diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_ptp.c b/drivers/net/= ethernet/aquantia/atlantic/aq_ptp.c index 9df8918216f6..7486a28d7ff8 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_ptp.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_ptp.c @@ -380,7 +380,7 @@ static int aq_ptp_hw_pin_conf(struct aq_nic_s *aq_nic, = u32 pin_index, u64 start, */ mutex_lock(&aq_nic->fwreq_mutex); aq_nic->aq_hw_ops->hw_gpio_pulse(aq_nic->aq_hw, pin_index, - start, (u32)period); + 0, start, (u32)period, 0); mutex_unlock(&aq_nic->fwreq_mutex); =20 return 0; @@ -454,7 +454,7 @@ static void aq_ptp_extts_pin_ctrl(struct aq_ptp_s *aq_p= tp) =20 if (aq_nic->aq_hw_ops->hw_extts_gpio_enable) aq_nic->aq_hw_ops->hw_extts_gpio_enable(aq_nic->aq_hw, 0, - enable); + 0, enable); } =20 static int aq_ptp_extts_pin_configure(struct ptp_clock_info *ptp, diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_ring.h b/drivers/net= /ethernet/aquantia/atlantic/aq_ring.h index d627ace850ff..e578fe04d22c 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_ring.h +++ b/drivers/net/ethernet/aquantia/atlantic/aq_ring.h @@ -85,7 +85,9 @@ struct __packed aq_ring_buff_s { u32 is_error:1; u32 is_vlan:1; u32 is_lro:1; - u32 rsvd3:3; + u32 request_ts:1; + u32 clk_sel:1; + u32 rsvd3:1; u16 eop_index; u16 rsvd4; }; diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c b/dr= ivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c index c7895bfb2ecf..6c25ad264b19 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c @@ -736,6 +736,15 @@ int hw_atl_b0_hw_ring_tx_xmit(struct aq_hw_s *self, st= ruct aq_ring_s *ring, txd->ctl |=3D HW_ATL_B0_TXD_CTL_CMD_WB; is_gso =3D false; is_vlan =3D false; + + if (ATL_HW_IS_CHIP_FEATURE(self, ANTIGUA) && + unlikely(buff->request_ts)) { + txd->ctl |=3D AQ_HW_TXD_CTL_TS_EN; + if (buff->clk_sel !=3D ATL_TSG_CLOCK_SEL_1) + txd->ctl |=3D AQ_HW_TXD_CTL_TS_TSG0; + /* The only DD+TS is required */ + txd->ctl &=3D ~HW_ATL_B0_TXD_CTL_CMD_WB; + } } } ring->sw_tail =3D aq_ring_next_dx(ring, ring->sw_tail); @@ -1323,8 +1332,8 @@ static int hw_atl_b0_adj_clock_freq(struct aq_hw_s *s= elf, s32 ppb) return self->aq_fw_ops->send_fw_request(self, &fwreq, size); } =20 -static int hw_atl_b0_gpio_pulse(struct aq_hw_s *self, u32 index, - u64 start, u32 period) +static int hw_atl_b0_gpio_pulse(struct aq_hw_s *self, u32 index, u32 clk_s= el, + u64 start, u32 period, u32 hightime) { struct hw_fw_request_iface fwreq; size_t size; @@ -1342,7 +1351,7 @@ static int hw_atl_b0_gpio_pulse(struct aq_hw_s *self,= u32 index, } =20 static int hw_atl_b0_extts_gpio_enable(struct aq_hw_s *self, u32 index, - u32 enable) + u32 channel, int enable) { /* Enable/disable Sync1588 GPIO Timestamping */ aq_phy_write_reg(self, MDIO_MMD_PCS, 0xc611, enable ? 0x71 : 0); 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Tue, 2 Jun 2026 06:55:47 -0700 (PDT) From: To: CC: , , , , , , , , Sukhdeep Singh Subject: [PATCH net-next v4 10/12] net: atlantic: add AQC113 PTP hardware ops in hw_atl2 Date: Tue, 2 Jun 2026 19:24:50 +0530 Message-ID: <20260602135452.516-11-sukhdeeps@marvell.com> X-Mailer: git-send-email 2.52.0.windows.1 In-Reply-To: <20260602135452.516-1-sukhdeeps@marvell.com> References: <20260602135452.516-1-sukhdeeps@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=GaInWwXL c=1 sm=1 tr=0 ts=6a1ee0e8 cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=FelO9ux0wxsA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=TtqV-g6YmW1Jfm2GSLaY:22 a=M5GUcnROAAAA:8 a=_Uech-6FvGySvUjt_wcA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-ORIG-GUID: q2VkyAN1MAI2GW9sfWATcDQjrQcjsRdP X-Proofpoint-GUID: q2VkyAN1MAI2GW9sfWATcDQjrQcjsRdP X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjAyMDEzMyBTYWx0ZWRfX2yLaC2dL3L44 cszPPHa83rbU6GbOQZhzY2BlkRrlU5dmQYOBxgzhYCByozY1il3C8tvIpAFmlGamcMvaozdgQDq lP9Jvq4OMbRRyfZX544y3Urr5k6Pujvwd1pSfNr5rrKbUX//jaafB0LcWc82h9kEyQKvI0UtpaF ckPxEyJ1PjqZOCjXcImcIcW12iYPBgCYdxOllrlSUM2++slMBfDR60Dk6FE7+x5RTGeVMwdJQMa XUZhYiYNsUhYrCfQZG6hyPwdLUgfpefdToIJ4fpxpQgg/P7hQdsu+xG1yN0L6WcGFR8cXC+vcMY dGC4lhh1J1GLfeOnJwBxm0xMbUVokQg6yk8fLabvIGEu4XH81TfnGjH+T5ifGNg+oO25F5dF4EN wM1VjzMyThzpu+1PO/2HxS4pXVWvRWiTbANApLJvXfLHLVp1TiFv5voMRP113RJBWDCKrGlXM2l FAU3wn7XLV6Yc5v11pg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-02_02,2026-05-28_03,2025-10-01_01 Content-Type: text/plain; charset="utf-8" From: Sukhdeep Singh Add the hardware-layer PTP implementation for AQC113 (Antigua): - hw_atl2.h/hw_atl2_utils.h/hw_atl2_internal.h: export PTP function prototypes, per-instance aq_ptp_offset arrays, RX timestamp size (HW_ATL2_RX_TS_SIZE=3D8), and reduced HW_ATL2_RXBUF_MAX=3D172 (AQC113 on-chip RX packet buffer hardware limit for data TCs). - hw_atl2.c: implement hw_atl2_enable_ptp() to program TSG clocks, PTP TC receive path and filter ART entries, and re-enable PTP state after hardware reset. - hw_atl2.c: implement hw_atl2_adj_sys_clock(), hw_atl2_adj_clock_freq(), and aq_get_ptp_ts() for TSG clock read/adjust/increment operations. - hw_atl2.c: implement hw_atl2_gpio_pulse() for PPS output generation via TSG pulse generator. - hw_atl2.c: implement hw_atl2_hw_tx_ptp_ring_init() and hw_atl2_hw_rx_ptp_ring_init() for PTP ring setup. - hw_atl2.c: implement hw_atl2_hw_ring_tx_ptp_get_ts() to read TX timestamp from descriptor writeback, and hw_atl2_hw_rx_extract_ts() to extract RX timestamp from the 8-byte packet trailer. - hw_atl2.c: add hw_atl2_hw_get_clk_sel() helper. - Wire all new ops into hw_atl2_ops. Signed-off-by: Sukhdeep Singh --- .../aquantia/atlantic/hw_atl2/hw_atl2.c | 202 +++++++++++++++++- .../aquantia/atlantic/hw_atl2/hw_atl2.h | 12 ++ .../atlantic/hw_atl2/hw_atl2_internal.h | 3 +- .../aquantia/atlantic/hw_atl2/hw_atl2_utils.h | 10 + 4 files changed, 224 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.c b/dri= vers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.c index 6d9ec4072d43..e94627c36163 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.c @@ -7,6 +7,7 @@ #include "aq_hw_utils.h" #include "aq_ring.h" #include "aq_nic.h" +#include "aq_ptp.h" #include "hw_atl/hw_atl_b0.h" #include "hw_atl/hw_atl_utils.h" #include "hw_atl/hw_atl_llh.h" @@ -20,6 +21,15 @@ static int hw_atl2_act_rslvr_table_set(struct aq_hw_s *self, u8 location, u32 tag, u32 mask, u32 action); =20 +static void hw_atl2_enable_ptp(struct aq_hw_s *self, + unsigned int param, int enable); +static int hw_atl2_hw_tx_ptp_ring_init(struct aq_hw_s *self, + struct aq_ring_s *aq_ring); +static int hw_atl2_hw_rx_ptp_ring_init(struct aq_hw_s *self, + struct aq_ring_s *aq_ring); +static void aq_get_ptp_ts(struct aq_hw_s *self, u64 *stamp); +static int hw_atl2_adj_clock_freq(struct aq_hw_s *self, s32 ppb); + #define DEFAULT_BOARD_BASIC_CAPABILITIES \ .is_64_dma =3D true, \ .op64bit =3D true, \ @@ -127,6 +137,7 @@ static u32 hw_atl2_sem_act_rslvr_get(struct aq_hw_s *se= lf) static int hw_atl2_hw_reset(struct aq_hw_s *self) { struct hw_atl2_priv *priv =3D self->priv; + s8 clk_sel; int err; int i; =20 @@ -144,6 +155,13 @@ static int hw_atl2_hw_reset(struct aq_hw_s *self) priv->l3l4_filters[i].l4_index =3D -1; } =20 + clk_sel =3D READ_ONCE(self->clk_select); + if (clk_sel !=3D -1) + hw_atl2_enable_ptp(self, + clk_sel, + aq_utils_obj_test(&self->flags, AQ_HW_PTP_AVAILABLE) ? + 1 : 0); + self->aq_fw_ops->set_state(self, MPI_RESET); =20 err =3D aq_hw_err_from_flags(self); @@ -725,14 +743,32 @@ static int hw_atl2_hw_ring_rx_init(struct aq_hw_s *se= lf, struct aq_ring_s *aq_ring, struct aq_ring_param_s *aq_ring_param) { - return hw_atl_b0_hw_ring_rx_init(self, aq_ring, aq_ring_param); + int res =3D hw_atl_b0_hw_ring_rx_init(self, aq_ring, aq_ring_param); + + if (!res && aq_ptp_ring(aq_ring->aq_nic, aq_ring)) { + int rx_err =3D hw_atl2_hw_rx_ptp_ring_init(self, aq_ring); + + if (!res) + res =3D rx_err; + } + + return res; } =20 static int hw_atl2_hw_ring_tx_init(struct aq_hw_s *self, struct aq_ring_s *aq_ring, struct aq_ring_param_s *aq_ring_param) { - return hw_atl_b0_hw_ring_tx_init(self, aq_ring, aq_ring_param); + int res =3D hw_atl_b0_hw_ring_tx_init(self, aq_ring, aq_ring_param); + + if (!res && aq_ptp_ring(aq_ring->aq_nic, aq_ring)) { + int tx_err =3D hw_atl2_hw_tx_ptp_ring_init(self, aq_ring); + + if (!res) + res =3D tx_err; + } + + return res; } =20 #define IS_FILTER_ENABLED(_F_) ((packet_filter & (_F_)) ? 1U : 0U) @@ -892,6 +928,151 @@ static struct aq_stats_s *hw_atl2_utils_get_hw_stats(= struct aq_hw_s *self) return &self->curr_stats; } =20 +static void hw_atl2_enable_ptp(struct aq_hw_s *self, + unsigned int param, int enable) +{ + WRITE_ONCE(self->clk_select, (s8)param); + + /* enable tsg counter */ + hw_atl2_tsg_clock_reset(self, self->clk_select); + hw_atl2_tsg_clock_en(self, !self->clk_select, enable); + hw_atl2_tsg_clock_en(self, self->clk_select, enable); + + if (enable) + hw_atl2_adj_clock_freq(self, 0); + + hw_atl2_tpb_tps_highest_priority_tc_enable_set(self, enable); +} + +static void aq_get_ptp_ts(struct aq_hw_s *self, u64 *stamp) +{ + s8 clk_sel =3D READ_ONCE(self->clk_select); + + if (clk_sel < 0) + return; + if (stamp) + *stamp =3D hw_atl2_tsg_clock_read(self, clk_sel); +} + +static u64 hw_atl2_hw_ring_tx_ptp_get_ts(struct aq_ring_s *ring) +{ + struct hw_atl2_txts_s *txts; + u32 ctrl; + + txts =3D (struct hw_atl2_txts_s *)&ring->dx_ring[ring->sw_head * + HW_ATL2_TXD_SIZE]; + /* DD + TS_VALID */ + ctrl =3D le32_to_cpu(READ_ONCE(txts->ctrl)); + if ((ctrl & HW_ATL2_TXTS_DD) && (ctrl & HW_ATL2_TXTS_TS_VALID)) { + dma_rmb(); + return le64_to_cpu(txts->ts); + } + + return 0; +} + +static u16 hw_atl2_hw_rx_extract_ts(struct aq_hw_s *self, u8 *p, + unsigned int len, u64 *timestamp) +{ + unsigned int offset =3D HW_ATL2_RX_TS_SIZE; + __le64 ts; + u8 *ptr; + + if (len <=3D offset || !timestamp) + return 0; + + ptr =3D p + (len - offset); + memcpy(&ts, ptr, sizeof(ts)); + *timestamp =3D le64_to_cpu(ts); + + return HW_ATL2_RX_TS_SIZE; +} + +static int hw_atl2_adj_sys_clock(struct aq_hw_s *self, s64 delta) +{ + s8 clk_sel =3D READ_ONCE(self->clk_select); + + if (clk_sel < 0) + return -ENODEV; + if (delta >=3D 0) + hw_atl2_tsg_clock_add(self, clk_sel, (u64)delta); + else + hw_atl2_tsg_clock_sub(self, clk_sel, (u64)(-delta)); + + return 0; +} + +static int hw_atl2_adj_clock_freq(struct aq_hw_s *self, s32 ppb) +{ + u32 freq =3D AQ2_HW_PTP_COUNTER_HZ; + u64 divisor =3D 0, base_ns; + u32 nsi_frac =3D 0, nsi; + u32 nsi_rem; + s8 clk_sel; + + base_ns =3D div_u64((u64)((s64)ppb + NSEC_PER_SEC) * NSEC_PER_SEC, freq); + nsi =3D (u32)div_u64_rem(base_ns, NSEC_PER_SEC, &nsi_rem); + if (nsi_rem !=3D 0) { + divisor =3D div_u64(mul_u32_u32(NSEC_PER_SEC, NSEC_PER_SEC), + nsi_rem); + nsi_frac =3D (u32)div64_u64(AQ_FRAC_PER_NS * NSEC_PER_SEC, + divisor); + } + + clk_sel =3D READ_ONCE(self->clk_select); + if (clk_sel < 0) + return -ENODEV; + hw_atl2_tsg_clock_increment_set(self, clk_sel, nsi, nsi_frac); + + return 0; +} + +static int hw_atl2_hw_tx_ptp_ring_init(struct aq_hw_s *self, + struct aq_ring_s *aq_ring) +{ + hw_atl2_tdm_tx_desc_timestamp_writeback_en_set(self, true, + aq_ring->idx); + hw_atl2_tdm_tx_desc_timestamp_en_set(self, true, aq_ring->idx); + hw_atl2_tdm_tx_desc_avb_en_set(self, true, aq_ring->idx); + + return aq_hw_err_from_flags(self); +} + +static int hw_atl2_hw_rx_ptp_ring_init(struct aq_hw_s *self, + struct aq_ring_s *aq_ring) +{ + hw_atl2_rpf_rx_desc_timestamp_req_set(self, + self->clk_select =3D=3D ATL_TSG_CLOCK_SEL_1 ? 2 : 1, + aq_ring->idx); + return aq_hw_err_from_flags(self); +} + +static u32 hw_atl2_hw_get_clk_sel(struct aq_hw_s *self) +{ + return READ_ONCE(self->clk_select); +} + +static int hw_atl2_gpio_pulse(struct aq_hw_s *self, u32 index, u32 clk_sel, + u64 start, u32 period, u32 hightime) +{ + u32 mode; + + if (index !=3D 1 && index !=3D 3) + return -EINVAL; + + if (start =3D=3D 0) + mode =3D HW_ATL2_GPIO_PIN_SPEC_MODE_GPIO; + else if (clk_sel =3D=3D ATL_TSG_CLOCK_SEL_0) + mode =3D HW_ATL2_GPIO_PIN_SPEC_MODE_TSG0_EVENT_OUTPUT; + else + mode =3D HW_ATL2_GPIO_PIN_SPEC_MODE_TSG1_EVENT_OUTPUT; + + hw_atl2_gpio_special_mode_set(self, mode, index); + hw_atl2_tsg_ptp_gpio_gen_pulse(self, clk_sel, start, period, hightime); + + return 0; +} + static bool hw_atl2_rxf_l3_is_equal(struct hw_atl2_l3_filter *f1, struct hw_atl2_l3_filter *f2) { @@ -1472,4 +1653,21 @@ const struct aq_hw_ops hw_atl2_ops =3D { .hw_set_offload =3D hw_atl_b0_hw_offload_set, .hw_set_loopback =3D hw_atl_b0_set_loopback, .hw_set_fc =3D hw_atl_b0_set_fc, + + .hw_ring_hwts_rx_fill =3D NULL, + .hw_ring_hwts_rx_receive =3D NULL, + + .hw_get_ptp_ts =3D aq_get_ptp_ts, + .hw_adj_clock_freq =3D hw_atl2_adj_clock_freq, + .hw_adj_sys_clock =3D hw_atl2_adj_sys_clock, + .hw_gpio_pulse =3D hw_atl2_gpio_pulse, + + .enable_ptp =3D hw_atl2_enable_ptp, + .hw_ring_tx_ptp_get_ts =3D hw_atl2_hw_ring_tx_ptp_get_ts, + .rx_extract_ts =3D hw_atl2_hw_rx_extract_ts, + .hw_tx_ptp_ring_init =3D hw_atl2_hw_tx_ptp_ring_init, + .hw_rx_ptp_ring_init =3D hw_atl2_hw_rx_ptp_ring_init, + .hw_get_clk_sel =3D hw_atl2_hw_get_clk_sel, + .extract_hwts =3D NULL, + .hw_extts_gpio_enable =3D NULL, }; diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.h b/dri= vers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.h index 346f0dc9912e..4b905231ae73 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.h +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.h @@ -7,6 +7,18 @@ #define HW_ATL2_H =20 #include "aq_common.h" +#define HW_ATL2_RX_TS_SIZE 8 + +#define HW_ATL2_PTP_OFFSET_INGRESS_100 768 +#define HW_ATL2_PTP_OFFSET_EGRESS_100 336 +#define HW_ATL2_PTP_OFFSET_INGRESS_1000 510 +#define HW_ATL2_PTP_OFFSET_EGRESS_1000 105 +#define HW_ATL2_PTP_OFFSET_INGRESS_2500 2447 +#define HW_ATL2_PTP_OFFSET_EGRESS_2500 634 +#define HW_ATL2_PTP_OFFSET_INGRESS_5000 1426 +#define HW_ATL2_PTP_OFFSET_EGRESS_5000 361 +#define HW_ATL2_PTP_OFFSET_INGRESS_10000 997 +#define HW_ATL2_PTP_OFFSET_EGRESS_10000 203 =20 extern const struct aq_hw_caps_s hw_atl2_caps_aqc113; extern const struct aq_hw_caps_s hw_atl2_caps_aqc115c; diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_interna= l.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_internal.h index 31d7cae6641a..8da3262c167d 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_internal.h +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_internal.h @@ -29,7 +29,8 @@ #define HW_ATL2_TXBUF_MAX 128U #define HW_ATL2_PTP_TXBUF_SIZE 8U =20 -#define HW_ATL2_RXBUF_MAX 192U +/* AQC113 on-chip RX packet buffer available for data TCs */ +#define HW_ATL2_RXBUF_MAX 172U #define HW_ATL2_PTP_RXBUF_SIZE 16U #define HW_ATL2_RSS_REDIRECTION_MAX 64U =20 diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils.h= b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils.h index c84955bc14ae..ee998aabf91e 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils.h +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils.h @@ -8,6 +8,16 @@ =20 #include "aq_hw.h" =20 +/* Hardware tx launch time descriptor */ +struct hw_atl2_txts_s { + __le64 ts; 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charset="utf-8" From: Sukhdeep Singh aq_ring.h / aq_ring.c: - Add ptp_ts_deadline field to aq_ring_s to track TX timestamp timeout. - In aq_ring_tx_clean(): when hw_ring_tx_ptp_get_ts() returns 0 (HW not yet written back the timestamp), clear buff->is_mapped and buff->pa before breaking to prevent double dma_unmap on retry. When ptp_ts_deadline expires, clear request_ts and free the skb via dev_kfree_skb_any() to unblock the ring if HW never delivers the timestamp. aq_main.c: - Add IPv6 PTP packet detection in aq_ndev_start_xmit() using ipv6_hdr()->nexthdr for ETH_P_IPV6 frames, steering them through aq_ptp_xmit() alongside the existing IPv4 path. - Use PTP_EV_PORT/PTP_GEN_PORT constants instead of magic numbers 319/320. - Remove stale aq_ndev_open() PTP call that was moved to aq_nic_start(). aq_nic.c: - Move aq_reapply_rxnfc_all_rules() and aq_filters_vlans_update() into aq_nic_start() after hardware init, replacing the duplicate calls that were removed from aq_ndev_open(). Signed-off-by: Sukhdeep Singh --- .../net/ethernet/aquantia/atlantic/aq_main.c | 30 ++++++++++--------- .../net/ethernet/aquantia/atlantic/aq_nic.c | 8 +++++ .../net/ethernet/aquantia/atlantic/aq_ring.c | 23 +++++++++++++- .../net/ethernet/aquantia/atlantic/aq_ring.h | 1 + 4 files changed, 47 insertions(+), 15 deletions(-) diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_main.c b/drivers/net= /ethernet/aquantia/atlantic/aq_main.c index 4ef4fe64b8ac..1da14786fe5c 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_main.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_main.c @@ -19,8 +19,10 @@ #include #include #include +#include #include #include +#include #include #include =20 @@ -68,14 +70,6 @@ int aq_ndev_open(struct net_device *ndev) if (err < 0) goto err_exit; =20 - err =3D aq_reapply_rxnfc_all_rules(aq_nic); - if (err < 0) - goto err_exit; - - err =3D aq_filters_vlans_update(aq_nic); - if (err < 0) - goto err_exit; - err =3D aq_nic_start(aq_nic); if (err < 0) { aq_nic_stop(aq_nic); @@ -113,12 +107,20 @@ static netdev_tx_t aq_ndev_start_xmit(struct sk_buff = *skb, struct net_device *nd * and hardware PTP design of the chip. Otherwise ptp stream * will fail to sync */ - if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) || - unlikely((ip_hdr(skb)->version =3D=3D 4) && - (ip_hdr(skb)->protocol =3D=3D IPPROTO_UDP) && - ((udp_hdr(skb)->dest =3D=3D htons(319)) || - (udp_hdr(skb)->dest =3D=3D htons(320)))) || - unlikely(eth_hdr(skb)->h_proto =3D=3D htons(ETH_P_1588))) + if (unlikely(skb->protocol =3D=3D htons(ETH_P_IP) && + ip_hdr(skb)->protocol =3D=3D IPPROTO_UDP && + (udp_hdr(skb)->dest =3D=3D htons(PTP_EV_PORT) || + udp_hdr(skb)->dest =3D=3D htons(PTP_GEN_PORT)))) + return aq_ptp_xmit(aq_nic, skb); + + /* PTP over IPv6 does not use extension headers */ + if (unlikely(skb->protocol =3D=3D htons(ETH_P_IPV6) && + ipv6_hdr(skb)->nexthdr =3D=3D IPPROTO_UDP && + (udp_hdr(skb)->dest =3D=3D htons(PTP_EV_PORT) || + udp_hdr(skb)->dest =3D=3D htons(PTP_GEN_PORT)))) + return aq_ptp_xmit(aq_nic, skb); + + if (unlikely(eth_hdr(skb)->h_proto =3D=3D htons(ETH_P_1588))) return aq_ptp_xmit(aq_nic, skb); } #endif diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_nic.c b/drivers/net/= ethernet/aquantia/atlantic/aq_nic.c index ef9447810071..09c90c969fb1 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_nic.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_nic.c @@ -496,6 +496,14 @@ int aq_nic_start(struct aq_nic_s *self) goto err_exit; } =20 + err =3D aq_reapply_rxnfc_all_rules(self); + if (err < 0) + goto err_exit; + + err =3D aq_filters_vlans_update(self); + if (err < 0) + goto err_exit; + err =3D aq_ptp_ring_start(self); if (err < 0) goto err_exit; diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_ring.c b/drivers/net= /ethernet/aquantia/atlantic/aq_ring.c index e270327e47fd..dd1af3deb2d1 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_ring.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_ring.c @@ -311,6 +311,27 @@ bool aq_ring_tx_clean(struct aq_ring_s *self) if (likely(!buff->is_eop)) goto out; =20 + if (unlikely(buff->request_ts) && + self->aq_nic->aq_hw_ops->hw_ring_tx_ptp_get_ts) { + u64 ts =3D self->aq_nic->aq_hw_ops->hw_ring_tx_ptp_get_ts(self); + + if (!ts) { + if (time_after(jiffies, + self->ptp_ts_deadline)) { + /* Timeout: free skb, unblock ring */ + buff->request_ts =3D 0; + dev_kfree_skb_any(buff->skb); + buff->skb =3D NULL; + goto out; + } else { + buff->is_mapped =3D 0; + buff->pa =3D 0U; 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charset="utf-8" From: Sukhdeep Singh aq_ptp.c / aq_ptp.h: - Add aq_ptp_state enum (AQ_PTP_FIRST_INIT, AQ_PTP_LINK_UP, AQ_PTP_NO_LINK) to distinguish first init from link-change events; on AQC113 only reset the TSG clock on first init to avoid disrupting ongoing synchronization. - Add aq_ptp_dpath_enable() for comprehensive L3/L4 PTP filter setup/teardown, replacing the previous single-filter approach with an array of 4 slots for IPv4 and IPv6 PTP multicast addresses (224.0.1.129, 224.0.0.107, ff0e::181, ff02::6b). - Add aq_ptp_parse_rx_filters() to map hwtstamp_rx_filters to L2/L4 enable flags and call aq_ptp_dpath_enable(). - Re-apply RX filters on link change (hardware state lost after reset). - Extend PTP ring alloc/init/start/stop to handle AQC113 PTP ring ops. - Add per-instance PTP offset table for AQC113 with empirically measured values at 100M/1G/2.5G/5G/10G link speeds. - Export aq_ptp_dpath_enable() and updated ring helpers in aq_ptp.h. aq_hw.h: - Include hw_atl2/hw_atl2.h for AQC113 PTP type definitions. aq_nic.c: - Account for PTP IRQ vector (AQ_HW_PTP_IRQS) in vector count math. - Call hw_atl2 PTP re-enable hook after hardware reset in aq_nic_update_link_status(). aq_pci_func.c: - Pass PTP IRQ index to aq_ptp_irq_alloc() in probe path. Signed-off-by: Sukhdeep Singh --- .../net/ethernet/aquantia/atlantic/aq_hw.h | 1 + .../net/ethernet/aquantia/atlantic/aq_nic.c | 42 +- .../ethernet/aquantia/atlantic/aq_pci_func.c | 5 +- .../net/ethernet/aquantia/atlantic/aq_ptp.c | 558 ++++++++++++++---- .../net/ethernet/aquantia/atlantic/aq_ptp.h | 15 +- 5 files changed, 483 insertions(+), 138 deletions(-) diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_hw.h b/drivers/net/e= thernet/aquantia/atlantic/aq_hw.h index 0ba29b8f95ab..338c956ad1f7 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_hw.h +++ b/drivers/net/ethernet/aquantia/atlantic/aq_hw.h @@ -15,6 +15,7 @@ #include "aq_common.h" #include "aq_rss.h" #include "hw_atl/hw_atl_utils.h" +#include "hw_atl2/hw_atl2.h" =20 #define AQ_HW_MAC_COUNTER_HZ 312500000ll #define AQ_HW_PHY_COUNTER_HZ 160000000ll diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_nic.c b/drivers/net/= ethernet/aquantia/atlantic/aq_nic.c index 09c90c969fb1..d6cb2c509950 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_nic.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_nic.c @@ -72,8 +72,15 @@ static void aq_nic_cfg_update_num_vecs(struct aq_nic_s *= self) =20 cfg->vecs =3D min(cfg->aq_hw_caps->vecs, AQ_CFG_VECS_DEF); cfg->vecs =3D min(cfg->vecs, num_online_cpus()); - if (self->irqvecs > AQ_HW_SERVICE_IRQS) - cfg->vecs =3D min(cfg->vecs, self->irqvecs - AQ_HW_SERVICE_IRQS); + if (self->irqvecs > AQ_HW_SERVICE_IRQS + AQ_HW_PTP_IRQS) + cfg->vecs =3D min(cfg->vecs, + self->irqvecs - AQ_HW_SERVICE_IRQS - AQ_HW_PTP_IRQS); + else if (self->irqvecs > AQ_HW_PTP_IRQS) + cfg->vecs =3D min(cfg->vecs, + self->irqvecs - AQ_HW_PTP_IRQS); + else + cfg->vecs =3D 1U; + /* cfg->vecs should be power of 2 for RSS */ cfg->vecs =3D rounddown_pow_of_two(cfg->vecs); =20 @@ -138,7 +145,8 @@ void aq_nic_cfg_start(struct aq_nic_s *self) * link status IRQ. If no - we'll know link state from * slower service task. */ - if (AQ_HW_SERVICE_IRQS > 0 && cfg->vecs + 1 <=3D self->irqvecs) + if (AQ_HW_SERVICE_IRQS > 0 && + self->irqvecs > AQ_HW_PTP_IRQS + AQ_HW_SERVICE_IRQS) cfg->link_irq_vec =3D cfg->vecs; else cfg->link_irq_vec =3D 0; @@ -172,7 +180,11 @@ static int aq_nic_update_link_status(struct aq_nic_s *= self) aq_nic_update_interrupt_moderation_settings(self); =20 if (self->aq_ptp) { - aq_ptp_clock_init(self); + /* PTP does not work in some modes even if physical link is up */ + bool ptp_link_good =3D (self->aq_hw->aq_link_status.mbps >=3D 100 && + self->aq_hw->aq_link_status.full_duplex); + + aq_ptp_clock_init(self, ptp_link_good ? AQ_PTP_LINK_UP : AQ_PTP_NO_LINK= ); aq_ptp_tm_offset_set(self, self->aq_hw->aq_link_status.mbps); aq_ptp_link_change(self); @@ -279,6 +291,7 @@ static int aq_nic_hw_prepare(struct aq_nic_s *self) int err =3D 0; =20 err =3D self->aq_hw_ops->hw_soft_reset(self->aq_hw); + if (err) goto exit; =20 @@ -450,7 +463,14 @@ int aq_nic_init(struct aq_nic_s *self) } =20 if (aq_nic_get_cfg(self)->is_ptp) { - err =3D aq_ptp_init(self, self->irqvecs - 1); + u32 ptp_isr_vec; + + if (self->irqvecs > AQ_HW_PTP_IRQS) + ptp_isr_vec =3D self->irqvecs - AQ_HW_PTP_IRQS; + else + ptp_isr_vec =3D 0; + + err =3D aq_ptp_init(self, ptp_isr_vec); if (err < 0) goto err_exit; =20 @@ -691,6 +711,7 @@ unsigned int aq_nic_map_skb(struct aq_nic_s *self, stru= ct sk_buff *skb, unsigned int ret =3D 0U; unsigned int dx; u8 l4proto =3D 0; + s32 clk_sel; =20 if (ipver =3D=3D 4) l4proto =3D ip_hdr(skb)->protocol; @@ -803,6 +824,17 @@ unsigned int aq_nic_map_skb(struct aq_nic_s *self, str= uct sk_buff *skb, dx_buff->is_eop =3D 1U; dx_buff->skb =3D skb; dx_buff->xdpf =3D NULL; + if (skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS && + self->aq_hw_ops->enable_ptp && + self->aq_hw_ops->hw_get_clk_sel && + aq_ptp_ring(self, ring)) { + clk_sel =3D (s32)self->aq_hw_ops->hw_get_clk_sel(self->aq_hw); + if (clk_sel < 0) + goto exit; + dx_buff->request_ts =3D 1U; + dx_buff->clk_sel =3D (u32)clk_sel; + ring->ptp_ts_deadline =3D jiffies + HZ; + } goto exit; =20 mapping_error: diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_pci_func.c b/drivers= /net/ethernet/aquantia/atlantic/aq_pci_func.c index e9e38af680c3..2e8378e595bd 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_pci_func.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_pci_func.c @@ -250,6 +250,7 @@ static int aq_pci_probe(struct pci_dev *pdev, goto err_ioremap; } self->aq_hw->aq_nic_cfg =3D aq_nic_get_cfg(self); + self->aq_hw->clk_select =3D -1; if (self->aq_hw->aq_nic_cfg->aq_hw_caps->priv_data_len) { int len =3D self->aq_hw->aq_nic_cfg->aq_hw_caps->priv_data_len; =20 @@ -293,8 +294,8 @@ static int aq_pci_probe(struct pci_dev *pdev, numvecs =3D min((u8)AQ_CFG_VECS_DEF, aq_nic_get_cfg(self)->aq_hw_caps->msix_irqs); numvecs =3D min(numvecs, num_online_cpus()); - /* Request IRQ vector for PTP */ - numvecs +=3D 1; + /* Request IRQ lines for PTP */ + numvecs +=3D AQ_HW_PTP_IRQS; =20 numvecs +=3D AQ_HW_SERVICE_IRQS; /*enable interrupts */ diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_ptp.c b/drivers/net/= ethernet/aquantia/atlantic/aq_ptp.c index 7486a28d7ff8..0822ac3b1dd3 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_ptp.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_ptp.c @@ -26,6 +26,18 @@ =20 #define POLL_SYNC_TIMER_MS 15 =20 +#define PTP_UDP_FILTERS_CNT 4 + +#define PTP_IPV4_MC_ADDR1 0xE0000181 +#define PTP_IPV4_MC_ADDR2 0xE000006B + +#define PTP_IPV6_MC_ADDR10 0xFF0E +#define PTP_IPV6_MC_ADDR14 0x0181 +#define PTP_IPV6_MC_ADDR20 0xFF02 +#define PTP_IPV6_MC_ADDR24 0x006B + +#define PTP_GPIO_HIGHTIME 100000 + enum ptp_speed_offsets { ptp_offset_idx_10 =3D 0, ptp_offset_idx_100, @@ -49,11 +61,18 @@ struct ptp_tx_timeout { unsigned long tx_start; }; =20 +struct ptp_tm_offset { + unsigned int mbps; + int egress; + int ingress; +}; + struct aq_ptp_s { struct aq_nic_s *aq_nic; struct kernel_hwtstamp_config hwtstamp_config; spinlock_t ptp_lock; spinlock_t ptp_ring_lock; + struct mutex ptp_filter_lock; /* serializes aq_ptp_dpath_enable() */ struct ptp_clock *ptp_clock; struct ptp_clock_info ptp_info; =20 @@ -64,7 +83,7 @@ struct aq_ptp_s { =20 struct ptp_tx_timeout ptp_tx_timeout; =20 - unsigned int idx_vector; + unsigned int idx_ptp_vector; struct napi_struct napi; =20 struct aq_ring_s ptp_tx; @@ -73,7 +92,7 @@ struct aq_ptp_s { =20 struct ptp_skb_ring skb_ring; =20 - struct aq_rx_filter_l3l4 udp_filter; + struct aq_rx_filter_l3l4 udp_filter[PTP_UDP_FILTERS_CNT]; struct aq_rx_filter_l2 eth_type_filter; =20 struct delayed_work poll_sync; @@ -81,18 +100,15 @@ struct aq_ptp_s { =20 bool extts_pin_enabled; u64 last_sync1588_ts; + /* TSG clock selection: 0 - PTP, 1 - PTM */ + u32 ptp_clock_sel; =20 bool a1_ptp; -}; + bool a2_ptp; =20 -struct ptp_tm_offset { - unsigned int mbps; - int egress; - int ingress; + struct ptp_tm_offset ptp_offset[6]; }; =20 -static struct ptp_tm_offset ptp_offset[6]; - void aq_ptp_tm_offset_set(struct aq_nic_s *aq_nic, unsigned int mbps) { struct aq_ptp_s *aq_ptp =3D aq_nic->aq_ptp; @@ -104,10 +120,10 @@ void aq_ptp_tm_offset_set(struct aq_nic_s *aq_nic, un= signed int mbps) egress =3D 0; ingress =3D 0; =20 - for (i =3D 0; i < ARRAY_SIZE(ptp_offset); i++) { - if (mbps =3D=3D ptp_offset[i].mbps) { - egress =3D ptp_offset[i].egress; - ingress =3D ptp_offset[i].ingress; + for (i =3D 0; i < ARRAY_SIZE(aq_ptp->ptp_offset); i++) { + if (mbps =3D=3D aq_ptp->ptp_offset[i].mbps) { + egress =3D aq_ptp->ptp_offset[i].egress; + ingress =3D aq_ptp->ptp_offset[i].ingress; break; } } @@ -366,6 +382,8 @@ static void aq_ptp_convert_to_hwtstamp(struct aq_ptp_s = *aq_ptp, static int aq_ptp_hw_pin_conf(struct aq_nic_s *aq_nic, u32 pin_index, u64 = start, u64 period) { + struct aq_ptp_s *aq_ptp =3D aq_nic->aq_ptp; + if (period) netdev_dbg(aq_nic->ndev, "Enable GPIO %d pulsing, start time %llu, period %u\n", @@ -380,7 +398,8 @@ static int aq_ptp_hw_pin_conf(struct aq_nic_s *aq_nic, = u32 pin_index, u64 start, */ mutex_lock(&aq_nic->fwreq_mutex); aq_nic->aq_hw_ops->hw_gpio_pulse(aq_nic->aq_hw, pin_index, - 0, start, (u32)period, 0); + aq_ptp->ptp_clock_sel, start, + (u32)period, PTP_GPIO_HIGHTIME); mutex_unlock(&aq_nic->fwreq_mutex); =20 return 0; @@ -454,7 +473,8 @@ static void aq_ptp_extts_pin_ctrl(struct aq_ptp_s *aq_p= tp) =20 if (aq_nic->aq_hw_ops->hw_extts_gpio_enable) aq_nic->aq_hw_ops->hw_extts_gpio_enable(aq_nic->aq_hw, 0, - 0, enable); + aq_ptp->ptp_clock_sel, + enable); } =20 static int aq_ptp_extts_pin_configure(struct ptp_clock_info *ptp, @@ -543,14 +563,206 @@ void aq_ptp_tx_hwtstamp(struct aq_nic_s *aq_nic, u64= timestamp) return; } =20 - timestamp +=3D atomic_read(&aq_ptp->offset_egress); - aq_ptp_convert_to_hwtstamp(aq_ptp, &hwtstamp, timestamp); - skb_tstamp_tx(skb, &hwtstamp); + if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { + timestamp +=3D atomic_read(&aq_ptp->offset_egress); + aq_ptp_convert_to_hwtstamp(aq_ptp, &hwtstamp, timestamp); + skb_tstamp_tx(skb, &hwtstamp); + } + dev_kfree_skb_any(skb); =20 aq_ptp_tx_timeout_update(aq_ptp); } =20 +static void aq_ptp_fill_udpv4_mc(struct ethtool_rx_flow_spec *fsp, + u16 rx_queue, __be32 mc_addr) +{ + memset(fsp, 0, sizeof(*fsp)); + fsp->ring_cookie =3D rx_queue; + fsp->flow_type =3D UDP_V4_FLOW; + fsp->h_u.udp_ip4_spec.pdst =3D cpu_to_be16(PTP_EV_PORT); + fsp->m_u.udp_ip4_spec.pdst =3D cpu_to_be16(0xffff); + fsp->h_u.udp_ip4_spec.ip4dst =3D mc_addr; + fsp->m_u.udp_ip4_spec.ip4dst =3D cpu_to_be32(0xffffffff); +} + +static void aq_ptp_fill_udpv6_mc(struct ethtool_rx_flow_spec *fsp, + u16 rx_queue, + __be32 ip6dst_hi, __be32 ip6dst_hi_mask, + __be32 ip6dst_lo, __be32 ip6dst_lo_mask) +{ + memset(fsp, 0, sizeof(*fsp)); + fsp->ring_cookie =3D rx_queue; + fsp->flow_type =3D UDP_V6_FLOW; + fsp->h_u.udp_ip6_spec.pdst =3D cpu_to_be16(PTP_EV_PORT); + fsp->m_u.udp_ip6_spec.pdst =3D cpu_to_be16(0xffff); + fsp->h_u.udp_ip6_spec.ip6dst[0] =3D ip6dst_hi; + fsp->m_u.udp_ip6_spec.ip6dst[0] =3D ip6dst_hi_mask; + fsp->h_u.udp_ip6_spec.ip6dst[3] =3D ip6dst_lo; + fsp->m_u.udp_ip6_spec.ip6dst[3] =3D ip6dst_lo_mask; +} + +static int aq_ptp_add_a2_filter(struct aq_ptp_s *aq_ptp, + struct ethtool_rx_flow_spec *fsp, + int *flt_idx) +{ + struct aq_nic_s *aq_nic =3D aq_ptp->aq_nic; + int err; + + err =3D aq_set_data_fl3l4(fsp, + &aq_ptp->udp_filter[*flt_idx], + aq_ptp->udp_filter[*flt_idx].location, + true); + if (!err) { + netdev_dbg(aq_nic->ndev, + "PTP MC filter prepared. Loc: %x\n", + aq_ptp->udp_filter[*flt_idx].location); + (*flt_idx)++; + } + return err; +} + +static int aq_ptp_dpath_enable(struct aq_ptp_s *aq_ptp, + int enable_flags, u16 rx_queue) +{ + struct aq_nic_s *aq_nic =3D aq_ptp->aq_nic; + struct ethtool_rxnfc cmd =3D { 0 }; + const struct aq_hw_ops *hw_ops =3D aq_nic->aq_hw_ops; + struct ethtool_rx_flow_spec *fsp =3D + (struct ethtool_rx_flow_spec *)&cmd.fs; + int err =3D 0, i =3D 0; + int flt_idx =3D 0; + + netdev_dbg(aq_nic->ndev, + "%sable ptp filters: %x.\n", + enable_flags ? "En" : "Dis", enable_flags); + + if (enable_flags) { + /* Clear all existing L4 filters before applying new config */ + for (i =3D 0; i < PTP_UDP_FILTERS_CNT; i++) { + aq_ptp->udp_filter[i].cmd &=3D + ~HW_ATL_RX_ENABLE_FLTR_L3L4; + if (hw_ops->hw_filter_l3l4_set) { + err =3D hw_ops->hw_filter_l3l4_set(aq_nic->aq_hw, + &aq_ptp->udp_filter[i]); + if (err) + netdev_dbg(aq_nic->ndev, + "Set UDP filter failed\n"); + } + } + if (enable_flags & (AQ_HW_PTP_L4_ENABLE)) { + if (aq_ptp->a1_ptp) { + fsp->ring_cookie =3D rx_queue; + fsp->flow_type =3D UDP_V4_FLOW; + fsp->h_u.udp_ip4_spec.pdst =3D + cpu_to_be16(PTP_EV_PORT); + fsp->m_u.udp_ip4_spec.pdst =3D + cpu_to_be16(0xffff); + err =3D aq_set_data_fl3l4(fsp, + &aq_ptp->udp_filter[flt_idx], + aq_ptp->udp_filter[flt_idx].location, + true); + if (!err) { + netdev_dbg(aq_nic->ndev, + "Set UDPv4, location: %x\n", + aq_ptp->udp_filter[flt_idx] + .location); + flt_idx++; + } + } else { + aq_ptp_fill_udpv4_mc(fsp, rx_queue, + cpu_to_be32(PTP_IPV4_MC_ADDR1)); + err =3D aq_ptp_add_a2_filter(aq_ptp, fsp, + &flt_idx); + if (err) + netdev_dbg(aq_nic->ndev, + "UDPv4 filter prepare failed\n"); + + aq_ptp_fill_udpv6_mc(fsp, rx_queue, + cpu_to_be32(PTP_IPV6_MC_ADDR20 << 16), + cpu_to_be32(0xffff0000), + cpu_to_be32(PTP_IPV6_MC_ADDR24), + cpu_to_be32(0x0000ffff)); + err =3D aq_ptp_add_a2_filter(aq_ptp, fsp, + &flt_idx); + if (err) + netdev_dbg(aq_nic->ndev, + "UDPv6 filter prepare failed\n"); + + aq_ptp_fill_udpv6_mc(fsp, rx_queue, + cpu_to_be32(PTP_IPV6_MC_ADDR10 << 16), + cpu_to_be32(0xffff0000), + cpu_to_be32(PTP_IPV6_MC_ADDR14), + cpu_to_be32(0x0000ffff)); + err =3D aq_ptp_add_a2_filter(aq_ptp, fsp, + &flt_idx); + if (err) + netdev_dbg(aq_nic->ndev, + "UDPv6 filter prepare failed\n"); + + aq_ptp_fill_udpv4_mc(fsp, rx_queue, + cpu_to_be32(PTP_IPV4_MC_ADDR2)); + err =3D aq_ptp_add_a2_filter(aq_ptp, fsp, + &flt_idx); + if (err) + netdev_dbg(aq_nic->ndev, + "UDPv4 filter prepare failed\n"); + } + } + + if (enable_flags & AQ_HW_PTP_L2_ENABLE) { + aq_ptp->eth_type_filter.ethertype =3D ETH_P_1588; + aq_ptp->eth_type_filter.queue =3D rx_queue; + } + + if (hw_ops->hw_filter_l3l4_set) { + for (i =3D 0; i < flt_idx; i++) { + err =3D hw_ops->hw_filter_l3l4_set(aq_nic->aq_hw, + &aq_ptp->udp_filter[i]); + + if (!err) { + netdev_dbg(aq_nic->ndev, + "Set UDP filter complete. Location: %x\n", + aq_ptp->udp_filter[i].location); + } else { + netdev_dbg(aq_nic->ndev, "Set UDP filter failed\n"); + break; + } + } + } + + if (!err && (enable_flags & AQ_HW_PTP_L2_ENABLE) && + hw_ops->hw_filter_l2_set) { + err =3D hw_ops->hw_filter_l2_set(aq_nic->aq_hw, + &aq_ptp->eth_type_filter); + + if (!err) + netdev_dbg(aq_nic->ndev, + "Set L2 filter complete. Location: %d\n", + aq_ptp->eth_type_filter.location); + } + } else { + /* PTP disabled, clear all UDP/L2 filters */ + for (i =3D 0; i < PTP_UDP_FILTERS_CNT; i++) { + aq_ptp->udp_filter[i].cmd &=3D + ~HW_ATL_RX_ENABLE_FLTR_L3L4; + if (hw_ops->hw_filter_l3l4_set) { + err =3D hw_ops->hw_filter_l3l4_set(aq_nic->aq_hw, + &aq_ptp->udp_filter[i]); + if (err) + netdev_dbg(aq_nic->ndev, + "Set UDP filter failed\n"); + } + } + + if (!err && hw_ops->hw_filter_l2_clear) + err =3D hw_ops->hw_filter_l2_clear(aq_nic->aq_hw, + &aq_ptp->eth_type_filter); + } + + return err; +} + /* aq_ptp_rx_hwtstamp - utility function which checks for RX time stamp * @adapter: pointer to adapter struct * @shhwtstamps: particular skb_shared_hwtstamps to save timestamp @@ -572,59 +784,62 @@ void aq_ptp_hwtstamp_config_get(struct aq_ptp_s *aq_p= tp, *config =3D aq_ptp->hwtstamp_config; } =20 -static void aq_ptp_prepare_filters(struct aq_ptp_s *aq_ptp) +static unsigned int aq_ptp_parse_rx_filters(enum hwtstamp_rx_filters rx_fi= lter) { - aq_ptp->udp_filter.cmd =3D HW_ATL_RX_ENABLE_FLTR_L3L4 | - HW_ATL_RX_ENABLE_CMP_PROT_L4 | - HW_ATL_RX_UDP | - HW_ATL_RX_ENABLE_CMP_DEST_PORT_L4 | - HW_ATL_RX_HOST << HW_ATL_RX_ACTION_FL3F4_SHIFT | - HW_ATL_RX_ENABLE_QUEUE_L3L4 | - aq_ptp->ptp_rx.idx << HW_ATL_RX_QUEUE_FL3L4_SHIFT; - aq_ptp->udp_filter.p_dst =3D PTP_EV_PORT; - - aq_ptp->eth_type_filter.ethertype =3D ETH_P_1588; - aq_ptp->eth_type_filter.queue =3D aq_ptp->ptp_rx.idx; + unsigned int ptp_en_flags =3D AQ_HW_PTP_DISABLE; + + switch (rx_filter) { + case HWTSTAMP_FILTER_NONE: + break; + case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: + case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: + case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: + ptp_en_flags =3D AQ_HW_PTP_L2_ENABLE; + break; + case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: + case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: + case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: + case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: + case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: + case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: + ptp_en_flags =3D AQ_HW_PTP_L4_ENABLE; + break; + case HWTSTAMP_FILTER_PTP_V2_EVENT: + case HWTSTAMP_FILTER_PTP_V2_SYNC: + case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: + case HWTSTAMP_FILTER_ALL: + default: + ptp_en_flags =3D AQ_HW_PTP_L4_ENABLE | AQ_HW_PTP_L2_ENABLE; + break; + } + return ptp_en_flags; } =20 int aq_ptp_hwtstamp_config_set(struct aq_ptp_s *aq_ptp, struct kernel_hwtstamp_config *config) { + unsigned int ptp_en_flags =3D aq_ptp_parse_rx_filters(config->rx_filter); struct aq_nic_s *aq_nic =3D aq_ptp->aq_nic; - const struct aq_hw_ops *hw_ops; int err =3D 0; =20 - hw_ops =3D aq_nic->aq_hw_ops; - if (config->tx_type =3D=3D HWTSTAMP_TX_ON || - config->rx_filter =3D=3D HWTSTAMP_FILTER_PTP_V2_EVENT) { - aq_ptp_prepare_filters(aq_ptp); - if (hw_ops->hw_filter_l3l4_set) { - err =3D hw_ops->hw_filter_l3l4_set(aq_nic->aq_hw, - &aq_ptp->udp_filter); - } - if (!err && hw_ops->hw_filter_l2_set) { - err =3D hw_ops->hw_filter_l2_set(aq_nic->aq_hw, - &aq_ptp->eth_type_filter); - } + if (aq_ptp->hwtstamp_config.rx_filter !=3D config->rx_filter) { + mutex_lock(&aq_ptp->ptp_filter_lock); + err =3D aq_ptp_dpath_enable(aq_ptp, + ptp_en_flags, + aq_ptp->ptp_rx.idx); + if (!err) + aq_ptp->hwtstamp_config =3D *config; + mutex_unlock(&aq_ptp->ptp_filter_lock); + } + + if (ptp_en_flags !=3D AQ_HW_PTP_DISABLE) aq_utils_obj_set(&aq_nic->flags, AQ_NIC_PTP_DPATH_UP); - } else { - aq_ptp->udp_filter.cmd &=3D ~HW_ATL_RX_ENABLE_FLTR_L3L4; - if (hw_ops->hw_filter_l3l4_set) { - err =3D hw_ops->hw_filter_l3l4_set(aq_nic->aq_hw, - &aq_ptp->udp_filter); - } - if (!err && hw_ops->hw_filter_l2_clear) { - err =3D hw_ops->hw_filter_l2_clear(aq_nic->aq_hw, - &aq_ptp->eth_type_filter); - } + else aq_utils_obj_clear(&aq_nic->flags, AQ_NIC_PTP_DPATH_UP); - } =20 if (err) return -EREMOTEIO; =20 - aq_ptp->hwtstamp_config =3D *config; - return 0; } =20 @@ -673,21 +888,23 @@ static int aq_ptp_poll(struct napi_struct *napi, int = budget) was_cleaned =3D true; } =20 - /* Processing HW_TIMESTAMP RX traffic */ - err =3D aq_nic->aq_hw_ops->hw_ring_hwts_rx_receive(aq_nic->aq_hw, - &aq_ptp->hwts_rx); - if (err < 0) - goto err_exit; - - if (aq_ptp->hwts_rx.sw_head !=3D aq_ptp->hwts_rx.hw_head) { - aq_ring_hwts_rx_clean(&aq_ptp->hwts_rx, aq_nic); - - err =3D aq_nic->aq_hw_ops->hw_ring_hwts_rx_fill(aq_nic->aq_hw, - &aq_ptp->hwts_rx); + if (aq_ptp->a1_ptp) { + /* Processing HW_TIMESTAMP RX traffic */ + err =3D aq_nic->aq_hw_ops->hw_ring_hwts_rx_receive(aq_nic->aq_hw, + &aq_ptp->hwts_rx); if (err < 0) goto err_exit; =20 - was_cleaned =3D true; + if (aq_ptp->hwts_rx.sw_head !=3D aq_ptp->hwts_rx.hw_head) { + aq_ring_hwts_rx_clean(&aq_ptp->hwts_rx, aq_nic); + + err =3D aq_nic->aq_hw_ops->hw_ring_hwts_rx_fill(aq_nic->aq_hw, + &aq_ptp->hwts_rx); + if (err < 0) + goto err_exit; + + was_cleaned =3D true; + } } =20 /* Processing PTP RX traffic */ @@ -818,7 +1035,7 @@ int aq_ptp_irq_alloc(struct aq_nic_s *aq_nic) return 0; =20 if (pdev->msix_enabled || pdev->msi_enabled) { - err =3D request_irq(pci_irq_vector(pdev, aq_ptp->idx_vector), + err =3D request_irq(pci_irq_vector(pdev, aq_ptp->idx_ptp_vector), aq_ptp_isr, 0, aq_nic->ndev->name, aq_ptp); } else { err =3D -EINVAL; @@ -837,7 +1054,7 @@ void aq_ptp_irq_free(struct aq_nic_s *aq_nic) if (!aq_ptp) return; =20 - free_irq(pci_irq_vector(pdev, aq_ptp->idx_vector), aq_ptp); + free_irq(pci_irq_vector(pdev, aq_ptp->idx_ptp_vector), aq_ptp); } =20 int aq_ptp_ring_init(struct aq_nic_s *aq_nic) @@ -875,6 +1092,9 @@ int aq_ptp_ring_init(struct aq_nic_s *aq_nic) if (err < 0) goto err_rx_free; =20 + if (aq_ptp->a2_ptp) + return 0; + err =3D aq_ring_init(&aq_ptp->hwts_rx, ATL_RING_RX); if (err < 0) goto err_rx_free; @@ -912,10 +1132,12 @@ int aq_ptp_ring_start(struct aq_nic_s *aq_nic) if (err < 0) goto err_exit; =20 - err =3D aq_nic->aq_hw_ops->hw_ring_rx_start(aq_nic->aq_hw, - &aq_ptp->hwts_rx); - if (err < 0) - goto err_exit; + if (aq_ptp->a1_ptp) { + err =3D aq_nic->aq_hw_ops->hw_ring_rx_start(aq_nic->aq_hw, + &aq_ptp->hwts_rx); + if (err < 0) + goto err_exit; + } =20 napi_enable(&aq_ptp->napi); =20 @@ -933,7 +1155,9 @@ void aq_ptp_ring_stop(struct aq_nic_s *aq_nic) aq_nic->aq_hw_ops->hw_ring_tx_stop(aq_nic->aq_hw, &aq_ptp->ptp_tx); aq_nic->aq_hw_ops->hw_ring_rx_stop(aq_nic->aq_hw, &aq_ptp->ptp_rx); =20 - aq_nic->aq_hw_ops->hw_ring_rx_stop(aq_nic->aq_hw, &aq_ptp->hwts_rx); + if (aq_ptp->a1_ptp) + aq_nic->aq_hw_ops->hw_ring_rx_stop(aq_nic->aq_hw, + &aq_ptp->hwts_rx); =20 napi_disable(&aq_ptp->napi); } @@ -972,11 +1196,13 @@ int aq_ptp_ring_alloc(struct aq_nic_s *aq_nic) if (err) goto err_exit_ptp_tx; =20 - err =3D aq_ring_hwts_rx_alloc(&aq_ptp->hwts_rx, aq_nic, PTP_HWST_RING_IDX, - aq_nic->aq_nic_cfg.rxds, - aq_nic->aq_nic_cfg.aq_hw_caps->rxd_size); - if (err) - goto err_exit_ptp_rx; + if (aq_ptp->a1_ptp) { + err =3D aq_ring_hwts_rx_alloc(&aq_ptp->hwts_rx, aq_nic, PTP_HWST_RING_ID= X, + aq_nic->aq_nic_cfg.rxds, + aq_nic->aq_nic_cfg.aq_hw_caps->rxd_size); + if (err) + goto err_exit_ptp_rx; + } =20 err =3D aq_ptp_skb_ring_init(&aq_ptp->skb_ring, aq_nic->aq_nic_cfg.rxds); if (err !=3D 0) { @@ -984,7 +1210,7 @@ int aq_ptp_ring_alloc(struct aq_nic_s *aq_nic) goto err_exit_hwts_rx; } =20 - aq_ptp->ptp_ring_param.vec_idx =3D aq_ptp->idx_vector; + aq_ptp->ptp_ring_param.vec_idx =3D aq_ptp->idx_ptp_vector; aq_ptp->ptp_ring_param.cpu =3D aq_ptp->ptp_ring_param.vec_idx + aq_nic_get_cfg(aq_nic)->aq_rss.base_cpu_number; cpumask_set_cpu(aq_ptp->ptp_ring_param.cpu, @@ -993,7 +1219,8 @@ int aq_ptp_ring_alloc(struct aq_nic_s *aq_nic) return 0; =20 err_exit_hwts_rx: - aq_ring_hwts_rx_free(&aq_ptp->hwts_rx); + if (aq_ptp->a1_ptp) + aq_ring_hwts_rx_free(&aq_ptp->hwts_rx); err_exit_ptp_rx: aq_ring_free(&aq_ptp->ptp_rx); err_exit_ptp_tx: @@ -1011,7 +1238,8 @@ void aq_ptp_ring_free(struct aq_nic_s *aq_nic) =20 aq_ring_free(&aq_ptp->ptp_tx); aq_ring_free(&aq_ptp->ptp_rx); - aq_ring_hwts_rx_free(&aq_ptp->hwts_rx); + if (aq_ptp->a1_ptp) + aq_ring_hwts_rx_free(&aq_ptp->hwts_rx); =20 aq_ptp_skb_ring_release(&aq_ptp->skb_ring); } @@ -1035,46 +1263,49 @@ static struct ptp_clock_info aq_ptp_clock =3D { .pin_config =3D NULL, }; =20 -#define ptp_offset_init(__idx, __mbps, __egress, __ingress) do { \ - ptp_offset[__idx].mbps =3D (__mbps); \ - ptp_offset[__idx].egress =3D (__egress); \ - ptp_offset[__idx].ingress =3D (__ingress); } \ - while (0) +static void ptp_offset_init(struct aq_ptp_s *aq_ptp, int idx, + unsigned int mbps, int egress, int ingress) +{ + aq_ptp->ptp_offset[idx].mbps =3D mbps; + aq_ptp->ptp_offset[idx].egress =3D egress; + aq_ptp->ptp_offset[idx].ingress =3D ingress; +} =20 -static void aq_ptp_offset_init_from_fw(const struct hw_atl_ptp_offset *off= sets) +static void aq_ptp_offset_init_from_fw(struct aq_ptp_s *aq_ptp, + const struct hw_atl_ptp_offset *offsets) { int i; =20 /* Load offsets for PTP */ - for (i =3D 0; i < ARRAY_SIZE(ptp_offset); i++) { + for (i =3D 0; i < ARRAY_SIZE(aq_ptp->ptp_offset); i++) { switch (i) { /* 100M */ case ptp_offset_idx_100: - ptp_offset_init(i, 100, + ptp_offset_init(aq_ptp, i, 100, offsets->egress_100, offsets->ingress_100); break; /* 1G */ case ptp_offset_idx_1000: - ptp_offset_init(i, 1000, + ptp_offset_init(aq_ptp, i, 1000, offsets->egress_1000, offsets->ingress_1000); break; /* 2.5G */ case ptp_offset_idx_2500: - ptp_offset_init(i, 2500, + ptp_offset_init(aq_ptp, i, 2500, offsets->egress_2500, offsets->ingress_2500); break; /* 5G */ case ptp_offset_idx_5000: - ptp_offset_init(i, 5000, + ptp_offset_init(aq_ptp, i, 5000, offsets->egress_5000, offsets->ingress_5000); break; /* 10G */ case ptp_offset_idx_10000: - ptp_offset_init(i, 10000, + ptp_offset_init(aq_ptp, i, 10000, offsets->egress_10000, offsets->ingress_10000); break; @@ -1082,11 +1313,12 @@ static void aq_ptp_offset_init_from_fw(const struct= hw_atl_ptp_offset *offsets) } } =20 -static void aq_ptp_offset_init(const struct hw_atl_ptp_offset *offsets) +static void aq_ptp_offset_init(struct aq_ptp_s *aq_ptp, + const struct hw_atl_ptp_offset *offsets) { - memset(ptp_offset, 0, sizeof(ptp_offset)); + memset(aq_ptp->ptp_offset, 0, sizeof(aq_ptp->ptp_offset)); =20 - aq_ptp_offset_init_from_fw(offsets); + aq_ptp_offset_init_from_fw(aq_ptp, offsets); } =20 static void aq_ptp_gpio_init(struct ptp_clock_info *info, @@ -1139,26 +1371,44 @@ static void aq_ptp_gpio_init(struct ptp_clock_info = *info, sizeof(struct ptp_pin_desc) * info->n_pins); } =20 -void aq_ptp_clock_init(struct aq_nic_s *aq_nic) +void aq_ptp_clock_init(struct aq_nic_s *aq_nic, enum aq_ptp_state state) { struct aq_ptp_s *aq_ptp =3D aq_nic->aq_ptp; - struct timespec64 ts; =20 - ktime_get_real_ts64(&ts); - aq_ptp_settime(&aq_ptp->ptp_info, &ts); + if (!aq_ptp) + return; + + if (aq_ptp->a1_ptp || state =3D=3D AQ_PTP_FIRST_INIT) { + struct timespec64 ts; + + ktime_get_real_ts64(&ts); + aq_ptp_settime(&aq_ptp->ptp_info, &ts); + } + + if (!aq_ptp->a1_ptp && state !=3D AQ_PTP_FIRST_INIT) { + unsigned int ptp_en_flags =3D + aq_ptp_parse_rx_filters(state =3D=3D AQ_PTP_LINK_UP ? + aq_ptp->hwtstamp_config.rx_filter : + HWTSTAMP_FILTER_NONE); + mutex_lock(&aq_ptp->ptp_filter_lock); + aq_ptp_dpath_enable(aq_ptp, ptp_en_flags, aq_ptp->ptp_rx.idx); + mutex_unlock(&aq_ptp->ptp_filter_lock); + } } =20 static void aq_ptp_poll_sync_work_cb(struct work_struct *w); =20 -int aq_ptp_init(struct aq_nic_s *aq_nic, unsigned int idx_vec) +int aq_ptp_init(struct aq_nic_s *aq_nic, unsigned int idx_ptp_vec) { bool a1_ptp =3D ATL_HW_IS_CHIP_FEATURE(aq_nic->aq_hw, ATLANTIC); + bool a2_ptp =3D ATL_HW_IS_CHIP_FEATURE(aq_nic->aq_hw, ANTIGUA); struct hw_atl_utils_mbox mbox; struct ptp_clock *clock; - struct aq_ptp_s *aq_ptp; + struct aq_ptp_s *aq_ptp =3D NULL; int err =3D 0; + int i; =20 - if (!a1_ptp) { + if (!a1_ptp && !a2_ptp) { aq_nic->aq_ptp =3D NULL; return 0; } @@ -1168,19 +1418,43 @@ int aq_ptp_init(struct aq_nic_s *aq_nic, unsigned i= nt idx_vec) return 0; } =20 - if (!aq_nic->aq_fw_ops->enable_ptp) { - aq_nic->aq_ptp =3D NULL; - return 0; + if (a1_ptp) { + if (!aq_nic->aq_fw_ops->enable_ptp) { + aq_nic->aq_ptp =3D NULL; + return 0; + } } =20 - hw_atl_utils_mpi_read_stats(aq_nic->aq_hw, &mbox); - - if (!(mbox.info.caps_ex & BIT(CAPS_EX_PHY_PTP_EN))) { + /* PTP requires at least 1 free irq vector for itself */ + if (aq_nic->irqvecs <=3D AQ_HW_PTP_IRQS) { + netdev_warn(aq_nic->ndev, + "Disabling PTP due to insufficient number of available IRQ vectors.= \n"); aq_nic->aq_ptp =3D NULL; return 0; } =20 - aq_ptp_offset_init(&mbox.info.ptp_offset); + if (a1_ptp) { + hw_atl_utils_mpi_read_stats(aq_nic->aq_hw, &mbox); + if (!(mbox.info.caps_ex & BIT(CAPS_EX_PHY_PTP_EN))) { + aq_nic->aq_ptp =3D NULL; + return 0; + } + } else { + memset(&mbox, 0, sizeof(mbox)); + + if (a2_ptp) { + mbox.info.ptp_offset.ingress_100 =3D HW_ATL2_PTP_OFFSET_INGRESS_100; + mbox.info.ptp_offset.egress_100 =3D HW_ATL2_PTP_OFFSET_EGRESS_100; + mbox.info.ptp_offset.ingress_1000 =3D HW_ATL2_PTP_OFFSET_INGRESS_1000; + mbox.info.ptp_offset.egress_1000 =3D HW_ATL2_PTP_OFFSET_EGRESS_1000; + mbox.info.ptp_offset.ingress_2500 =3D HW_ATL2_PTP_OFFSET_INGRESS_2500; + mbox.info.ptp_offset.egress_2500 =3D HW_ATL2_PTP_OFFSET_EGRESS_2500; + mbox.info.ptp_offset.ingress_5000 =3D HW_ATL2_PTP_OFFSET_INGRESS_5000; + mbox.info.ptp_offset.egress_5000 =3D HW_ATL2_PTP_OFFSET_EGRESS_5000; + mbox.info.ptp_offset.ingress_10000 =3D HW_ATL2_PTP_OFFSET_INGRESS_10000; + mbox.info.ptp_offset.egress_10000 =3D HW_ATL2_PTP_OFFSET_EGRESS_10000; + } + } =20 aq_ptp =3D kzalloc_obj(*aq_ptp); if (!aq_ptp) { @@ -1190,10 +1464,13 @@ int aq_ptp_init(struct aq_nic_s *aq_nic, unsigned i= nt idx_vec) =20 aq_ptp->aq_nic =3D aq_nic; aq_ptp->a1_ptp =3D a1_ptp; + aq_ptp->a2_ptp =3D a2_ptp; =20 spin_lock_init(&aq_ptp->ptp_lock); spin_lock_init(&aq_ptp->ptp_ring_lock); + mutex_init(&aq_ptp->ptp_filter_lock); =20 + aq_ptp_offset_init(aq_ptp, &mbox.info.ptp_offset); aq_ptp->ptp_info =3D aq_ptp_clock; aq_ptp_gpio_init(&aq_ptp->ptp_info, &mbox.info); clock =3D ptp_clock_register(&aq_ptp->ptp_info, &aq_nic->ndev->dev); @@ -1210,22 +1487,34 @@ int aq_ptp_init(struct aq_nic_s *aq_nic, unsigned i= nt idx_vec) =20 netif_napi_add(aq_nic_get_ndev(aq_nic), &aq_ptp->napi, aq_ptp_poll); =20 - aq_ptp->idx_vector =3D idx_vec; + aq_ptp->idx_ptp_vector =3D idx_ptp_vec; =20 aq_nic->aq_ptp =3D aq_ptp; =20 /* enable ptp counter */ + aq_ptp->ptp_clock_sel =3D ATL_TSG_CLOCK_SEL_0; aq_utils_obj_set(&aq_nic->aq_hw->flags, AQ_HW_PTP_AVAILABLE); - mutex_lock(&aq_nic->fwreq_mutex); - aq_nic->aq_fw_ops->enable_ptp(aq_nic->aq_hw, 1); - aq_ptp_clock_init(aq_nic); - mutex_unlock(&aq_nic->fwreq_mutex); + if (a1_ptp) { + mutex_lock(&aq_nic->fwreq_mutex); + aq_nic->aq_fw_ops->enable_ptp(aq_nic->aq_hw, 1); + mutex_unlock(&aq_nic->fwreq_mutex); + } + if (a2_ptp) + aq_nic->aq_hw_ops->enable_ptp(aq_nic->aq_hw, aq_ptp->ptp_clock_sel, 1); =20 INIT_DELAYED_WORK(&aq_ptp->poll_sync, &aq_ptp_poll_sync_work_cb); aq_ptp->eth_type_filter.location =3D - aq_nic_reserve_filter(aq_nic, aq_rx_filter_ethertype); - aq_ptp->udp_filter.location =3D + aq_nic_reserve_filter(aq_nic, aq_rx_filter_ethertype); + + for (i =3D 0; i < PTP_UDP_FILTERS_CNT; i++) { + aq_ptp->udp_filter[i].location =3D aq_nic_reserve_filter(aq_nic, aq_rx_filter_l3l4); + } + + aq_ptp_clock_init(aq_nic, AQ_PTP_FIRST_INIT); + netdev_info(aq_nic->ndev, + "Enable PTP Support. %d GPIO(s)\n", + aq_ptp->ptp_info.n_pins); =20 return 0; =20 @@ -1244,30 +1533,45 @@ void aq_ptp_unregister(struct aq_nic_s *aq_nic) if (!aq_ptp) return; =20 - ptp_clock_unregister(aq_ptp->ptp_clock); + if (aq_ptp->ptp_clock) { + ptp_clock_unregister(aq_ptp->ptp_clock); + aq_ptp->ptp_clock =3D NULL; + } } =20 void aq_ptp_free(struct aq_nic_s *aq_nic) { struct aq_ptp_s *aq_ptp =3D aq_nic->aq_ptp; + int i; =20 if (!aq_ptp) return; =20 - aq_nic_release_filter(aq_nic, aq_rx_filter_ethertype, - aq_ptp->eth_type_filter.location); - aq_nic_release_filter(aq_nic, aq_rx_filter_l3l4, - aq_ptp->udp_filter.location); cancel_delayed_work_sync(&aq_ptp->poll_sync); + /* disable ptp */ - mutex_lock(&aq_nic->fwreq_mutex); - aq_nic->aq_fw_ops->enable_ptp(aq_nic->aq_hw, 0); - mutex_unlock(&aq_nic->fwreq_mutex); + if (aq_ptp->a1_ptp) { + mutex_lock(&aq_nic->fwreq_mutex); + aq_nic->aq_fw_ops->enable_ptp(aq_nic->aq_hw, 0); + mutex_unlock(&aq_nic->fwreq_mutex); + } + + if (aq_ptp->a2_ptp) + aq_nic->aq_hw_ops->enable_ptp(aq_nic->aq_hw, + aq_ptp->ptp_clock_sel, 0); + + aq_nic_release_filter(aq_nic, aq_rx_filter_ethertype, + aq_ptp->eth_type_filter.location); + for (i =3D 0; i < PTP_UDP_FILTERS_CNT; i++) + aq_nic_release_filter(aq_nic, aq_rx_filter_l3l4, + aq_ptp->udp_filter[i].location); =20 kfree(aq_ptp->ptp_info.pin_config); + aq_ptp->ptp_info.pin_config =3D NULL; =20 netif_napi_del(&aq_ptp->napi); kfree(aq_ptp); + aq_utils_obj_clear(&aq_nic->aq_hw->flags, AQ_HW_PTP_AVAILABLE); aq_nic->aq_ptp =3D NULL; } =20 diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_ptp.h b/drivers/net/= ethernet/aquantia/atlantic/aq_ptp.h index 5e643ec7cc06..df93857deac9 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_ptp.h +++ b/drivers/net/ethernet/aquantia/atlantic/aq_ptp.h @@ -14,6 +14,12 @@ =20 #include "aq_ring.h" =20 +enum aq_ptp_state { + AQ_PTP_NO_LINK =3D 0, + AQ_PTP_FIRST_INIT =3D 1, + AQ_PTP_LINK_UP =3D 2, +}; + #define PTP_8TC_RING_IDX 8 #define PTP_4TC_RING_IDX 16 #define PTP_HWST_RING_IDX 31 @@ -32,7 +38,7 @@ static inline unsigned int aq_ptp_ring_idx(const enum aq_= tc_mode tc_mode) #if IS_REACHABLE(CONFIG_PTP_1588_CLOCK) =20 /* Common functions */ -int aq_ptp_init(struct aq_nic_s *aq_nic, unsigned int idx_vec); +int aq_ptp_init(struct aq_nic_s *aq_nic, unsigned int idx_ptp_vec); =20 void aq_ptp_unregister(struct aq_nic_s *aq_nic); void aq_ptp_free(struct aq_nic_s *aq_nic); @@ -52,7 +58,7 @@ void aq_ptp_service_task(struct aq_nic_s *aq_nic); =20 void aq_ptp_tm_offset_set(struct aq_nic_s *aq_nic, unsigned int mbps); =20 -void aq_ptp_clock_init(struct aq_nic_s *aq_nic); +void aq_ptp_clock_init(struct aq_nic_s *aq_nic, enum aq_ptp_state state); =20 /* Traffic processing functions */ int aq_ptp_xmit(struct aq_nic_s *aq_nic, struct sk_buff *skb); @@ -80,7 +86,7 @@ u64 *aq_ptp_get_stats(struct aq_nic_s *aq_nic, u64 *data); =20 #else =20 -static inline int aq_ptp_init(struct aq_nic_s *aq_nic, unsigned int idx_ve= c) +static inline int aq_ptp_init(struct aq_nic_s *aq_nic, unsigned int idx_pt= p_vec) { return 0; } @@ -122,7 +128,8 @@ static inline void aq_ptp_ring_deinit(struct aq_nic_s *= aq_nic) {} static inline void aq_ptp_service_task(struct aq_nic_s *aq_nic) {} static inline void aq_ptp_tm_offset_set(struct aq_nic_s *aq_nic, unsigned int mbps) {} -static inline void aq_ptp_clock_init(struct aq_nic_s *aq_nic) {} +static inline void aq_ptp_clock_init(struct aq_nic_s *aq_nic, + enum aq_ptp_state state) {} static inline int aq_ptp_xmit(struct aq_nic_s *aq_nic, struct sk_buff *skb) { return -EOPNOTSUPP; --=20 2.43.0