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charset="utf-8" Add/fix some comments and print statements. Signed-off-by: Andrei Stefanescu Signed-off-by: Khristine Andreea Barbulescu --- drivers/pinctrl/nxp/pinctrl-s32cc.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/nxp/pinctrl-s32cc.c b/drivers/pinctrl/nxp/pinc= trl-s32cc.c index fe7cd641fddd..4f88c24e62a2 100644 --- a/drivers/pinctrl/nxp/pinctrl-s32cc.c +++ b/drivers/pinctrl/nxp/pinctrl-s32cc.c @@ -60,6 +60,12 @@ static u32 get_pin_func(u32 pinmux) return pinmux & GENMASK(3, 0); } =20 +/* + * struct s32_pinctrl_mem_region - memory region for a set of SIUL2 regist= ers + * @map: regmap used for this range + * @pin_range: the pins controlled by these registers + * @name: name of the current range + */ struct s32_pinctrl_mem_region { struct regmap *map; const struct s32_pin_range *pin_range; @@ -67,7 +73,7 @@ struct s32_pinctrl_mem_region { }; =20 /* - * Holds pin configuration for GPIO's. + * struct gpio_pin_config - holds pin configuration for GPIO's * @pin_id: Pin ID for this GPIO * @config: Pin settings * @list: Linked list entry for each gpio pin @@ -79,20 +85,22 @@ struct gpio_pin_config { }; =20 /* - * Pad config save/restore for power suspend/resume. + * struct s32_pinctrl_context - pad config save/restore for suspend/resume + * @pads: saved values for the pards */ struct s32_pinctrl_context { unsigned int *pads; }; =20 /* + * struct s32_pinctrl - private driver data * @dev: a pointer back to containing device * @pctl: a pointer to the pinctrl device structure * @regions: reserved memory regions with start/end pin * @info: structure containing information about the pin - * @gpio_configs: Saved configurations for GPIO pins - * @gpiop_configs_lock: lock for the `gpio_configs` list - * @s32_pinctrl_context: Configuration saved over system sleep + * @gpio_configs: saved configurations for GPIO pins + * @gpio_configs_lock: lock for the `gpio_configs` list + * @saved_context: configuration saved over system sleep */ struct s32_pinctrl { struct device *dev; @@ -974,7 +982,7 @@ int s32_pinctrl_probe(struct platform_device *pdev, ipctl); if (IS_ERR(ipctl->pctl)) return dev_err_probe(&pdev->dev, PTR_ERR(ipctl->pctl), - "could not register s32 pinctrl driver\n"); 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charset="utf-8" Remove unnecessary inline specifiers from static functions. Reviewed-by: Bartosz Golaszewski Signed-off-by: Andrei Stefanescu Signed-off-by: Khristine Andreea Barbulescu --- drivers/pinctrl/nxp/pinctrl-s32cc.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/nxp/pinctrl-s32cc.c b/drivers/pinctrl/nxp/pinc= trl-s32cc.c index 4f88c24e62a2..2645a92df0ba 100644 --- a/drivers/pinctrl/nxp/pinctrl-s32cc.c +++ b/drivers/pinctrl/nxp/pinctrl-s32cc.c @@ -131,13 +131,13 @@ s32_get_region(struct pinctrl_dev *pctldev, unsigned = int pin) return NULL; } =20 -static inline int s32_check_pin(struct pinctrl_dev *pctldev, - unsigned int pin) +static int s32_check_pin(struct pinctrl_dev *pctldev, + unsigned int pin) { return s32_get_region(pctldev, pin) ? 0 : -EINVAL; } =20 -static inline int s32_regmap_read(struct pinctrl_dev *pctldev, +static int s32_regmap_read(struct pinctrl_dev *pctldev, unsigned int pin, unsigned int *val) { struct s32_pinctrl_mem_region *region; @@ -153,7 +153,7 @@ static inline int s32_regmap_read(struct pinctrl_dev *p= ctldev, return regmap_read(region->map, offset, val); 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charset="utf-8" From: Andrei Stefanescu Switch from "devm_pinctrl_register" to "devm_pinctrl_register_and_init" and "pinctrl_enable" since this is the recommended way. Reviewed-by: Frank Li Reviewed-by: Linus Walleij Reviewed-by: Bartosz Golaszewski Signed-off-by: Andrei Stefanescu Signed-off-by: Khristine Andreea Barbulescu --- drivers/pinctrl/nxp/pinctrl-s32cc.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/nxp/pinctrl-s32cc.c b/drivers/pinctrl/nxp/pinc= trl-s32cc.c index 2645a92df0ba..89a4eb2000ee 100644 --- a/drivers/pinctrl/nxp/pinctrl-s32cc.c +++ b/drivers/pinctrl/nxp/pinctrl-s32cc.c @@ -978,10 +978,10 @@ int s32_pinctrl_probe(struct platform_device *pdev, return ret; } =20 - ipctl->pctl =3D devm_pinctrl_register(&pdev->dev, s32_pinctrl_desc, - ipctl); - if (IS_ERR(ipctl->pctl)) - return dev_err_probe(&pdev->dev, PTR_ERR(ipctl->pctl), + ret =3D devm_pinctrl_register_and_init(&pdev->dev, s32_pinctrl_desc, + ipctl, &ipctl->pctl); + if (ret) + return dev_err_probe(&pdev->dev, ret, "Could not register s32 pinctrl driver\n"); =20 #ifdef CONFIG_PM_SLEEP @@ -994,7 +994,12 @@ int s32_pinctrl_probe(struct platform_device *pdev, return -ENOMEM; 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Tue, 2 Jun 2026 08:01:57 +0000 Received: from AM9PR04MB8179.eurprd04.prod.outlook.com ([fe80::a551:cde0:6730:1d85]) by AM9PR04MB8179.eurprd04.prod.outlook.com ([fe80::a551:cde0:6730:1d85%6]) with mapi id 15.21.0092.006; Tue, 2 Jun 2026 08:01:57 +0000 From: Khristine Andreea Barbulescu To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , Larisa Grigore , Lee Jones , Shawn Guo , Sascha Hauer , Fabio Estevam , Dong Aisheng , Jacky Bai , Greg Kroah-Hartman , "Rafael J. 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charset="utf-8" Extend the S32G2 SIUL2 pinctrl binding to describe the GPIO data and external interrupt resources present in the same SIUL2 hardware block. Besides the MSCR and IMCR registers used for pin multiplexing and pad configuration, SIUL2 also contains PGPDO and PGPDI registers for GPIO data and EIRQ registers for external interrupt control. Add GPIO controller properties because the SIUL2 block also provides GPIO functionality, and gpio-ranges are needed to describe the mapping between GPIO lines and pin controller pins. Document the interrupt controller properties. The SIUL2 block contains EIRQ hardware as part of the same register space. IRQ support itself will be added in a follow-up patch series. Update the example accordingly to show the complete SIUL2 register layout, including the GPIO data and EIRQ register windows. Signed-off-by: Khristine Andreea Barbulescu --- .../pinctrl/nxp,s32g2-siul2-pinctrl.yaml | 83 +++++++++++++++++-- 1 file changed, 78 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctr= l.yaml index a24286e4def6..e4cc1a3a795c 100644 --- a/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -# Copyright 2022 NXP +# Copyright 2022, 2026 NXP %YAML 1.2 --- $id: http://devicetree.org/schemas/pinctrl/nxp,s32g2-siul2-pinctrl.yaml# @@ -17,8 +17,10 @@ description: | SIUL2_0 @ 0x4009c000 SIUL2_1 @ 0x44010000 =20 - Every SIUL2 region has multiple register types, and here only MSCR and - IMCR registers need to be revealed for kernel to configure pinmux. + Every SIUL2 region has multiple register types. MSCR and IMCR registers + need to be revealed for kernel to configure pinmux. PGPDO and PGPDI + registers are used for GPIO output/input operations. EIRQ registers + are used for external interrupt configuration. =20 Please note that some register indexes are reserved in S32G2, such as MSCR102-MSCR111, MSCR123-MSCR143, IMCR84-IMCR118 and IMCR398-IMCR429. @@ -29,14 +31,22 @@ properties: - nxp,s32g2-siul2-pinctrl =20 reg: + minItems: 6 description: | - A list of MSCR/IMCR register regions to be reserved. + A list of MSCR/IMCR/PGPDO/PGPDI/EIRQ register regions to be reserved. - MSCR (Multiplexed Signal Configuration Register) An MSCR register can configure the associated pin as either a GPIO= pin or a function output pin depends on the selected signal source. - IMCR (Input Multiplexed Signal Configuration Register) An IMCR register can configure the associated pin as function input pin depends on the selected signal source. + - PGPDO (Parallel GPIO Pad Data Out Register) + A PGPDO register is used to set the output value of a GPIO pin. + - PGPDI (Parallel GPIO Pad Data In Register) + A PGPDI register is used to read the input value of a GPIO pin. + - EIRQ (External Interrupt Request) + EIRQ registers are used to configure and manage external interrupt= s. + items: - description: MSCR registers group 0 in SIUL2_0 - description: MSCR registers group 1 in SIUL2_1 @@ -44,6 +54,28 @@ properties: - description: IMCR registers group 0 in SIUL2_0 - description: IMCR registers group 1 in SIUL2_1 - description: IMCR registers group 2 in SIUL2_1 + - description: PGPDO registers in SIUL2_0 + - description: PGPDI registers in SIUL2_0 + - description: PGPDO registers in SIUL2_1 + - description: PGPDI registers in SIUL2_1 + - description: EIRQ registers in SIUL2_1 + + gpio-controller: true + + "#gpio-cells": + const: 2 + + gpio-ranges: + minItems: 1 + maxItems: 4 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + interrupts: + maxItems: 1 =20 patternProperties: '-pins$': @@ -86,10 +118,32 @@ required: - compatible - reg =20 +oneOf: + - description: Legacy pinctrl-only node + properties: + reg: + minItems: 6 + maxItems: 6 + + - description: Pinctrl node with GPIO and external interrupt support + required: + - gpio-controller + - "#gpio-cells" + - gpio-ranges + - interrupt-controller + - "#interrupt-cells" + - interrupts + properties: + reg: + minItems: 11 + maxItems: 11 + additionalProperties: false =20 examples: - | + #include + pinctrl@4009c240 { compatible =3D "nxp,s32g2-siul2-pinctrl"; =20 @@ -104,7 +158,26 @@ examples: /* IMCR119-IMCR397 registers on siul2_1 */ <0x44010c1c 0x45c>, /* IMCR430-IMCR495 registers on siul2_1 */ - <0x440110f8 0x108>; + <0x440110f8 0x108>, + /* PGPDO registers on siul2_0 */ + <0x4009d700 0x10>, + /* PGPDI registers on siul2_0 */ + <0x4009d740 0x10>, + /* PGPDO registers on siul2_1 */ + <0x44011700 0x18>, + /* PGPDI registers on siul2_1 */ + <0x44011740 0x18>, + /* EIRQ registers on siul2_1 */ + <0x44010010 0x34>; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl 0 0 102>, + <&pinctrl 112 112 79>; + + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts =3D ; =20 llce-can0-pins { llce-can0-grp0 { --=20 2.34.1 From nobody Mon Jun 8 04:27:21 2026 Received: from DUZPR83CU001.outbound.protection.outlook.com (mail-northeuropeazon11012061.outbound.protection.outlook.com [52.101.66.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C9883BFAE0; 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The SIUL2 driver is therefore structured as a monolithic pinctrl/GPIO driver. GPIO data access and direction handling are implemented using the gpio-regmap library backed by a virtual regmap. The virtual regmap translates the gpio-regmap register model to the underlying SIUL2 registers: MSCR for direction, PGPDI for input values and PGPDO for output values. The existing pinctrl GPIO callbacks are used for the request/free path: they switch the pad to GPIO mode on request and restore the previous MSCR configuration when the GPIO is released. This change came as a result of upstream review in the following series: https://lore.kernel.org/linux-gpio/20260120115923.3463866-4-khristineandree= a.barbulescu@oss.nxp.com/T/#m543c9edbdde74bdc68b6a2364e8b975356c33043 https://lore.kernel.org/all/20260504131148.3622697-7-khristineandreea.barbu= lescu@oss.nxp.com/ Support both SIUL2 DT layouts: - legacy pinctrl-only binding - extended pinctrl/GPIO/irqchip binding Signed-off-by: Andrei Stefanescu Signed-off-by: Khristine Andreea Barbulescu --- drivers/pinctrl/nxp/Kconfig | 1 + drivers/pinctrl/nxp/pinctrl-s32.h | 32 +- drivers/pinctrl/nxp/pinctrl-s32cc.c | 685 +++++++++++++++++++++++++--- drivers/pinctrl/nxp/pinctrl-s32g2.c | 46 +- 4 files changed, 686 insertions(+), 78 deletions(-) diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig index abca7ef97003..59fc6adf5b0b 100644 --- a/drivers/pinctrl/nxp/Kconfig +++ b/drivers/pinctrl/nxp/Kconfig @@ -5,6 +5,7 @@ config PINCTRL_S32CC select GENERIC_PINCTRL_GROUPS select GENERIC_PINMUX_FUNCTIONS select GENERIC_PINCONF + select GPIO_REGMAP select REGMAP_MMIO =20 config PINCTRL_S32G2 diff --git a/drivers/pinctrl/nxp/pinctrl-s32.h b/drivers/pinctrl/nxp/pinctr= l-s32.h index 8715befd5f05..c2fc5eda7eb4 100644 --- a/drivers/pinctrl/nxp/pinctrl-s32.h +++ b/drivers/pinctrl/nxp/pinctrl-s32.h @@ -2,7 +2,7 @@ * * S32 pinmux core definitions * - * Copyright 2016-2020, 2022 NXP + * Copyright 2016-2020, 2022, 2026 NXP * Copyright (C) 2022 SUSE LLC * Copyright 2015-2016 Freescale Semiconductor, Inc. * Copyright (C) 2012 Linaro Ltd. @@ -34,11 +34,39 @@ struct s32_pin_range { unsigned int end; }; =20 +/** + * struct s32_gpio_range - contiguous GPIO pin range within a SIUL2 module + * @gpio_base: first GPIO line offset in the GPIO range + * @pin_base: first pinctrl pin number mapped by this GPIO range + * @gpio_num: number of consecutive GPIO pins in the range + */ +struct s32_gpio_range { + unsigned int gpio_base; + unsigned int pin_base; + unsigned int gpio_num; +}; + +/** + * struct s32_gpio_pad_map - mapping between GPIO ranges and PGPD pads + * @gpio_start: first GPIO line offset in the range + * @gpio_end: last GPIO line offset in the range + * @pad: PGPD pad number serving the range + */ +struct s32_gpio_pad_map { + unsigned int gpio_start; + unsigned int gpio_end; + unsigned int pad; +}; + struct s32_pinctrl_soc_data { const struct pinctrl_pin_desc *pins; unsigned int npins; const struct s32_pin_range *mem_pin_ranges; unsigned int mem_regions; + const struct s32_gpio_range *gpio_ranges; + unsigned int num_gpio_ranges; + const struct s32_gpio_pad_map *gpio_pad_maps; + unsigned int num_gpio_pad_maps; }; =20 struct s32_pinctrl_soc_info { @@ -53,6 +81,8 @@ struct s32_pinctrl_soc_info { =20 #define S32_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin) #define S32_PIN_RANGE(_start, _end) { .start =3D _start, .end =3D _end } +#define S32_GPIO_RANGE(gpio, pin, num) \ + { .gpio_base =3D gpio, .pin_base =3D pin, .gpio_num =3D num } =20 int s32_pinctrl_probe(struct platform_device *pdev, const struct s32_pinctrl_soc_data *soc_data); diff --git a/drivers/pinctrl/nxp/pinctrl-s32cc.c b/drivers/pinctrl/nxp/pinc= trl-s32cc.c index 89a4eb2000ee..8843926345ec 100644 --- a/drivers/pinctrl/nxp/pinctrl-s32cc.c +++ b/drivers/pinctrl/nxp/pinctrl-s32cc.c @@ -2,7 +2,7 @@ /* * Core driver for the S32 CC (Common Chassis) pin controller * - * Copyright 2017-2022,2024 NXP + * Copyright 2017-2022,2024-2026 NXP * Copyright (C) 2022 SUSE LLC * Copyright 2015-2016 Freescale Semiconductor, Inc. */ @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -39,6 +40,40 @@ #define S32_MSCR_ODE BIT(20) #define S32_MSCR_OBE BIT(21) =20 +#define S32_GPIO_OP_SHIFT 16 +#define S32_GPIO_OP_MASK GENMASK(19, 16) + +#define S32_GPIO_OP_DIR 0 /* MSCR direction */ +#define S32_GPIO_OP_DAT BIT(S32_GPIO_OP_SHIFT) /* PGPDI read */ +#define S32_GPIO_OP_SET BIT(S32_GPIO_OP_SHIFT + 1) /* PGPDO write */ + +/* + * [15:12] =3D GPIO bank / gpio range index + * [11:0] =3D real register offset or pin id + */ +#define S32_GPIO_BANK_SHIFT 12 +#define S32_GPIO_BANK_MASK GENMASK(15, 12) +#define S32_GPIO_REG_MASK GENMASK(11, 0) + +#define S32_GPIO_ENCODE(bank, off) \ + ((((bank) << S32_GPIO_BANK_SHIFT) & S32_GPIO_BANK_MASK) | \ + ((off) & S32_GPIO_REG_MASK)) + +#define S32_GPIO_DECODE_BANK(reg) \ + (((reg) & S32_GPIO_BANK_MASK) >> S32_GPIO_BANK_SHIFT) + +#define S32_GPIO_DECODE_OFF(reg) \ + ((reg) & S32_GPIO_REG_MASK) + +/* + * PGPDOs are 16bit registers that come in big endian + * order if they are grouped in pairs of two. + * + * For example, the order is PGPDO1, PGPDO0, PGPDO3, PGPDO2... + */ +#define S32_PGPD(N) (((N) ^ 1) * 2) +#define S32_PGPD_SIZE 16 + enum s32_write_type { S32_PINCONF_UPDATE_ONLY, S32_PINCONF_OVERWRITE, @@ -72,6 +107,18 @@ struct s32_pinctrl_mem_region { char name[8]; }; =20 +/* + * struct s32_gpio_regmaps - GPIO register maps for a SIUL2 instance + * @pgpdo: regmap for Parallel GPIO Pad Data Out registers + * @pgpdi: regmap for Parallel GPIO Pad Data In registers + * @range: GPIO range info + */ +struct s32_gpio_regmaps { + struct regmap *pgpdo; + struct regmap *pgpdi; + const struct s32_gpio_range *range; +}; + /* * struct gpio_pin_config - holds pin configuration for GPIO's * @pin_id: Pin ID for this GPIO @@ -98,6 +145,12 @@ struct s32_pinctrl_context { * @pctl: a pointer to the pinctrl device structure * @regions: reserved memory regions with start/end pin * @info: structure containing information about the pin + * @gpio_regmaps: PGPDO/PGPDI regmaps for each SIUL2 module + * @num_gpio_regmaps: number of GPIO regmap entries + * @gpio_regmap: regmap bridging gpio-regmap to SIUL2 registers + * @gpio_rgm: gpio-regmap instance registered for this controller + * @ngpio: total number of GPIO line offsets + * @gpio_names: GPIO line names array passed to gpio-regmap * @gpio_configs: saved configurations for GPIO pins * @gpio_configs_lock: lock for the `gpio_configs` list * @saved_context: configuration saved over system sleep @@ -107,6 +160,12 @@ struct s32_pinctrl { struct pinctrl_dev *pctl; struct s32_pinctrl_mem_region *regions; struct s32_pinctrl_soc_info *info; + struct s32_gpio_regmaps *gpio_regmaps; + unsigned int num_gpio_regmaps; + struct regmap *gpio_regmap; + struct gpio_regmap *gpio_rgm; + unsigned int ngpio; + const char *const *gpio_names; struct list_head gpio_configs; spinlock_t gpio_configs_lock; #ifdef CONFIG_PM_SLEEP @@ -356,88 +415,84 @@ static int s32_pmx_get_funcs_count(struct pinctrl_dev= *pctldev) return info->nfunctions; } =20 -static const char *s32_pmx_get_func_name(struct pinctrl_dev *pctldev, - unsigned int selector) -{ - struct s32_pinctrl *ipctl =3D pinctrl_dev_get_drvdata(pctldev); - const struct s32_pinctrl_soc_info *info =3D ipctl->info; - - return info->functions[selector].name; -} - -static int s32_pmx_get_groups(struct pinctrl_dev *pctldev, - unsigned int selector, - const char * const **groups, - unsigned int * const num_groups) -{ - struct s32_pinctrl *ipctl =3D pinctrl_dev_get_drvdata(pctldev); - const struct s32_pinctrl_soc_info *info =3D ipctl->info; - - *groups =3D info->functions[selector].groups; - *num_groups =3D info->functions[selector].ngroups; - - return 0; -} - static int s32_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, - unsigned int offset) + unsigned int pin) { struct s32_pinctrl *ipctl =3D pinctrl_dev_get_drvdata(pctldev); - struct gpio_pin_config *gpio_pin; + struct gpio_pin_config *gpio_pin __free(kfree) =3D NULL; unsigned int config; - unsigned long flags; int ret; =20 - ret =3D s32_regmap_read(pctldev, offset, &config); + ret =3D s32_regmap_read(pctldev, pin, &config); if (ret) return ret; =20 - /* Save current configuration */ - gpio_pin =3D kmalloc_obj(*gpio_pin); + gpio_pin =3D kmalloc(sizeof(*gpio_pin), GFP_KERNEL); if (!gpio_pin) return -ENOMEM; =20 - gpio_pin->pin_id =3D offset; + gpio_pin->pin_id =3D pin; gpio_pin->config =3D config; - INIT_LIST_HEAD(&gpio_pin->list); - - spin_lock_irqsave(&ipctl->gpio_configs_lock, flags); - list_add(&gpio_pin->list, &ipctl->gpio_configs); - spin_unlock_irqrestore(&ipctl->gpio_configs_lock, flags); =20 /* GPIO pin means SSS =3D 0 */ - config &=3D ~S32_MSCR_SSS_MASK; + ret =3D s32_regmap_update(pctldev, pin, + S32_MSCR_SSS_MASK | S32_MSCR_IBE, + S32_MSCR_IBE); + if (ret) + return ret; + + scoped_guard(spinlock_irqsave, &ipctl->gpio_configs_lock) + list_add(&no_free_ptr(gpio_pin)->list, &ipctl->gpio_configs); =20 - return s32_regmap_write(pctldev, offset, config); + return 0; } =20 static void s32_pmx_gpio_disable_free(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, - unsigned int offset) + unsigned int pin) { struct s32_pinctrl *ipctl =3D pinctrl_dev_get_drvdata(pctldev); - struct gpio_pin_config *gpio_pin, *tmp; + struct gpio_pin_config *gpio_pin, *found =3D NULL; unsigned long flags; - int ret; =20 spin_lock_irqsave(&ipctl->gpio_configs_lock, flags); - - list_for_each_entry_safe(gpio_pin, tmp, &ipctl->gpio_configs, list) { - if (gpio_pin->pin_id =3D=3D offset) { - ret =3D s32_regmap_write(pctldev, gpio_pin->pin_id, - gpio_pin->config); - if (ret !=3D 0) - goto unlock; - + list_for_each_entry(gpio_pin, &ipctl->gpio_configs, list) { + if (gpio_pin->pin_id =3D=3D pin) { list_del(&gpio_pin->list); - kfree(gpio_pin); + found =3D gpio_pin; break; } } - -unlock: spin_unlock_irqrestore(&ipctl->gpio_configs_lock, flags); + + if (found) { + s32_regmap_write(pctldev, found->pin_id, found->config); + kfree(found); + } +} + +static const char *s32_pmx_get_func_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + struct s32_pinctrl *ipctl =3D pinctrl_dev_get_drvdata(pctldev); + const struct s32_pinctrl_soc_info *info =3D ipctl->info; + + return info->functions[selector].name; +} + +static int s32_pmx_get_groups(struct pinctrl_dev *pctldev, + unsigned int selector, + const char * const **groups, + unsigned int * const num_groups) +{ + struct s32_pinctrl *ipctl =3D pinctrl_dev_get_drvdata(pctldev); + const struct s32_pinctrl_soc_info *info =3D ipctl->info; + + *groups =3D info->functions[selector].groups; + *num_groups =3D info->functions[selector].ngroups; + + return 0; } =20 static int s32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, @@ -649,9 +704,9 @@ static void s32_pinconf_dbg_show(struct pinctrl_dev *pc= tldev, =20 ret =3D s32_regmap_read(pctldev, pin_id, &config); if (ret) - return; - - seq_printf(s, "0x%x", config); + seq_printf(s, "error %d", ret); + else + seq_printf(s, "0x%x", config); } =20 static void s32_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, @@ -662,15 +717,13 @@ static void s32_pinconf_group_dbg_show(struct pinctrl= _dev *pctldev, struct s32_pin_group *grp; unsigned int config; const char *name; - int i, ret; + int i; =20 seq_puts(s, "\n"); grp =3D &info->groups[selector]; for (i =3D 0; i < grp->data.npins; i++) { name =3D pin_get_name(pctldev, grp->data.pins[i]); - ret =3D s32_regmap_read(pctldev, grp->data.pins[i], &config); - if (ret) - return; + s32_regmap_read(pctldev, grp->data.pins[i], &config); seq_printf(s, "%s: 0x%x\n", name, config); } } @@ -683,6 +736,450 @@ static const struct pinconf_ops s32_pinconf_ops =3D { .pin_config_group_dbg_show =3D s32_pinconf_group_dbg_show, }; =20 +static void s32_gpio_free_saved_configs(void *data) +{ + struct s32_pinctrl *ipctl =3D data; + struct gpio_pin_config *gpio_pin, *tmp; + unsigned long flags; + + spin_lock_irqsave(&ipctl->gpio_configs_lock, flags); + list_for_each_entry_safe(gpio_pin, tmp, &ipctl->gpio_configs, list) { + list_del(&gpio_pin->list); + kfree(gpio_pin); + } + spin_unlock_irqrestore(&ipctl->gpio_configs_lock, flags); +} + +static unsigned int s32_pin2pad(unsigned int pin) +{ + return pin / S32_PGPD_SIZE; +} + +static u16 s32_pin2mask(unsigned int pin) +{ + /* + * From Reference manual : + * PGPDOx[PPDOy] =3D GPDO(x =C3=97 16) + (15 - y)[PDO_(x =C3=97 16) + (15= - y)] + */ + return BIT(S32_PGPD_SIZE - 1 - pin % S32_PGPD_SIZE); +} + +static int s32_gpio_get_range(struct s32_pinctrl *ipctl, + unsigned int gpio, + unsigned int *pin, + unsigned int *bank) +{ + const struct s32_pinctrl_soc_data *soc_data =3D ipctl->info->soc_data; + const struct s32_gpio_range *range; + int i; + + for (i =3D 0; i < soc_data->num_gpio_ranges; i++) { + range =3D &soc_data->gpio_ranges[i]; + + if (gpio < range->gpio_base || + gpio >=3D range->gpio_base + range->gpio_num) + continue; + + if (pin) + *pin =3D range->pin_base + gpio - range->gpio_base; + + if (bank) + *bank =3D i; + + return 0; + } + + return -EINVAL; +} + +static int s32_gpio_pad_map_xlate(struct s32_pinctrl *ipctl, + unsigned int gpio, + unsigned int *reg_offset, + u16 *mask) +{ + const struct s32_pinctrl_soc_data *soc_data =3D ipctl->info->soc_data; + const struct s32_gpio_pad_map *map; + unsigned int bit; + int i; + + if (!soc_data->gpio_pad_maps || !soc_data->num_gpio_pad_maps) + return -EINVAL; + + for (i =3D 0; i < soc_data->num_gpio_pad_maps; i++) { + map =3D &soc_data->gpio_pad_maps[i]; + + if (gpio < map->gpio_start || gpio > map->gpio_end) + continue; + + bit =3D gpio - map->gpio_start; + *mask =3D BIT(S32_PGPD_SIZE - 1 - bit); + *reg_offset =3D S32_PGPD(map->pad); + + return 0; + } + + return -EINVAL; +} + +static int s32_gpio_xlate_pgpd(struct s32_pinctrl *ipctl, + unsigned int pin, + unsigned int *reg_offset, + u16 *mask) +{ + /* + * SIUL2_1 does not expose GPIO data registers as a linear pad sequence. + * Valid PGPD offsets there correspond to PGPD7, PGPD9, PGPD10, PGPD11. + */ + if (pin >=3D 112) + return s32_gpio_pad_map_xlate(ipctl, pin, reg_offset, mask); + + *mask =3D s32_pin2mask(pin); + *reg_offset =3D S32_PGPD(s32_pin2pad(pin)); + + return 0; +} + +static int s32_gpio_reg_mask_xlate(struct gpio_regmap *gpio, + unsigned int base, unsigned int offset, + unsigned int *reg, unsigned int *mask) +{ + struct s32_pinctrl *ipctl =3D gpio_regmap_get_drvdata(gpio); + unsigned int pgpd_reg, pin, bank; + u16 pgpd_mask; + int ret; + + ret =3D s32_gpio_get_range(ipctl, offset, &pin, &bank); + if (ret) + return ret; + + switch (base) { + case S32_GPIO_OP_DIR: + /* + * Direction is controlled through MSCR OBE. + * Encode the real pin id in the virtual register. + */ + *reg =3D S32_GPIO_OP_DIR | pin; + *mask =3D S32_MSCR_OBE; + return 0; + + case S32_GPIO_OP_DAT: + case S32_GPIO_OP_SET: + ret =3D s32_gpio_xlate_pgpd(ipctl, pin, &pgpd_reg, &pgpd_mask); + if (ret) + return ret; + /* + * Encode both the GPIO bank and the real PGPD register offset. + */ + *reg =3D base | S32_GPIO_ENCODE(bank, pgpd_reg); + *mask =3D pgpd_mask; + return 0; + default: + return -EINVAL; + } +} + +static int s32_gpio_reg_read(void *context, unsigned int reg, + unsigned int *val) +{ + struct s32_pinctrl *ipctl =3D context; + unsigned int op =3D reg & S32_GPIO_OP_MASK; + unsigned int vreg =3D reg & ~S32_GPIO_OP_MASK; + unsigned int bank; + unsigned int offset; + struct regmap *map; + + switch (op) { + case S32_GPIO_OP_DIR: + /* + * Lower bits contain the real MSCR pin id. + */ + offset =3D S32_GPIO_DECODE_OFF(vreg); + + return s32_regmap_read(ipctl->pctl, offset, val); + + case S32_GPIO_OP_DAT: + bank =3D S32_GPIO_DECODE_BANK(vreg); + offset =3D S32_GPIO_DECODE_OFF(vreg); + + if (bank >=3D ipctl->num_gpio_regmaps) + return -EINVAL; + + map =3D ipctl->gpio_regmaps[bank].pgpdi; + if (!map) + return -ENODEV; + + return regmap_read(map, offset, val); + + case S32_GPIO_OP_SET: + /* + * gpio-regmap uses update_bits() for set, so it needs to read + * the output register before writing the updated value. + */ + bank =3D S32_GPIO_DECODE_BANK(vreg); + offset =3D S32_GPIO_DECODE_OFF(vreg); + + if (bank >=3D ipctl->num_gpio_regmaps) + return -EINVAL; + + map =3D ipctl->gpio_regmaps[bank].pgpdo; + if (!map) + return -ENODEV; + + return regmap_read(map, offset, val); + + default: + return -EINVAL; + } +} + +static int s32_gpio_reg_write(void *context, unsigned int reg, + unsigned int val) +{ + struct s32_pinctrl *ipctl =3D context; + unsigned int op =3D reg & S32_GPIO_OP_MASK; + unsigned int vreg =3D reg & ~S32_GPIO_OP_MASK; + unsigned int bank, offset, config; + struct regmap *map; + + switch (op) { + case S32_GPIO_OP_DIR: + /* + * gpio-regmap sets S32_MSCR_OBE for output and clears it for + * input. Keep IBE enabled for GPIOs in both cases. + */ + offset =3D S32_GPIO_DECODE_OFF(vreg); + + config =3D S32_MSCR_IBE; + if (val & S32_MSCR_OBE) + config |=3D S32_MSCR_OBE; + + return s32_regmap_update(ipctl->pctl, offset, + S32_MSCR_OBE | S32_MSCR_IBE, + config); + + case S32_GPIO_OP_SET: + bank =3D S32_GPIO_DECODE_BANK(vreg); + offset =3D S32_GPIO_DECODE_OFF(vreg); + + if (bank >=3D ipctl->num_gpio_regmaps) + return -EINVAL; + + map =3D ipctl->gpio_regmaps[bank].pgpdo; + if (!map) + return -ENODEV; + + return regmap_write(map, offset, val); + + default: + return -EINVAL; + } +} + +static const struct regmap_bus s32_gpio_regmap_bus =3D { + .reg_read =3D s32_gpio_reg_read, + .reg_write =3D s32_gpio_reg_write, +}; + +static const struct regmap_config s32_gpio_regmap_config =3D { + .name =3D "s32-gpio", + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 1, + .max_register =3D S32_GPIO_OP_SET | S32_GPIO_BANK_MASK | S32_GPIO_REG_MAS= K, + .cache_type =3D REGCACHE_NONE, +}; + +static int s32_gpio_get_ngpio(const struct s32_pinctrl_soc_data *soc_data, + unsigned int *ngpio) +{ + const struct s32_gpio_range *range; + unsigned int end, max =3D 0; + int i; + + if (!soc_data->gpio_ranges || !soc_data->num_gpio_ranges) + return -EINVAL; + + for (i =3D 0; i < soc_data->num_gpio_ranges; i++) { + range =3D &soc_data->gpio_ranges[i]; + + if (!range->gpio_num) + return -EINVAL; + + end =3D range->gpio_base + range->gpio_num; + + /* + * gpio_ranges must be ordered by gpio_base and must not overlap. + * The GPIO line space size is derived from the highest range end. + */ + if (i > 0 && range->gpio_base < max) + return -EINVAL; + + if (end > max) + max =3D end; + } + + *ngpio =3D max; + + return 0; +} + +static int s32_init_gpio_regmap(struct platform_device *pdev, + struct s32_pinctrl *ipctl) +{ + ipctl->gpio_regmap =3D + devm_regmap_init(&pdev->dev, &s32_gpio_regmap_bus, + ipctl, &s32_gpio_regmap_config); + if (IS_ERR(ipctl->gpio_regmap)) + return dev_err_probe(&pdev->dev, + PTR_ERR(ipctl->gpio_regmap), + "Failed to init GPIO regmap\n"); + + return 0; +} + +static int s32_init_valid_mask(struct gpio_chip *chip, unsigned long *mask, + unsigned int ngpios) +{ + struct gpio_regmap *gpio =3D gpiochip_get_data(chip); + struct s32_pinctrl *ipctl =3D gpio_regmap_get_drvdata(gpio); + unsigned int gpio_num, pin, reg_offset; + u16 pgpd_mask; + int ret; + + bitmap_zero(mask, ngpios); + + for (gpio_num =3D 0; gpio_num < ngpios; gpio_num++) { + ret =3D s32_gpio_get_range(ipctl, gpio_num, &pin, NULL); + if (ret) + continue; + + ret =3D s32_gpio_xlate_pgpd(ipctl, pin, ®_offset, &pgpd_mask); + if (ret) + continue; + + bitmap_set(mask, gpio_num, 1); + } + + return 0; +} + +static int s32_gpio_populate_names(struct s32_pinctrl *ipctl) +{ + char **names; + unsigned int gpio; + unsigned int pin; + char port; + int ret; + + names =3D devm_kcalloc(ipctl->dev, ipctl->ngpio, sizeof(*names), + GFP_KERNEL); + if (!names) + return -ENOMEM; + + for (gpio =3D 0; gpio < ipctl->ngpio; gpio++) { + ret =3D s32_gpio_get_range(ipctl, gpio, &pin, NULL); + if (ret) + continue; + + port =3D 'A' + pin / 16; + + names[gpio] =3D devm_kasprintf(ipctl->dev, GFP_KERNEL, + "P%c_%02u", port, pin & 0xf); + if (!names[gpio]) + return -ENOMEM; + } + + ipctl->gpio_names =3D (const char *const *)names; + + return 0; +} + +static int s32_pinctrl_init_gpio_regmaps(struct platform_device *pdev, + struct s32_pinctrl *ipctl) +{ + const struct s32_pinctrl_soc_data *soc_data =3D ipctl->info->soc_data; + static const struct regmap_config pgpd_config =3D { + .reg_bits =3D 32, + .val_bits =3D 16, + .reg_stride =3D 2, + }; + struct regmap_config cfg; + struct resource *res; + void __iomem *base; + unsigned int pgpdo_idx, pgpdi_idx; + unsigned int i; + + if (!soc_data->gpio_ranges || !soc_data->num_gpio_ranges) + return 0; + + ipctl->num_gpio_regmaps =3D soc_data->num_gpio_ranges; + ipctl->gpio_regmaps =3D devm_kcalloc(&pdev->dev, ipctl->num_gpio_regmaps, + sizeof(*ipctl->gpio_regmaps), + GFP_KERNEL); + if (!ipctl->gpio_regmaps) + return -ENOMEM; + + for (i =3D 0; i < ipctl->num_gpio_regmaps; i++) { + ipctl->gpio_regmaps[i].range =3D &soc_data->gpio_ranges[i]; + + /* + * GPIO resources are placed after the pinctrl regions + */ + pgpdo_idx =3D soc_data->mem_regions + i * 2; + pgpdi_idx =3D soc_data->mem_regions + i * 2 + 1; + + /* PGPDO */ + res =3D platform_get_resource(pdev, IORESOURCE_MEM, pgpdo_idx); + if (!res) + return dev_err_probe(&pdev->dev, -ENOENT, + "Missing PGPDO resource %u\n", i); + + base =3D devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + cfg =3D pgpd_config; + cfg.name =3D devm_kasprintf(&pdev->dev, GFP_KERNEL, "pgpdo%u", i); + if (!cfg.name) + return -ENOMEM; + + cfg.max_register =3D resource_size(res) - cfg.reg_stride; + + ipctl->gpio_regmaps[i].pgpdo =3D + devm_regmap_init_mmio(&pdev->dev, base, &cfg); + if (IS_ERR(ipctl->gpio_regmaps[i].pgpdo)) + return dev_err_probe(&pdev->dev, + PTR_ERR(ipctl->gpio_regmaps[i].pgpdo), + "Failed to init PGPDO regmap %u\n", i); + + /* PGPDI */ + res =3D platform_get_resource(pdev, IORESOURCE_MEM, pgpdi_idx); + if (!res) + return dev_err_probe(&pdev->dev, -ENOENT, + "Missing PGPDI resource %u\n", i); + + base =3D devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + cfg =3D pgpd_config; + cfg.name =3D devm_kasprintf(&pdev->dev, GFP_KERNEL, "pgpdi%u", i); + if (!cfg.name) + return -ENOMEM; + + cfg.max_register =3D resource_size(res) - cfg.reg_stride; + + ipctl->gpio_regmaps[i].pgpdi =3D + devm_regmap_init_mmio(&pdev->dev, base, &cfg); + if (IS_ERR(ipctl->gpio_regmaps[i].pgpdi)) + return dev_err_probe(&pdev->dev, + PTR_ERR(ipctl->gpio_regmaps[i].pgpdi), + "Failed to init PGPDI regmap %u\n", i); + } + + return 0; +} + #ifdef CONFIG_PM_SLEEP static bool s32_pinctrl_should_save(struct s32_pinctrl *ipctl, unsigned int pin) @@ -710,7 +1207,6 @@ int s32_pinctrl_suspend(struct device *dev) const struct s32_pinctrl_soc_info *info =3D ipctl->info; struct s32_pinctrl_context *saved_context =3D &ipctl->saved_context; int i; - int ret; unsigned int config; =20 for (i =3D 0; i < info->soc_data->npins; i++) { @@ -719,9 +1215,7 @@ int s32_pinctrl_suspend(struct device *dev) if (!s32_pinctrl_should_save(ipctl, pin->number)) continue; =20 - ret =3D s32_regmap_read(ipctl->pctl, pin->number, &config); - if (ret) - return -EINVAL; + s32_regmap_read(ipctl->pctl, pin->number, &config); =20 saved_context->pads[i] =3D config; } @@ -736,7 +1230,7 @@ int s32_pinctrl_resume(struct device *dev) const struct s32_pinctrl_soc_info *info =3D ipctl->info; const struct pinctrl_pin_desc *pin; struct s32_pinctrl_context *saved_context =3D &ipctl->saved_context; - int ret, i; + int i; =20 for (i =3D 0; i < info->soc_data->npins; i++) { pin =3D &info->soc_data->pins[i]; @@ -744,10 +1238,8 @@ int s32_pinctrl_resume(struct device *dev) if (!s32_pinctrl_should_save(ipctl, pin->number)) continue; =20 - ret =3D s32_regmap_write(ipctl->pctl, pin->number, - saved_context->pads[i]); - if (ret) - return ret; + s32_regmap_write(ipctl->pctl, pin->number, + saved_context->pads[i]); } =20 return 0; @@ -927,13 +1419,15 @@ static int s32_pinctrl_probe_dt(struct platform_devi= ce *pdev, int s32_pinctrl_probe(struct platform_device *pdev, const struct s32_pinctrl_soc_data *soc_data) { - struct s32_pinctrl *ipctl; - int ret; - struct pinctrl_desc *s32_pinctrl_desc; - struct s32_pinctrl_soc_info *info; #ifdef CONFIG_PM_SLEEP struct s32_pinctrl_context *saved_context; #endif + struct gpio_regmap_config gpio_cfg =3D {}; + struct pinctrl_desc *s32_pinctrl_desc; + struct s32_pinctrl_soc_info *info; + struct s32_pinctrl *ipctl; + unsigned int ngpio; + int ret; =20 if (!soc_data || !soc_data->pins || !soc_data->npins) { dev_err(&pdev->dev, "wrong pinctrl info\n"); @@ -959,6 +1453,11 @@ int s32_pinctrl_probe(struct platform_device *pdev, INIT_LIST_HEAD(&ipctl->gpio_configs); spin_lock_init(&ipctl->gpio_configs_lock); =20 + ret =3D devm_add_action_or_reset(&pdev->dev, + s32_gpio_free_saved_configs, ipctl); + if (ret) + return ret; + s32_pinctrl_desc =3D devm_kzalloc(&pdev->dev, sizeof(*s32_pinctrl_desc), GFP_KERNEL); if (!s32_pinctrl_desc) @@ -978,6 +1477,11 @@ int s32_pinctrl_probe(struct platform_device *pdev, return ret; } =20 + ret =3D s32_pinctrl_init_gpio_regmaps(pdev, ipctl); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "Failed to init GPIO regmaps\n"); + ret =3D devm_pinctrl_register_and_init(&pdev->dev, s32_pinctrl_desc, ipctl, &ipctl->pctl); if (ret) @@ -999,7 +1503,42 @@ int s32_pinctrl_probe(struct platform_device *pdev, return dev_err_probe(&pdev->dev, ret, "Failed to enable pinctrl\n"); =20 - dev_info(&pdev->dev, "Initialized S32 pinctrl driver\n"); + /* Setup GPIO if GPIO ranges are defined */ + if (!soc_data->gpio_ranges || !soc_data->num_gpio_ranges) + return 0; + + ret =3D s32_gpio_get_ngpio(soc_data, &ngpio); + if (ret) + return dev_err_probe(&pdev->dev, ret, "Invalid GPIO ranges\n"); + + ipctl->ngpio =3D ngpio; + + ret =3D s32_gpio_populate_names(ipctl); + if (ret) + return ret; + + ret =3D s32_init_gpio_regmap(pdev, ipctl); + if (ret) + return ret; + + gpio_cfg.parent =3D &pdev->dev; + gpio_cfg.fwnode =3D dev_fwnode(&pdev->dev); + gpio_cfg.label =3D dev_name(&pdev->dev); + gpio_cfg.regmap =3D ipctl->gpio_regmap; + gpio_cfg.ngpio =3D ngpio; + gpio_cfg.names =3D ipctl->gpio_names; + gpio_cfg.reg_dir_out_base =3D GPIO_REGMAP_ADDR(S32_GPIO_OP_DIR); + gpio_cfg.reg_dat_base =3D GPIO_REGMAP_ADDR(S32_GPIO_OP_DAT); + gpio_cfg.reg_set_base =3D GPIO_REGMAP_ADDR(S32_GPIO_OP_SET); + gpio_cfg.reg_mask_xlate =3D s32_gpio_reg_mask_xlate; + gpio_cfg.init_valid_mask =3D s32_init_valid_mask; + gpio_cfg.drvdata =3D ipctl; + + ipctl->gpio_rgm =3D devm_gpio_regmap_register(&pdev->dev, &gpio_cfg); + if (IS_ERR(ipctl->gpio_rgm)) + return dev_err_probe(&pdev->dev, + PTR_ERR(ipctl->gpio_rgm), + "Unable to add gpio_regmap chip\n"); =20 return 0; } diff --git a/drivers/pinctrl/nxp/pinctrl-s32g2.c b/drivers/pinctrl/nxp/pinc= trl-s32g2.c index c49d28793b69..0bd6e6ab5ad1 100644 --- a/drivers/pinctrl/nxp/pinctrl-s32g2.c +++ b/drivers/pinctrl/nxp/pinctrl-s32g2.c @@ -3,7 +3,7 @@ * NXP S32G pinctrl driver * * Copyright 2015-2016 Freescale Semiconductor, Inc. - * Copyright 2017-2018, 2020-2022 NXP + * Copyright 2017-2018, 2020-2022, 2025-2026 NXP * Copyright (C) 2022 SUSE LLC */ =20 @@ -773,17 +773,47 @@ static const struct s32_pin_range s32_pin_ranges_siul= 2[] =3D { S32_PIN_RANGE(942, 1007), }; =20 -static const struct s32_pinctrl_soc_data s32_pinctrl_data =3D { +static const struct s32_gpio_range s32_gpio_ranges_siul2[] =3D { + S32_GPIO_RANGE(0, 0, 102), + S32_GPIO_RANGE(112, 112, 79), +}; + +/* + * SIUL2_1 GPIO ranges mapped to sparse PGPD pads. + * + * SIUL2_1 does not expose GPIO data registers as a linear pad + * sequence. Each entry describes a contiguous GPIO offset range + * and the PGPD pad servicing that range. + */ +static const struct s32_gpio_pad_map s32g_gpio_pad_maps[] =3D { + { 112, 122, 7 }, /* PH_00 .. PH_10 -> PGPD7 */ + { 144, 159, 9 }, /* PJ_00 .. PJ_15 -> PGPD9 */ + { 160, 175, 10 }, /* PK_00 .. PK_15 -> PGPD10 */ + { 176, 190, 11 }, /* PL_00 .. PL_14 -> PGPD11 */ +}; + +/* Legacy data for old DT bindings without GPIO support */ +static const struct s32_pinctrl_soc_data legacy_s32g_pinctrl_data =3D { + .pins =3D s32_pinctrl_pads_siul2, + .npins =3D ARRAY_SIZE(s32_pinctrl_pads_siul2), + .mem_pin_ranges =3D s32_pin_ranges_siul2, + .mem_regions =3D ARRAY_SIZE(s32_pin_ranges_siul2), +}; + +static const struct s32_pinctrl_soc_data s32g_pinctrl_data =3D { .pins =3D s32_pinctrl_pads_siul2, .npins =3D ARRAY_SIZE(s32_pinctrl_pads_siul2), .mem_pin_ranges =3D s32_pin_ranges_siul2, .mem_regions =3D ARRAY_SIZE(s32_pin_ranges_siul2), + .gpio_ranges =3D s32_gpio_ranges_siul2, + .num_gpio_ranges =3D ARRAY_SIZE(s32_gpio_ranges_siul2), + .gpio_pad_maps =3D s32g_gpio_pad_maps, + .num_gpio_pad_maps =3D ARRAY_SIZE(s32g_gpio_pad_maps), }; =20 static const struct of_device_id s32_pinctrl_of_match[] =3D { { .compatible =3D "nxp,s32g2-siul2-pinctrl", - .data =3D &s32_pinctrl_data, }, { /* sentinel */ } }; @@ -792,8 +822,16 @@ MODULE_DEVICE_TABLE(of, s32_pinctrl_of_match); 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charset="utf-8" Update the SIUL2 pinctrl node to describe the additional register ranges and DT properties used by the updated SIUL2 driver. Besides the MSCR and IMCR ranges used for pinmux and pin configuration, the SIUL2 block also provides PGPDO and PGPDI registers for GPIO output and input operations, as well as an EIRQ register window for external interrupt configuration. The driver supports both legacy pinctrl-only DTs and extended DTs with GPIO and IRQ. Reflect these resources in the SIUL2 pinctrl node by adding: - the PGPDO and PGPDI register ranges - the EIRQ register range - gpio-controller, #gpio-cells and gpio-ranges - interrupt-controller, #interrupt-cells and interrupts Keep the hardware description aligned with the updated SIUL2 driver, where pinctrl, GPIO data access and the EIRQ register block are described under the same device node. Signed-off-by: Khristine Andreea Barbulescu --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 23 +++++++++++++++++++++-- arch/arm64/boot/dts/freescale/s32g3.dtsi | 23 +++++++++++++++++++++-- 2 files changed, 42 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts= /freescale/s32g2.dtsi index 51d00dac12de..f21c8d19bcfe 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -3,7 +3,7 @@ * NXP S32G2 SoC family * * Copyright (c) 2021 SUSE LLC - * Copyright 2017-2021, 2024-2025 NXP + * Copyright 2017-2021, 2024-2026 NXP */ =20 #include @@ -135,7 +135,26 @@ pinctrl: pinctrl@4009c240 { /* IMCR119-IMCR397 registers on siul2_1 */ <0x44010c1c 0x45c>, /* IMCR430-IMCR495 registers on siul2_1 */ - <0x440110f8 0x108>; + <0x440110f8 0x108>, + /* PGPDO registers on siul2_0 */ + <0x4009d700 0x10>, + /* PGPDI registers on siul2_0 */ + <0x4009d740 0x10>, + /* PGPDO registers on siul2_1 */ + <0x44011700 0x18>, + /* PGPDI registers on siul2_1 */ + <0x44011740 0x18>, + /* EIRQ window: DISR0..IFEER0 */ + <0x44010010 0x34>; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl 0 0 102>, + <&pinctrl 112 112 79>; + + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts =3D ; =20 jtag_pins: jtag-pins { jtag-grp0 { diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts= /freescale/s32g3.dtsi index e314f3c7d61d..f5825881fd69 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright 2021-2025 NXP + * Copyright 2021-2026 NXP * * Authors: Ghennadi Procopciuc * Ciprian Costea @@ -193,7 +193,26 @@ pinctrl: pinctrl@4009c240 { /* IMCR119-IMCR397 registers on siul2_1 */ <0x44010c1c 0x45c>, /* IMCR430-IMCR495 registers on siul2_1 */ - <0x440110f8 0x108>; + <0x440110f8 0x108>, + /* PGPDO registers on siul2_0 */ + <0x4009d700 0x10>, + /* PGPDI registers on siul2_0 */ + <0x4009d740 0x10>, + /* PGPDO registers on siul2_1 */ + <0x44011700 0x18>, + /* PGPDI registers on siul2_1 */ + <0x44011740 0x18>, + /* EIRQ window: DISR0..IFEER0 */ + <0x44010010 0x34>; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl 0 0 102>, + <&pinctrl 112 112 79>; + + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts =3D ; =20 jtag_pins: jtag-pins { jtag-grp0 { --=20 2.34.1