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As a result, COMPILE_TEST is added for extra compile coverage. Assisted-by: opencode:big-pickle Signed-off-by: Rosen Penev --- drivers/char/Kconfig | 2 +- drivers/char/xilinx_hwicap/buffer_icap.c | 16 +++++------ drivers/char/xilinx_hwicap/fifo_icap.c | 34 +++++++++++------------- 3 files changed, 24 insertions(+), 28 deletions(-) diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig index 9865227af167..b892bcf28af4 100644 --- a/drivers/char/Kconfig +++ b/drivers/char/Kconfig @@ -201,7 +201,7 @@ source "drivers/char/hw_random/Kconfig" =20 config XILINX_HWICAP tristate "Xilinx HWICAP Support" - depends on MICROBLAZE + depends on MICROBLAZE || COMPILE_TEST help This option enables support for Xilinx Internal Configuration Access Port (ICAP) driver. The ICAP is used on Xilinx Virtex diff --git a/drivers/char/xilinx_hwicap/buffer_icap.c b/drivers/char/xilinx= _hwicap/buffer_icap.c index 35981cae1afa..24e73f1502c2 100644 --- a/drivers/char/xilinx_hwicap/buffer_icap.c +++ b/drivers/char/xilinx_hwicap/buffer_icap.c @@ -87,7 +87,7 @@ **/ u32 buffer_icap_get_status(struct hwicap_drvdata *drvdata) { - return in_be32(drvdata->base_address + XHI_STATUS_REG_OFFSET); + return ioread32be(drvdata->base_address + XHI_STATUS_REG_OFFSET); } =20 /** @@ -101,7 +101,7 @@ u32 buffer_icap_get_status(struct hwicap_drvdata *drvda= ta) static inline u32 buffer_icap_get_bram(void __iomem *base_address, u32 offset) { - return in_be32(base_address + (offset << 2)); + return ioread32be(base_address + (offset << 2)); } =20 /** @@ -114,7 +114,7 @@ static inline u32 buffer_icap_get_bram(void __iomem *ba= se_address, **/ static inline bool buffer_icap_busy(void __iomem *base_address) { - u32 status =3D in_be32(base_address + XHI_STATUS_REG_OFFSET); + u32 status =3D ioread32be(base_address + XHI_STATUS_REG_OFFSET); return (status & 1) =3D=3D XHI_NOT_FINISHED; } =20 @@ -129,7 +129,7 @@ static inline bool buffer_icap_busy(void __iomem *base_= address) static inline void buffer_icap_set_size(void __iomem *base_address, u32 data) { - out_be32(base_address + XHI_SIZE_REG_OFFSET, data); + iowrite32be(data, base_address + XHI_SIZE_REG_OFFSET); } =20 /** @@ -143,7 +143,7 @@ static inline void buffer_icap_set_size(void __iomem *b= ase_address, static inline void buffer_icap_set_offset(void __iomem *base_address, u32 data) { - out_be32(base_address + XHI_BRAM_OFFSET_REG_OFFSET, data); + iowrite32be(data, base_address + XHI_BRAM_OFFSET_REG_OFFSET); } =20 /** @@ -159,7 +159,7 @@ static inline void buffer_icap_set_offset(void __iomem = *base_address, static inline void buffer_icap_set_rnc(void __iomem *base_address, u32 data) { - out_be32(base_address + XHI_RNC_REG_OFFSET, data); + iowrite32be(data, base_address + XHI_RNC_REG_OFFSET); } =20 /** @@ -174,7 +174,7 @@ static inline void buffer_icap_set_rnc(void __iomem *ba= se_address, static inline void buffer_icap_set_bram(void __iomem *base_address, u32 offset, u32 data) { - out_be32(base_address + (offset << 2), data); + iowrite32be(data, base_address + (offset << 2)); } =20 /** @@ -255,7 +255,7 @@ static int buffer_icap_device_write(struct hwicap_drvda= ta *drvdata, **/ void buffer_icap_reset(struct hwicap_drvdata *drvdata) { - out_be32(drvdata->base_address + XHI_STATUS_REG_OFFSET, 0xFEFE); + iowrite32be(0xFEFE, drvdata->base_address + XHI_STATUS_REG_OFFSET); } =20 /** diff --git a/drivers/char/xilinx_hwicap/fifo_icap.c b/drivers/char/xilinx_h= wicap/fifo_icap.c index 7bd786fa1be8..928ee4ca3012 100644 --- a/drivers/char/xilinx_hwicap/fifo_icap.c +++ b/drivers/char/xilinx_hwicap/fifo_icap.c @@ -94,7 +94,7 @@ static inline void fifo_icap_fifo_write(struct hwicap_drv= data *drvdata, u32 data) { dev_dbg(drvdata->dev, "fifo_write: %x\n", data); - out_be32(drvdata->base_address + XHI_WF_OFFSET, data); + iowrite32be(data, drvdata->base_address + XHI_WF_OFFSET); } =20 /** @@ -107,7 +107,7 @@ static inline void fifo_icap_fifo_write(struct hwicap_d= rvdata *drvdata, **/ static inline u32 fifo_icap_fifo_read(struct hwicap_drvdata *drvdata) { - u32 data =3D in_be32(drvdata->base_address + XHI_RF_OFFSET); + u32 data =3D ioread32be(drvdata->base_address + XHI_RF_OFFSET); dev_dbg(drvdata->dev, "fifo_read: %x\n", data); return data; } @@ -120,7 +120,7 @@ static inline u32 fifo_icap_fifo_read(struct hwicap_drv= data *drvdata) static inline void fifo_icap_set_read_size(struct hwicap_drvdata *drvdata, u32 data) { - out_be32(drvdata->base_address + XHI_SZ_OFFSET, data); + iowrite32be(data, drvdata->base_address + XHI_SZ_OFFSET); } =20 /** @@ -129,7 +129,7 @@ static inline void fifo_icap_set_read_size(struct hwica= p_drvdata *drvdata, **/ static inline void fifo_icap_start_config(struct hwicap_drvdata *drvdata) { - out_be32(drvdata->base_address + XHI_CR_OFFSET, XHI_CR_WRITE_MASK); + iowrite32be(XHI_CR_WRITE_MASK, drvdata->base_address + XHI_CR_OFFSET); dev_dbg(drvdata->dev, "configuration started\n"); } =20 @@ -139,7 +139,7 @@ static inline void fifo_icap_start_config(struct hwicap= _drvdata *drvdata) **/ static inline void fifo_icap_start_readback(struct hwicap_drvdata *drvdata) { - out_be32(drvdata->base_address + XHI_CR_OFFSET, XHI_CR_READ_MASK); + iowrite32be(XHI_CR_READ_MASK, drvdata->base_address + XHI_CR_OFFSET); dev_dbg(drvdata->dev, "readback started\n"); } =20 @@ -163,7 +163,7 @@ static inline void fifo_icap_start_readback(struct hwic= ap_drvdata *drvdata) **/ u32 fifo_icap_get_status(struct hwicap_drvdata *drvdata) { - u32 status =3D in_be32(drvdata->base_address + XHI_SR_OFFSET); + u32 status =3D ioread32be(drvdata->base_address + XHI_SR_OFFSET); dev_dbg(drvdata->dev, "Getting status =3D %x\n", status); return status; } @@ -177,7 +177,7 @@ u32 fifo_icap_get_status(struct hwicap_drvdata *drvdata) **/ static inline u32 fifo_icap_busy(struct hwicap_drvdata *drvdata) { - u32 status =3D in_be32(drvdata->base_address + XHI_SR_OFFSET); + u32 status =3D ioread32be(drvdata->base_address + XHI_SR_OFFSET); return (status & XHI_SR_DONE_MASK) ? 0 : 1; } =20 @@ -190,7 +190,7 @@ static inline u32 fifo_icap_busy(struct hwicap_drvdata = *drvdata) static inline u32 fifo_icap_write_fifo_vacancy( struct hwicap_drvdata *drvdata) { - return in_be32(drvdata->base_address + XHI_WFV_OFFSET); + return ioread32be(drvdata->base_address + XHI_WFV_OFFSET); } =20 /** @@ -202,7 +202,7 @@ static inline u32 fifo_icap_write_fifo_vacancy( static inline u32 fifo_icap_read_fifo_occupancy( struct hwicap_drvdata *drvdata) { - return in_be32(drvdata->base_address + XHI_RFO_OFFSET); + return ioread32be(drvdata->base_address + XHI_RFO_OFFSET); } =20 /** @@ -372,13 +372,11 @@ void fifo_icap_reset(struct hwicap_drvdata *drvdata) * Reset the device by setting/clearing the RESET bit in the * Control Register. */ - reg_data =3D in_be32(drvdata->base_address + XHI_CR_OFFSET); + reg_data =3D ioread32be(drvdata->base_address + XHI_CR_OFFSET); =20 - out_be32(drvdata->base_address + XHI_CR_OFFSET, - reg_data | XHI_CR_SW_RESET_MASK); + iowrite32be(reg_data | XHI_CR_SW_RESET_MASK, drvdata->base_address + XHI_= CR_OFFSET); =20 - out_be32(drvdata->base_address + XHI_CR_OFFSET, - reg_data & (~XHI_CR_SW_RESET_MASK)); + iowrite32be(reg_data & (~XHI_CR_SW_RESET_MASK), drvdata->base_address + X= HI_CR_OFFSET); =20 } =20 @@ -393,12 +391,10 @@ void fifo_icap_flush_fifo(struct hwicap_drvdata *drvd= ata) * Flush the FIFO by setting/clearing the FIFO Clear bit in the * Control Register. */ - reg_data =3D in_be32(drvdata->base_address + XHI_CR_OFFSET); + reg_data =3D ioread32be(drvdata->base_address + XHI_CR_OFFSET); =20 - out_be32(drvdata->base_address + XHI_CR_OFFSET, - reg_data | XHI_CR_FIFO_CLR_MASK); + iowrite32be(reg_data | XHI_CR_FIFO_CLR_MASK, drvdata->base_address + XHI_= CR_OFFSET); =20 - out_be32(drvdata->base_address + XHI_CR_OFFSET, - reg_data & (~XHI_CR_FIFO_CLR_MASK)); + iowrite32be(reg_data & (~XHI_CR_FIFO_CLR_MASK), drvdata->base_address + X= HI_CR_OFFSET); } =20 --=20 2.54.0