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charset="utf-8" Replace the hardcoded 47-bit DMA mask with a GPU HAL method that provides the correct value for the architecture. Set the DMA mask in Gpu::new(). Gpu owns all DMA allocations for the device, so no concurrent allocations can exist while the constructor is still running. Acked-by: Danilo Krummrich Reviewed-by: Gary Guo Co-developed-by: Alexandre Courbot Signed-off-by: Alexandre Courbot Signed-off-by: John Hubbard Reviewed-by: Eliot Courtney --- drivers/gpu/nova-core/driver.rs | 15 --------------- drivers/gpu/nova-core/gpu.rs | 12 ++++++++++-- drivers/gpu/nova-core/gpu/hal.rs | 8 +++++++- drivers/gpu/nova-core/gpu/hal/gh100.rs | 9 ++++++++- drivers/gpu/nova-core/gpu/hal/tu102.rs | 5 +++++ 5 files changed, 30 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/nova-core/driver.rs b/drivers/gpu/nova-core/driver= .rs index cff5034c2dcd..ade73da68be5 100644 --- a/drivers/gpu/nova-core/driver.rs +++ b/drivers/gpu/nova-core/driver.rs @@ -3,8 +3,6 @@ use kernel::{ auxiliary, device::Core, - dma::Device, - dma::DmaMask, pci, pci::{ Class, @@ -38,14 +36,6 @@ pub(crate) struct NovaCore<'bound> { =20 const BAR0_SIZE: usize =3D SZ_16M; =20 -// For now we only support Ampere which can use up to 47-bit DMA addresses. -// -// TODO: Add an abstraction for this to support newer GPUs which may suppo= rt -// larger DMA addresses. Limiting these GPUs to smaller address widths won= 't -// have any adverse affects, unless installed on systems which require lar= ger -// DMA addresses. These systems should be quite rare. -const GPU_DMA_BITS: u32 =3D 47; - pub(crate) type Bar0 =3D kernel::io::Mmio; =20 kernel::pci_device_table!( @@ -88,11 +78,6 @@ fn probe<'bound>( pdev.enable_device_mem()?; pdev.set_master(); =20 - // SAFETY: No concurrent DMA allocations or mappings can be ma= de because - // the device is still being probed and therefore isn't being = used by - // other threads of execution. - unsafe { pdev.dma_set_mask_and_coherent(DmaMask::new::())? }; - Ok(try_pin_init!(NovaCore { bar: pdev.iomap_region_sized::(0, c"nova-core/b= ar0")?, // TODO: Use `&bar` self-referential pin-init syntax once = available. diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index aed992488db3..38c75df77e16 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -2,6 +2,7 @@ =20 use kernel::{ device, + dma::Device, fmt, io::Io, num::Bounded, @@ -269,7 +270,7 @@ pub(crate) struct Gpu<'gpu> { =20 impl<'gpu> Gpu<'gpu> { pub(crate) fn new( - pdev: &'gpu pci::Device, + pdev: &'gpu pci::Device>, bar: &'gpu Bar0, ) -> impl PinInit + 'gpu { try_pin_init!(Self { @@ -280,7 +281,14 @@ pub(crate) fn new( =20 // We must wait for GFW_BOOT completion before doing any signi= ficant setup on the GPU. _: { - hal::gpu_hal(spec.chipset).wait_gfw_boot_completion(bar) + let hal =3D hal::gpu_hal(spec.chipset); + let dma_mask =3D hal.dma_mask(); + + // SAFETY: `Gpu` owns all DMA allocations for this device,= and we are + // still constructing it, so no concurrent DMA allocations= can exist. + unsafe { pdev.dma_set_mask_and_coherent(dma_mask)? }; + + hal.wait_gfw_boot_completion(bar) .inspect_err(|_| dev_err!(pdev, "GFW boot did not comp= lete\n"))?; }, =20 diff --git a/drivers/gpu/nova-core/gpu/hal.rs b/drivers/gpu/nova-core/gpu/h= al.rs index 788de20ab5d3..0b636b713593 100644 --- a/drivers/gpu/nova-core/gpu/hal.rs +++ b/drivers/gpu/nova-core/gpu/hal.rs @@ -1,6 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 =20 -use kernel::prelude::*; +use kernel::{ + dma::DmaMask, + prelude::*, // +}; =20 use crate::{ driver::Bar0, @@ -16,6 +19,9 @@ pub(crate) trait GpuHal { /// Waits for GFW_BOOT completion if required by this hardware family. fn wait_gfw_boot_completion(&self, bar: &Bar0) -> Result; + + /// Returns the DMA mask for the current architecture. + fn dma_mask(&self) -> DmaMask; } =20 pub(super) fn gpu_hal(chipset: Chipset) -> &'static dyn GpuHal { diff --git a/drivers/gpu/nova-core/gpu/hal/gh100.rs b/drivers/gpu/nova-core= /gpu/hal/gh100.rs index 1ed5bccdda1d..41fbabb04ff8 100644 --- a/drivers/gpu/nova-core/gpu/hal/gh100.rs +++ b/drivers/gpu/nova-core/gpu/hal/gh100.rs @@ -1,6 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 =20 -use kernel::prelude::*; +use kernel::{ + dma::DmaMask, + prelude::*, // +}; =20 use crate::driver::Bar0; =20 @@ -12,6 +15,10 @@ impl GpuHal for Gh100 { fn wait_gfw_boot_completion(&self, _bar: &Bar0) -> Result { Ok(()) } + + fn dma_mask(&self) -> DmaMask { + DmaMask::new::<52>() + } } =20 const GH100: Gh100 =3D Gh100; diff --git a/drivers/gpu/nova-core/gpu/hal/tu102.rs b/drivers/gpu/nova-core= /gpu/hal/tu102.rs index 08dd4434bd72..2881ab03dbcd 100644 --- a/drivers/gpu/nova-core/gpu/hal/tu102.rs +++ b/drivers/gpu/nova-core/gpu/hal/tu102.rs @@ -19,6 +19,7 @@ //! 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charset="utf-8" Hopper and Blackwell GPUs moved the PCI config space mirror from 0x088000 to 0x092000. Select the correct address per architecture when building the GSP system info command. Reviewed-by: Eliot Courtney Co-developed-by: Alexandre Courbot Signed-off-by: Alexandre Courbot Signed-off-by: John Hubbard --- drivers/gpu/nova-core/gpu.rs | 7 +++++++ drivers/gpu/nova-core/gpu/hal.rs | 5 +++++ drivers/gpu/nova-core/gpu/hal/gh100.rs | 9 +++++++++ drivers/gpu/nova-core/gpu/hal/tu102.rs | 9 +++++++++ drivers/gpu/nova-core/gsp/boot.rs | 2 +- drivers/gpu/nova-core/gsp/commands.rs | 8 +++++--- drivers/gpu/nova-core/gsp/fw/commands.rs | 15 +++++++++++---- 7 files changed, 47 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index 38c75df77e16..7dd736e5b190 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -1,5 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 =20 +use core::ops::Range; + use kernel::{ device, dma::Device, @@ -134,6 +136,11 @@ pub(crate) const fn arch(self) -> Architecture { pub(crate) const fn needs_fwsec_bootloader(self) -> bool { matches!(self.arch(), Architecture::Turing) || matches!(self, Self= ::GA100) } + + /// Returns the address range of the PCI config mirror space. + pub(crate) fn pci_config_mirror_range(self) -> Range { + hal::gpu_hal(self).pci_config_mirror_range() + } } =20 // TODO diff --git a/drivers/gpu/nova-core/gpu/hal.rs b/drivers/gpu/nova-core/gpu/h= al.rs index 0b636b713593..cd833bd49b9b 100644 --- a/drivers/gpu/nova-core/gpu/hal.rs +++ b/drivers/gpu/nova-core/gpu/hal.rs @@ -1,5 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 =20 +use core::ops::Range; + use kernel::{ dma::DmaMask, prelude::*, // @@ -22,6 +24,9 @@ pub(crate) trait GpuHal { =20 /// Returns the DMA mask for the current architecture. fn dma_mask(&self) -> DmaMask; + + /// Returns the address range of the PCI config mirror space. + fn pci_config_mirror_range(&self) -> Range; } =20 pub(super) fn gpu_hal(chipset: Chipset) -> &'static dyn GpuHal { diff --git a/drivers/gpu/nova-core/gpu/hal/gh100.rs b/drivers/gpu/nova-core= /gpu/hal/gh100.rs index 41fbabb04ff8..17778a618900 100644 --- a/drivers/gpu/nova-core/gpu/hal/gh100.rs +++ b/drivers/gpu/nova-core/gpu/hal/gh100.rs @@ -1,5 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 =20 +use core::ops::Range; + use kernel::{ dma::DmaMask, prelude::*, // @@ -19,6 +21,13 @@ fn wait_gfw_boot_completion(&self, _bar: &Bar0) -> Resul= t { fn dma_mask(&self) -> DmaMask { DmaMask::new::<52>() } + + fn pci_config_mirror_range(&self) -> Range { + const PCI_CONFIG_MIRROR_START: u32 =3D 0x092000; + const PCI_CONFIG_MIRROR_SIZE: u32 =3D 0x001000; + + PCI_CONFIG_MIRROR_START..PCI_CONFIG_MIRROR_START + PCI_CONFIG_MIRR= OR_SIZE + } } =20 const GH100: Gh100 =3D Gh100; diff --git a/drivers/gpu/nova-core/gpu/hal/tu102.rs b/drivers/gpu/nova-core= /gpu/hal/tu102.rs index 2881ab03dbcd..125478bfe07a 100644 --- a/drivers/gpu/nova-core/gpu/hal/tu102.rs +++ b/drivers/gpu/nova-core/gpu/hal/tu102.rs @@ -18,6 +18,8 @@ //! //! Note that the devinit sequence also needs to run during suspend/resume. =20 +use core::ops::Range; + use kernel::{ dma::DmaMask, io::{ @@ -85,6 +87,13 @@ fn wait_gfw_boot_completion(&self, bar: &Bar0) -> Result= { fn dma_mask(&self) -> DmaMask { DmaMask::new::<47>() } + + fn pci_config_mirror_range(&self) -> Range { + const PCI_CONFIG_MIRROR_START: u32 =3D 0x088000; + const PCI_CONFIG_MIRROR_SIZE: u32 =3D 0x001000; + + PCI_CONFIG_MIRROR_START..PCI_CONFIG_MIRROR_START + PCI_CONFIG_MIRR= OR_SIZE + } } =20 const TU102: Tu102 =3D Tu102; diff --git a/drivers/gpu/nova-core/gsp/boot.rs b/drivers/gpu/nova-core/gsp/= boot.rs index 087ee59da6d9..8c316fa2e585 100644 --- a/drivers/gpu/nova-core/gsp/boot.rs +++ b/drivers/gpu/nova-core/gsp/boot.rs @@ -144,7 +144,7 @@ pub(crate) fn boot( dev_dbg!(pdev, "RISC-V active? {}\n", gsp_falcon.is_riscv_active(b= ar),); =20 self.cmdq - .send_command_no_wait(bar, commands::SetSystemInfo::new(pdev))= ?; + .send_command_no_wait(bar, commands::SetSystemInfo::new(pdev, = chipset))?; self.cmdq .send_command_no_wait(bar, commands::SetRegistry::new())?; =20 diff --git a/drivers/gpu/nova-core/gsp/commands.rs b/drivers/gpu/nova-core/= gsp/commands.rs index 3a365455d10c..f84de9f4f045 100644 --- a/drivers/gpu/nova-core/gsp/commands.rs +++ b/drivers/gpu/nova-core/gsp/commands.rs @@ -19,6 +19,7 @@ }; =20 use crate::{ + gpu::Chipset, gsp::{ cmdq::{ Cmdq, @@ -37,12 +38,13 @@ /// The `GspSetSystemInfo` command. pub(crate) struct SetSystemInfo<'a> { pdev: &'a pci::Device, + chipset: Chipset, } =20 impl<'a> SetSystemInfo<'a> { /// Creates a new `GspSetSystemInfo` command using the parameters of `= pdev`. - pub(crate) fn new(pdev: &'a pci::Device) -> Self { - Self { pdev } + pub(crate) fn new(pdev: &'a pci::Device, chipset: Chips= et) -> Self { + Self { pdev, chipset } } } =20 @@ -53,7 +55,7 @@ impl<'a> CommandToGsp for SetSystemInfo<'a> { type InitError =3D Error; =20 fn init(&self) -> impl Init { - Self::Command::init(self.pdev) + Self::Command::init(self.pdev, self.chipset) } } =20 diff --git a/drivers/gpu/nova-core/gsp/fw/commands.rs b/drivers/gpu/nova-co= re/gsp/fw/commands.rs index 42985d446bae..7bcc41fc7fa0 100644 --- a/drivers/gpu/nova-core/gsp/fw/commands.rs +++ b/drivers/gpu/nova-core/gsp/fw/commands.rs @@ -11,7 +11,10 @@ }, // }; =20 -use crate::gsp::GSP_PAGE_SIZE; +use crate::{ + gpu::Chipset, + gsp::GSP_PAGE_SIZE, // +}; =20 use super::bindings; =20 @@ -25,8 +28,12 @@ pub(crate) struct GspSetSystemInfo { impl GspSetSystemInfo { /// Returns an in-place initializer for the `GspSetSystemInfo` command. #[allow(non_snake_case)] - pub(crate) fn init<'a>(dev: &'a pci::Device) -> impl In= it + 'a { + pub(crate) fn init<'a>( + dev: &'a pci::Device, + chipset: Chipset, + ) -> impl Init + 'a { type InnerGspSystemInfo =3D bindings::GspSystemInfo; + let pci_config_mirror_range =3D chipset.pci_config_mirror_range(); let init_inner =3D try_init!(InnerGspSystemInfo { gpuPhysAddr: dev.resource_start(0)?, gpuPhysFbAddr: dev.resource_start(1)?, @@ -36,8 +43,8 @@ pub(crate) fn init<'a>(dev: &'a pci::Device) -> impl Init; Tue, 2 Jun 2026 03:21:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.201.65 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780370498; cv=fail; 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charset="utf-8" GSP boot needs to know how much framebuffer memory is reserved for the PMU. Compute it per architecture: Blackwell dGPUs reserve a non-zero amount, earlier architectures leave it at zero, matching Open RM behavior. Reviewed-by: Eliot Courtney Co-developed-by: Alexandre Courbot Signed-off-by: Alexandre Courbot Signed-off-by: John Hubbard --- drivers/gpu/nova-core/fb.rs | 3 ++ drivers/gpu/nova-core/fb/hal.rs | 12 +++--- drivers/gpu/nova-core/fb/hal/ga100.rs | 5 +++ drivers/gpu/nova-core/fb/hal/ga102.rs | 7 +++- drivers/gpu/nova-core/fb/hal/gb100.rs | 57 +++++++++++++++++++++++++++ drivers/gpu/nova-core/fb/hal/tu102.rs | 9 +++++ drivers/gpu/nova-core/gsp/fw.rs | 1 + 7 files changed, 88 insertions(+), 6 deletions(-) create mode 100644 drivers/gpu/nova-core/fb/hal/gb100.rs diff --git a/drivers/gpu/nova-core/fb.rs b/drivers/gpu/nova-core/fb.rs index 1fb65d4eb290..d7a4dc944131 100644 --- a/drivers/gpu/nova-core/fb.rs +++ b/drivers/gpu/nova-core/fb.rs @@ -165,6 +165,8 @@ pub(crate) struct FbLayout { pub(crate) wpr2: FbRange, pub(crate) heap: FbRange, pub(crate) vf_partition_count: u8, + /// PMU reserved memory size, in bytes. + pub(crate) pmu_reserved_size: u32, } =20 impl FbLayout { @@ -265,6 +267,7 @@ pub(crate) fn new(chipset: Chipset, bar: &Bar0, gsp_fw:= &GspFirmware) -> Result< wpr2, heap, vf_partition_count: 0, + pmu_reserved_size: hal.pmu_reserved_size(), }) } } diff --git a/drivers/gpu/nova-core/fb/hal.rs b/drivers/gpu/nova-core/fb/hal= .rs index 8b192a503363..b45784ad5f2e 100644 --- a/drivers/gpu/nova-core/fb/hal.rs +++ b/drivers/gpu/nova-core/fb/hal.rs @@ -1,4 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: Copyright (c) 2025-2026 NVIDIA CORPORATION & AF= FILIATES. All rights reserved. =20 use kernel::prelude::*; =20 @@ -12,6 +13,7 @@ =20 mod ga100; mod ga102; +mod gb100; mod tu102; =20 pub(crate) trait FbHal { @@ -29,6 +31,9 @@ pub(crate) trait FbHal { /// Returns the VRAM size, in bytes. fn vidmem_size(&self, bar: &Bar0) -> u64; =20 + /// Returns the amount of VRAM to reserve for the PMU. + fn pmu_reserved_size(&self) -> u32; + /// Returns the FRTS size, in bytes. fn frts_size(&self) -> u64; } @@ -38,10 +43,7 @@ pub(super) fn fb_hal(chipset: Chipset) -> &'static dyn F= bHal { match chipset.arch() { Architecture::Turing =3D> tu102::TU102_HAL, Architecture::Ampere if chipset =3D=3D Chipset::GA100 =3D> ga100::= GA100_HAL, - Architecture::Ampere =3D> ga102::GA102_HAL, - Architecture::Ada - | Architecture::Hopper - | Architecture::BlackwellGB10x - | Architecture::BlackwellGB20x =3D> ga102::GA102_HAL, + Architecture::Ampere | Architecture::Ada | Architecture::Hopper = =3D> ga102::GA102_HAL, + Architecture::BlackwellGB10x | Architecture::BlackwellGB20x =3D> g= b100::GB100_HAL, } } diff --git a/drivers/gpu/nova-core/fb/hal/ga100.rs b/drivers/gpu/nova-core/= fb/hal/ga100.rs index 2f5871d915c3..0f5132aa9c31 100644 --- a/drivers/gpu/nova-core/fb/hal/ga100.rs +++ b/drivers/gpu/nova-core/fb/hal/ga100.rs @@ -1,4 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: Copyright (c) 2025-2026 NVIDIA CORPORATION & AF= FILIATES. All rights reserved. =20 use kernel::{ io::Io, @@ -67,6 +68,10 @@ fn vidmem_size(&self, bar: &Bar0) -> u64 { super::tu102::vidmem_size_gp102(bar) } =20 + fn pmu_reserved_size(&self) -> u32 { + super::tu102::pmu_reserved_size_tu102() + } + // GA100 is a special case where its FRTS region exists, but is empty.= We // return a size of 0 because we still need to record where the region= starts. fn frts_size(&self) -> u64 { diff --git a/drivers/gpu/nova-core/fb/hal/ga102.rs b/drivers/gpu/nova-core/= fb/hal/ga102.rs index 3bb66f64bef7..17a2fef1ad44 100644 --- a/drivers/gpu/nova-core/fb/hal/ga102.rs +++ b/drivers/gpu/nova-core/fb/hal/ga102.rs @@ -1,4 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: Copyright (c) 2025-2026 NVIDIA CORPORATION & AF= FILIATES. All rights reserved. =20 use kernel::{ io::Io, @@ -11,7 +12,7 @@ regs, // }; =20 -fn vidmem_size_ga102(bar: &Bar0) -> u64 { +pub(super) fn vidmem_size_ga102(bar: &Bar0) -> u64 { bar.read(regs::NV_USABLE_FB_SIZE_IN_MB).usable_fb_size() } =20 @@ -36,6 +37,10 @@ fn vidmem_size(&self, bar: &Bar0) -> u64 { vidmem_size_ga102(bar) } =20 + fn pmu_reserved_size(&self) -> u32 { + super::tu102::pmu_reserved_size_tu102() + } + fn frts_size(&self) -> u64 { super::tu102::frts_size_tu102() } diff --git a/drivers/gpu/nova-core/fb/hal/gb100.rs b/drivers/gpu/nova-core/= fb/hal/gb100.rs new file mode 100644 index 000000000000..c78027c26a9e --- /dev/null +++ b/drivers/gpu/nova-core/fb/hal/gb100.rs @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIA= TES. All rights reserved. + +//! Blackwell framebuffer HAL. + +use kernel::{ + prelude::*, + ptr::{ + const_align_up, + Alignment, // + }, + sizes::*, // +}; + +use crate::{ + driver::Bar0, + fb::hal::FbHal, + num::usize_into_u32, // +}; + +struct Gb100; + +const fn pmu_reserved_size_gb100() -> u32 { + usize_into_u32::<{ const_align_up(SZ_8M + SZ_16M + SZ_4K, Alignment::n= ew::()).unwrap() }>( + ) +} + +impl FbHal for Gb100 { + fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64 { + super::ga100::read_sysmem_flush_page_ga100(bar) + } + + fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result { + super::ga100::write_sysmem_flush_page_ga100(bar, addr); + + Ok(()) + } + + fn supports_display(&self, bar: &Bar0) -> bool { + super::ga100::display_enabled_ga100(bar) + } + + fn vidmem_size(&self, bar: &Bar0) -> u64 { + super::ga102::vidmem_size_ga102(bar) + } + + fn pmu_reserved_size(&self) -> u32 { + pmu_reserved_size_gb100() + } + + fn frts_size(&self) -> u64 { + super::tu102::frts_size_tu102() + } +} + +const GB100: Gb100 =3D Gb100; +pub(super) const GB100_HAL: &dyn FbHal =3D &GB100; diff --git a/drivers/gpu/nova-core/fb/hal/tu102.rs b/drivers/gpu/nova-core/= fb/hal/tu102.rs index 22c174bf1472..1755bbc27866 100644 --- a/drivers/gpu/nova-core/fb/hal/tu102.rs +++ b/drivers/gpu/nova-core/fb/hal/tu102.rs @@ -1,4 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: Copyright (c) 2025-2026 NVIDIA CORPORATION & AF= FILIATES. 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charset="utf-8" Hopper and Blackwell need a larger non-WPR heap than the 1 MiB that earlier architectures use. Hopper and Blackwell GB10x need 2 MiB, while Blackwell GB20x needs 2 MiB + 128 KiB. These sizes diverge by family, so give Hopper and each Blackwell family its own framebuffer HAL and select the non-WPR heap size per chipset family. Reviewed-by: Eliot Courtney Signed-off-by: John Hubbard --- drivers/gpu/nova-core/fb.rs | 5 ++- drivers/gpu/nova-core/fb/hal.rs | 11 ++++-- drivers/gpu/nova-core/fb/hal/ga100.rs | 4 +++ drivers/gpu/nova-core/fb/hal/ga102.rs | 4 +++ drivers/gpu/nova-core/fb/hal/gb100.rs | 9 +++-- drivers/gpu/nova-core/fb/hal/gb202.rs | 52 +++++++++++++++++++++++++++ drivers/gpu/nova-core/fb/hal/gh100.rs | 50 ++++++++++++++++++++++++++ drivers/gpu/nova-core/fb/hal/tu102.rs | 8 +++++ 8 files changed, 136 insertions(+), 7 deletions(-) create mode 100644 drivers/gpu/nova-core/fb/hal/gb202.rs create mode 100644 drivers/gpu/nova-core/fb/hal/gh100.rs diff --git a/drivers/gpu/nova-core/fb.rs b/drivers/gpu/nova-core/fb.rs index d7a4dc944131..0aaee718c2c3 100644 --- a/drivers/gpu/nova-core/fb.rs +++ b/drivers/gpu/nova-core/fb.rs @@ -252,9 +252,8 @@ pub(crate) fn new(chipset: Chipset, bar: &Bar0, gsp_fw:= &GspFirmware) -> Result< }; =20 let heap =3D { - const HEAP_SIZE: u64 =3D u64::SZ_1M; - - FbRange(wpr2.start - HEAP_SIZE..wpr2.start) + let heap_size =3D u64::from(hal.non_wpr_heap_size()); + FbRange(wpr2.start - heap_size..wpr2.start) }; =20 Ok(Self { diff --git a/drivers/gpu/nova-core/fb/hal.rs b/drivers/gpu/nova-core/fb/hal= .rs index b45784ad5f2e..be9e75f990f0 100644 --- a/drivers/gpu/nova-core/fb/hal.rs +++ b/drivers/gpu/nova-core/fb/hal.rs @@ -14,6 +14,8 @@ mod ga100; mod ga102; mod gb100; +mod gb202; +mod gh100; mod tu102; =20 pub(crate) trait FbHal { @@ -34,6 +36,9 @@ pub(crate) trait FbHal { /// Returns the amount of VRAM to reserve for the PMU. fn pmu_reserved_size(&self) -> u32; =20 + /// Returns the non-WPR heap size for this chipset, in bytes. + fn non_wpr_heap_size(&self) -> u32; + /// Returns the FRTS size, in bytes. fn frts_size(&self) -> u64; } @@ -43,7 +48,9 @@ pub(super) fn fb_hal(chipset: Chipset) -> &'static dyn Fb= Hal { match chipset.arch() { Architecture::Turing =3D> tu102::TU102_HAL, Architecture::Ampere if chipset =3D=3D Chipset::GA100 =3D> ga100::= GA100_HAL, - Architecture::Ampere | Architecture::Ada | Architecture::Hopper = =3D> ga102::GA102_HAL, - Architecture::BlackwellGB10x | Architecture::BlackwellGB20x =3D> g= b100::GB100_HAL, + Architecture::Ampere | Architecture::Ada =3D> ga102::GA102_HAL, + Architecture::Hopper =3D> gh100::GH100_HAL, + Architecture::BlackwellGB10x =3D> gb100::GB100_HAL, + Architecture::BlackwellGB20x =3D> gb202::GB202_HAL, } } diff --git a/drivers/gpu/nova-core/fb/hal/ga100.rs b/drivers/gpu/nova-core/= fb/hal/ga100.rs index 0f5132aa9c31..af95f1bdd273 100644 --- a/drivers/gpu/nova-core/fb/hal/ga100.rs +++ b/drivers/gpu/nova-core/fb/hal/ga100.rs @@ -72,6 +72,10 @@ fn pmu_reserved_size(&self) -> u32 { super::tu102::pmu_reserved_size_tu102() } =20 + fn non_wpr_heap_size(&self) -> u32 { + super::tu102::non_wpr_heap_size_tu102() + } + // GA100 is a special case where its FRTS region exists, but is empty.= We // return a size of 0 because we still need to record where the region= starts. fn frts_size(&self) -> u64 { diff --git a/drivers/gpu/nova-core/fb/hal/ga102.rs b/drivers/gpu/nova-core/= fb/hal/ga102.rs index 17a2fef1ad44..e06dbb08349e 100644 --- a/drivers/gpu/nova-core/fb/hal/ga102.rs +++ b/drivers/gpu/nova-core/fb/hal/ga102.rs @@ -41,6 +41,10 @@ fn pmu_reserved_size(&self) -> u32 { super::tu102::pmu_reserved_size_tu102() } =20 + fn non_wpr_heap_size(&self) -> u32 { + super::tu102::non_wpr_heap_size_tu102() + } + fn frts_size(&self) -> u64 { super::tu102::frts_size_tu102() } diff --git a/drivers/gpu/nova-core/fb/hal/gb100.rs b/drivers/gpu/nova-core/= fb/hal/gb100.rs index c78027c26a9e..8d63350abf8a 100644 --- a/drivers/gpu/nova-core/fb/hal/gb100.rs +++ b/drivers/gpu/nova-core/fb/hal/gb100.rs @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 // SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIA= TES. All rights reserved. =20 -//! Blackwell framebuffer HAL. +//! Blackwell GB10x framebuffer HAL. =20 use kernel::{ prelude::*, @@ -20,7 +20,7 @@ =20 struct Gb100; =20 -const fn pmu_reserved_size_gb100() -> u32 { +pub(super) const fn pmu_reserved_size_gb100() -> u32 { usize_into_u32::<{ const_align_up(SZ_8M + SZ_16M + SZ_4K, Alignment::n= ew::()).unwrap() }>( ) } @@ -48,6 +48,11 @@ fn pmu_reserved_size(&self) -> u32 { pmu_reserved_size_gb100() } =20 + fn non_wpr_heap_size(&self) -> u32 { + // Non-WPR heap for GB10x (see Open RM: kgspGetNonWprHeapSize, GB1= 00/GB102). + u32::SZ_2M + } + fn frts_size(&self) -> u64 { super::tu102::frts_size_tu102() } diff --git a/drivers/gpu/nova-core/fb/hal/gb202.rs b/drivers/gpu/nova-core/= fb/hal/gb202.rs new file mode 100644 index 000000000000..542c1d7429e9 --- /dev/null +++ b/drivers/gpu/nova-core/fb/hal/gb202.rs @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIA= TES. All rights reserved. + +//! Blackwell GB20x framebuffer HAL. + +use kernel::{ + prelude::*, + sizes::SizeConstants, // +}; + +use crate::{ + driver::Bar0, + fb::hal::FbHal, // +}; + +struct Gb202; + +impl FbHal for Gb202 { + fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64 { + super::ga100::read_sysmem_flush_page_ga100(bar) + } + + fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result { + super::ga100::write_sysmem_flush_page_ga100(bar, addr); + + Ok(()) + } + + fn supports_display(&self, bar: &Bar0) -> bool { + super::ga100::display_enabled_ga100(bar) + } + + fn vidmem_size(&self, bar: &Bar0) -> u64 { + super::ga102::vidmem_size_ga102(bar) + } + + fn pmu_reserved_size(&self) -> u32 { + super::gb100::pmu_reserved_size_gb100() + } + + fn non_wpr_heap_size(&self) -> u32 { + // Non-WPR heap for GB20x (see Open RM: kgspGetNonWprHeapSize, GB2= 02+). + u32::SZ_2M + u32::SZ_128K + } + + fn frts_size(&self) -> u64 { + super::tu102::frts_size_tu102() + } +} + +const GB202: Gb202 =3D Gb202; +pub(super) const GB202_HAL: &dyn FbHal =3D &GB202; diff --git a/drivers/gpu/nova-core/fb/hal/gh100.rs b/drivers/gpu/nova-core/= fb/hal/gh100.rs new file mode 100644 index 000000000000..8f79c72b1823 --- /dev/null +++ b/drivers/gpu/nova-core/fb/hal/gh100.rs @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIA= TES. All rights reserved. + +use kernel::{ + prelude::*, + sizes::SizeConstants, // +}; + +use crate::{ + driver::Bar0, + fb::hal::FbHal, // +}; + +struct Gh100; + +impl FbHal for Gh100 { + fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64 { + super::ga100::read_sysmem_flush_page_ga100(bar) + } + + fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result { + super::ga100::write_sysmem_flush_page_ga100(bar, addr); + + Ok(()) + } + + fn supports_display(&self, bar: &Bar0) -> bool { + super::ga100::display_enabled_ga100(bar) + } + + fn vidmem_size(&self, bar: &Bar0) -> u64 { + super::ga102::vidmem_size_ga102(bar) + } + + fn pmu_reserved_size(&self) -> u32 { + super::tu102::pmu_reserved_size_tu102() + } + + fn non_wpr_heap_size(&self) -> u32 { + // Non-WPR heap for Hopper (see Open RM: kgspCalculateFbLayout_GH1= 00). + u32::SZ_2M + } + + fn frts_size(&self) -> u64 { + super::tu102::frts_size_tu102() + } +} + +const GH100: Gh100 =3D Gh100; +pub(super) const GH100_HAL: &dyn FbHal =3D &GH100; diff --git a/drivers/gpu/nova-core/fb/hal/tu102.rs b/drivers/gpu/nova-core/= fb/hal/tu102.rs index 1755bbc27866..62d9357987f7 100644 --- a/drivers/gpu/nova-core/fb/hal/tu102.rs +++ b/drivers/gpu/nova-core/fb/hal/tu102.rs @@ -44,6 +44,10 @@ pub(super) const fn pmu_reserved_size_tu102() -> u32 { 0 } =20 +pub(super) const fn non_wpr_heap_size_tu102() -> u32 { + u32::SZ_1M +} + pub(super) const fn frts_size_tu102() -> u64 { u64::SZ_1M } @@ -71,6 +75,10 @@ fn pmu_reserved_size(&self) -> u32 { pmu_reserved_size_tu102() } =20 + fn non_wpr_heap_size(&self) -> u32 { + non_wpr_heap_size_tu102() + } + fn frts_size(&self) -> u64 { frts_size_tu102() } --=20 2.54.0 From nobody Mon Jun 8 04:24:52 2026 Received: from CY3PR05CU001.outbound.protection.outlook.com (mail-westcentralusazon11013065.outbound.protection.outlook.com [40.93.201.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C84CE35E93E for ; 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charset="utf-8" The GSP-RM boot working memory portion of the WPR2 heap must be larger on Hopper and later GPUs than on Turing, Ampere, and Ada. Select the larger value for those generations. Reviewed-by: Eliot Courtney Signed-off-by: John Hubbard --- drivers/gpu/nova-core/gsp/fw.rs | 20 +++++++++++++------ .../gpu/nova-core/gsp/fw/r570_144/bindings.rs | 1 + 2 files changed, 15 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/nova-core/gsp/fw.rs b/drivers/gpu/nova-core/gsp/fw= .rs index 919d3ab00075..0c54e8bf4bb3 100644 --- a/drivers/gpu/nova-core/gsp/fw.rs +++ b/drivers/gpu/nova-core/gsp/fw.rs @@ -1,4 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: Copyright (c) 2025-2026 NVIDIA CORPORATION & AF= FILIATES. All rights reserved. =20 pub(crate) mod commands; mod r570_144; @@ -29,7 +30,10 @@ use crate::{ fb::FbLayout, firmware::gsp::GspFirmware, - gpu::Chipset, + gpu::{ + Architecture, + Chipset, // + }, gsp::{ cmdq::Cmdq, // GSP_PAGE_SIZE, @@ -106,11 +110,15 @@ enum GspFwHeapParams {} impl GspFwHeapParams { /// Returns the amount of GSP-RM heap memory used during GSP-RM boot a= nd initialization (up to /// and including the first client subdevice allocation). - fn base_rm_size(_chipset: Chipset) -> u64 { - // TODO: this needs to be updated to return the correct value for = Hopper+ once support for - // them is added: - // u64::from(bindings::GSP_FW_HEAP_PARAM_BASE_RM_SIZE_GH100) - u64::from(bindings::GSP_FW_HEAP_PARAM_BASE_RM_SIZE_TU10X) + fn base_rm_size(chipset: Chipset) -> u64 { + match chipset.arch() { + Architecture::Turing | Architecture::Ampere | Architecture::Ad= a =3D> { + u64::from(bindings::GSP_FW_HEAP_PARAM_BASE_RM_SIZE_TU10X) + } + Architecture::Hopper | Architecture::BlackwellGB10x | Architec= ture::BlackwellGB20x =3D> { + u64::from(bindings::GSP_FW_HEAP_PARAM_BASE_RM_SIZE_GH100) + } + } } =20 /// Returns the amount of heap memory required to support a single cha= nnel allocation. diff --git a/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs b/drivers/gp= u/nova-core/gsp/fw/r570_144/bindings.rs index f82ed097b283..1d592bd3f9ed 100644 --- a/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs +++ b/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs @@ -37,6 +37,7 @@ fn fmt(&self, fmt: &mut ::core::fmt::Formatter<'_>) -> ::= core::fmt::Result { pub const GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS2: u32 =3D 0; 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charset="utf-8" Blackwell GPUs moved the sysmem flush page registers away from the Ampere/Ada location. GB10x routes the flush through a pair of HSHUB0 register sets (primary and egress) that must both be programmed to the same address. GB20x routes it through FBHUB0. Define these registers relative to their HSHUB0 and FBHUB0 bases, as Open RM does, and implement the flush paths in the GB10x and GB20x framebuffer HALs. Signed-off-by: John Hubbard Reviewed-by: Eliot Courtney --- drivers/gpu/nova-core/fb/hal/gb100.rs | 66 +++++++++++++++++++++++++-- drivers/gpu/nova-core/fb/hal/gb202.rs | 49 ++++++++++++++++++-- drivers/gpu/nova-core/regs.rs | 45 ++++++++++++++++++ 3 files changed, 154 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/nova-core/fb/hal/gb100.rs b/drivers/gpu/nova-core/= fb/hal/gb100.rs index 8d63350abf8a..ecea4ff446ff 100644 --- a/drivers/gpu/nova-core/fb/hal/gb100.rs +++ b/drivers/gpu/nova-core/fb/hal/gb100.rs @@ -4,6 +4,14 @@ //! Blackwell GB10x framebuffer HAL. =20 use kernel::{ + io::{ + register::{ + RegisterBase, + WithBase, // + }, + Io, // + }, + num::Bounded, prelude::*, ptr::{ const_align_up, @@ -15,11 +23,61 @@ use crate::{ driver::Bar0, fb::hal::FbHal, - num::usize_into_u32, // + num::usize_into_u32, + regs, // }; =20 struct Gb100; =20 +impl RegisterBase for Gb100 { + const BASE: usize =3D 0x0087_0000; +} + +fn read_sysmem_flush_page_gb100(bar: &Bar0) -> u64 { + let lo =3D u64::from( + bar.read(regs::NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_LO::of::= ()) + .adr(), + ); + let hi =3D u64::from( + bar.read(regs::NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_HI::of::= ()) + .adr(), + ); + + lo | (hi << 32) +} + +/// Write the sysmem flush page address through the GB10x HSHUB0 registers. +/// +/// Both the primary and EG (egress) register pairs must be programmed to = the same address, +/// as required by hardware. +fn write_sysmem_flush_page_gb100(bar: &Bar0, addr: Bounded) { + // CAST: lower 32 bits. Hardware ignores bits 7:0. + let addr_lo =3D *addr as u32; + let addr_hi =3D addr.shr::<32, 20>().cast::(); + + // Write HI first. The hardware will trigger the flush on the LO write. + + // Primary HSHUB pair. + bar.write( + regs::NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_HI::of::(), + regs::NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_HI::zeroed().with_adr(ad= dr_hi), + ); + bar.write( + regs::NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_LO::of::(), + regs::NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_LO::zeroed().with_adr(ad= dr_lo), + ); + + // EG (egress) pair -- must match the primary pair. + bar.write( + regs::NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_HI::of::(), + regs::NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_HI::zeroed().with_adr= (addr_hi), + ); + bar.write( + regs::NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_LO::of::(), + regs::NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_LO::zeroed().with_adr= (addr_lo), + ); +} + pub(super) const fn pmu_reserved_size_gb100() -> u32 { usize_into_u32::<{ const_align_up(SZ_8M + SZ_16M + SZ_4K, Alignment::n= ew::()).unwrap() }>( ) @@ -27,11 +85,13 @@ pub(super) const fn pmu_reserved_size_gb100() -> u32 { =20 impl FbHal for Gb100 { fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64 { - super::ga100::read_sysmem_flush_page_ga100(bar) + read_sysmem_flush_page_gb100(bar) } =20 fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result { - super::ga100::write_sysmem_flush_page_ga100(bar, addr); + let addr =3D Bounded::::try_new(addr).ok_or(EINVAL)?; + + write_sysmem_flush_page_gb100(bar, addr); =20 Ok(()) } diff --git a/drivers/gpu/nova-core/fb/hal/gb202.rs b/drivers/gpu/nova-core/= fb/hal/gb202.rs index 542c1d7429e9..fa5c3f7f2b2e 100644 --- a/drivers/gpu/nova-core/fb/hal/gb202.rs +++ b/drivers/gpu/nova-core/fb/hal/gb202.rs @@ -4,24 +4,67 @@ //! Blackwell GB20x framebuffer HAL. =20 use kernel::{ + io::{ + register::{ + RegisterBase, + WithBase, // + }, + Io, // + }, + num::Bounded, prelude::*, sizes::SizeConstants, // }; =20 use crate::{ driver::Bar0, - fb::hal::FbHal, // + fb::hal::FbHal, + regs, // }; =20 struct Gb202; =20 +impl RegisterBase for Gb202 { + const BASE: usize =3D 0x008a_0000; +} + +fn read_sysmem_flush_page_gb202(bar: &Bar0) -> u64 { + let lo =3D u64::from( + bar.read(regs::NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_LO::of::= ()) + .adr(), + ); + let hi =3D u64::from( + bar.read(regs::NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI::of::= ()) + .adr(), + ); + + lo | (hi << 32) +} + +/// Write the sysmem flush page address through the GB20x FBHUB0 registers. +fn write_sysmem_flush_page_gb202(bar: &Bar0, addr: Bounded) { + // Write HI first. The hardware will trigger the flush on the LO write. + bar.write( + regs::NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI::of::(), + regs::NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI::zeroed() + .with_adr(addr.shr::<32, 20>().cast::()), + ); + bar.write( + regs::NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_LO::of::(), + // CAST: lower 32 bits. Hardware ignores bits 7:0. + regs::NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_LO::zeroed().with_adr(*a= ddr as u32), + ); +} + impl FbHal for Gb202 { fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64 { - super::ga100::read_sysmem_flush_page_ga100(bar) + read_sysmem_flush_page_gb202(bar) } =20 fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result { - super::ga100::write_sysmem_flush_page_ga100(bar, addr); + let addr =3D Bounded::::try_new(addr).ok_or(EINVAL)?; + + write_sysmem_flush_page_gb202(bar, addr); =20 Ok(()) } diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 356fbf364ea5..b39647684dd1 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -1,4 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: Copyright (c) 2025-2026 NVIDIA CORPORATION & AF= FILIATES. All rights reserved. =20 use kernel::{ io::{ @@ -147,6 +148,50 @@ fn fmt(&self, f: &mut kernel::fmt::Formatter<'_>) -> k= ernel::fmt::Result { } } =20 +/// Base of the GB10x HSHUB0 register window (`NV_HSHUB0_PRIV_BASE` in Ope= n RM). +/// +/// The base is provided by the GB10x framebuffer HAL. +pub(crate) struct Hshub0Base(()); + +/// Base of the GB20x FBHUB0 register window (`NV_FBHUB0_PRI_BASE` in Open= RM). +/// +/// The base is provided by the GB20x framebuffer HAL. +pub(crate) struct Fbhub0Base(()); + +register! { + // GB10x sysmem flush registers, relative to the HSHUB0 base. GB10x ro= utes sysmembar + // through a primary and an EG (egress) pair that must both be program= med to the same + // address. Hardware ignores bits 7:0 of each LO register. The boot pa= th uses a fixed + // HSHUB0 base, so the multiple runtime-discovered HSHUB bases are not= needed here. + pub(crate) NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_LO(u32) @ Hshub0Base + = 0x00000e50 { + 31:0 adr =3D> u32; + } + + pub(crate) NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_HI(u32) @ Hshub0Base + = 0x00000e54 { + 19:0 adr; + } + + pub(crate) NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_LO(u32) @ Hshub0Base= + 0x000006c0 { + 31:0 adr =3D> u32; + } + + pub(crate) NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_HI(u32) @ Hshub0Base= + 0x000006c4 { + 19:0 adr; + } + + // GB20x sysmem flush registers, relative to the FBHUB0 base. Unlike t= he older + // NV_PFB_NISO_FLUSH_SYSMEM_ADDR registers which encode the address wi= th an 8-bit + // right-shift, these take the raw address split into lower and upper = halves. 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charset="utf-8" Introduce a single ELF format abstraction that ties each ELF header type to its matching section-header type. This keeps the shared section parser ready for upcoming ELF32 support and avoids mixing 32-bit and 64-bit ELF layouts by mistake. Reviewed-by: Eliot Courtney Signed-off-by: John Hubbard --- drivers/gpu/nova-core/firmware.rs | 112 +++++++++++++++++++++++------- 1 file changed, 85 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firm= ware.rs index 3aac073efee2..38088e950980 100644 --- a/drivers/gpu/nova-core/firmware.rs +++ b/drivers/gpu/nova-core/firmware.rs @@ -1,4 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: Copyright (c) 2025-2026 NVIDIA CORPORATION & AF= FILIATES. All rights reserved. =20 //! Contains structures and functions dedicated to the parsing, building a= nd patching of firmwares //! to be loaded into a given execution unit. @@ -467,17 +468,72 @@ mod elf { transmute::FromBytes, // }; =20 + /// Trait to abstract over ELF header differences. + trait ElfHeader: FromBytes { + fn shnum(&self) -> u16; + fn shoff(&self) -> u64; + fn shstrndx(&self) -> u16; + } + + /// Trait to abstract over ELF section-header differences. + trait ElfSectionHeader: FromBytes { + fn name(&self) -> u32; + fn offset(&self) -> u64; + fn size(&self) -> u64; + } + + /// Trait describing a matching ELF header and section-header format. + trait ElfFormat { + type Header: ElfHeader; + type SectionHeader: ElfSectionHeader; + } + /// Newtype to provide a [`FromBytes`] implementation. #[repr(transparent)] struct Elf64Hdr(bindings::elf64_hdr); // SAFETY: all bit patterns are valid for this type, and it doesn't us= e interior mutability. unsafe impl FromBytes for Elf64Hdr {} =20 + impl ElfHeader for Elf64Hdr { + fn shnum(&self) -> u16 { + self.0.e_shnum + } + + fn shoff(&self) -> u64 { + self.0.e_shoff + } + + fn shstrndx(&self) -> u16 { + self.0.e_shstrndx + } + } + #[repr(transparent)] struct Elf64SHdr(bindings::elf64_shdr); // SAFETY: all bit patterns are valid for this type, and it doesn't us= e interior mutability. unsafe impl FromBytes for Elf64SHdr {} =20 + impl ElfSectionHeader for Elf64SHdr { + fn name(&self) -> u32 { + self.0.sh_name + } + + fn offset(&self) -> u64 { + self.0.sh_offset + } + + fn size(&self) -> u64 { + self.0.sh_size + } + } + + struct Elf64Format; + + impl ElfFormat for Elf64Format { + type Header =3D Elf64Hdr; + type SectionHeader =3D Elf64SHdr; + } + /// Returns a NULL-terminated string from the ELF image at `offset`. fn elf_str(elf: &[u8], offset: u64) -> Option<&str> { let idx =3D usize::try_from(offset).ok()?; @@ -485,47 +541,49 @@ fn elf_str(elf: &[u8], offset: u64) -> Option<&str> { CStr::from_bytes_until_nul(bytes).ok()?.to_str().ok() } =20 - /// Tries to extract section with name `name` from the ELF64 image `el= f`, and returns it. - pub(super) fn elf64_section<'a, 'b>(elf: &'a [u8], name: &'b str) -> O= ption<&'a [u8]> { - let hdr =3D &elf - .get(0..size_of::()) - .and_then(Elf64Hdr::from_bytes)? - .0; - - // Get all the section headers. - let mut shdr =3D { - let shdr_num =3D usize::from(hdr.e_shnum); - let shdr_start =3D usize::try_from(hdr.e_shoff).ok()?; - let shdr_end =3D shdr_num - .checked_mul(size_of::()) - .and_then(|v| v.checked_add(shdr_start))?; - - elf.get(shdr_start..shdr_end) - .map(|slice| slice.chunks_exact(size_of::()))? - }; + fn elf_section_generic<'a, F>(elf: &'a [u8], name: &str) -> Option<&'a= [u8]> + where + F: ElfFormat, + { + let hdr =3D F::Header::from_bytes(elf.get(0..size_of::(= ))?)?; + + let shdr_num =3D usize::from(hdr.shnum()); + let shdr_start =3D usize::try_from(hdr.shoff()).ok()?; + let shdr_end =3D shdr_num + .checked_mul(size_of::()) + .and_then(|v| v.checked_add(shdr_start))?; + + // Get all the section headers as an iterator over byte chunks. + let shdr_bytes =3D elf.get(shdr_start..shdr_end)?; + let mut shdr_iter =3D shdr_bytes.chunks_exact(size_of::()); =20 // Get the strings table. - let strhdr =3D shdr + let strhdr =3D shdr_iter .clone() - .nth(usize::from(hdr.e_shstrndx)) - .and_then(Elf64SHdr::from_bytes)?; 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charset="utf-8" Some GPU firmware images are packaged as 32-bit ELF rather than 64-bit. Add a 32-bit implementation of the shared ELF section-parsing abstraction so those images can be parsed alongside the existing 64-bit path. Reviewed-by: Eliot Courtney Signed-off-by: John Hubbard --- drivers/gpu/nova-core/firmware.rs | 53 +++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firm= ware.rs index 38088e950980..e4dcc9a87b7e 100644 --- a/drivers/gpu/nova-core/firmware.rs +++ b/drivers/gpu/nova-core/firmware.rs @@ -534,6 +534,53 @@ impl ElfFormat for Elf64Format { type SectionHeader =3D Elf64SHdr; } =20 + /// Newtype to provide [`FromBytes`] and [`ElfHeader`] implementations= for ELF32. + #[repr(transparent)] + struct Elf32Hdr(bindings::elf32_hdr); + // SAFETY: all bit patterns are valid for this type, and it doesn't us= e interior mutability. + unsafe impl FromBytes for Elf32Hdr {} + + impl ElfHeader for Elf32Hdr { + fn shnum(&self) -> u16 { + self.0.e_shnum + } + + fn shoff(&self) -> u64 { + u64::from(self.0.e_shoff) + } + + fn shstrndx(&self) -> u16 { + self.0.e_shstrndx + } + } + + /// Newtype to provide [`FromBytes`] and [`ElfSectionHeader`] implemen= tations for ELF32. + #[repr(transparent)] + struct Elf32SHdr(bindings::elf32_shdr); + // SAFETY: all bit patterns are valid for this type, and it doesn't us= e interior mutability. + unsafe impl FromBytes for Elf32SHdr {} + + impl ElfSectionHeader for Elf32SHdr { + fn name(&self) -> u32 { + self.0.sh_name + } + + fn offset(&self) -> u64 { + u64::from(self.0.sh_offset) + } + + fn size(&self) -> u64 { + u64::from(self.0.sh_size) + } + } + + struct Elf32Format; + + impl ElfFormat for Elf32Format { + type Header =3D Elf32Hdr; + type SectionHeader =3D Elf32SHdr; + } + /// Returns a NULL-terminated string from the ELF image at `offset`. fn elf_str(elf: &[u8], offset: u64) -> Option<&str> { let idx =3D usize::try_from(offset).ok()?; @@ -586,4 +633,10 @@ fn elf_section_generic<'a, F>(elf: &'a [u8], name: &st= r) -> Option<&'a [u8]> pub(super) fn elf64_section<'a>(elf: &'a [u8], name: &str) -> Option<&= 'a [u8]> { elf_section_generic::(elf, name) } + + /// Extract the section with name `name` from the ELF32 image `elf`. + #[expect(dead_code)] + pub(super) fn elf32_section<'a>(elf: &'a [u8], name: &str) -> Option<&= 'a [u8]> { + elf_section_generic::(elf, name) + } } --=20 2.54.0 From nobody Mon Jun 8 04:24:52 2026 Received: from PH7PR06CU001.outbound.protection.outlook.com (mail-westus3azon11010028.outbound.protection.outlook.com [52.101.201.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E40D8366814 for ; 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charset="utf-8" A firmware image may be either a 32-bit or a 64-bit ELF, and callers should not have to know which. Detect the ELF class from the image header at parse time and dispatch to the matching parser, so a single entry point handles both layouts. Reviewed-by: Eliot Courtney Signed-off-by: John Hubbard --- drivers/gpu/nova-core/firmware.rs | 27 +++++++++++++++++++++++---- drivers/gpu/nova-core/firmware/gsp.rs | 4 ++-- 2 files changed, 25 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firm= ware.rs index e4dcc9a87b7e..87588cb24f11 100644 --- a/drivers/gpu/nova-core/firmware.rs +++ b/drivers/gpu/nova-core/firmware.rs @@ -629,14 +629,33 @@ fn elf_section_generic<'a, F>(elf: &'a [u8], name: &s= tr) -> Option<&'a [u8]> }) } =20 - /// Tries to extract section with name `name` from the ELF64 image `el= f`, and returns it. - pub(super) fn elf64_section<'a>(elf: &'a [u8], name: &str) -> Option<&= 'a [u8]> { + /// Extract the section with name `name` from the ELF64 image `elf`. + fn elf64_section<'a>(elf: &'a [u8], name: &str) -> Option<&'a [u8]> { elf_section_generic::(elf, name) } =20 /// Extract the section with name `name` from the ELF32 image `elf`. - #[expect(dead_code)] - pub(super) fn elf32_section<'a>(elf: &'a [u8], name: &str) -> Option<&= 'a [u8]> { + fn elf32_section<'a>(elf: &'a [u8], name: &str) -> Option<&'a [u8]> { elf_section_generic::(elf, name) } + + /// Automatically detects ELF32 vs ELF64 based on the ELF header. + pub(super) fn elf_section<'a>(elf: &'a [u8], name: &str) -> Option<&'a= [u8]> { + // ELF identification: a 4-byte magic followed by a class byte (32= - vs 64-bit). + const ELFMAG: &[u8] =3D b"\x7fELF"; + const SELFMAG: usize =3D ELFMAG.len(); + const EI_CLASS: usize =3D 4; + const ELFCLASS32: u8 =3D 1; + const ELFCLASS64: u8 =3D 2; + + if elf.get(0..SELFMAG) !=3D Some(ELFMAG) { + return None; + } + + match *elf.get(EI_CLASS)? { + ELFCLASS32 =3D> elf32_section(elf, name), + ELFCLASS64 =3D> elf64_section(elf, name), + _ =3D> None, + } + } } diff --git a/drivers/gpu/nova-core/firmware/gsp.rs b/drivers/gpu/nova-core/= firmware/gsp.rs index e576bc8a9b1c..99a302bae567 100644 --- a/drivers/gpu/nova-core/firmware/gsp.rs +++ b/drivers/gpu/nova-core/firmware/gsp.rs @@ -88,7 +88,7 @@ pub(crate) fn new<'a>( pin_init::pin_init_scope(move || { let firmware =3D super::request_firmware(dev, chipset, "gsp", = ver)?; =20 - let fw_section =3D elf::elf64_section(firmware.data(), ".fwima= ge").ok_or(EINVAL)?; + let fw_section =3D elf::elf_section(firmware.data(), ".fwimage= ").ok_or(EINVAL)?; =20 let size =3D fw_section.len(); =20 @@ -148,7 +148,7 @@ pub(crate) fn new<'a>( signatures: { let sigs_section =3D Self::find_gsp_sigs_section(chips= et); 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charset="utf-8" Add the FSP (Foundation Security Processor) falcon engine type that will handle secure boot and Chain of Trust operations on Hopper and Blackwell architectures. The FSP falcon replaces SEC2's role in the boot sequence for these newer architectures. This initial stub just defines the falcon type and its base address. Signed-off-by: John Hubbard Reviewed-by: Eliot Courtney --- drivers/gpu/nova-core/falcon.rs | 1 + drivers/gpu/nova-core/falcon/fsp.rs | 29 +++++++++++++++++++++++++++++ 2 files changed, 30 insertions(+) create mode 100644 drivers/gpu/nova-core/falcon/fsp.rs diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon= .rs index 24cc2c26e28d..053ce5bea6cd 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -40,6 +40,7 @@ regs, }; =20 +pub(crate) mod fsp; pub(crate) mod gsp; mod hal; pub(crate) mod sec2; diff --git a/drivers/gpu/nova-core/falcon/fsp.rs b/drivers/gpu/nova-core/fa= lcon/fsp.rs new file mode 100644 index 000000000000..c4a9ce8a47f8 --- /dev/null +++ b/drivers/gpu/nova-core/falcon/fsp.rs @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIA= TES. All rights reserved. + +//! FSP (Foundation Security Processor) falcon engine for Hopper/Blackwell= GPUs. +//! +//! The FSP falcon handles secure boot and Chain of Trust operations +//! on Hopper and Blackwell architectures, replacing SEC2's role. + +use kernel::io::register::RegisterBase; + +use crate::falcon::{ + FalconEngine, + PFalcon2Base, + PFalconBase, // +}; + +/// Type specifying the `Fsp` falcon engine. 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charset="utf-8" FSP is the Falcon that runs FMC firmware on Hopper and Blackwell. Load the FMC ELF in two forms: the image section that FSP boots from, and the full Firmware object for later signature extraction during Chain of Trust verification. Declare the FMC image in the module's firmware table so it is bundled for FSP-based chipsets. Co-developed-by: Alexandre Courbot Signed-off-by: Alexandre Courbot Signed-off-by: John Hubbard Reviewed-by: Eliot Courtney --- drivers/gpu/nova-core/firmware.rs | 9 ++++- drivers/gpu/nova-core/firmware/fsp.rs | 47 ++++++++++++++++++++++++++ drivers/gpu/nova-core/gpu.rs | 9 +++++ drivers/gpu/nova-core/gsp/hal/gh100.rs | 10 ++++-- 4 files changed, 72 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/nova-core/firmware/fsp.rs diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firm= ware.rs index 87588cb24f11..366d3b76360e 100644 --- a/drivers/gpu/nova-core/firmware.rs +++ b/drivers/gpu/nova-core/firmware.rs @@ -28,6 +28,7 @@ }; =20 pub(crate) mod booter; +pub(crate) mod fsp; pub(crate) mod fwsec; pub(crate) mod gsp; pub(crate) mod riscv; @@ -431,10 +432,16 @@ const fn make_entry_chipset(self, chipset: gpu::Chips= et) -> Self { .make_entry_file(name, "bootloader") .make_entry_file(name, "gsp"); =20 - if chipset.needs_fwsec_bootloader() { + let this =3D if chipset.needs_fwsec_bootloader() { this.make_entry_file(name, "gen_bootloader") } else { this + }; + + if chipset.uses_fsp() { + this.make_entry_file(name, "fmc") + } else { + this } } =20 diff --git a/drivers/gpu/nova-core/firmware/fsp.rs b/drivers/gpu/nova-core/= firmware/fsp.rs new file mode 100644 index 000000000000..011be1e571c2 --- /dev/null +++ b/drivers/gpu/nova-core/firmware/fsp.rs @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIA= TES. All rights reserved. + +//! FSP is a hardware unit that runs FMC firmware. + +use kernel::{ + device, + dma::Coherent, + firmware::Firmware, + prelude::*, // +}; + +use crate::{ + firmware::elf, + gpu::Chipset, // +}; + +pub(crate) struct FspFirmware { + /// FMC firmware image data (only the "image" ELF section). + #[expect(dead_code)] + pub(crate) fmc_image: Coherent<[u8]>, + /// Full FMC ELF for signature extraction. + #[expect(dead_code)] + pub(crate) fmc_elf: Firmware, +} + +impl FspFirmware { + pub(crate) fn new( + dev: &device::Device, + chipset: Chipset, + ver: &str, + ) -> Result { + let fw =3D super::request_firmware(dev, chipset, "fmc", ver)?; + + // FSP expects only the "image" section, not the entire ELF file. + let fmc_image_data =3D elf::elf_section(fw.data(), "image").ok_or_= else(|| { + dev_err!(dev, "FMC ELF file missing 'image' section\n"); + EINVAL + })?; + let fmc_image =3D Coherent::from_slice(dev, fmc_image_data, GFP_KE= RNEL)?; + + Ok(Self { + fmc_image, + fmc_elf: fw, + }) + } +} diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index 7dd736e5b190..b7341bde04be 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -137,6 +137,15 @@ pub(crate) const fn needs_fwsec_bootloader(self) -> bo= ol { matches!(self.arch(), Architecture::Turing) || matches!(self, Self= ::GA100) } =20 + /// Returns `true` if this chipset boots via FSP (Hopper and later), w= hich requires the FMC + /// firmware image. + pub(crate) const fn uses_fsp(self) -> bool { + matches!( + self.arch(), + Architecture::Hopper | Architecture::BlackwellGB10x | Architec= ture::BlackwellGB20x + ) + } + /// Returns the address range of the PCI config mirror space. pub(crate) fn pci_config_mirror_range(self) -> Range { hal::gpu_hal(self).pci_config_mirror_range() diff --git a/drivers/gpu/nova-core/gsp/hal/gh100.rs b/drivers/gpu/nova-core= /gsp/hal/gh100.rs index 9a4bb22578b3..9681f9a73e86 100644 --- a/drivers/gpu/nova-core/gsp/hal/gh100.rs +++ b/drivers/gpu/nova-core/gsp/hal/gh100.rs @@ -16,6 +16,10 @@ Falcon, // }, fb::FbLayout, + firmware::{ + fsp::FspFirmware, + FIRMWARE_VERSION, // + }, gpu::Chipset, gsp::{ boot::BootUnloadGuard, @@ -35,14 +39,16 @@ impl GspHal for Gh100 { fn boot<'a>( &self, _gsp: &'a Gsp, - _dev: &'a device::Device, + dev: &'a device::Device, _bar: &'a Bar0, - _chipset: Chipset, + chipset: Chipset, _fb_layout: &FbLayout, _wpr_meta: &Coherent, _gsp_falcon: &'a Falcon, _sec2_falcon: &'a Falcon, ) -> Result> { + let _fsp_fw =3D FspFirmware::new(dev, chipset, FIRMWARE_VERSION)?; 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charset="utf-8" Hopper and Blackwell use FSP instead of SEC2 for secure boot. The driver must wait for FSP secure boot to complete before continuing with GSP bring-up. Poll for boot success with a 5-second timeout, and return the FSP interface only on success so that later Chain of Trust operations cannot run before FSP is ready. The interface owns the FSP falcon and the FMC firmware. Co-developed-by: Alexandre Courbot Signed-off-by: Alexandre Courbot Signed-off-by: John Hubbard Reviewed-by: Eliot Courtney --- drivers/gpu/nova-core/falcon/fsp.rs | 1 - drivers/gpu/nova-core/fsp.rs | 73 ++++++++++++++++++++++++++ drivers/gpu/nova-core/fsp/hal.rs | 27 ++++++++++ drivers/gpu/nova-core/fsp/hal/gb202.rs | 23 ++++++++ drivers/gpu/nova-core/fsp/hal/gh100.rs | 23 ++++++++ drivers/gpu/nova-core/gsp/hal/gh100.rs | 6 ++- drivers/gpu/nova-core/nova_core.rs | 1 + drivers/gpu/nova-core/regs.rs | 36 +++++++++++++ 8 files changed, 187 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/nova-core/fsp.rs create mode 100644 drivers/gpu/nova-core/fsp/hal.rs create mode 100644 drivers/gpu/nova-core/fsp/hal/gb202.rs create mode 100644 drivers/gpu/nova-core/fsp/hal/gh100.rs diff --git a/drivers/gpu/nova-core/falcon/fsp.rs b/drivers/gpu/nova-core/fa= lcon/fsp.rs index c4a9ce8a47f8..d9f87262e8b1 100644 --- a/drivers/gpu/nova-core/falcon/fsp.rs +++ b/drivers/gpu/nova-core/falcon/fsp.rs @@ -15,7 +15,6 @@ }; =20 /// Type specifying the `Fsp` falcon engine. Cannot be instantiated. -#[expect(dead_code)] pub(crate) struct Fsp(()); =20 impl RegisterBase for Fsp { diff --git a/drivers/gpu/nova-core/fsp.rs b/drivers/gpu/nova-core/fsp.rs new file mode 100644 index 000000000000..f3524137d9f7 --- /dev/null +++ b/drivers/gpu/nova-core/fsp.rs @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIA= TES. All rights reserved. + +//! FSP (Foundation Security Processor) interface for Hopper/Blackwell GPU= s. +//! +//! Hopper/Blackwell use a simplified firmware boot sequence: FMC, then FS= P, then GSP. +//! Unlike Turing/Ampere/Ada, there is no SEC2 (Security Engine 2) usage. +//! FSP handles secure boot directly using FMC firmware and Chain of Trust. + +use kernel::{ + device, + io::poll::read_poll_timeout, + prelude::*, + time::Delta, // +}; + +use crate::{ + driver::Bar0, + falcon::{ + fsp::Fsp as FspEngine, + Falcon, // + }, + firmware::fsp::FspFirmware, + gpu::Chipset, + regs, // +}; + +mod hal; + +/// FSP interface for Hopper/Blackwell GPUs. +/// +/// An `Fsp` is produced by [`Fsp::wait_secure_boot`], which only returns = once FSP secure boot +/// has completed. It owns the FSP falcon and the FMC firmware, which are = used for the subsequent +/// Chain of Trust boot. +pub(crate) struct Fsp { + #[expect(dead_code)] + falcon: Falcon, + #[expect(dead_code)] + fsp_fw: FspFirmware, +} + +impl Fsp { + /// Waits for FSP secure boot completion, then returns the [`Fsp`] int= erface. + /// + /// Polls the thermal scratch register until FSP signals boot completi= on or the timeout + /// elapses. Returning an [`Fsp`] only on success guarantees, at the A= PI level, that the + /// interface is not used before secure boot has completed. + pub(crate) fn wait_secure_boot( + dev: &device::Device, + bar: &Bar0, + chipset: Chipset, + fsp_fw: FspFirmware, + ) -> Result { + /// FSP secure boot completion timeout in milliseconds. + const FSP_SECURE_BOOT_TIMEOUT_MS: i64 =3D 5000; + + let hal =3D hal::fsp_hal(chipset).ok_or(ENOTSUPP)?; + let falcon =3D Falcon::::new(dev, chipset)?; + + read_poll_timeout( + || Ok(hal.fsp_boot_status(bar)), + |&status| status =3D=3D regs::NV_THERM_I2CS_SCRATCH_FSP_BOOT_C= OMPLETE_STATUS_SUCCESS, + Delta::from_millis(10), + Delta::from_millis(FSP_SECURE_BOOT_TIMEOUT_MS), + ) + .map_err(|_| { + dev_err!(dev, "FSP secure boot completion timeout\n"); + ETIMEDOUT + })?; + + Ok(Fsp { falcon, fsp_fw }) + } +} diff --git a/drivers/gpu/nova-core/fsp/hal.rs b/drivers/gpu/nova-core/fsp/h= al.rs new file mode 100644 index 000000000000..83d1e7daa998 --- /dev/null +++ b/drivers/gpu/nova-core/fsp/hal.rs @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIA= TES. All rights reserved. + +use crate::{ + driver::Bar0, + gpu::{ + Architecture, + Chipset, // + }, +}; + +mod gb202; +mod gh100; + +pub(super) trait FspHal { + /// Returns the secure boot status from the architecture-specific `NV_= THERM_I2CS_SCRATCH` register. + fn fsp_boot_status(&self, bar: &Bar0) -> u32; +} + +/// Returns the FSP HAL, or `None` if the architecture doesn't support FSP. +pub(crate) fn fsp_hal(chipset: Chipset) -> Option<&'static dyn FspHal> { + match chipset.arch() { + Architecture::Turing | Architecture::Ampere | Architecture::Ada = =3D> None, + Architecture::Hopper | Architecture::BlackwellGB10x =3D> Some(gh10= 0::GH100_HAL), + Architecture::BlackwellGB20x =3D> Some(gb202::GB202_HAL), + } +} diff --git a/drivers/gpu/nova-core/fsp/hal/gb202.rs b/drivers/gpu/nova-core= /fsp/hal/gb202.rs new file mode 100644 index 000000000000..2f08b6c9f308 --- /dev/null +++ b/drivers/gpu/nova-core/fsp/hal/gb202.rs @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIA= TES. All rights reserved. + +use kernel::io::Io; + +use crate::{ + driver::Bar0, + fsp::hal::FspHal, + regs, // +}; + +struct Gb202; + +impl FspHal for Gb202 { + fn fsp_boot_status(&self, bar: &Bar0) -> u32 { + bar.read(regs::gb202::NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE) + .fsp_boot_complete() + .into() + } +} + +const GB202: Gb202 =3D Gb202; +pub(super) const GB202_HAL: &dyn FspHal =3D &GB202; diff --git a/drivers/gpu/nova-core/fsp/hal/gh100.rs b/drivers/gpu/nova-core= /fsp/hal/gh100.rs new file mode 100644 index 000000000000..290fb55a81da --- /dev/null +++ b/drivers/gpu/nova-core/fsp/hal/gh100.rs @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIA= TES. All rights reserved. + +use kernel::io::Io; + +use crate::{ + driver::Bar0, + fsp::hal::FspHal, + regs, // +}; + +struct Gh100; + +impl FspHal for Gh100 { + fn fsp_boot_status(&self, bar: &Bar0) -> u32 { + bar.read(regs::gh100::NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE) + .fsp_boot_complete() + .into() + } +} + +const GH100: Gh100 =3D Gh100; +pub(super) const GH100_HAL: &dyn FspHal =3D &GH100; diff --git a/drivers/gpu/nova-core/gsp/hal/gh100.rs b/drivers/gpu/nova-core= /gsp/hal/gh100.rs index 9681f9a73e86..b25970dd4561 100644 --- a/drivers/gpu/nova-core/gsp/hal/gh100.rs +++ b/drivers/gpu/nova-core/gsp/hal/gh100.rs @@ -20,6 +20,7 @@ fsp::FspFirmware, FIRMWARE_VERSION, // }, + fsp::Fsp, gpu::Chipset, gsp::{ boot::BootUnloadGuard, @@ -40,14 +41,15 @@ fn boot<'a>( &self, _gsp: &'a Gsp, dev: &'a device::Device, - _bar: &'a Bar0, + bar: &'a Bar0, chipset: Chipset, _fb_layout: &FbLayout, _wpr_meta: &Coherent, _gsp_falcon: &'a Falcon, _sec2_falcon: &'a Falcon, ) -> Result> { - let _fsp_fw =3D FspFirmware::new(dev, chipset, FIRMWARE_VERSION)?; + let fsp_fw =3D FspFirmware::new(dev, chipset, FIRMWARE_VERSION)?; + let _fsp =3D Fsp::wait_secure_boot(dev, bar, chipset, fsp_fw)?; =20 Err(ENOTSUPP) } diff --git a/drivers/gpu/nova-core/nova_core.rs b/drivers/gpu/nova-core/nov= a_core.rs index 5a260062295f..7b6c331da10e 100644 --- a/drivers/gpu/nova-core/nova_core.rs +++ b/drivers/gpu/nova-core/nova_core.rs @@ -17,6 +17,7 @@ mod falcon; mod fb; mod firmware; +mod fsp; mod gpu; mod gsp; #[macro_use] diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index b39647684dd1..2cb1f02f35a4 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -587,3 +587,39 @@ pub(crate) mod ga100 { } } } + +pub(crate) const NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS_SUCCESS: u= 32 =3D 0xff; + +pub(crate) mod gh100 { + use kernel::io::register; + + // PTHERM + + register! { + pub(crate) NV_THERM_I2CS_SCRATCH(u32) @ 0x000200bc { + 31:0 data; + } + + // Alias to `NV_THERM_I2CS_SCRATCH` when used to check for FSP boo= t completion. + pub(crate) NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE(u32) =3D> NV_TH= ERM_I2CS_SCRATCH { + 31:0 fsp_boot_complete; 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charset="utf-8" Extract the SHA-384 hash, RSA public key, and RSA signature from the FMC ELF32 firmware sections. FSP Chain of Trust verification needs these to validate the FMC image during boot. Co-developed-by: Alexandre Courbot Signed-off-by: Alexandre Courbot Signed-off-by: John Hubbard Reviewed-by: Eliot Courtney --- drivers/gpu/nova-core/firmware/fsp.rs | 94 ++++++++++++++++++++++++++- 1 file changed, 91 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nova-core/firmware/fsp.rs b/drivers/gpu/nova-core/= firmware/fsp.rs index 011be1e571c2..db61905eac9d 100644 --- a/drivers/gpu/nova-core/firmware/fsp.rs +++ b/drivers/gpu/nova-core/firmware/fsp.rs @@ -15,13 +15,35 @@ gpu::Chipset, // }; =20 +/// Size of the FSP SHA-384 hash, in bytes. +const FSP_HASH_SIZE: usize =3D 48; +/// Maximum size of the FSP public key (RSA-3072), in bytes. +/// +/// The FMC ELF `publickey` section may be shorter, so the remaining bytes= are zero-padded. +const FSP_PKEY_SIZE: usize =3D 384; +/// Maximum size of the FSP signature (RSA-3072), in bytes. +/// +/// The FMC ELF `signature` section may be shorter, so the remaining bytes= are zero-padded. +const FSP_SIG_SIZE: usize =3D 384; + +/// Structure to hold FMC signatures. +/// +/// C representation is used because this type is used for communication w= ith the FSP. +#[derive(Debug, Clone, Copy)] +#[repr(C)] +pub(crate) struct FmcSignatures { + pub(crate) hash384: [u8; FSP_HASH_SIZE], + pub(crate) public_key: [u8; FSP_PKEY_SIZE], + pub(crate) signature: [u8; FSP_SIG_SIZE], +} + pub(crate) struct FspFirmware { /// FMC firmware image data (only the "image" ELF section). #[expect(dead_code)] pub(crate) fmc_image: Coherent<[u8]>, - /// Full FMC ELF for signature extraction. + /// FMC firmware signatures. #[expect(dead_code)] - pub(crate) fmc_elf: Firmware, + pub(crate) fmc_sigs: KBox, } =20 impl FspFirmware { @@ -41,7 +63,73 @@ pub(crate) fn new( =20 Ok(Self { fmc_image, - fmc_elf: fw, + fmc_sigs: Self::extract_fmc_signatures(&fw, dev)?, }) } + + /// Extract FMC firmware signatures for Chain of Trust verification. + /// + /// Extracts real cryptographic signatures from FMC ELF32 firmware sec= tions. + /// Returns signatures in a heap-allocated structure to prevent stack = overflow. + fn extract_fmc_signatures( + fmc_fw: &Firmware, + dev: &device::Device, + ) -> Result> { + let get_section =3D |name: &str, max_len: usize| { + elf::elf_section(fmc_fw.data(), name) + .ok_or(EINVAL) + .inspect_err(|_| dev_err!(dev, "FMC firmware missing '{}' = section\n", name)) + .and_then(|section| { + if section.len() > max_len { + dev_err!( + dev, + "FMC {} section size {} > maximum {}\n", + name, + section.len(), + max_len + ); + Err(EINVAL) + } else { + Ok(section) + } + }) + }; + + let hash_section =3D get_section("hash", FSP_HASH_SIZE)?; + let pkey_section =3D get_section("publickey", FSP_PKEY_SIZE)?; + let sig_section =3D get_section("signature", FSP_SIG_SIZE)?; + + // The hash section is a SHA-384 output: it must be exactly FSP_HA= SH_SIZE bytes. + if hash_section.len() !=3D FSP_HASH_SIZE { + dev_err!( + dev, + "FMC hash section size {} !=3D expected {}\n", + hash_section.len(), + FSP_HASH_SIZE + ); + return Err(EINVAL); + } + + // Initialize the signatures in place to avoid building the large = `FmcSignatures` on the + // stack, then fill each section from the firmware. + let signatures =3D KBox::init( + init!(FmcSignatures { + hash384: [0; _], + public_key: [0; _], + signature: [0; _], + }) + .chain(|sigs| { + // PANIC: src and dst lengths are both FSP_HASH_SIZE (veri= fied above). + sigs.hash384.copy_from_slice(hash_section); + // PANIC: dst is sliced to src.len(); src.len() <=3D FSP_P= KEY_SIZE per `get_section`. + sigs.public_key[..pkey_section.len()].copy_from_slice(pkey= _section); + // PANIC: dst is sliced to src.len(); src.len() <=3D FSP_S= IG_SIZE per `get_section`. + sigs.signature[..sig_section.len()].copy_from_slice(sig_se= ction); + Ok(()) + }), + GFP_KERNEL, + )?; + + Ok(signatures) + } } --=20 2.54.0 From nobody Mon Jun 8 04:24:52 2026 Received: from CY3PR05CU001.outbound.protection.outlook.com (mail-westcentralusazon11013065.outbound.protection.outlook.com [40.93.201.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A28AB36E48D for ; Tue, 2 Jun 2026 03:21:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.201.65 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780370515; cv=fail; b=jFHLy2wNEowSH8Yw/4U2lz55jxfBslb3KZQxiSxgmu72zhFYhZVd4NPJ7oh3fwJ5qxp7gGwlmC8aqhPBU07uuMDegkVKE3jb7HgvkwvSFOacLemqElRfT3Dx1S7Ydno+mTILlvPGfy10+zmeI6h7vnKlyf39ii435nereXavkgE= ARC-Message-Signature: i=2; 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Tue, 2 Jun 2026 03:21:31 +0000 Received: from DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8]) by DM3PR12MB9416.namprd12.prod.outlook.com ([fe80::8cdd:504c:7d2a:59c8%5]) with mapi id 15.21.0071.015; Tue, 2 Jun 2026 03:21:31 +0000 From: John Hubbard To: Danilo Krummrich , Alexandre Courbot Cc: Timur Tabi , Alistair Popple , Eliot Courtney , Shashank Sharma , Zhi Wang , David Airlie , Simona Vetter , Bjorn Helgaas , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , nova-gpu@lists.linux.dev, LKML , John Hubbard Subject: [PATCH v12 14/22] gpu: nova-core: Hopper/Blackwell: add FSP falcon EMEM operations Date: Mon, 1 Jun 2026 20:21:02 -0700 Message-ID: <20260602032111.224790-15-jhubbard@nvidia.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260602032111.224790-1-jhubbard@nvidia.com> References: <20260602032111.224790-1-jhubbard@nvidia.com> X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SJ0PR13CA0069.namprd13.prod.outlook.com (2603:10b6:a03:2c4::14) To DM3PR12MB9416.namprd12.prod.outlook.com (2603:10b6:0:4b::8) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM3PR12MB9416:EE_|MN6PR12MB8565:EE_ X-MS-Office365-Filtering-Correlation-Id: a10f41eb-d43b-4e01-7af7-08dec0560a97 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|366016|22082099003|18002099003|11063799006|56012099006; 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charset="utf-8" Add external memory (EMEM) read/write operations to the GPU's FSP falcon engine. These operations use Falcon PIO (Programmed I/O) to communicate with the FSP through indirect memory access. Signed-off-by: John Hubbard --- drivers/gpu/nova-core/falcon/fsp.rs | 130 ++++++++++++++++++++++++++-- drivers/gpu/nova-core/regs.rs | 15 ++++ 2 files changed, 140 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/nova-core/falcon/fsp.rs b/drivers/gpu/nova-core/fa= lcon/fsp.rs index d9f87262e8b1..6b057d958115 100644 --- a/drivers/gpu/nova-core/falcon/fsp.rs +++ b/drivers/gpu/nova-core/falcon/fsp.rs @@ -6,12 +6,28 @@ //! The FSP falcon handles secure boot and Chain of Trust operations //! on Hopper and Blackwell architectures, replacing SEC2's role. =20 -use kernel::io::register::RegisterBase; +use kernel::{ + io::{ + register::{ + RegisterBase, + WithBase, // + }, + Io, // + }, + num::Bounded, + prelude::*, + ptr::Alignment, // +}; =20 -use crate::falcon::{ - FalconEngine, - PFalcon2Base, - PFalconBase, // +use crate::{ + driver::Bar0, + falcon::{ + Falcon, + FalconEngine, + PFalcon2Base, + PFalconBase, // + }, + regs, }; =20 /// Type specifying the `Fsp` falcon engine. Cannot be instantiated. @@ -26,3 +42,107 @@ impl RegisterBase for Fsp { } =20 impl FalconEngine for Fsp {} + +/// Maximum addressable EMEM size, derived from the 24-bit offset field +/// in `NV_PFALCON_FALCON_EMEM_CTL`. +const EMEM_MAX_SIZE: Alignment =3D Alignment::new::<{ 1 << 24 }>(); + +/// I/O backend for the FSP falcon's external memory (EMEM). +/// +/// `EMEM_CTL` is programmed once with a start offset and an auto-increment +/// mode, then each access to `EMEM_DATA` advances the offset by one 32-bit +/// word in hardware. +struct Emem<'a> { + bar: &'a Bar0, +} + +impl<'a> Emem<'a> { + fn new(bar: &'a Bar0) -> Self { + Self { bar } + } + + /// Programs `EMEM_CTL` with the start byte `offset` and the `ctl` mod= e bits. + /// + /// Returns `EINVAL` if `offset` is outside the addressable EMEM windo= w. + fn program(&mut self, offset: usize, ctl: regs::NV_PFALCON_FALCON_EMEM= _CTL) -> Result { + let offset =3D Bounded::::try_new= (offset) + .map(Bounded::cast::) + .ok_or(EINVAL)?; + + self.bar + .write(WithBase::of::(), ctl.with_offset(offset)); + + Ok(()) + } + + /// Begins a write burst at byte `offset`, auto-incrementing on each w= rite. + fn begin_write(&mut self, offset: usize) -> Result { + self.program( + offset, + regs::NV_PFALCON_FALCON_EMEM_CTL::zeroed().with_auto_increment= _write(true), + ) + } + + /// Begins a read burst at byte `offset`, auto-incrementing on each re= ad. + fn begin_read(&mut self, offset: usize) -> Result { + self.program( + offset, + regs::NV_PFALCON_FALCON_EMEM_CTL::zeroed().with_auto_increment= _read(true), + ) + } + + /// Writes the next 32-bit `value`; hardware advances the offset. + fn write_next(&mut self, value: u32) { + self.bar.write( + WithBase::of::(), + regs::NV_PFALCON_FALCON_EMEM_DATA::zeroed().with_data(value), + ); + } + + /// Reads the next 32-bit word; hardware advances the offset. + fn read_next(&mut self) -> u32 { + self.bar + .read(regs::NV_PFALCON_FALCON_EMEM_DATA::of::()) + .data() + } +} + +impl Falcon { + /// Writes `data` to FSP external memory at byte `offset`. + /// + /// `data` is interpreted as little-endian 32-bit words. Returns `EINV= AL` + /// if `offset` or the `data` length is not 4-byte aligned. + #[expect(dead_code)] + fn write_emem(&mut self, bar: &Bar0, offset: u32, data: &[u8]) -> Resu= lt { + if offset % 4 !=3D 0 || data.len() % 4 !=3D 0 { + return Err(EINVAL); + } + + let mut emem =3D Emem::new(bar); + emem.begin_write(offset as usize)?; + for chunk in data.chunks_exact(4) { + emem.write_next(u32::from_le_bytes([chunk[0], chunk[1], chunk[= 2], chunk[3]])); + } + + Ok(()) + } + + /// Reads FSP external memory at byte `offset` into `data`. + /// + /// `data` is stored as little-endian 32-bit words. Returns `EINVAL` if + /// `offset` or the `data` length is not 4-byte aligned. + #[expect(dead_code)] + fn read_emem(&mut self, bar: &Bar0, offset: u32, data: &mut [u8]) -> R= esult { + if offset % 4 !=3D 0 || data.len() % 4 !=3D 0 { + return Err(EINVAL); + } + + let mut emem =3D Emem::new(bar); + emem.begin_read(offset as usize)?; + for chunk in data.chunks_exact_mut(4) { + chunk.copy_from_slice(&emem.read_next().to_le_bytes()); + } + + Ok(()) + } +} diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 2cb1f02f35a4..da7a10c0346a 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -475,6 +475,21 @@ pub(crate) fn vga_workspace_addr(self) -> Option { pub(crate) NV_PFALCON_FBIF_CTL(u32) @ PFalconBase + 0x00000624 { 7:7 allow_phys_no_ctx =3D> bool; } + + // Falcon EMEM PIO registers (used by FSP on Hopper/Blackwell). + // These provide the falcon external memory communication interface. + pub(crate) NV_PFALCON_FALCON_EMEM_CTL(u32) @ PFalconBase + 0x00000ac0 { + /// EMEM byte offset (must be 4-byte aligned). + 23:0 offset; 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charset="utf-8" FSP communication uses a pair of non-circular queues in the FSP falcon's EMEM, one for messages from the driver to FSP and one for replies, with the driver polling for response data. Add the queue registers and the low-level helpers used by the higher-level FSP message layer. Signed-off-by: John Hubbard --- drivers/gpu/nova-core/falcon/fsp.rs | 61 ++++++++++++++++++++++++++++- drivers/gpu/nova-core/regs.rs | 21 ++++++++++ 2 files changed, 80 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nova-core/falcon/fsp.rs b/drivers/gpu/nova-core/fa= lcon/fsp.rs index 6b057d958115..0ec1c55213bc 100644 --- a/drivers/gpu/nova-core/falcon/fsp.rs +++ b/drivers/gpu/nova-core/falcon/fsp.rs @@ -112,7 +112,6 @@ impl Falcon { /// /// `data` is interpreted as little-endian 32-bit words. Returns `EINV= AL` /// if `offset` or the `data` length is not 4-byte aligned. - #[expect(dead_code)] fn write_emem(&mut self, bar: &Bar0, offset: u32, data: &[u8]) -> Resu= lt { if offset % 4 !=3D 0 || data.len() % 4 !=3D 0 { return Err(EINVAL); @@ -131,7 +130,6 @@ fn write_emem(&mut self, bar: &Bar0, offset: u32, data:= &[u8]) -> Result { /// /// `data` is stored as little-endian 32-bit words. Returns `EINVAL` if /// `offset` or the `data` length is not 4-byte aligned. - #[expect(dead_code)] fn read_emem(&mut self, bar: &Bar0, offset: u32, data: &mut [u8]) -> R= esult { if offset % 4 !=3D 0 || data.len() % 4 !=3D 0 { return Err(EINVAL); @@ -145,4 +143,63 @@ fn read_emem(&mut self, bar: &Bar0, offset: u32, data:= &mut [u8]) -> Result { =20 Ok(()) } + + /// Poll FSP for incoming data. + /// + /// Returns the size of available data in bytes, or 0 if no data is av= ailable. + /// + /// The FSP message queue is not circular. Pointers are reset to 0 aft= er each + /// message exchange, so `tail >=3D head` is always true when data is = present. + #[expect(dead_code)] + pub(crate) fn poll_msgq(&self, bar: &Bar0) -> u32 { + let head =3D bar.read(regs::NV_PFSP_MSGQ_HEAD).address(); + let tail =3D bar.read(regs::NV_PFSP_MSGQ_TAIL).address(); + + if head =3D=3D tail { + return 0; + } + + // TAIL points at last DWORD written, so add 4 to get total size + tail.saturating_sub(head) + 4 + } + + /// Writes `packet` to FSP EMEM and updates the queue pointers to noti= fy FSP. + /// + /// Returns `EINVAL` if `packet` is empty or its length is not 4-byte = aligned. + #[expect(dead_code)] + pub(crate) fn send_msg(&mut self, bar: &Bar0, packet: &[u8]) -> Result= { + if packet.is_empty() { + return Err(EINVAL); + } + + // Write message to EMEM at offset 0 (validates 4-byte alignment) + self.write_emem(bar, 0, packet)?; + + // Update queue pointers. TAIL points at the last DWORD written. + let tail_offset =3D u32::try_from(packet.len() - 4).map_err(|_| EI= NVAL)?; + bar.write_reg(regs::NV_PFSP_QUEUE_TAIL::zeroed().with_address(tail= _offset)); + bar.write_reg(regs::NV_PFSP_QUEUE_HEAD::zeroed().with_address(0)); + + Ok(()) + } + + /// Reads `size` bytes from FSP EMEM into `buffer` and resets the queu= e pointers. + /// + /// `size` comes from `poll_msgq`. Returns `EINVAL` if `size` is 0, ex= ceeds + /// `buffer`, or is not 4-byte aligned. + #[expect(dead_code)] + pub(crate) fn recv_msg(&mut self, bar: &Bar0, buffer: &mut [u8], size:= usize) -> Result { + if size =3D=3D 0 || size > buffer.len() { + return Err(EINVAL); + } + + // Read response from EMEM at offset 0 (validates 4-byte alignment) + self.read_emem(bar, 0, &mut buffer[..size])?; + + // Reset message queue pointers after reading + bar.write_reg(regs::NV_PFSP_MSGQ_TAIL::zeroed().with_address(0)); + bar.write_reg(regs::NV_PFSP_MSGQ_HEAD::zeroed().with_address(0)); + + Ok(()) + } } diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index da7a10c0346a..8c51609d0281 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -576,6 +576,27 @@ pub(crate) fn mem_scrubbing_done(self) -> bool { } } =20 +// FSP (Foundation Security Processor) queue registers for Hopper/Blackwel= l Chain of Trust. +// These registers manage falcon EMEM communication queues. + +register! { + pub(crate) NV_PFSP_QUEUE_HEAD(u32) @ 0x008f2c00 { + 31:0 address =3D> u32; + } + + pub(crate) NV_PFSP_QUEUE_TAIL(u32) @ 0x008f2c04 { + 31:0 address =3D> u32; + } + + pub(crate) NV_PFSP_MSGQ_HEAD(u32) @ 0x008f2c80 { + 31:0 address =3D> u32; + } + + pub(crate) NV_PFSP_MSGQ_TAIL(u32) @ 0x008f2c84 { + 31:0 address =3D> u32; + } +} + // The modules below provide registers that are not identical on all suppo= rted chips. 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charset="utf-8" Add the MCTP (Management Component Transport Protocol) and NVDM (NVIDIA Device Management) wire-format types used for communication between the kernel driver and GPU firmware processors. This includes typed MCTP transport headers, NVDM message headers, and NVDM message type identifiers. Both the FSP boot path and the upcoming GSP RPC message queue share this protocol layer. Signed-off-by: John Hubbard Reviewed-by: Eliot Courtney --- drivers/gpu/nova-core/mctp.rs | 102 +++++++++++++++++++++++++++++ drivers/gpu/nova-core/nova_core.rs | 1 + 2 files changed, 103 insertions(+) create mode 100644 drivers/gpu/nova-core/mctp.rs diff --git a/drivers/gpu/nova-core/mctp.rs b/drivers/gpu/nova-core/mctp.rs new file mode 100644 index 000000000000..a13146dc0cca --- /dev/null +++ b/drivers/gpu/nova-core/mctp.rs @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIA= TES. All rights reserved. + +//! MCTP/NVDM protocol types for NVIDIA GPU firmware communication. +//! +//! MCTP (Management Component Transport Protocol) carries NVDM (NVIDIA +//! Device Management) messages between the kernel driver and GPU firmware +//! processors such as FSP and GSP. + +#![expect(dead_code)] + +use kernel::pci::Vendor; + +/// NVDM message type identifiers carried over MCTP. +#[derive(Debug, Clone, Copy, Default, PartialEq, Eq)] +#[repr(u8)] +pub(crate) enum NvdmType { + #[default] + /// Chain of Trust boot message. + Cot =3D 0x14, + /// FSP command response. + FspResponse =3D 0x15, +} + +impl TryFrom for NvdmType { + type Error =3D u8; + + fn try_from(value: u8) -> Result { + match value { + x if x =3D=3D u8::from(Self::Cot) =3D> Ok(Self::Cot), + x if x =3D=3D u8::from(Self::FspResponse) =3D> Ok(Self::FspRes= ponse), + _ =3D> Err(value), + } + } +} + +impl From for u8 { + fn from(value: NvdmType) -> Self { + value as u8 + } +} + +bitfield! { + pub(crate) struct MctpHeader(u32), "MCTP transport header for NVIDIA f= irmware messages." { + 31:31 som as bool, "Start-of-message bit."; + 30:30 eom as bool, "End-of-message bit."; + 29:28 seq as u8, "Packet sequence number."; + 23:16 seid as u8, "Source endpoint ID."; + } +} + +impl MctpHeader { + /// Builds a single-packet MCTP header (`SOM=3D1`, `EOM=3D1`, `SEQ=3D0= `, `SEID=3D0`). + pub(crate) fn single_packet() -> Self { + Self::default().set_som(true).set_eom(true) + } + + /// Returns whether this is a complete single-packet message (`SOM=3D1= ` and `EOM=3D1`). + pub(crate) fn is_single_packet(self) -> bool { + self.som() && self.eom() + } +} + +impl From for MctpHeader { + fn from(raw: u32) -> Self { + Self(raw) + } +} + +/// MCTP message type for PCI vendor-defined messages. +const MSG_TYPE_VENDOR_PCI: u8 =3D 0x7e; + +bitfield! { + pub(crate) struct NvdmHeader(u32), "NVIDIA Vendor-Defined Message head= er over MCTP." { + 31:24 nvdm_type as u8 ?=3D> NvdmType, "NVDM message type."; + 23:8 vendor_id as u16, "PCI vendor ID."; + 6:0 msg_type as u8, "MCTP vendor-defined message type."; + } +} + +impl NvdmHeader { + /// Builds an NVDM header for the given message type. + pub(crate) fn new(nvdm_type: NvdmType) -> Self { + Self::default() + .set_msg_type(MSG_TYPE_VENDOR_PCI) + .set_vendor_id(Vendor::NVIDIA.as_raw()) + .set_nvdm_type(nvdm_type) + } + + /// Validates this header against the expected NVIDIA NVDM format and = type. + pub(crate) fn validate(self, expected_type: NvdmType) -> bool { + self.msg_type() =3D=3D MSG_TYPE_VENDOR_PCI + && self.vendor_id() =3D=3D Vendor::NVIDIA.as_raw() + && matches!(self.nvdm_type(), Ok(nvdm_type) if nvdm_type =3D= =3D expected_type) + } +} + +impl From for NvdmHeader { + fn from(raw: u32) -> Self { + Self(raw) + } +} diff --git a/drivers/gpu/nova-core/nova_core.rs b/drivers/gpu/nova-core/nov= a_core.rs index 7b6c331da10e..9f0199f7b38c 100644 --- a/drivers/gpu/nova-core/nova_core.rs +++ b/drivers/gpu/nova-core/nova_core.rs @@ -20,6 +20,7 @@ mod fsp; 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charset="utf-8" FSP exchanges are request/response: the driver sends an MCTP/NVDM message and must match the reply against the request before acting on it. Add the synchronous send-and-wait path that validates the response transport and message headers and confirms the reply corresponds to the request that was sent. Signed-off-by: John Hubbard --- drivers/gpu/nova-core/falcon/fsp.rs | 3 - drivers/gpu/nova-core/fsp.rs | 121 +++++++++++++++++++++++++++- 2 files changed, 119 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/nova-core/falcon/fsp.rs b/drivers/gpu/nova-core/fa= lcon/fsp.rs index 0ec1c55213bc..3df1cb2385cb 100644 --- a/drivers/gpu/nova-core/falcon/fsp.rs +++ b/drivers/gpu/nova-core/falcon/fsp.rs @@ -150,7 +150,6 @@ fn read_emem(&mut self, bar: &Bar0, offset: u32, data: = &mut [u8]) -> Result { /// /// The FSP message queue is not circular. Pointers are reset to 0 aft= er each /// message exchange, so `tail >=3D head` is always true when data is = present. - #[expect(dead_code)] pub(crate) fn poll_msgq(&self, bar: &Bar0) -> u32 { let head =3D bar.read(regs::NV_PFSP_MSGQ_HEAD).address(); let tail =3D bar.read(regs::NV_PFSP_MSGQ_TAIL).address(); @@ -166,7 +165,6 @@ pub(crate) fn poll_msgq(&self, bar: &Bar0) -> u32 { /// Writes `packet` to FSP EMEM and updates the queue pointers to noti= fy FSP. /// /// Returns `EINVAL` if `packet` is empty or its length is not 4-byte = aligned. - #[expect(dead_code)] pub(crate) fn send_msg(&mut self, bar: &Bar0, packet: &[u8]) -> Result= { if packet.is_empty() { return Err(EINVAL); @@ -187,7 +185,6 @@ pub(crate) fn send_msg(&mut self, bar: &Bar0, packet: &= [u8]) -> Result { /// /// `size` comes from `poll_msgq`. Returns `EINVAL` if `size` is 0, ex= ceeds /// `buffer`, or is not 4-byte aligned. - #[expect(dead_code)] pub(crate) fn recv_msg(&mut self, bar: &Bar0, buffer: &mut [u8], size:= usize) -> Result { if size =3D=3D 0 || size > buffer.len() { return Err(EINVAL); diff --git a/drivers/gpu/nova-core/fsp.rs b/drivers/gpu/nova-core/fsp.rs index f3524137d9f7..67cf83aba83c 100644 --- a/drivers/gpu/nova-core/fsp.rs +++ b/drivers/gpu/nova-core/fsp.rs @@ -11,7 +11,11 @@ device, io::poll::read_poll_timeout, prelude::*, - time::Delta, // + time::Delta, + transmute::{ + AsBytes, + FromBytes, // + }, }; =20 use crate::{ @@ -22,18 +26,56 @@ }, firmware::fsp::FspFirmware, gpu::Chipset, + mctp::{ + MctpHeader, + NvdmHeader, + NvdmType, // + }, + num, regs, // }; =20 mod hal; =20 +/// FSP message timeout in milliseconds. +const FSP_MSG_TIMEOUT_MS: i64 =3D 2000; + +/// FSP command response payload (`NVDM_PAYLOAD_COMMAND_RESPONSE`). +#[repr(C, packed)] +#[derive(Clone, Copy)] +struct NvdmPayloadCommandResponse { + task_id: u32, + command_nvdm_type: u32, + error_code: u32, +} + +/// Complete FSP response structure with MCTP and NVDM headers. +#[repr(C, packed)] +#[derive(Clone, Copy)] +struct FspResponse { + mctp_header: MctpHeader, + nvdm_header: NvdmHeader, + response: NvdmPayloadCommandResponse, +} + +// SAFETY: FspResponse is a packed C struct with only integral fields. +unsafe impl FromBytes for FspResponse {} + +/// Trait implemented by types representing a message to send to FSP. +/// +/// This provides [`Fsp::send_sync_fsp`] with the information it needs to = send +/// a given message, following the same pattern as GSP's `CommandToGsp`. +pub(crate) trait MessageToFsp: AsBytes { + /// NVDM type identifying this message to FSP. + const NVDM_TYPE: u32; +} + /// FSP interface for Hopper/Blackwell GPUs. /// /// An `Fsp` is produced by [`Fsp::wait_secure_boot`], which only returns = once FSP secure boot /// has completed. It owns the FSP falcon and the FMC firmware, which are = used for the subsequent /// Chain of Trust boot. pub(crate) struct Fsp { - #[expect(dead_code)] falcon: Falcon, #[expect(dead_code)] fsp_fw: FspFirmware, @@ -70,4 +112,79 @@ pub(crate) fn wait_secure_boot( =20 Ok(Fsp { falcon, fsp_fw }) } + + /// Sends a message to FSP and waits for the response. + #[expect(dead_code)] + fn send_sync_fsp(&mut self, dev: &device::Device, bar: &Bar0, msg: = &M) -> Result + where + M: MessageToFsp, + { + self.falcon.send_msg(bar, msg.as_bytes())?; + + let packet_size =3D read_poll_timeout( + || Ok(self.falcon.poll_msgq(bar)), + |&size| size > 0, + Delta::from_millis(10), + Delta::from_millis(FSP_MSG_TIMEOUT_MS), + ) + .map_err(|_| { + dev_err!(dev, "FSP response timeout\n"); + ETIMEDOUT + })?; + + let packet_size =3D num::u32_as_usize(packet_size); + let mut response_buf =3D KVec::::new(); + response_buf.resize(packet_size, 0, GFP_KERNEL)?; + self.falcon.recv_msg(bar, &mut response_buf, packet_size)?; + + let (response, _) =3D FspResponse::from_bytes_prefix(&response_buf= [..]).ok_or_else(|| { + dev_err!(dev, "FSP response too small: {}\n", response_buf.len= ()); + EIO + })?; + + let mctp_header =3D response.mctp_header; + let nvdm_header =3D response.nvdm_header; + let command_nvdm_type =3D response.response.command_nvdm_type; + let error_code =3D response.response.error_code; + + if !mctp_header.is_single_packet() { + dev_err!( + dev, + "Unexpected MCTP header in FSP reply: {:x?}\n", + mctp_header, + ); + return Err(EIO); + } + + if !nvdm_header.validate(NvdmType::FspResponse) { + dev_err!( + dev, + "Unexpected NVDM header in FSP reply: {:x?}\n", + nvdm_header, + ); + return Err(EIO); + } + + if command_nvdm_type !=3D M::NVDM_TYPE { + dev_err!( + dev, + "Expected NVDM type {:#x} in reply, got {:#x}\n", + M::NVDM_TYPE, + command_nvdm_type + ); + return Err(EIO); + } + + if error_code !=3D 0 { + dev_err!( + dev, + "NVDM command {:#x} failed with error {:#x}\n", + M::NVDM_TYPE, + error_code + ); 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charset="utf-8" The FSP Chain of Trust handshake is versioned: Hopper speaks version 1 and Blackwell speaks version 2. Provide the version through the FSP HAL so the boot message carries the value FSP expects, and so chipsets that do not use FSP need not express a version at all. Signed-off-by: John Hubbard Reviewed-by: Eliot Courtney --- drivers/gpu/nova-core/fsp/hal.rs | 8 +++++++- drivers/gpu/nova-core/fsp/hal/gb100.rs | 23 +++++++++++++++++++++++ drivers/gpu/nova-core/fsp/hal/gb202.rs | 4 ++++ drivers/gpu/nova-core/fsp/hal/gh100.rs | 15 ++++++++++++--- 4 files changed, 46 insertions(+), 4 deletions(-) create mode 100644 drivers/gpu/nova-core/fsp/hal/gb100.rs diff --git a/drivers/gpu/nova-core/fsp/hal.rs b/drivers/gpu/nova-core/fsp/h= al.rs index 83d1e7daa998..8f9c031102e0 100644 --- a/drivers/gpu/nova-core/fsp/hal.rs +++ b/drivers/gpu/nova-core/fsp/hal.rs @@ -9,19 +9,25 @@ }, }; =20 +mod gb100; mod gb202; mod gh100; =20 pub(super) trait FspHal { /// Returns the secure boot status from the architecture-specific `NV_= THERM_I2CS_SCRATCH` register. fn fsp_boot_status(&self, bar: &Bar0) -> u32; + + /// Returns the FSP Chain of Trust protocol version this chipset adver= tises. + #[expect(dead_code)] + fn cot_version(&self) -> u16; } =20 /// Returns the FSP HAL, or `None` if the architecture doesn't support FSP. pub(crate) fn fsp_hal(chipset: Chipset) -> Option<&'static dyn FspHal> { match chipset.arch() { Architecture::Turing | Architecture::Ampere | Architecture::Ada = =3D> None, - Architecture::Hopper | Architecture::BlackwellGB10x =3D> Some(gh10= 0::GH100_HAL), + Architecture::Hopper =3D> Some(gh100::GH100_HAL), + Architecture::BlackwellGB10x =3D> Some(gb100::GB100_HAL), Architecture::BlackwellGB20x =3D> Some(gb202::GB202_HAL), } } diff --git a/drivers/gpu/nova-core/fsp/hal/gb100.rs b/drivers/gpu/nova-core= /fsp/hal/gb100.rs new file mode 100644 index 000000000000..d50aaba0a84f --- /dev/null +++ b/drivers/gpu/nova-core/fsp/hal/gb100.rs @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIA= TES. All rights reserved. + +use crate::{ + driver::Bar0, + fsp::hal::FspHal, // +}; + +struct Gb100; + +impl FspHal for Gb100 { + fn fsp_boot_status(&self, bar: &Bar0) -> u32 { + // GB10x shares Hopper's FSP secure boot status register. + super::gh100::fsp_boot_status_gh100(bar) + } + + fn cot_version(&self) -> u16 { + 2 + } +} + +const GB100: Gb100 =3D Gb100; +pub(super) const GB100_HAL: &dyn FspHal =3D &GB100; diff --git a/drivers/gpu/nova-core/fsp/hal/gb202.rs b/drivers/gpu/nova-core= /fsp/hal/gb202.rs index 2f08b6c9f308..2bca76c8fd64 100644 --- a/drivers/gpu/nova-core/fsp/hal/gb202.rs +++ b/drivers/gpu/nova-core/fsp/hal/gb202.rs @@ -17,6 +17,10 @@ fn fsp_boot_status(&self, bar: &Bar0) -> u32 { .fsp_boot_complete() .into() } + + fn cot_version(&self) -> u16 { + 2 + } } =20 const GB202: Gb202 =3D Gb202; diff --git a/drivers/gpu/nova-core/fsp/hal/gh100.rs b/drivers/gpu/nova-core= /fsp/hal/gh100.rs index 290fb55a81da..c38a7e96eb60 100644 --- a/drivers/gpu/nova-core/fsp/hal/gh100.rs +++ b/drivers/gpu/nova-core/fsp/hal/gh100.rs @@ -11,11 +11,20 @@ =20 struct Gh100; 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charset="utf-8" Build and send the Chain of Trust message to FSP, bundling the DMA-coherent boot parameters that FSP reads at boot time. Co-developed-by: Alexandre Courbot Signed-off-by: Alexandre Courbot Signed-off-by: John Hubbard --- drivers/gpu/nova-core/firmware/fsp.rs | 2 - drivers/gpu/nova-core/fsp.rs | 140 +++++++++++++++++- drivers/gpu/nova-core/fsp/hal.rs | 1 - drivers/gpu/nova-core/gsp.rs | 1 + drivers/gpu/nova-core/gsp/fw.rs | 64 ++++++++ .../gpu/nova-core/gsp/fw/r570_144/bindings.rs | 82 ++++++++++ drivers/gpu/nova-core/gsp/hal/gh100.rs | 23 ++- drivers/gpu/nova-core/mctp.rs | 2 - 8 files changed, 302 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/nova-core/firmware/fsp.rs b/drivers/gpu/nova-core/= firmware/fsp.rs index db61905eac9d..938aa3a3bad5 100644 --- a/drivers/gpu/nova-core/firmware/fsp.rs +++ b/drivers/gpu/nova-core/firmware/fsp.rs @@ -39,10 +39,8 @@ pub(crate) struct FmcSignatures { =20 pub(crate) struct FspFirmware { /// FMC firmware image data (only the "image" ELF section). - #[expect(dead_code)] pub(crate) fmc_image: Coherent<[u8]>, /// FMC firmware signatures. - #[expect(dead_code)] pub(crate) fmc_sigs: KBox, } =20 diff --git a/drivers/gpu/nova-core/fsp.rs b/drivers/gpu/nova-core/fsp.rs index 67cf83aba83c..352ef7683cf2 100644 --- a/drivers/gpu/nova-core/fsp.rs +++ b/drivers/gpu/nova-core/fsp.rs @@ -9,8 +9,14 @@ =20 use kernel::{ device, + dma::Coherent, io::poll::read_poll_timeout, prelude::*, + ptr::{ + Alignable, + Alignment, // + }, + sizes::SZ_2M, time::Delta, transmute::{ AsBytes, @@ -24,8 +30,13 @@ fsp::Fsp as FspEngine, Falcon, // }, - firmware::fsp::FspFirmware, + fb::FbLayout, + firmware::fsp::{ + FmcSignatures, + FspFirmware, // + }, gpu::Chipset, + gsp::GspFmcBootParams, mctp::{ MctpHeader, NvdmHeader, @@ -49,6 +60,35 @@ struct NvdmPayloadCommandResponse { error_code: u32, } =20 +/// NVDM (NVIDIA Device Management) CoT (Chain of Trust) payload, the main +/// message body sent to FSP for Chain of Trust boot. +#[repr(C, packed)] +#[derive(Clone, Copy)] +struct NvdmPayloadCot { + version: u16, + size: u16, + gsp_fmc_sysmem_offset: u64, + frts_sysmem_offset: u64, + frts_sysmem_size: u32, + frts_vidmem_offset: u64, + frts_vidmem_size: u32, + sigs: FmcSignatures, + gsp_boot_args_sysmem_offset: u64, +} + +/// Complete FSP message structure with MCTP and NVDM headers. +#[repr(C, packed)] +#[derive(Clone, Copy)] +struct FspMessage { + mctp_header: MctpHeader, + nvdm_header: NvdmHeader, + cot: NvdmPayloadCot, +} + +// SAFETY: `FspMessage` is `#[repr(C, packed)]` with no padding, so all of= its +// bytes are initialized. +unsafe impl AsBytes for FspMessage {} + /// Complete FSP response structure with MCTP and NVDM headers. #[repr(C, packed)] #[derive(Clone, Copy)] @@ -70,6 +110,44 @@ pub(crate) trait MessageToFsp: AsBytes { const NVDM_TYPE: u32; } =20 +impl MessageToFsp for FspMessage { + const NVDM_TYPE: u32 =3D NvdmType::Cot as u32; +} + +/// Bundled arguments for FMC boot via FSP Chain of Trust. +pub(crate) struct FmcBootArgs { + chipset: Chipset, + fmc_boot_params: Coherent, + resume: bool, +} + +impl FmcBootArgs { + /// Builds FMC boot arguments, allocating the DMA-coherent boot parame= ter + /// structure that FSP will read. + pub(crate) fn new( + dev: &device::Device, + chipset: Chipset, + wpr_meta_addr: u64, + libos_addr: u64, + resume: bool, + ) -> Result { + let init =3D GspFmcBootParams::new(wpr_meta_addr, libos_addr); + + Ok(Self { + chipset, + fmc_boot_params: Coherent::::init(dev, GFP_K= ERNEL, init)?, + resume, + }) + } + + /// DMA address of the FMC boot parameters, needed after boot for lock= down + /// release polling. + #[expect(dead_code)] + pub(crate) fn boot_params_dma_handle(&self) -> u64 { + self.fmc_boot_params.dma_handle() + } +} + /// FSP interface for Hopper/Blackwell GPUs. /// /// An `Fsp` is produced by [`Fsp::wait_secure_boot`], which only returns = once FSP secure boot @@ -77,7 +155,6 @@ pub(crate) trait MessageToFsp: AsBytes { /// Chain of Trust boot. pub(crate) struct Fsp { falcon: Falcon, - #[expect(dead_code)] fsp_fw: FspFirmware, } =20 @@ -113,8 +190,65 @@ pub(crate) fn wait_secure_boot( Ok(Fsp { falcon, fsp_fw }) } =20 + /// Boots GSP FMC via FSP Chain of Trust. + /// + /// Builds the CoT message from the pre-configured [`FmcBootArgs`], se= nds it + /// to FSP, and waits for the response. + pub(crate) fn boot_fmc( + &mut self, + dev: &device::Device, + bar: &Bar0, + fb_layout: &FbLayout, + args: &FmcBootArgs, + ) -> Result { + dev_dbg!(dev, "Starting FSP boot sequence for {}\n", args.chipset); + + let fmc_addr =3D self.fsp_fw.fmc_image.dma_handle(); + let fmc_boot_params_addr =3D args.fmc_boot_params.dma_handle(); + + // frts_offset is relative to FB end: FRTS_location =3D FB_END - f= rts_offset + let frts_offset =3D if !args.resume { + let frts_reserved_size =3D fb_layout.heap.len() + u64::from(fb= _layout.pmu_reserved_size); + + frts_reserved_size + .align_up(Alignment::new::()) + .ok_or(EINVAL)? + } else { + 0 + }; + let frts_size: u32 =3D if !args.resume { + fb_layout.frts.len().try_into()? + } else { + 0 + }; + + let msg =3D KBox::new( + FspMessage { + mctp_header: MctpHeader::single_packet(), + nvdm_header: NvdmHeader::new(NvdmType::Cot), + cot: NvdmPayloadCot { + version: hal::fsp_hal(args.chipset).ok_or(ENOTSUPP)?.c= ot_version(), + size: u16::try_from(core::mem::size_of::()) + .map_err(|_| EINVAL)?, + gsp_fmc_sysmem_offset: fmc_addr, + frts_sysmem_offset: 0, + frts_sysmem_size: 0, + frts_vidmem_offset: frts_offset, + frts_vidmem_size: frts_size, + sigs: *self.fsp_fw.fmc_sigs, + gsp_boot_args_sysmem_offset: fmc_boot_params_addr, + }, + }, + GFP_KERNEL, + )?; + + self.send_sync_fsp(dev, bar, &*msg)?; + + dev_dbg!(dev, "FSP Chain of Trust completed successfully\n"); + Ok(()) + } + /// Sends a message to FSP and waits for the response. - #[expect(dead_code)] fn send_sync_fsp(&mut self, dev: &device::Device, bar: &Bar0, msg: = &M) -> Result where M: MessageToFsp, diff --git a/drivers/gpu/nova-core/fsp/hal.rs b/drivers/gpu/nova-core/fsp/h= al.rs index 8f9c031102e0..9b6c5a3bfb6b 100644 --- a/drivers/gpu/nova-core/fsp/hal.rs +++ b/drivers/gpu/nova-core/fsp/hal.rs @@ -18,7 +18,6 @@ pub(super) trait FspHal { fn fsp_boot_status(&self, bar: &Bar0) -> u32; =20 /// Returns the FSP Chain of Trust protocol version this chipset adver= tises. - #[expect(dead_code)] fn cot_version(&self) -> u16; } =20 diff --git a/drivers/gpu/nova-core/gsp.rs b/drivers/gpu/nova-core/gsp.rs index 1885cfa5cb38..69175ca3315c 100644 --- a/drivers/gpu/nova-core/gsp.rs +++ b/drivers/gpu/nova-core/gsp.rs @@ -25,6 +25,7 @@ mod sequencer; =20 pub(crate) use fw::{ + GspFmcBootParams, GspFwWprMeta, LibosParams, // }; diff --git a/drivers/gpu/nova-core/gsp/fw.rs b/drivers/gpu/nova-core/gsp/fw= .rs index 0c54e8bf4bb3..558b37863f00 100644 --- a/drivers/gpu/nova-core/gsp/fw.rs +++ b/drivers/gpu/nova-core/gsp/fw.rs @@ -934,3 +934,67 @@ fn new(cmdq: &Cmdq) -> impl Init + '_ { }) } } + +#[repr(u32)] +pub(crate) enum GspDmaTarget { + #[expect(dead_code)] + LocalFb =3D bindings::GSP_DMA_TARGET_GSP_DMA_TARGET_LOCAL_FB, + CoherentSystem =3D bindings::GSP_DMA_TARGET_GSP_DMA_TARGET_COHERENT_SY= STEM, + NoncoherentSystem =3D bindings::GSP_DMA_TARGET_GSP_DMA_TARGET_NONCOHER= ENT_SYSTEM, +} + +type GspAcrBootGspRmParams =3D bindings::GSP_ACR_BOOT_GSP_RM_PARAMS; + +impl GspAcrBootGspRmParams { + fn new(target: GspDmaTarget, wpr_meta_addr: u64) -> impl Init { + #[allow(non_snake_case)] + let params =3D init!(Self { + target: target as u32, + gspRmDescSize: num::usize_into_u32::<{ size_of::= () }>(), + gspRmDescOffset: wpr_meta_addr, + bIsGspRmBoot: 1, + wprCarveoutOffset: 0, + wprCarveoutSize: 0, + __bindgen_padding_0: Default::default(), + }); + + params + } +} + +type GspRmParams =3D bindings::GSP_RM_PARAMS; + +impl GspRmParams { + fn new(target: GspDmaTarget, libos_addr: u64) -> impl Init { + #[allow(non_snake_case)] + let params =3D init!(Self { + target: target as u32, + bootArgsOffset: libos_addr, + __bindgen_padding_0: Default::default(), + }); + + params + } +} + +pub(crate) type GspFmcBootParams =3D bindings::GSP_FMC_BOOT_PARAMS; + +// SAFETY: Padding is explicit and will not contain uninitialized data. +unsafe impl AsBytes for GspFmcBootParams {} +// SAFETY: This struct only contains integer types for which all bit patte= rns are valid. +unsafe impl FromBytes for GspFmcBootParams {} + +impl GspFmcBootParams { + pub(crate) fn new(wpr_meta_addr: u64, libos_addr: u64) -> impl Init { + #[allow(non_snake_case)] + let init =3D init!(Self { + // Blackwell FSP obtains WPR info from other sources, so + // wprCarveoutOffset and wprCarveoutSize are left zero. + bootGspRmParams <- GspAcrBootGspRmParams::new(GspDmaTarget::Co= herentSystem, wpr_meta_addr), + gspRmParams <- GspRmParams::new(GspDmaTarget::NoncoherentSyste= m, libos_addr), + ..Zeroable::init_zeroed() + }); + + init + } +} diff --git a/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs b/drivers/gp= u/nova-core/gsp/fw/r570_144/bindings.rs index 1d592bd3f9ed..ea350f9b2cc4 100644 --- a/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs +++ b/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs @@ -883,6 +883,88 @@ fn default() -> Self { } } } +pub const GSP_DMA_TARGET_GSP_DMA_TARGET_LOCAL_FB: GSP_DMA_TARGET =3D 0; +pub const GSP_DMA_TARGET_GSP_DMA_TARGET_COHERENT_SYSTEM: GSP_DMA_TARGET = =3D 1; +pub const GSP_DMA_TARGET_GSP_DMA_TARGET_NONCOHERENT_SYSTEM: GSP_DMA_TARGET= =3D 2; +pub const GSP_DMA_TARGET_GSP_DMA_TARGET_COUNT: GSP_DMA_TARGET =3D 3; +pub type GSP_DMA_TARGET =3D ffi::c_uint; +#[repr(C)] +#[derive(Debug, Default, Copy, Clone, MaybeZeroable)] +pub struct GSP_FMC_INIT_PARAMS { + pub regkeys: u32_, +} +#[repr(C)] +#[derive(Debug, Copy, Clone, MaybeZeroable)] +pub struct GSP_ACR_BOOT_GSP_RM_PARAMS { + pub target: GSP_DMA_TARGET, + pub gspRmDescSize: u32_, + pub gspRmDescOffset: u64_, + pub wprCarveoutOffset: u64_, + pub wprCarveoutSize: u32_, + pub bIsGspRmBoot: u8_, + pub __bindgen_padding_0: [u8; 3usize], +} +impl Default for GSP_ACR_BOOT_GSP_RM_PARAMS { + fn default() -> Self { + let mut s =3D ::core::mem::MaybeUninit::::uninit(); + unsafe { + ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1); + s.assume_init() + } + } +} +#[repr(C)] +#[derive(Debug, Copy, Clone, MaybeZeroable)] +pub struct GSP_RM_PARAMS { + pub target: GSP_DMA_TARGET, + pub __bindgen_padding_0: [u8; 4usize], + pub bootArgsOffset: u64_, +} +impl Default for GSP_RM_PARAMS { + fn default() -> Self { + let mut s =3D ::core::mem::MaybeUninit::::uninit(); + unsafe { + ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1); + s.assume_init() + } + } +} +#[repr(C)] +#[derive(Debug, Copy, Clone, MaybeZeroable)] +pub struct GSP_SPDM_PARAMS { + pub target: GSP_DMA_TARGET, + pub __bindgen_padding_0: [u8; 4usize], + pub payloadBufferOffset: u64_, + pub payloadBufferSize: u32_, + pub __bindgen_padding_1: [u8; 4usize], +} +impl Default for GSP_SPDM_PARAMS { + fn default() -> Self { + let mut s =3D ::core::mem::MaybeUninit::::uninit(); + unsafe { + ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1); + s.assume_init() + } + } +} +#[repr(C)] +#[derive(Debug, Copy, Clone, MaybeZeroable)] +pub struct GSP_FMC_BOOT_PARAMS { + pub initParams: GSP_FMC_INIT_PARAMS, + pub __bindgen_padding_0: [u8; 4usize], + pub bootGspRmParams: GSP_ACR_BOOT_GSP_RM_PARAMS, + pub gspRmParams: GSP_RM_PARAMS, + pub gspSpdmParams: GSP_SPDM_PARAMS, +} +impl Default for GSP_FMC_BOOT_PARAMS { + fn default() -> Self { + let mut s =3D ::core::mem::MaybeUninit::::uninit(); + unsafe { + ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1); + s.assume_init() + } + } +} #[repr(C)] #[derive(Debug, Default, Copy, Clone, MaybeZeroable)] pub struct rpc_unloading_guest_driver_v1F_07 { diff --git a/drivers/gpu/nova-core/gsp/hal/gh100.rs b/drivers/gpu/nova-core= /gsp/hal/gh100.rs index b25970dd4561..f41f3fea15ff 100644 --- a/drivers/gpu/nova-core/gsp/hal/gh100.rs +++ b/drivers/gpu/nova-core/gsp/hal/gh100.rs @@ -20,7 +20,10 @@ fsp::FspFirmware, FIRMWARE_VERSION, // }, - fsp::Fsp, + fsp::{ + FmcBootArgs, + Fsp, // + }, gpu::Chipset, gsp::{ boot::BootUnloadGuard, @@ -39,17 +42,27 @@ impl GspHal for Gh100 { /// the GSP boot internally - no manual GSP reset/boot is needed. fn boot<'a>( &self, - _gsp: &'a Gsp, + gsp: &'a Gsp, dev: &'a device::Device, bar: &'a Bar0, chipset: Chipset, - _fb_layout: &FbLayout, - _wpr_meta: &Coherent, + fb_layout: &FbLayout, + wpr_meta: &Coherent, _gsp_falcon: &'a Falcon, _sec2_falcon: &'a Falcon, ) -> Result> { let fsp_fw =3D FspFirmware::new(dev, chipset, FIRMWARE_VERSION)?; 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charset="utf-8" On Hopper and Blackwell, FSP boots GSP with hardware lockdown enabled. After FSP Chain of Trust completes, the driver must poll for lockdown release before proceeding with GSP initialization. Add the register bit and helper functions needed for this polling. Signed-off-by: John Hubbard --- drivers/gpu/nova-core/fsp.rs | 1 - drivers/gpu/nova-core/gsp/hal/gh100.rs | 90 +++++++++++++++++++++++++- drivers/gpu/nova-core/regs.rs | 2 + 3 files changed, 90 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nova-core/fsp.rs b/drivers/gpu/nova-core/fsp.rs index 352ef7683cf2..aec991afa669 100644 --- a/drivers/gpu/nova-core/fsp.rs +++ b/drivers/gpu/nova-core/fsp.rs @@ -142,7 +142,6 @@ pub(crate) fn new( =20 /// DMA address of the FMC boot parameters, needed after boot for lock= down /// release polling. - #[expect(dead_code)] pub(crate) fn boot_params_dma_handle(&self) -> u64 { self.fmc_boot_params.dma_handle() } diff --git a/drivers/gpu/nova-core/gsp/hal/gh100.rs b/drivers/gpu/nova-core= /gsp/hal/gh100.rs index f41f3fea15ff..02aec5281389 100644 --- a/drivers/gpu/nova-core/gsp/hal/gh100.rs +++ b/drivers/gpu/nova-core/gsp/hal/gh100.rs @@ -5,7 +5,13 @@ =20 use kernel::{ device, - dma::Coherent, // + dma::Coherent, + io::{ + poll::read_poll_timeout, + register::WithBase, + Io, // + }, + time::Delta, }; =20 use crate::{ @@ -31,8 +37,85 @@ Gsp, GspFwWprMeta, // }, + regs, }; =20 +/// GSP lockdown pattern written by firmware to mbox0 while RISC-V branch = privilege +/// lockdown is active. The low byte varies, the upper 24 bits are fixed. +const GSP_LOCKDOWN_PATTERN: u32 =3D 0xbadf_4100; +const GSP_LOCKDOWN_MASK: u32 =3D 0xffff_ff00; + +/// GSP falcon mailbox state, used to track lockdown release status. +struct GspMbox { + mbox0: u32, + mbox1: u32, +} + +impl GspMbox { + /// Reads both mailboxes from the GSP falcon. + fn read(gsp_falcon: &Falcon, bar: &Bar0) -> Self { + Self { + mbox0: gsp_falcon.read_mailbox0(bar), + mbox1: gsp_falcon.read_mailbox1(bar), + } + } + + /// Returns `true` if the lockdown pattern is present in `mbox0`. + fn is_locked_down(&self) -> bool { + (self.mbox0 & GSP_LOCKDOWN_MASK) =3D=3D GSP_LOCKDOWN_PATTERN + } + + /// Combines mailbox0 and mailbox1 into a 64-bit address. + fn combined_addr(&self) -> u64 { + (u64::from(self.mbox1) << 32) | u64::from(self.mbox0) + } + + /// Returns `true` if GSP lockdown has been released. + /// + /// Checks the lockdown pattern, validates the boot params address, + /// and verifies the `HWCFG2` lockdown bit is clear. + fn lockdown_released(&self, bar: &Bar0, fmc_boot_params_addr: u64) -> = bool { + if self.is_locked_down() { + return false; + } + + if self.mbox0 !=3D 0 && self.combined_addr() !=3D fmc_boot_params_= addr { + return true; + } + + let hwcfg2 =3D bar.read(regs::NV_PFALCON_FALCON_HWCFG2::of::()); + !hwcfg2.riscv_br_priv_lockdown() + } +} + +/// Waits for GSP lockdown to be released after FSP Chain of Trust. +fn wait_for_gsp_lockdown_release( + dev: &device::Device, + bar: &Bar0, + gsp_falcon: &Falcon, + fmc_boot_params_addr: u64, +) -> Result { + dev_dbg!(dev, "Waiting for GSP lockdown release\n"); + + let mbox =3D read_poll_timeout( + || Ok(GspMbox::read(gsp_falcon, bar)), + |mbox| mbox.lockdown_released(bar, fmc_boot_params_addr), + Delta::from_millis(10), + Delta::from_secs(30), + ) + .inspect_err(|_| { + dev_err!(dev, "GSP lockdown release timeout\n"); + })?; + + if mbox.mbox0 !=3D 0 { + dev_err!(dev, "GSP-FMC boot failed (mbox: {:#x})\n", mbox.mbox0); + return Err(EIO); + } + + dev_dbg!(dev, "GSP lockdown released\n"); + Ok(()) +} + struct Gh100; =20 impl GspHal for Gh100 { @@ -48,7 +131,7 @@ fn boot<'a>( chipset: Chipset, fb_layout: &FbLayout, wpr_meta: &Coherent, - _gsp_falcon: &'a Falcon, + gsp_falcon: &'a Falcon, _sec2_falcon: &'a Falcon, ) -> Result> { let fsp_fw =3D FspFirmware::new(dev, chipset, FIRMWARE_VERSION)?; @@ -64,6 +147,9 @@ fn boot<'a>( =20 fsp.boot_fmc(dev, bar, fb_layout, &args)?; =20 + let fmc_boot_params_addr =3D args.boot_params_dma_handle(); + wait_for_gsp_lockdown_release(dev, bar, gsp_falcon, fmc_boot_param= s_addr)?; + Err(ENOTSUPP) } } diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 8c51609d0281..a4a986f89340 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -363,6 +363,8 @@ pub(crate) fn vga_workspace_addr(self) -> Option { pub(crate) NV_PFALCON_FALCON_HWCFG2(u32) @ PFalconBase + 0x000000f4 { /// Signal indicating that reset is completed (GA102+). 31:31 reset_ready =3D> bool; + /// RISC-V branch privilege lockdown bit. + 13:13 riscv_br_priv_lockdown =3D> bool; /// Set to 0 after memory scrubbing is completed. 12:12 mem_scrubbing =3D> bool; 10:10 riscv =3D> bool; --=20 2.54.0 From nobody Mon Jun 8 04:24:52 2026 Received: from MW6PR02CU001.outbound.protection.outlook.com (mail-westus2azon11012067.outbound.protection.outlook.com [52.101.48.67]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 15B6936D9EB for ; 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charset="utf-8" From: Eliot Courtney For non-sec2 it is only required to wait for GSP falcon to halt. This is because GSP does the main work of unloading on GPUs not using sec2. Signed-off-by: Eliot Courtney [ jhubbard: use Result instead of Result<()> in the UnloadBundle impl ] Signed-off-by: John Hubbard --- drivers/gpu/nova-core/gsp/hal/gh100.rs | 38 ++++++++++++++++++++++++-- 1 file changed, 36 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nova-core/gsp/hal/gh100.rs b/drivers/gpu/nova-core= /gsp/hal/gh100.rs index 02aec5281389..d372ae85c5bc 100644 --- a/drivers/gpu/nova-core/gsp/hal/gh100.rs +++ b/drivers/gpu/nova-core/gsp/hal/gh100.rs @@ -33,7 +33,10 @@ gpu::Chipset, gsp::{ boot::BootUnloadGuard, - hal::GspHal, + hal::{ + GspHal, + UnloadBundle, // + }, Gsp, GspFwWprMeta, // }, @@ -116,6 +119,28 @@ fn wait_for_gsp_lockdown_release( Ok(()) } =20 +struct FspUnloadBundle; + +impl UnloadBundle for FspUnloadBundle { + fn run( + &self, + dev: &device::Device, + bar: &Bar0, + gsp_falcon: &Falcon, + _sec2_falcon: &Falcon, + ) -> Result { + // GSP falcon does most of the work of resetting, so just wait for= it to finish. + read_poll_timeout( + || Ok(gsp_falcon.is_riscv_active(bar)), + |&active| !active, + Delta::from_millis(10), + Delta::from_secs(5), + ) + .map(|_| ()) + .inspect_err(|_| dev_err!(dev, "GSP falcon failed to halt\n")) + } +} + struct Gh100; =20 impl GspHal for Gh100 { @@ -132,9 +157,18 @@ fn boot<'a>( fb_layout: &FbLayout, wpr_meta: &Coherent, gsp_falcon: &'a Falcon, - _sec2_falcon: &'a Falcon, + sec2_falcon: &'a Falcon, ) -> Result> { let fsp_fw =3D FspFirmware::new(dev, chipset, FIRMWARE_VERSION)?; + + let unload_bundle =3D crate::gsp::UnloadBundle( + KBox::new(FspUnloadBundle, GFP_KERNEL)? as KBox + ); + + // Wrap the unload bundle into a drop guard so it is automatically= run upon failure. + let _unload_guard =3D + BootUnloadGuard::new(gsp, dev, bar, gsp_falcon, sec2_falcon, S= ome(unload_bundle)); + let mut fsp =3D Fsp::wait_secure_boot(dev, bar, chipset, fsp_fw)?; =20 let args =3D FmcBootArgs::new( --=20 2.54.0 From nobody Mon Jun 8 04:24:52 2026 Received: from PH0PR06CU001.outbound.protection.outlook.com (mail-westus3azon11011022.outbound.protection.outlook.com [40.107.208.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4E28336F8FA for ; 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charset="utf-8" From: Alexandre Courbot Now that all the elements are in place, enable the FSP boot path so Hopper and Blackwell can boot. Signed-off-by: Alexandre Courbot Signed-off-by: John Hubbard --- drivers/gpu/nova-core/gsp/hal/gh100.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nova-core/gsp/hal/gh100.rs b/drivers/gpu/nova-core= /gsp/hal/gh100.rs index d372ae85c5bc..93d8a72fe930 100644 --- a/drivers/gpu/nova-core/gsp/hal/gh100.rs +++ b/drivers/gpu/nova-core/gsp/hal/gh100.rs @@ -166,7 +166,7 @@ fn boot<'a>( ); =20 // Wrap the unload bundle into a drop guard so it is automatically= run upon failure. - let _unload_guard =3D + let unload_guard =3D BootUnloadGuard::new(gsp, dev, bar, gsp_falcon, sec2_falcon, S= ome(unload_bundle)); =20 let mut fsp =3D Fsp::wait_secure_boot(dev, bar, chipset, fsp_fw)?; @@ -184,7 +184,7 @@ fn boot<'a>( let fmc_boot_params_addr =3D args.boot_params_dma_handle(); wait_for_gsp_lockdown_release(dev, bar, gsp_falcon, fmc_boot_param= s_addr)?; =20 - Err(ENOTSUPP) + Ok(unload_guard) } } =20 --=20 2.54.0