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Mon, 01 Jun 2026 19:07:41 -0700 (PDT) Received: from ryzen ([2601:644:8000:5b5d:7285:c2ff:fe45:8a32]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2bf23c1e46asm115215045ad.61.2026.06.01.19.07.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jun 2026 19:07:41 -0700 (PDT) From: Rosen Penev To: linux-mtd@lists.infradead.org Cc: Miquel Raynal , chleroy@kernel.org, Richard Weinberger , Vignesh Raghavendra , linux-kernel@vger.kernel.org (open list) Subject: [PATCH] mtd: rawnand: ndfc: use ioread32be/iowrite32be and allow COMPILE_TEST Date: Mon, 1 Jun 2026 19:07:23 -0700 Message-ID: <20260602020723.533971-1-rosenp@gmail.com> X-Mailer: git-send-email 2.54.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Replace ppc4xx-specific in_be32/out_be32 with generic ioread32be/ iowrite32be to make the driver portable. Add COMPILE_TEST dependency to get build coverage on non-ppc4xx architectures. While at it, replace 4xx with 44x. The latter was removed a while ago and is only kept for compatibility. Assisted-by: opencode:big-pickle Signed-off-by: Rosen Penev --- drivers/mtd/nand/raw/Kconfig | 2 +- drivers/mtd/nand/raw/ndfc.c | 20 ++++++++++---------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index d488213b631f..64b8b99a3a68 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -71,7 +71,7 @@ config MTD_NAND_AU1550 =20 config MTD_NAND_NDFC tristate "IBM/MCC 4xx NAND controller" - depends on 4xx + depends on 44x || COMPILE_TEST select MTD_NAND_ECC_SW_HAMMING select MTD_NAND_ECC_SW_HAMMING_SMC help diff --git a/drivers/mtd/nand/raw/ndfc.c b/drivers/mtd/nand/raw/ndfc.c index 7ad8bc04be1a..a937ca3eeff5 100644 --- a/drivers/mtd/nand/raw/ndfc.c +++ b/drivers/mtd/nand/raw/ndfc.c @@ -44,13 +44,13 @@ static void ndfc_select_chip(struct nand_chip *nchip, i= nt chip) uint32_t ccr; struct ndfc_controller *ndfc =3D nand_get_controller_data(nchip); =20 - ccr =3D in_be32(ndfc->ndfcbase + NDFC_CCR); + ccr =3D ioread32be(ndfc->ndfcbase + NDFC_CCR); if (chip >=3D 0) { ccr &=3D ~NDFC_CCR_BS_MASK; ccr |=3D NDFC_CCR_BS(chip + ndfc->chip_select); } else ccr |=3D NDFC_CCR_RESET_CE; - out_be32(ndfc->ndfcbase + NDFC_CCR, ccr); + iowrite32be(ccr, ndfc->ndfcbase + NDFC_CCR); } =20 static void ndfc_hwcontrol(struct nand_chip *chip, int cmd, unsigned int c= trl) @@ -70,7 +70,7 @@ static int ndfc_ready(struct nand_chip *chip) { struct ndfc_controller *ndfc =3D nand_get_controller_data(chip); =20 - return in_be32(ndfc->ndfcbase + NDFC_STAT) & NDFC_STAT_IS_READY; + return ioread32be(ndfc->ndfcbase + NDFC_STAT) & NDFC_STAT_IS_READY; } =20 static void ndfc_enable_hwecc(struct nand_chip *chip, int mode) @@ -78,9 +78,9 @@ static void ndfc_enable_hwecc(struct nand_chip *chip, int= mode) uint32_t ccr; struct ndfc_controller *ndfc =3D nand_get_controller_data(chip); =20 - ccr =3D in_be32(ndfc->ndfcbase + NDFC_CCR); + ccr =3D ioread32be(ndfc->ndfcbase + NDFC_CCR); ccr |=3D NDFC_CCR_RESET_ECC; - out_be32(ndfc->ndfcbase + NDFC_CCR, ccr); + iowrite32be(ccr, ndfc->ndfcbase + NDFC_CCR); wmb(); } =20 @@ -92,7 +92,7 @@ static int ndfc_calculate_ecc(struct nand_chip *chip, uint8_t *p =3D (uint8_t *)&ecc; =20 wmb(); - ecc =3D in_be32(ndfc->ndfcbase + NDFC_ECC); + ecc =3D ioread32be(ndfc->ndfcbase + NDFC_ECC); /* The NDFC uses Smart Media (SMC) bytes order */ ecc_code[0] =3D p[1]; ecc_code[1] =3D p[2]; @@ -114,7 +114,7 @@ static void ndfc_read_buf(struct nand_chip *chip, uint8= _t *buf, int len) uint32_t *p =3D (uint32_t *) buf; =20 for(;len > 0; len -=3D 4) - *p++ =3D in_be32(ndfc->ndfcbase + NDFC_DATA); + *p++ =3D ioread32be(ndfc->ndfcbase + NDFC_DATA); } =20 static void ndfc_write_buf(struct nand_chip *chip, const uint8_t *buf, int= len) @@ -123,7 +123,7 @@ static void ndfc_write_buf(struct nand_chip *chip, cons= t uint8_t *buf, int len) uint32_t *p =3D (uint32_t *) buf; =20 for(;len > 0; len -=3D 4) - out_be32(ndfc->ndfcbase + NDFC_DATA, *p++); + iowrite32be(*p++, ndfc->ndfcbase + NDFC_DATA); } =20 /* @@ -223,13 +223,13 @@ static int ndfc_probe(struct platform_device *ofdev) if (reg) ccr |=3D be32_to_cpup(reg); =20 - out_be32(ndfc->ndfcbase + NDFC_CCR, ccr); + iowrite32be(ccr, ndfc->ndfcbase + NDFC_CCR); =20 /* Set the bank settings if given */ reg =3D of_get_property(ofdev->dev.of_node, "bank-settings", NULL); if (reg) { int offset =3D NDFC_BCFG0 + (ndfc->chip_select << 2); - out_be32(ndfc->ndfcbase + offset, be32_to_cpup(reg)); + iowrite32be(be32_to_cpup(reg), ndfc->ndfcbase + offset); } =20 err =3D ndfc_chip_init(ndfc, ofdev->dev.of_node); --=20 2.54.0