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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-137b3d8f839sm8006025c88.15.2026.06.02.01.08.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 01:08:14 -0700 (PDT) From: Qiang Yu Date: Tue, 02 Jun 2026 01:02:17 -0700 Subject: [PATCH v5 1/7] dt-bindings: clock: qcom: Move glymur TCSR to own binding and add mahua Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260602-tcsr_qref_0527-v5-1-8ea174a59d7e@oss.qualcomm.com> References: <20260602-tcsr_qref_0527-v5-0-8ea174a59d7e@oss.qualcomm.com> In-Reply-To: <20260602-tcsr_qref_0527-v5-0-8ea174a59d7e@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Qiang Yu , krishna.chundru@oss.qualcomm.com X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780387692; l=6370; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=FAKBWcIX5mgY1WAddlCaxXrp5BD2oKuWSr+axNOz1nY=; b=UddEBnN7GiB2L2JeGtrEwfLrn6/aTN2yJqcAiOPX6043r20fVlM5xWlkUG5GoM5GJnnys/eaJ gNaHTe/eZIyAK+opBgOXFASZwqHoDuvEoUEUfQ7UNVneS/kSQa6aZPa X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjAyMDA3NSBTYWx0ZWRfX0//QWKm7hMUb uw9dL+GS6IvzMLQt1bX/1tDguT/aEW5qr0ApxYBIeL92E6VWK9tHQmIFYPcEeWtEvWqm/tgjSq0 leKxFBo87jrFAvPAkUp7ak0ZsM730eDA87oPDYFawHpcVJ7bqmkNb4C+IFhO1TGMCuY6qreYxma 0b6mzmimbCeVb1TyW4T7KEd4m1CI9eebiBKHsT8vJnavucTedH/z6F11L9oNCgFB5CeNzuZPKp8 6IyuYEV8eNN4n/cGixdagzjwu8/Wt89bsjBUa/dzxada4hJgU2WBAt/gZKb1HemKd4YQ4zQW6ru kTBuBoTLvqkIT03QlJk+zjD+kHLozl8fCNZiUCcKrD7J8/taKw+tLRkfvPgVGL3t/sErhDbt1UJ /fSDKvs9hqM/cQdtRE0ICUCQrfSyiOdJkq/xR7HEGn5tWXauU6RBKg9hZbRTzhbROFzV+aUCmqK 3Mu59r+dRerFNYINsAg== X-Proofpoint-GUID: HZYp0lR9m5HLYzN-7v8Ejm5X489iheiQ X-Authority-Analysis: v=2.4 cv=AJZ7LEvz c=1 sm=1 tr=0 ts=6a1e8f70 cx=c_pps a=bS7HVuBVfinNPG3f6cIo3Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=fCDs2mesohUn3a4l0kMA:9 a=QEXdDO2ut3YA:10 a=vBUdepa8ALXHeOFLBtFW:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-ORIG-GUID: HZYp0lR9m5HLYzN-7v8Ejm5X489iheiQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-01_07,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 suspectscore=0 malwarescore=0 phishscore=0 bulkscore=0 impostorscore=0 clxscore=1015 lowpriorityscore=0 spamscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606020075 The QREF block supplies reference clocks to PCIe PHYs and requires dedicated LDO supplies to operate. The digital control interface for QREF (clkref_en registers) resides in TCSR on glymur and mahua. Since QREF has no dedicated DT node of its own, these supply properties are placed in the TCSR node which acts as the control interface for QREF. Add a dedicated binding file for qcom,glymur-tcsr and qcom,mahua-tcsr and document the supply properties. Both SoCs share the same QREF TX/RPT/RX component naming, but differ in topology: Glymur has two independent QREF blocks fed by REFGEN3 and REFGEN4. Mahua has a single QREF block fed by REFGEN3 only. Mark the relevant supplies as required per compatible using allOf/if/then conditionals. Signed-off-by: Qiang Yu --- .../bindings/clock/qcom,glymur-tcsr.yaml | 146 +++++++++++++++++= ++++ .../bindings/clock/qcom,sm8550-tcsr.yaml | 2 - 2 files changed, 146 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,glymur-tcsr.yaml = b/Documentation/devicetree/bindings/clock/qcom,glymur-tcsr.yaml new file mode 100644 index 000000000000..2b6422627165 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,glymur-tcsr.yaml @@ -0,0 +1,146 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,glymur-tcsr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm TCSR Clock Controller on Glymur + +maintainers: + - Bjorn Andersson + - Taniya Das + +description: | + Qualcomm TCSR clock control module provides the clocks, resets and + power domains on Glymur + + See also: + - include/dt-bindings/clock/qcom,glymur-tcsr.h + +properties: + compatible: + items: + - enum: + - qcom,glymur-tcsr + - qcom,mahua-tcsr + - const: syscon + + clocks: + items: + - description: TCXO pad clock + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + vdda-qrefrpt0-0p9-supply: true + vdda-qrefrpt1-0p9-supply: true + vdda-qrefrpt2-0p9-supply: true + vdda-qrefrpt3-0p9-supply: true + vdda-qrefrpt4-0p9-supply: true + vdda-qrefrpt5-0p9-supply: true + vdda-qrefrx0-0p9-supply: true + vdda-qrefrx1-0p9-supply: true + vdda-qrefrx2-0p9-supply: true + vdda-qrefrx3-0p9-supply: true + vdda-qrefrx4-0p9-supply: true + vdda-qrefrx5-0p9-supply: true + vdda-qreftx0-0p9-supply: true + vdda-qreftx0-1p2-supply: true + vdda-qreftx1-0p9-supply: true + vdda-refgen3-0p9-supply: true + vdda-refgen3-1p2-supply: true + vdda-refgen4-0p9-supply: true + vdda-refgen4-1p2-supply: true + +allOf: + - if: + properties: + compatible: + contains: + const: qcom,glymur-tcsr + then: + required: + - vdda-qrefrpt0-0p9-supply + - vdda-qrefrpt1-0p9-supply + - vdda-qrefrpt2-0p9-supply + - vdda-qrefrpt3-0p9-supply + - vdda-qrefrpt4-0p9-supply + - vdda-qrefrx0-0p9-supply + - vdda-qrefrx1-0p9-supply + - vdda-qrefrx2-0p9-supply + - vdda-qrefrx4-0p9-supply + - vdda-qrefrx5-0p9-supply + - vdda-qreftx0-0p9-supply + - vdda-qreftx0-1p2-supply + - vdda-qreftx1-0p9-supply + - vdda-refgen3-0p9-supply + - vdda-refgen3-1p2-supply + - vdda-refgen4-0p9-supply + - vdda-refgen4-1p2-supply + - if: + properties: + compatible: + contains: + const: qcom,mahua-tcsr + then: + required: + - vdda-qrefrpt0-0p9-supply + - vdda-qrefrpt1-0p9-supply + - vdda-qrefrpt2-0p9-supply + - vdda-qrefrpt3-0p9-supply + - vdda-qrefrpt4-0p9-supply + - vdda-qrefrpt5-0p9-supply + - vdda-qrefrx1-0p9-supply + - vdda-qrefrx2-0p9-supply + - vdda-qrefrx3-0p9-supply + - vdda-qreftx1-0p9-supply + - vdda-refgen3-0p9-supply + - vdda-refgen3-1p2-supply + +required: + - compatible + - clocks + +additionalProperties: false + +examples: + - | + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + clock-controller@1fd5000 { + compatible =3D "qcom,glymur-tcsr", "syscon"; + reg =3D <0x0 0x1fd5000 0x0 0x21000>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + vdda-qrefrpt0-0p9-supply =3D <&vreg_l1a>; + vdda-qrefrpt1-0p9-supply =3D <&vreg_l1a>; + vdda-qrefrpt2-0p9-supply =3D <&vreg_l1a>; + vdda-qrefrpt3-0p9-supply =3D <&vreg_l1a>; + vdda-qrefrpt4-0p9-supply =3D <&vreg_l1a>; + vdda-qrefrx0-0p9-supply =3D <&vreg_l1a>; + vdda-qrefrx1-0p9-supply =3D <&vreg_l1a>; + vdda-qrefrx2-0p9-supply =3D <&vreg_l1a>; + vdda-qrefrx4-0p9-supply =3D <&vreg_l1a>; + vdda-qrefrx5-0p9-supply =3D <&vreg_l1a>; + vdda-qreftx0-0p9-supply =3D <&vreg_l1a>; + vdda-qreftx0-1p2-supply =3D <&vreg_l2a>; + vdda-qreftx1-0p9-supply =3D <&vreg_l1a>; + vdda-refgen3-0p9-supply =3D <&vreg_l1a>; + vdda-refgen3-1p2-supply =3D <&vreg_l2a>; + vdda-refgen4-0p9-supply =3D <&vreg_l1a>; + vdda-refgen4-1p2-supply =3D <&vreg_l2a>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml = b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml index 08824f848973..19ae0634b922 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml @@ -16,7 +16,6 @@ description: | =20 See also: - include/dt-bindings/clock/qcom,eliza-tcsr.h - - include/dt-bindings/clock/qcom,glymur-tcsr.h - include/dt-bindings/clock/qcom,hawi-tcsrcc.h - include/dt-bindings/clock/qcom,nord-tcsrcc.h - include/dt-bindings/clock/qcom,sm8550-tcsr.h @@ -28,7 +27,6 @@ properties: items: - enum: - qcom,eliza-tcsr - - qcom,glymur-tcsr - qcom,hawi-tcsrcc - qcom,kaanapali-tcsr - qcom,milos-tcsr --=20 2.34.1 From nobody Mon Jun 8 04:26:42 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F5B33A8749 for ; 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QREF is powered by dedicated LDO rails, and the clkref_en register controls whether refclk is gated through to the PHY side. These clkref controls are different from typical GCC branch clocks: - only a single enable bit is present, without branch-style config bits - regulators must be voted before enable and unvoted after disable Model this as a dedicated clk_ref clock type with custom clk_ops instead of reusing struct clk_branch semantics. Also provide a common registration/probe API so the same clkref model can be reused regardless of where clkref_en registers are placed, e.g. TCSR on glymur and TLMM on SM8750. Signed-off-by: Qiang Yu --- drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-ref.c | 205 +++++++++++++++++++++++++++++++++++++++++= ++++ include/linux/clk/qcom.h | 69 +++++++++++++++ 3 files changed, 275 insertions(+) diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index e100cfd6a52d..c5b02360861d 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -8,6 +8,7 @@ clk-qcom-y +=3D clk-pll.o clk-qcom-y +=3D clk-rcg.o clk-qcom-y +=3D clk-rcg2.o clk-qcom-y +=3D clk-branch.o +clk-qcom-y +=3D clk-ref.o clk-qcom-y +=3D clk-regmap-divider.o clk-qcom-y +=3D clk-regmap-mux.o clk-qcom-y +=3D clk-regmap-mux-div.o diff --git a/drivers/clk/qcom/clk-ref.c b/drivers/clk/qcom/clk-ref.c new file mode 100644 index 000000000000..af82e344ddc4 --- /dev/null +++ b/drivers/clk/qcom/clk-ref.c @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2026, Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define QCOM_CLK_REF_EN_MASK BIT(0) + +struct qcom_clk_ref_provider { + struct qcom_clk_ref *refs; + size_t num_refs; +}; + +static inline struct qcom_clk_ref *to_qcom_clk_ref(struct clk_hw *hw) +{ + return container_of(hw, struct qcom_clk_ref, hw); +} + +static const struct clk_parent_data qcom_clk_ref_parent_data =3D { + .index =3D 0, +}; + +static int qcom_clk_ref_prepare(struct clk_hw *hw) +{ + struct qcom_clk_ref *rclk =3D to_qcom_clk_ref(hw); + int ret; + + if (!rclk->desc.num_regulators) + return 0; + + ret =3D regulator_bulk_enable(rclk->desc.num_regulators, rclk->regulators= ); + if (ret) + pr_err("Failed to enable regulators for %s: %d\n", + clk_hw_get_name(hw), ret); + + return ret; +} + +static void qcom_clk_ref_unprepare(struct clk_hw *hw) +{ + struct qcom_clk_ref *rclk =3D to_qcom_clk_ref(hw); + + if (rclk->desc.num_regulators) + regulator_bulk_disable(rclk->desc.num_regulators, rclk->regulators); +} + +static int qcom_clk_ref_enable(struct clk_hw *hw) +{ + struct qcom_clk_ref *rclk =3D to_qcom_clk_ref(hw); + int ret; + + ret =3D regmap_update_bits(rclk->regmap, rclk->desc.offset, QCOM_CLK_REF_= EN_MASK, + QCOM_CLK_REF_EN_MASK); + if (ret) + return ret; + + udelay(10); + + return 0; +} + +static void qcom_clk_ref_disable(struct clk_hw *hw) +{ + struct qcom_clk_ref *rclk =3D to_qcom_clk_ref(hw); + + regmap_update_bits(rclk->regmap, rclk->desc.offset, QCOM_CLK_REF_EN_MASK,= 0); + udelay(10); +} + +static int qcom_clk_ref_is_enabled(struct clk_hw *hw) +{ + struct qcom_clk_ref *rclk =3D to_qcom_clk_ref(hw); + u32 val; + int ret; + + ret =3D regmap_read(rclk->regmap, rclk->desc.offset, &val); + if (ret) + return 0; + + return !!(val & QCOM_CLK_REF_EN_MASK); +} + +static const struct clk_ops qcom_clk_ref_ops =3D { + .prepare =3D qcom_clk_ref_prepare, + .unprepare =3D qcom_clk_ref_unprepare, + .enable =3D qcom_clk_ref_enable, + .disable =3D qcom_clk_ref_disable, + .is_enabled =3D qcom_clk_ref_is_enabled, +}; + +static int qcom_clk_ref_register(struct device *dev, struct regmap *regmap, + struct qcom_clk_ref *clk_refs, + const struct qcom_clk_ref_desc *descs, + size_t num_clk_refs) +{ + const struct qcom_clk_ref_desc *desc; + struct qcom_clk_ref *clk_ref; + size_t clk_idx; + unsigned int i; + int ret; + + for (clk_idx =3D 0; clk_idx < num_clk_refs; clk_idx++) { + clk_ref =3D &clk_refs[clk_idx]; + desc =3D &descs[clk_idx]; + + if (!desc->name) + continue; + + clk_ref->regmap =3D regmap; + clk_ref->desc =3D *desc; + + if (clk_ref->desc.num_regulators) { + clk_ref->regulators =3D devm_kcalloc(dev, clk_ref->desc.num_regulators, + sizeof(*clk_ref->regulators), + GFP_KERNEL); + if (!clk_ref->regulators) + return -ENOMEM; + + for (i =3D 0; i < clk_ref->desc.num_regulators; i++) + clk_ref->regulators[i].supply =3D + clk_ref->desc.regulator_names[i]; + + ret =3D devm_regulator_bulk_get(dev, clk_ref->desc.num_regulators, + clk_ref->regulators); + if (ret) + return dev_err_probe(dev, ret, + "Failed to get regulators for %s\n", + clk_ref->desc.name); + } + + clk_ref->init_data.name =3D clk_ref->desc.name; + clk_ref->init_data.parent_data =3D &qcom_clk_ref_parent_data; + clk_ref->init_data.num_parents =3D 1; + clk_ref->init_data.ops =3D &qcom_clk_ref_ops; + clk_ref->hw.init =3D &clk_ref->init_data; + + ret =3D devm_clk_hw_register(dev, &clk_ref->hw); + if (ret) + return ret; + } + + return 0; +} + +static struct clk_hw *qcom_clk_ref_provider_get(struct of_phandle_args *cl= kspec, void *data) +{ + struct qcom_clk_ref_provider *provider =3D data; + unsigned int idx =3D clkspec->args[0]; + + if (idx >=3D provider->num_refs) + return ERR_PTR(-EINVAL); + + if (!provider->refs[idx].regmap) + return ERR_PTR(-ENOENT); + + return &provider->refs[idx].hw; +} + +int qcom_clk_ref_probe(struct platform_device *pdev, + const struct regmap_config *config, + const struct qcom_clk_ref_desc *descs, + size_t num_clk_refs) +{ + struct qcom_clk_ref_provider *provider; + struct device *dev =3D &pdev->dev; + struct regmap *regmap; + void __iomem *base; + int ret; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + regmap =3D devm_regmap_init_mmio(dev, base, config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + provider =3D devm_kzalloc(dev, sizeof(*provider), GFP_KERNEL); + if (!provider) + return -ENOMEM; + + provider->refs =3D devm_kcalloc(dev, num_clk_refs, sizeof(*provider->refs= ), + GFP_KERNEL); + if (!provider->refs) + return -ENOMEM; + + provider->num_refs =3D num_clk_refs; + + ret =3D qcom_clk_ref_register(dev, regmap, provider->refs, descs, + provider->num_refs); + if (ret) + return ret; + + return devm_of_clk_add_hw_provider(dev, qcom_clk_ref_provider_get, provid= er); +} +EXPORT_SYMBOL_GPL(qcom_clk_ref_probe); diff --git a/include/linux/clk/qcom.h b/include/linux/clk/qcom.h new file mode 100644 index 000000000000..09e2e3178cfb --- /dev/null +++ b/include/linux/clk/qcom.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2026, Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __LINUX_CLK_QCOM_H +#define __LINUX_CLK_QCOM_H + +#include +#include +#include +#include +#include + +struct device; +struct platform_device; +struct regulator_bulk_data; + +/** + * struct qcom_clk_ref_desc - descriptor for a clkref_en gate clock + * @name: clock name exposed to the common clock framework + * @offset: clkref_en register offset from the block base + * @regulator_names: optional supply names enabled while preparing the clo= ck + * @num_regulators: number of entries in @regulator_names + */ +struct qcom_clk_ref_desc { + const char *name; + u32 offset; + const char * const *regulator_names; + unsigned int num_regulators; +}; + +/** + * struct qcom_clk_ref - per-clock data for a clkref_en gate clock + * @hw: common clock framework hardware clock handle + * @init_data: common clock framework registration data + * @regmap: register map backing the clkref_en register + * @desc: clock descriptor copied at registration time + * @regulators: optional bulk regulator handles for @desc.regulator_names + */ +struct qcom_clk_ref { + struct clk_hw hw; + struct clk_init_data init_data; + struct regmap *regmap; + struct qcom_clk_ref_desc desc; + struct regulator_bulk_data *regulators; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-137b3d8f839sm8006025c88.15.2026.06.02.01.08.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 01:08:17 -0700 (PDT) From: Qiang Yu Date: Tue, 02 Jun 2026 01:02:19 -0700 Subject: [PATCH v5 3/7] clk: qcom: tcsrcc-glymur: Migrate tcsr_pcie_N_clkref_en to clk_ref common helper Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260602-tcsr_qref_0527-v5-3-8ea174a59d7e@oss.qualcomm.com> References: <20260602-tcsr_qref_0527-v5-0-8ea174a59d7e@oss.qualcomm.com> In-Reply-To: <20260602-tcsr_qref_0527-v5-0-8ea174a59d7e@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Qiang Yu , krishna.chundru@oss.qualcomm.com X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780387692; l=11025; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=O3ZxKboNsvmFGx4zTywd6Z8ltIMwvsi+CEsUiesxLPI=; b=6DYnC/eNuEdAgwV+SBvye0Qj6AFiBApEa9HEyZbmzx/pTnOcbaefOrCsumFHAYi/UWzi5dnll SFBg3JQxq8HDTf07RLKpN+QToSCDfhdcCKe81Z5oV/o5wErLgBxQlkE X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjAyMDA3NSBTYWx0ZWRfX6iB/0jNUXa+D kvfWsukFbdRDFA0xuQpV+mqbHbsXURCYHmXZ+UkQJJGBom4xl6QuaUqYAu+msTVRSjLR9LAH1mH dBw0B6/mepeZXd6//aMHAmnnvFtJrq3opoOrHab0m4vLSBciNd4RQKsynyQzvHoZKXy9nXiNKQJ Ofx7Ujrg8JcLb4nxQDcJmprEfVnkFwNp8nu9NnwylMBQ4iQyK+kBtl9eqtvl/AUPJ/dbaDekTaq Di+TdthZvcPKx1SBDaV8nbwd2VjmkUjFvkl0W+5+xJ2jb7b9G2fqFC+MUbo1W6V3P8DOGH1Xwci DMyKMNXxQtMHOum6qpe/euz/g+s1XkjZL2/ol1j5rto2ZJGTTrZqsPChRBrMlvk+ZncinmsWi3B 22fk1fzRfNHP3GsFXoqAyyuBr+/NpQukXyBKy/3ObAOL2oRy5sSxG6Jaa/LvUWnFcO9tjZrujjB IOPDMywRntF9H4s8jRw== X-Proofpoint-ORIG-GUID: 50VaSB12PGdD-nlHIaGiQ0JeFmuIRyNB X-Proofpoint-GUID: 50VaSB12PGdD-nlHIaGiQ0JeFmuIRyNB X-Authority-Analysis: v=2.4 cv=Rrv16imK c=1 sm=1 tr=0 ts=6a1e8f75 cx=c_pps a=SvEPeNj+VMjHSW//kvnxuw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=IStsj7P7hPwQKhcmRzYA:9 a=QEXdDO2ut3YA:10 a=Kq8ClHjjuc5pcCNDwlU0:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-01_07,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 spamscore=0 suspectscore=0 impostorscore=0 phishscore=0 priorityscore=1501 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606020075 Replace local clk_branch-based clkref definitions with descriptor-based registration via qcom_clk_ref_probe(). This keeps the glymur driver focused on clock metadata and reuses common runtime logic for regulator handling, enable/disable sequencing, and OF provider wiring. Signed-off-by: Qiang Yu --- drivers/clk/qcom/tcsrcc-glymur.c | 330 ++++++++++-------------------------= ---- 1 file changed, 83 insertions(+), 247 deletions(-) diff --git a/drivers/clk/qcom/tcsrcc-glymur.c b/drivers/clk/qcom/tcsrcc-gly= mur.c index 9c0edebcdbb1..e317003398d1 100644 --- a/drivers/clk/qcom/tcsrcc-glymur.c +++ b/drivers/clk/qcom/tcsrcc-glymur.c @@ -4,277 +4,111 @@ */ =20 #include +#include #include #include +#include #include #include =20 #include =20 -#include "clk-alpha-pll.h" -#include "clk-branch.h" -#include "clk-pll.h" -#include "clk-rcg.h" -#include "clk-regmap.h" -#include "clk-regmap-divider.h" -#include "clk-regmap-mux.h" -#include "common.h" -#include "gdsc.h" -#include "reset.h" - -enum { - DT_BI_TCXO_PAD, +static const char * const glymur_tcsr_tx0_rx5_regulators[] =3D { + "vdda-refgen3-0p9", + "vdda-refgen3-1p2", + "vdda-qrefrx5-0p9", + "vdda-qreftx0-0p9", + "vdda-qreftx0-1p2", }; =20 -static struct clk_branch tcsr_edp_clkref_en =3D { - .halt_reg =3D 0x60, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x60, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_edp_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, - }, +static const char * const glymur_tcsr_tx1_rpt01_rx1_regulators[] =3D { + "vdda-refgen4-0p9", + "vdda-refgen4-1p2", + "vdda-qreftx1-0p9", + "vdda-qrefrpt0-0p9", + "vdda-qrefrpt1-0p9", + "vdda-qrefrx1-0p9", }; =20 -static struct clk_branch tcsr_pcie_1_clkref_en =3D { - .halt_reg =3D 0x48, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x48, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_pcie_1_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, - }, +static const char * const glymur_tcsr_tx1_rpt012_rx2_regulators[] =3D { + "vdda-refgen4-0p9", + "vdda-refgen4-1p2", + "vdda-qreftx1-0p9", + "vdda-qrefrpt0-0p9", + "vdda-qrefrpt1-0p9", + "vdda-qrefrpt2-0p9", + "vdda-qrefrx2-0p9", }; =20 -static struct clk_branch tcsr_pcie_2_clkref_en =3D { - .halt_reg =3D 0x4c, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x4c, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_pcie_2_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, - }, +static const struct regmap_config tcsr_cc_glymur_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x94, + .fast_io =3D true, }; =20 -static struct clk_branch tcsr_pcie_3_clkref_en =3D { - .halt_reg =3D 0x54, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x54, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_pcie_3_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, +static const struct qcom_clk_ref_desc tcsr_cc_glymur_clk_descs[] =3D { + [TCSR_EDP_CLKREF_EN] =3D { + .name =3D "tcsr_edp_clkref_en", + .offset =3D 0x60, }, -}; - -static struct clk_branch tcsr_pcie_4_clkref_en =3D { - .halt_reg =3D 0x58, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x58, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_pcie_4_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_PCIE_1_CLKREF_EN] =3D { + .name =3D "tcsr_pcie_1_clkref_en", + .offset =3D 0x48, + .regulator_names =3D glymur_tcsr_tx0_rx5_regulators, + .num_regulators =3D ARRAY_SIZE(glymur_tcsr_tx0_rx5_regulators), }, -}; - -static struct clk_branch tcsr_usb2_1_clkref_en =3D { - .halt_reg =3D 0x6c, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x6c, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_usb2_1_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_PCIE_2_CLKREF_EN] =3D { + .name =3D "tcsr_pcie_2_clkref_en", + .offset =3D 0x4c, + .regulator_names =3D glymur_tcsr_tx1_rpt012_rx2_regulators, + .num_regulators =3D ARRAY_SIZE(glymur_tcsr_tx1_rpt012_rx2_regulators), }, -}; - -static struct clk_branch tcsr_usb2_2_clkref_en =3D { - .halt_reg =3D 0x70, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x70, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_usb2_2_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_PCIE_3_CLKREF_EN] =3D { + .name =3D "tcsr_pcie_3_clkref_en", + .offset =3D 0x54, + .regulator_names =3D glymur_tcsr_tx1_rpt01_rx1_regulators, + .num_regulators =3D ARRAY_SIZE(glymur_tcsr_tx1_rpt01_rx1_regulators), }, -}; - -static struct clk_branch tcsr_usb2_3_clkref_en =3D { - .halt_reg =3D 0x74, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x74, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_usb2_3_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_PCIE_4_CLKREF_EN] =3D { + .name =3D "tcsr_pcie_4_clkref_en", + .offset =3D 0x58, + .regulator_names =3D glymur_tcsr_tx1_rpt012_rx2_regulators, + .num_regulators =3D ARRAY_SIZE(glymur_tcsr_tx1_rpt012_rx2_regulators), }, -}; - -static struct clk_branch tcsr_usb2_4_clkref_en =3D { - .halt_reg =3D 0x88, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x88, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_usb2_4_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_USB2_1_CLKREF_EN] =3D { + .name =3D "tcsr_usb2_1_clkref_en", + .offset =3D 0x6c, }, -}; - -static struct clk_branch tcsr_usb3_0_clkref_en =3D { - .halt_reg =3D 0x64, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x64, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_usb3_0_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_USB2_2_CLKREF_EN] =3D { + .name =3D "tcsr_usb2_2_clkref_en", + .offset =3D 0x70, }, -}; - -static struct clk_branch tcsr_usb3_1_clkref_en =3D { - .halt_reg =3D 0x68, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x68, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_usb3_1_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_USB2_3_CLKREF_EN] =3D { + .name =3D "tcsr_usb2_3_clkref_en", + .offset =3D 0x74, }, -}; - -static struct clk_branch tcsr_usb4_1_clkref_en =3D { - .halt_reg =3D 0x44, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x44, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_usb4_1_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_USB2_4_CLKREF_EN] =3D { + .name =3D "tcsr_usb2_4_clkref_en", + .offset =3D 0x88, }, -}; - -static struct clk_branch tcsr_usb4_2_clkref_en =3D { - .halt_reg =3D 0x5c, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x5c, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_usb4_2_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_USB3_0_CLKREF_EN] =3D { + .name =3D "tcsr_usb3_0_clkref_en", + .offset =3D 0x64, + }, + [TCSR_USB3_1_CLKREF_EN] =3D { + .name =3D "tcsr_usb3_1_clkref_en", + .offset =3D 0x68, + }, + [TCSR_USB4_1_CLKREF_EN] =3D { + .name =3D "tcsr_usb4_1_clkref_en", + .offset =3D 0x44, + }, + [TCSR_USB4_2_CLKREF_EN] =3D { + .name =3D "tcsr_usb4_2_clkref_en", + .offset =3D 0x5c, }, -}; - -static struct clk_regmap *tcsr_cc_glymur_clocks[] =3D { - [TCSR_EDP_CLKREF_EN] =3D &tcsr_edp_clkref_en.clkr, - [TCSR_PCIE_1_CLKREF_EN] =3D &tcsr_pcie_1_clkref_en.clkr, - [TCSR_PCIE_2_CLKREF_EN] =3D &tcsr_pcie_2_clkref_en.clkr, - [TCSR_PCIE_3_CLKREF_EN] =3D &tcsr_pcie_3_clkref_en.clkr, - [TCSR_PCIE_4_CLKREF_EN] =3D &tcsr_pcie_4_clkref_en.clkr, - [TCSR_USB2_1_CLKREF_EN] =3D &tcsr_usb2_1_clkref_en.clkr, - [TCSR_USB2_2_CLKREF_EN] =3D &tcsr_usb2_2_clkref_en.clkr, - [TCSR_USB2_3_CLKREF_EN] =3D &tcsr_usb2_3_clkref_en.clkr, - [TCSR_USB2_4_CLKREF_EN] =3D &tcsr_usb2_4_clkref_en.clkr, - [TCSR_USB3_0_CLKREF_EN] =3D &tcsr_usb3_0_clkref_en.clkr, - [TCSR_USB3_1_CLKREF_EN] =3D &tcsr_usb3_1_clkref_en.clkr, - [TCSR_USB4_1_CLKREF_EN] =3D &tcsr_usb4_1_clkref_en.clkr, - [TCSR_USB4_2_CLKREF_EN] =3D &tcsr_usb4_2_clkref_en.clkr, -}; - -static const struct regmap_config tcsr_cc_glymur_regmap_config =3D { - .reg_bits =3D 32, - .reg_stride =3D 4, - .val_bits =3D 32, - .max_register =3D 0x94, - .fast_io =3D true, -}; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-137b3d8f839sm8006025c88.15.2026.06.02.01.08.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 01:08:20 -0700 (PDT) From: Qiang Yu Date: Tue, 02 Jun 2026 01:02:20 -0700 Subject: [PATCH v5 4/7] clk: qcom: tcsrcc-glymur: Add Mahua QREF regulator support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260602-tcsr_qref_0527-v5-4-8ea174a59d7e@oss.qualcomm.com> References: <20260602-tcsr_qref_0527-v5-0-8ea174a59d7e@oss.qualcomm.com> In-Reply-To: <20260602-tcsr_qref_0527-v5-0-8ea174a59d7e@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Qiang Yu , krishna.chundru@oss.qualcomm.com X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780387692; l=4461; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=wsIfzYkqIgUdZWrV5+PdN0Qh7eYY91KcaR7Usw26blQ=; b=aDFb2uVNTxQj7Yxbj/PImvdLe9Kb5iRz86HHuzbnJmYu0NYzzeNpnqkVBWfIONgVzSG7vUnq3 SIl1pNt/dyCAAh+K9dwNOeywAelHuri650T08PaOY71F1fnYiq87LWo X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjAyMDA3NSBTYWx0ZWRfX0p1Vr2TrPNhT i8q0sW7JlO0WqI76wzkW/jl6I6iiaONgj8XYb101HbwIE/RQ+hIqIxcihxfNE2L9J4wzIlaNaum VXoTxDu9udVL8C52bBROcjMPC6MMMRiOKwH6VFQjj4bxUZmS0pDsVdyITZaNTUQdNPNWiTUpck+ IMnxzX0E6bmijnrU5GfsKUsD56SCuRO1gmqY9Opy9SSoYzwHzlsrv8S3Por1Fso+8kfWhpjRXC6 OhWGaYpOMdGNCyHE82H/38MHpuCHyc7uV7WfEB0BLgpQLe3+hNquuXj8NtKAIUF5zFfd4mFVLO/ E1y98nqIR+eRpX3vAC+8YyPwXYYfQoKi3M7txi+x7hQu/LLVBC4dY6bEVCtWTjG3lE9nDX0QR8t h1DnXUC4n7CGcSw0Syp1qRM6j3DQPb0qXdLlyYeAxJH2IDSYVlgB7EeLNtXSwTXp3XNsdO6laLF oc1GCGLoN209WWzGFlA== X-Proofpoint-GUID: ZR09ug_OcQJysFcBVqWjxrs2qkS53Uo8 X-Authority-Analysis: v=2.4 cv=AJZ7LEvz c=1 sm=1 tr=0 ts=6a1e8f77 cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=ejsaoIeHybvuXmj4E6UA:9 a=QEXdDO2ut3YA:10 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-ORIG-GUID: ZR09ug_OcQJysFcBVqWjxrs2qkS53Uo8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-01_07,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 suspectscore=0 malwarescore=0 phishscore=0 bulkscore=0 impostorscore=0 clxscore=1015 lowpriorityscore=0 spamscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606020075 Mahua is based on Glymur but uses a different QREF topology, requiring distinct regulator lists and clock descriptors for its PCIe clock references. Add mahua-specific regulator arrays and clk descriptor table, and use match_data to select the correct descriptor table per compatible string at probe time. Signed-off-by: Qiang Yu --- drivers/clk/qcom/tcsrcc-glymur.c | 99 ++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 96 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/tcsrcc-glymur.c b/drivers/clk/qcom/tcsrcc-gly= mur.c index e317003398d1..deca9b8794b4 100644 --- a/drivers/clk/qcom/tcsrcc-glymur.c +++ b/drivers/clk/qcom/tcsrcc-glymur.c @@ -13,6 +13,11 @@ =20 #include =20 +struct tcsrcc_glymur_data { + const struct qcom_clk_ref_desc *descs; + size_t num_descs; +}; + static const char * const glymur_tcsr_tx0_rx5_regulators[] =3D { "vdda-refgen3-0p9", "vdda-refgen3-1p2", @@ -40,6 +45,25 @@ static const char * const glymur_tcsr_tx1_rpt012_rx2_reg= ulators[] =3D { "vdda-qrefrx2-0p9", }; =20 +static const char * const mahua_tcsr_tx1_rpt01_rx1_regulators[] =3D { + "vdda-refgen3-0p9", + "vdda-refgen3-1p2", + "vdda-qreftx1-0p9", + "vdda-qrefrpt0-0p9", + "vdda-qrefrpt1-0p9", + "vdda-qrefrx1-0p9", +}; + +static const char * const mahua_tcsr_tx1_rpt012_rx2_regulators[] =3D { + "vdda-refgen3-0p9", + "vdda-refgen3-1p2", + "vdda-qreftx1-0p9", + "vdda-qrefrpt0-0p9", + "vdda-qrefrpt1-0p9", + "vdda-qrefrpt2-0p9", + "vdda-qrefrx2-0p9", +}; + static const struct regmap_config tcsr_cc_glymur_regmap_config =3D { .reg_bits =3D 32, .reg_stride =3D 4, @@ -111,17 +135,86 @@ static const struct qcom_clk_ref_desc tcsr_cc_glymur_= clk_descs[] =3D { }, }; =20 +static const struct qcom_clk_ref_desc tcsr_cc_mahua_clk_descs[] =3D { + [TCSR_EDP_CLKREF_EN] =3D { + .name =3D "tcsr_edp_clkref_en", + .offset =3D 0x60, + }, + [TCSR_PCIE_2_CLKREF_EN] =3D { + .name =3D "tcsr_pcie_2_clkref_en", + .offset =3D 0x4c, + .regulator_names =3D mahua_tcsr_tx1_rpt01_rx1_regulators, + .num_regulators =3D ARRAY_SIZE(mahua_tcsr_tx1_rpt01_rx1_regulators), + }, + [TCSR_PCIE_3_CLKREF_EN] =3D { + .name =3D "tcsr_pcie_3_clkref_en", + .offset =3D 0x54, + .regulator_names =3D mahua_tcsr_tx1_rpt012_rx2_regulators, + .num_regulators =3D ARRAY_SIZE(mahua_tcsr_tx1_rpt012_rx2_regulators), + }, + [TCSR_PCIE_4_CLKREF_EN] =3D { + .name =3D "tcsr_pcie_4_clkref_en", + .offset =3D 0x58, + .regulator_names =3D mahua_tcsr_tx1_rpt01_rx1_regulators, + .num_regulators =3D ARRAY_SIZE(mahua_tcsr_tx1_rpt01_rx1_regulators), + }, + [TCSR_USB2_1_CLKREF_EN] =3D { + .name =3D "tcsr_usb2_1_clkref_en", + .offset =3D 0x6c, + }, + [TCSR_USB2_2_CLKREF_EN] =3D { + .name =3D "tcsr_usb2_2_clkref_en", + .offset =3D 0x70, + }, + [TCSR_USB2_3_CLKREF_EN] =3D { + .name =3D "tcsr_usb2_3_clkref_en", + .offset =3D 0x74, + }, + [TCSR_USB2_4_CLKREF_EN] =3D { + .name =3D "tcsr_usb2_4_clkref_en", + .offset =3D 0x88, + }, + [TCSR_USB3_0_CLKREF_EN] =3D { + .name =3D "tcsr_usb3_0_clkref_en", + .offset =3D 0x64, + }, + [TCSR_USB3_1_CLKREF_EN] =3D { + .name =3D "tcsr_usb3_1_clkref_en", + .offset =3D 0x68, + }, + [TCSR_USB4_1_CLKREF_EN] =3D { + .name =3D "tcsr_usb4_1_clkref_en", + .offset =3D 0x44, + }, + [TCSR_USB4_2_CLKREF_EN] =3D { + .name =3D "tcsr_usb4_2_clkref_en", + .offset =3D 0x5c, + }, +}; + +static const struct tcsrcc_glymur_data tcsr_cc_glymur_data =3D { + .descs =3D tcsr_cc_glymur_clk_descs, + .num_descs =3D ARRAY_SIZE(tcsr_cc_glymur_clk_descs), +}; + +static const struct tcsrcc_glymur_data tcsr_cc_mahua_data =3D { + .descs =3D tcsr_cc_mahua_clk_descs, + .num_descs =3D ARRAY_SIZE(tcsr_cc_mahua_clk_descs), +}; + static const struct of_device_id tcsr_cc_glymur_match_table[] =3D { - { .compatible =3D "qcom,glymur-tcsr" }, + { .compatible =3D "qcom,glymur-tcsr", .data =3D &tcsr_cc_glymur_data }, + { .compatible =3D "qcom,mahua-tcsr", .data =3D &tcsr_cc_mahua_data }, { } }; MODULE_DEVICE_TABLE(of, tcsr_cc_glymur_match_table); =20 static int tcsr_cc_glymur_probe(struct platform_device *pdev) { + const struct tcsrcc_glymur_data *data =3D device_get_match_data(&pdev->de= v); + return qcom_clk_ref_probe(pdev, &tcsr_cc_glymur_regmap_config, - tcsr_cc_glymur_clk_descs, - ARRAY_SIZE(tcsr_cc_glymur_clk_descs)); + data->descs, data->num_descs); } =20 static struct platform_driver tcsr_cc_glymur_driver =3D { --=20 2.34.1 From nobody Mon Jun 8 04:26:42 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 80B253C457C for ; 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Wire up the LDO supplies required by the QREF and refgen blocks on the CRD board. Signed-off-by: Qiang Yu --- arch/arm64/boot/dts/qcom/glymur-crd.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/= qcom/glymur-crd.dts index c98dfb3941fa..92b929ee3448 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -278,6 +278,26 @@ &smb2370_k_e2_eusb2_repeater { vdd3-supply =3D <&vreg_l7b_e0_2p79>; }; =20 +&tcsr { + vdda-qrefrpt0-0p9-supply =3D <&vreg_l2f_e1_0p83>; + vdda-qrefrpt1-0p9-supply =3D <&vreg_l2f_e1_0p83>; + vdda-qrefrpt2-0p9-supply =3D <&vreg_l2f_e1_0p83>; + vdda-qrefrpt3-0p9-supply =3D <&vreg_l2h_e0_0p72>; + vdda-qrefrpt4-0p9-supply =3D <&vreg_l2h_e0_0p72>; + vdda-qrefrx0-0p9-supply =3D <&vreg_l2f_e1_0p83>; + vdda-qrefrx1-0p9-supply =3D <&vreg_l2f_e1_0p83>; + vdda-qrefrx2-0p9-supply =3D <&vreg_l2f_e1_0p83>; + vdda-qrefrx4-0p9-supply =3D <&vreg_l2h_e0_0p72>; + vdda-qrefrx5-0p9-supply =3D <&vreg_l3f_e0_0p72>; + vdda-qreftx0-0p9-supply =3D <&vreg_l3f_e0_0p72>; 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Override the TCSR compatible to qcom,mahua-tcsr in mahua.dtsi, and wire up the required LDO supplies for the PCIe clkref paths on the CRD board. Signed-off-by: Qiang Yu --- arch/arm64/boot/dts/qcom/mahua-crd.dts | 15 +++++++++++++++ arch/arm64/boot/dts/qcom/mahua.dtsi | 4 ++++ 2 files changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/mahua-crd.dts b/arch/arm64/boot/dts/q= com/mahua-crd.dts index 9c8244e892dd..8b42f5174b31 100644 --- a/arch/arm64/boot/dts/qcom/mahua-crd.dts +++ b/arch/arm64/boot/dts/qcom/mahua-crd.dts @@ -19,3 +19,18 @@ / { model =3D "Qualcomm Technologies, Inc. Mahua CRD"; compatible =3D "qcom,mahua-crd", "qcom,mahua"; }; + +&tcsr { + vdda-qrefrpt0-0p9-supply =3D <&vreg_l2f_e1_0p83>; + vdda-qrefrpt1-0p9-supply =3D <&vreg_l2f_e1_0p83>; + vdda-qrefrpt2-0p9-supply =3D <&vreg_l2f_e1_0p83>; + vdda-qrefrpt3-0p9-supply =3D <&vreg_l1f_e1_0p82>; + vdda-qrefrpt4-0p9-supply =3D <&vreg_l2h_e0_0p72>; + vdda-qrefrpt5-0p9-supply =3D <&vreg_l2h_e0_0p72>; + vdda-qrefrx1-0p9-supply =3D <&vreg_l2f_e1_0p83>; + vdda-qrefrx2-0p9-supply =3D <&vreg_l2f_e1_0p83>; + vdda-qrefrx3-0p9-supply =3D <&vreg_l2h_e0_0p72>; + vdda-qreftx1-0p9-supply =3D <&vreg_l1f_e1_0p82>; + vdda-refgen3-0p9-supply =3D <&vreg_l1f_e1_0p82>; + vdda-refgen3-1p2-supply =3D <&vreg_l4f_e1_1p08>; +}; diff --git a/arch/arm64/boot/dts/qcom/mahua.dtsi b/arch/arm64/boot/dts/qcom= /mahua.dtsi index 22822b6b2e8b..eb45adc8a0a2 100644 --- a/arch/arm64/boot/dts/qcom/mahua.dtsi +++ b/arch/arm64/boot/dts/qcom/mahua.dtsi @@ -286,6 +286,10 @@ gpuss-4-critical { }; }; =20 +&tcsr { + compatible =3D "qcom,mahua-tcsr", "syscon"; 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Override the clock list to use RPMH_CXO_CLK directly instead. Signed-off-by: Qiang Yu --- arch/arm64/boot/dts/qcom/mahua.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/mahua.dtsi b/arch/arm64/boot/dts/qcom= /mahua.dtsi index eb45adc8a0a2..e6c059708912 100644 --- a/arch/arm64/boot/dts/qcom/mahua.dtsi +++ b/arch/arm64/boot/dts/qcom/mahua.dtsi @@ -115,6 +115,15 @@ &oobm_ss_noc { compatible =3D "qcom,mahua-oobm-ss-noc", "qcom,glymur-oobm-ss-noc"; }; =20 +&pcie5_phy { + clocks =3D <&gcc GCC_PCIE_PHY_5_AUX_CLK>, + <&gcc GCC_PCIE_5_CFG_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_5_PIPE_CLK>, + <&gcc GCC_PCIE_5_PIPE_DIV2_CLK>; +}; + &pcie_east_anoc { compatible =3D "qcom,mahua-pcie-east-anoc", "qcom,glymur-pcie-east-anoc"; }; --=20 2.34.1