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Tue, 02 Jun 2026 08:22:07 -0700 (PDT) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2bf239e71cbsm135136465ad.15.2026.06.02.08.22.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 08:22:07 -0700 (PDT) From: Taniya Das Date: Tue, 02 Jun 2026 20:51:49 +0530 Subject: [PATCH 1/5] dt-bindings: clock: qcom: Add bindings for PDM GP_MN clock divider Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260602-pdm_clk_gp_mnd_v1-v1-1-1522662b6c53@oss.qualcomm.com> References: <20260602-pdm_clk_gp_mnd_v1-v1-0-1522662b6c53@oss.qualcomm.com> In-Reply-To: <20260602-pdm_clk_gp_mnd_v1-v1-0-1522662b6c53@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Richard Cochran , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, netdev@vger.kernel.org, Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-ORIG-GUID: bGWm_neIstgLbd7ZK14F8mgJmUbM2HPk X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjAyMDE0OCBTYWx0ZWRfXwDVthFbiP/a5 3Dk+HMCIT2SLHehPiEm+ngfCGMkUiGlFcNZ6lrKCzfA35iNXSZbCAbklVjRCJ3vV82zJotwqH7R dQrgUqHlcO0cMCgSxWVAMof1Dx0Rq9ELU1/SEhagtzIQWj7INN+jTSyCcWpYTvrRYwPE7V+906l mbo3LYk1t8GPqNDy7Txthzf0hhq2+u2TN6zvC6uOYhg/P9LwovveyEUh5i5Frtb8oPmmPV4vOZx Zq/zggQwbfgtE9RQOG5YlGqhhAcUvjbdXKPsbVYyhUjeTU6CX3fBHq7Ztu+gh+bcglcjYTbpdCt mvmsLfwbayxX57pvhg3wz0hlWA0PrsNeMe3rtCis6KyvZkSjpkSxSXyuOZcL4BmEDAGDNGDXbFw Tf8OuKFT97FXZmFwVd3WQGpQE4cnXAB5AFkTvgO3jjLjSTs7GkwMrIIoEvXEkyzqM8RVAMc/Q6q 0mlYG8XV3m9Rdgkg8eQ== X-Authority-Analysis: v=2.4 cv=ZYAt8MVA c=1 sm=1 tr=0 ts=6a1ef520 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=nhq6iwPr6d6TsRTX7tUA:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-GUID: bGWm_neIstgLbd7ZK14F8mgJmUbM2HPk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-02_02,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 clxscore=1015 adultscore=0 impostorscore=0 spamscore=0 phishscore=0 suspectscore=0 malwarescore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606020148 Add device tree bindings for the Qualcomm Peripheral Web's PDM GP_MN clock divider. The hardware generates a fractional output frequency from a fixed input clock (typically TCXO4) using the relation Fout =3D Fin * (M / N), with duty cycle controlled by a separate D register. The clock output is routed over a gpio controlled pin. Signed-off-by: Taniya Das --- .../devicetree/bindings/clock/qcom,clk-gp-mnd.yaml | 105 +++++++++++++++++= ++++ 1 file changed, 105 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,clk-gp-mnd.yaml b= /Documentation/devicetree/bindings/clock/qcom,clk-gp-mnd.yaml new file mode 100644 index 0000000000000000000000000000000000000000..c1688bb3d68d8d476a8d498aa27= 74606b8b26018 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,clk-gp-mnd.yaml @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,clk-gp-mnd.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Peripheral Web's PDM GP_MN Clock Divider + +maintainers: + - Taniya Das + +description: | + The Peripheral Web's PDM GP_MN clock divider receives an input clock + (TCXO4) with frequency Fin and generates an output clock with + frequency Fout =3D Fin * (M / N) and a duty cycle controlled by D + and routed over a gpio pin. + + The divider is configured using three registers: + + - GP_MN_CLK_MDIV: holds the M value. + - GP_MN_CLK_NDIV: holds the ones complement of (N - M). + - GP_MN_CLK_DUTY: holds the D value. + + For every N input clock cycles the GP_MN produces M output clock + cycles. D is the number of native clock cycles in which the GP_MN + output is low, counted over 2^13 native clock cycles. + + Hardware constraints: + + M <=3D 511 + N <=3D 8191 + N > 2 * M + M < D < (N - M) + M and N must be coprime (no common divisor) + +properties: + compatible: + const: qcom,clk-gp-mnd + + reg: + maxItems: 1 + + clocks: + items: + - description: PDM XO4 source clock + - description: PDM AHB bus clock for register access + + clock-names: + items: + - const: pdm_clk + - const: ahb_clk + + '#clock-cells': + const: 0 + + clock-output-names: + maxItems: 1 + + pinctrl-0: + description: Pin configuration for the GP_MN output in the active stat= e. + + pinctrl-names: + items: + - const: active + + assigned-clocks: + maxItems: 1 + description: Parent clock phandle used to set the input frequency. + + assigned-clock-rates: + maxItems: 1 + description: | + Rate for the parent clock in Hz. + Supported rates: 19200000, 9600000, 6400000, 4800000. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - clock-output-names + - pinctrl-0 + - pinctrl-names + - assigned-clocks + - assigned-clock-rates + +additionalProperties: false + +examples: + - | + #include + gp_mn: clock-controller@88d3000 { + compatible =3D "qcom,clk-gp-mnd"; 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Tue, 02 Jun 2026 08:22:14 -0700 (PDT) X-Received: by 2002:a17:902:ecc7:b0:2c0:b319:fb36 with SMTP id d9443c01a7336-2c0b31a00c7mr153524825ad.28.1780413733559; Tue, 02 Jun 2026 08:22:13 -0700 (PDT) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2bf239e71cbsm135136465ad.15.2026.06.02.08.22.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 08:22:13 -0700 (PDT) From: Taniya Das Date: Tue, 02 Jun 2026 20:51:50 +0530 Subject: [PATCH 2/5] clk: qcom: Add a driver for PDM GP_MN fractional clock divider Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260602-pdm_clk_gp_mnd_v1-v1-2-1522662b6c53@oss.qualcomm.com> References: <20260602-pdm_clk_gp_mnd_v1-v1-0-1522662b6c53@oss.qualcomm.com> In-Reply-To: <20260602-pdm_clk_gp_mnd_v1-v1-0-1522662b6c53@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Richard Cochran , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, netdev@vger.kernel.org, Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjAyMDE0OCBTYWx0ZWRfXwrlsu7uL30bd VNDPWG0c5IRzZs/94xjgMD8UBU5DR58W3Sy+xeRS/dyGr8BdZ7w81c5RuR0zEhpsVg42ywVyY1u 0WsEOq2tvO7YliawzBMwrIRf8KWhtESKsGC0x6CKFFU6d1XWpJ49gbRmC0NcyxA9wEv98g/QUvB Povuq+JeqaMSkTy/SAULxAddyn5bVtirpmI3BmgCgD7Ulnz4D0MmFy4mD8K9DYBNANAICmOnbLm 1TBdOCEfCCqU/tExhVMXCPJCgggXk28Ly24SwhyV1TxCwT3VEo/dbXfEhe6Z5pTRtVWXwOYPaRg tyIv5zphEmd+vwykMsnt9hFon6p/QtBr5ow9BBByoM9Lik3prbRuYP4HUBpXxHfagUqN88mzsmE Pq+DFonSeFY3YPDb7/6aCDlx5ufsV0lY1Jam4cw1gig8GZgq+CRH2uPDXwFvfk7SnfDmd40r3LL 1BQQhpTwMgk+9XHoI4g== X-Proofpoint-ORIG-GUID: 6H_y5sNGcfEPdgWrKfsbrpv1KFbctTcU X-Proofpoint-GUID: 6H_y5sNGcfEPdgWrKfsbrpv1KFbctTcU X-Authority-Analysis: v=2.4 cv=Rrv16imK c=1 sm=1 tr=0 ts=6a1ef527 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=9rGeCgy22yGQcie6hdYA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-02_02,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 spamscore=0 suspectscore=0 impostorscore=0 phishscore=0 priorityscore=1501 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606020148 The PDM (Pulse Density Modulation) hardware block on Qualcomm SoCs contains a GP_MN clock divider that produces a fractional output frequency from a fixed input clock (typically TCXO4): Fout =3D Fin * (M / N) The hardware encodes the period in the NDIV register as the 1's complement of (N - M), and controls the duty cycle via a separate DUTY register that counts the number of low-phase native clock cycles over the period N. Add a standalone platform driver for this block that uses rational_best_approximation() to find the closest M/N pair within the 9-bit M and 13-bit N hardware limits, programs the MDIV, NDIV, and DUTY registers via regmap, and implements the full clk_ops surface including determine_rate, set_rate, recalc_rate, get_duty_cycle, and set_duty_cycle. The PDM AHB bus clock is gated around every register access. Signed-off-by: Taniya Das --- drivers/clk/qcom/Kconfig | 15 ++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-gp-mnd.c | 333 ++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 349 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index d9cff5b0281d8cc373b8ab14683370cb9b7f8bf3..df27aa10243435a20a57cca3ed4= 644284630d11e 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -1759,4 +1759,19 @@ config SM_VIDEOCC_8450 SM8450 or SM8475 devices. Say Y if you want to support video devices and functionality such as video encode/decode. + +config QCOM_CLK_GP_MND + tristate "Qualcomm PDM GP_MN clock divider" + depends on ARM64 || COMPILE_TEST + help + Support for the Qualcomm PDM GP_MN clock divider found in PDM + (Pulse Density Modulation) hardware blocks. + Given an input clock of frequency Fin (TCXO4), the output + frequency is Fout =3D Fin * (M / N). For every N input cycles + the divider produces M output cycles. D controls the duty + cycle: it is the number of native clock cycles in which the + GP_MN output is low, counted over 8192 native clock cycles. + + Say Y or M if you want to support GP_MN-based frequency and + duty-cycle configuration on Qualcomm SoCs. endif diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index e100cfd6a52de9f88f11720d9c2043db5e553618..438f59b25c009ee72308fe41707= d6efff6613690 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -207,6 +207,7 @@ obj-$(CONFIG_SM_VIDEOCC_8550) +=3D videocc-sm8550.o obj-$(CONFIG_SM_VIDEOCC_8750) +=3D videocc-sm8750.o obj-$(CONFIG_SM_VIDEOCC_MILOS) +=3D videocc-milos.o obj-$(CONFIG_SPMI_PMIC_CLKDIV) +=3D clk-spmi-pmic-div.o +obj-$(CONFIG_QCOM_CLK_GP_MND) +=3D clk-gp-mnd.o obj-$(CONFIG_KPSS_XCC) +=3D kpss-xcc.o obj-$(CONFIG_QCOM_HFPLL) +=3D hfpll.o obj-$(CONFIG_KRAITCC) +=3D krait-cc.o diff --git a/drivers/clk/qcom/clk-gp-mnd.c b/drivers/clk/qcom/clk-gp-mnd.c new file mode 100644 index 0000000000000000000000000000000000000000..826b6b62ddc7b272511accde1ca= 0e885018a8064 --- /dev/null +++ b/drivers/clk/qcom/clk-gp-mnd.c @@ -0,0 +1,333 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * PDM GP_MND clock divider register offsets. + * + * The hardware computes: + * Fout =3D Fin * (M / N) + * + * with duty cycle controlled by D, where M < D < (N - M). + * + * Register encoding: + * MDIV =3D M + * NDIV =3D ~(N - M) [1's complement of (N - M), masked to N_REG_WIDTH= bits] + * DUTY =3D D + */ +#define GP_MND_MDIV_REG 0x0 +#define GP_MND_NDIV_REG 0x4 +#define GP_MND_DUTY_REG 0x8 + +#define GP_MND_M_WIDTH 9 +#define GP_MND_N_WIDTH 13 + +#define GP_MND_MAX_M GENMASK(GP_MND_M_WIDTH - 1, 0) +#define GP_MND_MAX_N GENMASK(GP_MND_N_WIDTH - 1, 0) + +/** + * struct clk_gp_mnd - GP_MND fractional clock divider + * @pdm_ahb_clk: AHB bus clock required for register access + * @regmap: register map for the PDM block + * @hw: handle between common and hardware-specific interfaces + * @m_val: M value (numerator) + * @n_val: N value (period) + */ +struct clk_gp_mnd { + struct clk *pdm_ahb_clk; + struct regmap *regmap; + struct clk_hw hw; + unsigned int m_val; + unsigned int n_val; +}; + +#define to_clk_gp_mnd(_hw) container_of(_hw, struct clk_gp_mnd, hw) + +static int gp_mnd_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + unsigned long m =3D 0, n =3D 0; + + rational_best_approximation(req->rate, req->best_parent_rate, + (unsigned long)GP_MND_MAX_M, + (unsigned long)GP_MND_MAX_N, + &m, &n); + + if (!m || !n) + return -EINVAL; + + /* N =3D 2M + 1 leaves no valid D satisfying M < D < (N - M) */ + if (n =3D=3D 2 * m + 1) + return -EINVAL; + + req->rate =3D DIV_ROUND_CLOSEST_ULL((u64)req->best_parent_rate * m, n); + + return 0; +} + +static int gp_mnd_clk_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_gp_mnd *gp =3D to_clk_gp_mnd(hw); + unsigned long m =3D 0, n =3D 0; + unsigned int d_val, n_val; + int ret; + + rational_best_approximation(rate, parent_rate, + (unsigned long)GP_MND_MAX_M, + (unsigned long)GP_MND_MAX_N, + &m, &n); + + if (!m || !n) + return -EINVAL; + + /* + * When N =3D 2M + 1 the valid D range [M+1, M] is empty; no duty + * cycle can satisfy M < D < (N - M). Reject before touching hw. + */ + if (n =3D=3D 2 * m + 1) + return -EINVAL; + + ret =3D clk_prepare_enable(gp->pdm_ahb_clk); + if (ret) + return ret; + + ret =3D regmap_write(gp->regmap, GP_MND_MDIV_REG, m); + if (ret) + goto err_unprepare; + + /* N divider holds the 1's complement of (N - M), N_WIDTH bits wide */ + n_val =3D ~(n - m) & GP_MND_MAX_N; + ret =3D regmap_write(gp->regmap, GP_MND_NDIV_REG, n_val); + if (ret) + goto err_unprepare; + + /* Program the closest-to-50% duty cycle. */ + d_val =3D n / 2; + ret =3D regmap_write(gp->regmap, GP_MND_DUTY_REG, d_val); + if (ret) + goto err_unprepare; + + gp->m_val =3D m; + gp->n_val =3D n; + +err_unprepare: + clk_disable_unprepare(gp->pdm_ahb_clk); + + return ret; +} + +static unsigned long gp_mnd_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_gp_mnd *gp =3D to_clk_gp_mnd(hw); + unsigned int m_val, n_val; + int ret; + + ret =3D clk_prepare_enable(gp->pdm_ahb_clk); + if (ret) + return 0; + + ret =3D regmap_read(gp->regmap, GP_MND_MDIV_REG, &m_val); + if (ret) + goto out_unprepare; + + m_val &=3D GP_MND_MAX_M; + + ret =3D regmap_read(gp->regmap, GP_MND_NDIV_REG, &n_val); + if (ret) + goto out_unprepare; + + /* Reverse the 1's complement encoding: N =3D ~NDIV_REG + M */ + n_val =3D (~n_val & GP_MND_MAX_N) + m_val; + +out_unprepare: + clk_disable_unprepare(gp->pdm_ahb_clk); + + if (ret) + return 0; + + if (!n_val) + return 0; + + gp->m_val =3D m_val; + gp->n_val =3D n_val; + + return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * m_val, n_val); +} + +static int gp_mnd_clk_get_duty_cycle(struct clk_hw *hw, struct clk_duty *d= uty) +{ + struct clk_gp_mnd *gp =3D to_clk_gp_mnd(hw); + unsigned int d_val; + int ret; + + if (!gp->n_val) { + duty->num =3D 1; + duty->den =3D 2; + return 0; + } + + ret =3D clk_prepare_enable(gp->pdm_ahb_clk); + if (ret) + return ret; + + ret =3D regmap_read(gp->regmap, GP_MND_DUTY_REG, &d_val); + + clk_disable_unprepare(gp->pdm_ahb_clk); + + if (ret) + return ret; + + duty->num =3D d_val; + duty->den =3D gp->n_val; + + return 0; +} + +static int gp_mnd_clk_set_duty_cycle(struct clk_hw *hw, struct clk_duty *d= uty) +{ + struct clk_gp_mnd *gp =3D to_clk_gp_mnd(hw); + unsigned int d_val; + int ret; + + if (!gp->n_val || !gp->m_val) + return -EINVAL; + + /* D =3D (1 - duty) * N, giving the low-phase count */ + d_val =3D DIV_ROUND_UP((u64)(duty->den - duty->num) * gp->n_val, duty->de= n); + + /* Hardware constraint: M < D < (N - M) */ + if (d_val <=3D gp->m_val || d_val >=3D (gp->n_val - gp->m_val)) + return -EINVAL; + + ret =3D clk_prepare_enable(gp->pdm_ahb_clk); + if (ret) + return ret; + + ret =3D regmap_write(gp->regmap, GP_MND_DUTY_REG, d_val); + + clk_disable_unprepare(gp->pdm_ahb_clk); + + return ret; +} + +static const struct clk_ops clk_gp_mnd_ops =3D { + .determine_rate =3D gp_mnd_clk_determine_rate, + .set_rate =3D gp_mnd_clk_set_rate, + .recalc_rate =3D gp_mnd_clk_recalc_rate, + .get_duty_cycle =3D gp_mnd_clk_get_duty_cycle, + .set_duty_cycle =3D gp_mnd_clk_set_duty_cycle, +}; + +static const struct regmap_config gp_mnd_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .fast_io =3D true, +}; + +static int clk_gp_mnd_probe(struct platform_device *pdev) +{ + struct clk_parent_data parent_data =3D { .index =3D 0 }; + struct clk_init_data init =3D { + .ops =3D &clk_gp_mnd_ops, + .parent_data =3D &parent_data, + .num_parents =3D 1, + .flags =3D CLK_GET_RATE_NOCACHE, + }; + struct device *dev =3D &pdev->dev; + struct clk_gp_mnd *gp; + struct clk *clk; + struct pinctrl *pin; + struct pinctrl_state *pin_default_state; + void __iomem *base; + int ret; + + gp =3D devm_kzalloc(dev, sizeof(*gp), GFP_KERNEL); + if (!gp) + return -ENOMEM; + + gp->pdm_ahb_clk =3D devm_clk_get(dev, "ahb_clk"); + if (IS_ERR(gp->pdm_ahb_clk)) + return dev_err_probe(dev, PTR_ERR(gp->pdm_ahb_clk), + "failed to get ahb_clk\n"); + + clk =3D devm_clk_get(dev, "pdm_clk"); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + /* Set default rate if not already configured */ + if (!clk_get_rate(clk)) { + ret =3D clk_set_rate(clk, 19200000); + if (ret) + dev_warn(dev, "failed to set default pdm_clk rate\n"); + } + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return dev_err_probe(dev, PTR_ERR(base), + "failed to map PDM registers\n"); + + gp->regmap =3D devm_regmap_init_mmio(dev, base, &gp_mnd_regmap_config); + if (IS_ERR(gp->regmap)) + return dev_err_probe(dev, PTR_ERR(gp->regmap), + "failed to init regmap\n"); + + ret =3D of_property_read_string_index(dev->of_node, + "clock-output-names", 0, + &init.name); + if (ret) + return dev_err_probe(dev, ret, "missing clock-output-names\n"); + + gp->hw.init =3D &init; + + pin =3D devm_pinctrl_get(dev); + if (IS_ERR(pin)) + return dev_err_probe(dev, PTR_ERR(pin), "missing pinctrl device\n"); + + pin_default_state =3D pinctrl_lookup_state(pin, "active"); + if (IS_ERR(pin_default_state)) + return dev_err_probe(dev, PTR_ERR(pin_default_state), + "missing pinctrl default state\n"); + + ret =3D pinctrl_select_state(pin, pin_default_state); + if (ret) + return dev_err_probe(dev, ret, + "failed to select pinctrl default state\n"); + + ret =3D devm_clk_hw_register(dev, &gp->hw); + if (ret) + return dev_err_probe(dev, ret, + "failed to register gp_mnd clock\n"); + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &gp->hw); +} + +static const struct of_device_id clk_gp_mnd_match_table[] =3D { + { .compatible =3D "qcom,clk-gp-mnd" }, + { } +}; +MODULE_DEVICE_TABLE(of, clk_gp_mnd_match_table); + +static struct platform_driver clk_gp_mnd_driver =3D { + .probe =3D clk_gp_mnd_probe, + .driver =3D { + .name =3D "qcom-clk-gp-mnd", + .of_match_table =3D clk_gp_mnd_match_table, + }, +}; +module_platform_driver(clk_gp_mnd_driver); + +MODULE_DESCRIPTION("Qualcomm PDM GP_MND clock divider driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Mon Jun 8 04:28:30 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC2E23EF652 for ; Tue, 2 Jun 2026 15:22:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; 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This function exposes the GP M/N divider clock output on a dedicated GPIO pin, allowing the clock signal to be routed externally. - QCS8300: gpio32 - SA8775P: gpio35 - SC7280: gpio60 Signed-off-by: Taniya Das --- drivers/pinctrl/qcom/pinctrl-qcs8300.c | 9 ++++++++- drivers/pinctrl/qcom/pinctrl-sa8775p.c | 8 +++++++- drivers/pinctrl/qcom/pinctrl-sc7280.c | 8 +++++++- 3 files changed, 22 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-qcs8300.c b/drivers/pinctrl/qcom/= pinctrl-qcs8300.c index 852cd36df6d5fc6d0aece7d57f8f59fe48c0cfee..1430abd9258989bdbd8a1224919= 6bbf4e9bbbde3 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcs8300.c +++ b/drivers/pinctrl/qcom/pinctrl-qcs8300.c @@ -429,6 +429,7 @@ enum qcs8300_functions { msm_mux_gcc_gp3, msm_mux_gcc_gp4, msm_mux_gcc_gp5, + msm_mux_gp_mn, msm_mux_hs0_mi2s, msm_mux_hs1_mi2s, msm_mux_hs2_mi2s, @@ -656,6 +657,10 @@ static const char *const gcc_gp5_groups[] =3D { "gpio76", "gpio77", }; =20 +static const char *const gp_mn_groups[] =3D { + "gpio32", +}; + static const char * const hs0_mi2s_groups[] =3D { "gpio106", "gpio107", "gpio108", "gpio109", }; @@ -960,6 +965,7 @@ static const struct pinfunction qcs8300_functions[] =3D= { MSM_PIN_FUNCTION(gcc_gp3), MSM_PIN_FUNCTION(gcc_gp4), MSM_PIN_FUNCTION(gcc_gp5), + MSM_PIN_FUNCTION(gp_mn), MSM_PIN_FUNCTION(hs0_mi2s), MSM_PIN_FUNCTION(hs1_mi2s), MSM_PIN_FUNCTION(hs2_mi2s), @@ -1067,7 +1073,8 @@ static const struct msm_pingroup qcs8300_groups[] =3D= { [30] =3D PINGROUP(30, qup0_se4, cci_i2c_scl, cci_async, emac0_ptp_pps, tgu_ch3, _, _, _, _, _, _), [31] =3D PINGROUP(31, qup0_se4, cci_i2c_sda, cci_async, emac0_ptp_aux, _,= _, _, _, _, _, _), - [32] =3D PINGROUP(32, qup0_se4, cci_i2c_scl, emac0_ptp_aux, mdp_vsync, _,= _, _, _, _, _, _), + [32] =3D PINGROUP(32, qup0_se4, cci_i2c_scl, emac0_ptp_aux, mdp_vsync, gp= _mn, _, _, _, _, + _, _), [33] =3D PINGROUP(33, qup0_se2, qdss_gpio, _, _, _, _, _, _, _, _, _), [34] =3D PINGROUP(34, qup0_se2, qdss_gpio, _, _, _, _, _, _, _, _, _), [35] =3D PINGROUP(35, qup0_se2, gcc_gp1, _, _, _, _, _, _, _, _, _), diff --git a/drivers/pinctrl/qcom/pinctrl-sa8775p.c b/drivers/pinctrl/qcom/= pinctrl-sa8775p.c index e9a510d3583f5c392acb833be4ce67c6b421cd48..2c29743cca7a259b5a41e73de34= 7c536d373a01e 100644 --- a/drivers/pinctrl/qcom/pinctrl-sa8775p.c +++ b/drivers/pinctrl/qcom/pinctrl-sa8775p.c @@ -486,6 +486,7 @@ enum sa8775p_functions { msm_mux_gcc_gp3, msm_mux_gcc_gp4, msm_mux_gcc_gp5, + msm_mux_gp_mn, msm_mux_hs0_mi2s, msm_mux_hs1_mi2s, msm_mux_hs2_mi2s, @@ -834,6 +835,10 @@ static const char * const gcc_gp5_groups[] =3D { "gpio34", "gpio42", }; =20 +static const char * const gp_mn_groups[] =3D { + "gpio35", +}; + static const char * const hs0_mi2s_groups[] =3D { "gpio114", "gpio115", "gpio116", "gpio117", }; @@ -1236,6 +1241,7 @@ static const struct pinfunction sa8775p_functions[] = =3D { MSM_PIN_FUNCTION(gcc_gp3), MSM_PIN_FUNCTION(gcc_gp4), MSM_PIN_FUNCTION(gcc_gp5), + MSM_PIN_FUNCTION(gp_mn), MSM_PIN_FUNCTION(hs0_mi2s), MSM_PIN_FUNCTION(hs1_mi2s), MSM_PIN_FUNCTION(hs2_mi2s), @@ -1367,7 +1373,7 @@ static const struct msm_pingroup sa8775p_groups[] =3D= { [32] =3D PINGROUP(32, qup0_se4, phase_flag, _, _, _, _, _, _, _), [33] =3D PINGROUP(33, qup0_se4, gcc_gp4, _, ddr_pxi0, _, _, _, _, _), [34] =3D PINGROUP(34, qup0_se4, gcc_gp5, _, ddr_pxi0, _, _, _, _, _), - [35] =3D PINGROUP(35, qup0_se4, phase_flag, _, _, _, _, _, _, _), + [35] =3D PINGROUP(35, qup0_se4, phase_flag, gp_mn, _, _, _, _, _, _), [36] =3D PINGROUP(36, qup0_se2, qup0_se5, phase_flag, tgu_ch2, _, _, _, _= , _), [37] =3D PINGROUP(37, qup0_se2, qup0_se5, phase_flag, tgu_ch3, _, _, _, _= , _), [38] =3D PINGROUP(38, qup0_se5, qup0_se2, qdss_cti, phase_flag, tgu_ch4, = _, _, _, _), diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280.c b/drivers/pinctrl/qcom/p= inctrl-sc7280.c index bb32a56649df6faf1aecd470435d74558c20db27..5e210b399f88f5beb68e511bca9= c0dd93a1b75dc 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc7280.c +++ b/drivers/pinctrl/qcom/pinctrl-sc7280.c @@ -515,6 +515,7 @@ enum sc7280_functions { msm_mux_gcc_gp1, msm_mux_gcc_gp2, msm_mux_gcc_gp3, + msm_mux_gp_mn, msm_mux_gpio, msm_mux_host2wlan_sol, msm_mux_ibi_i3c, @@ -788,6 +789,10 @@ static const char * const gcc_gp2_groups[] =3D { static const char * const gcc_gp3_groups[] =3D { "gpio78", "gpio107", }; + +static const char *const gp_mn_groups[] =3D { + "gpio60", +}; static const char * const host2wlan_sol_groups[] =3D { "gpio26", }; @@ -1154,6 +1159,7 @@ static const struct pinfunction sc7280_functions[] = =3D { MSM_PIN_FUNCTION(gcc_gp1), MSM_PIN_FUNCTION(gcc_gp2), MSM_PIN_FUNCTION(gcc_gp3), + MSM_PIN_FUNCTION(gp_mn), MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(host2wlan_sol), MSM_PIN_FUNCTION(ibi_i3c), @@ -1325,7 +1331,7 @@ static const struct msm_pingroup sc7280_groups[] =3D { [57] =3D PINGROUP(57, qup16, ddr_bist, phase_flag, _, _, _, _, _, _), [58] =3D PINGROUP(58, qup16, ddr_bist, phase_flag, qdss, _, _, _, _, _), [59] =3D PINGROUP(59, qup16, ddr_bist, phase_flag, qdss, _, _, _, _, _), - [60] =3D PINGROUP(60, qup17, edp_hot, _, phase_flag, _, _, _, _, _), + [60] =3D PINGROUP(60, qup17, edp_hot, gp_mn, phase_flag, _, _, _, _, _), [61] =3D PINGROUP(61, qup17, sd_write, phase_flag, tsense_pwm1, tsense_pw= m2, _, _, _, _), [62] =3D PINGROUP(62, qup17, qup16, phase_flag, _, _, _, _, _, _), [63] =3D PINGROUP(63, qup17, qup16, phase_flag, _, _, _, _, _, _), --=20 2.34.1 From nobody Mon Jun 8 04:28:30 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A9A783EF652 for ; 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Signed-off-by: Taniya Das --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 7 +++++++ arch/arm64/boot/dts/qcom/lemans.dtsi | 7 +++++++ arch/arm64/boot/dts/qcom/monaco.dtsi | 7 +++++++ 3 files changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qco= m/kodiak.dtsi index fa540d8c2615dc02d941eb16bc7253204c2750bd..1ff9e1598d00429c03b2bcae41f= a370ab2c892bd 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -5908,6 +5908,13 @@ edp_hot_plug_det: edp-hot-plug-det-state { function =3D "edp_hot"; }; =20 + gp_mn_active: gp_mn_active-state { + pins =3D "gpio35"; + function =3D "gp_mn"; + drive-strength =3D <2>; + bias-disable; + }; + mi2s0_data0: mi2s0-data0-state { pins =3D "gpio98"; function =3D "mi2s0_data0"; diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qco= m/lemans.dtsi index 353a6e6fd3acb22ef228bee340212b8b2c300957..19f8cf4e15482947f6049188050= c370340afaead 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -6022,6 +6022,13 @@ dp1_hot_plug_det: dp1-hot-plug-det-state { bias-disable; }; =20 + gp_mn_active: gp_mn_active-state { + pins =3D "gpio35"; + function =3D "gp_mn"; + drive-strength =3D <2>; + bias-disable; + }; + hs0_mi2s_active: hs0-mi2s-active-state { pins =3D "gpio114", "gpio115", "gpio116", "gpio117"; function =3D "hs0_mi2s"; diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qco= m/monaco.dtsi index e4c8466f941bdba04f99b988fd7bf5afd926b31d..ebe5889daa5300efa7857314e91= 70d7d2fc33ef7 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -6433,6 +6433,13 @@ dp_hot_plug_det: dp-hot-plug-det-state { bias-disable; }; =20 + gp_mn_active: gp_mn_active-state { + pins =3D "gpio32"; + function =3D "gp_mn"; + drive-strength =3D <2>; + bias-disable; + }; + hs0_mi2s_active: hs0-mi2s-active-state { pins =3D "gpio106", "gpio107", "gpio108", "gpio109"; function =3D "hs0_mi2s"; --=20 2.34.1 From nobody Mon Jun 8 04:28:30 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D66A33EDE54 for ; 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The node uses the qcom,clk-gp-mnd compatible, is clocked by the PDM XO4 and AHB clocks from GCC, and exposes a single clock output (gp_mn_clk) on the dedicated gp_mn pin mux function. The XO4 clock is pre-assigned to 4.8 MHz (XO/4). Signed-off-by: Taniya Das --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 14 ++++++++++++++ arch/arm64/boot/dts/qcom/lemans.dtsi | 14 ++++++++++++++ arch/arm64/boot/dts/qcom/monaco.dtsi | 14 ++++++++++++++ 3 files changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qco= m/kodiak.dtsi index 1ff9e1598d00429c03b2bcae41fa370ab2c892bd..cbc13ac37f8aeb0b1071ad0609e= c11e829d2c798 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -4412,6 +4412,20 @@ usb2_role_switch: endpoint { }; }; =20 + gp_mn: clock-controller@88d3000 { + compatible =3D "qcom,clk-gp-mnd"; + reg =3D <0x0 0x088d3000 0x0 0xc>; + clocks =3D <&gcc GCC_PDM_XO4_CLK>, + <&gcc GCC_PDM_AHB_CLK>; + clock-names =3D "pdm_clk", "ahb_clk"; + clock-output-names =3D "gp_mn_clk"; + #clock-cells =3D <0>; + pinctrl-names =3D "active"; + pinctrl-0 =3D <&gp_mn_active>; + assigned-clocks =3D <&gcc GCC_PDM_XO4_CLK>; + assigned-clock-rates =3D <4800000>; + }; + qspi: spi@88dc000 { compatible =3D "qcom,sc7280-qspi", "qcom,qspi-v1"; reg =3D <0 0x088dc000 0 0x1000>; diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qco= m/lemans.dtsi index 19f8cf4e15482947f6049188050c370340afaead..d192f92a896bb13017abdf82062= e8305aab3e5d5 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -4353,6 +4353,20 @@ opp-384000000 { }; }; =20 + gp_mn: clock-controller@88d3000 { + compatible =3D "qcom,clk-gp-mnd"; + reg =3D <0x0 0x088d3000 0x0 0xc>; + clocks =3D <&gcc GCC_PDM_XO4_CLK>, + <&gcc GCC_PDM_AHB_CLK>; + clock-names =3D "pdm_clk", "ahb_clk"; + clock-output-names =3D "gp_mn_clk"; + #clock-cells =3D <0>; + pinctrl-names =3D "active"; + pinctrl-0 =3D <&gp_mn_active>; + assigned-clocks =3D <&gcc GCC_PDM_XO4_CLK>; + assigned-clock-rates =3D <4800000>; + }; + usb_0_hsphy: phy@88e4000 { compatible =3D "qcom,sa8775p-usb-hs-phy", "qcom,usb-snps-hs-5nm-phy"; diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qco= m/monaco.dtsi index ebe5889daa5300efa7857314e9170d7d2fc33ef7..f6c5ec38c7491b7a16ebfb853f8= af88bdf1f0db3 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -4867,6 +4867,20 @@ opp-384000000 { }; }; =20 + gp_mn: clock-controller@88d3000 { + compatible =3D "qcom,clk-gp-mnd"; + reg =3D <0x0 0x088d3000 0x0 0xc>; + clocks =3D <&gcc GCC_PDM_XO4_CLK>, + <&gcc GCC_PDM_AHB_CLK>; + clock-names =3D "pdm_clk", "ahb_clk"; + clock-output-names =3D "gp_mn_clk"; + #clock-cells =3D <0>; + pinctrl-names =3D "active"; + pinctrl-0 =3D <&gp_mn_active>; + assigned-clocks =3D <&gcc GCC_PDM_XO4_CLK>; + assigned-clock-rates =3D <4800000>; + }; + usb_1_hsphy: phy@8904000 { compatible =3D "qcom,qcs8300-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy"; --=20 2.34.1