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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-36dd91f1affsm2154028a91.11.2026.06.02.02.22.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 02:22:09 -0700 (PDT) From: Kathiravan Thirumoorthy Date: Tue, 02 Jun 2026 14:51:59 +0530 Subject: [PATCH 1/2] regulator: dt-bindings: qcom,sdm845-refgen-regulator: Document IPQ9650 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260602-ipq9650_refgen-v1-1-55e2afa5ff64@oss.qualcomm.com> References: <20260602-ipq9650_refgen-v1-0-55e2afa5ff64@oss.qualcomm.com> In-Reply-To: <20260602-ipq9650_refgen-v1-0-55e2afa5ff64@oss.qualcomm.com> To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Kathiravan Thirumoorthy X-Mailer: b4 0.15.2 X-Authority-Analysis: v=2.4 cv=WKRPmHsR c=1 sm=1 tr=0 ts=6a1ea0c3 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=VjL3xhqMjkKYvgIonoEA:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-GUID: daBRvnltG1VKiH6-zwaNUtEXwrNtXBum X-Proofpoint-ORIG-GUID: daBRvnltG1VKiH6-zwaNUtEXwrNtXBum X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjAyMDA4NyBTYWx0ZWRfX0ChqDIkp4Ik4 A7USRb8kj3ocyxzdKd5d7VmzyFIAmPTL/qiNKmUrjMejQ7zosvYHxxzDBoXv2jVfPFqDKH+lJck gmlKF9WbJor8MVjV08iTER8EHv80b0ofn3IPg1iYehGgFjoTq3BeYphKlrfiPSlKlH64kPI5iSA zxszwbITDM2RuopaIb/sCLWGdz1nCjKfT8fLKnHQDA5PGKfqr39NcNBS3etVqp4HCDtR/a7d+k6 LVDAm5A1+IiigoDB0yW3U0K4NFiUiMFVJ3NBNp4RZs0PbHxzzUcTL+hpmPJhqHaBLJgDCqOWtw0 cE0okq1sZgjRUt5c659umSopK2xcDfatJl7Gge4lKXVJ9VPQzkjwAVEe5n0KwoIoYpffPHDVcTh f27r0Rj5gaB7axtGg5n2BWgApRHiixnxqp1iKpzYVYU/4TFHYotoa4AGIpDfPCn0RUxqMq6MOPc 10F65j1akZyiUPtOtyA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-01_07,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 suspectscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 phishscore=0 priorityscore=1501 clxscore=1015 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606020087 IPQ9650 has two REFGEN blocks which provide reference current to the PCIe, USB and UNIPHY PHYs. Unlike other supported platforms, IPQ9650 requires the REFGEN clocks to be enabled explicitly. Document the IPQ9650 compatible and the required clocks for it. Signed-off-by: Kathiravan Thirumoorthy --- .../regulator/qcom,sdm845-refgen-regulator.yaml | 21 +++++++++++++++++= ++++ 1 file changed, 21 insertions(+) diff --git a/Documentation/devicetree/bindings/regulator/qcom,sdm845-refgen= -regulator.yaml b/Documentation/devicetree/bindings/regulator/qcom,sdm845-r= efgen-regulator.yaml index 40f9223d4c27..2686569ca060 100644 --- a/Documentation/devicetree/bindings/regulator/qcom,sdm845-refgen-regula= tor.yaml +++ b/Documentation/devicetree/bindings/regulator/qcom,sdm845-refgen-regula= tor.yaml @@ -16,6 +16,16 @@ description: allOf: - $ref: regulator.yaml# =20 + - if: + properties: + compatible: + contains: + const: qcom,ipq9650-refgen-regulator + then: + required: + - clocks + - clock-names + properties: compatible: oneOf: @@ -29,6 +39,7 @@ properties: =20 - items: - enum: + - qcom,ipq9650-refgen-regulator - qcom,qcs8300-refgen-regulator - qcom,sa8775p-refgen-regulator - qcom,sc7280-refgen-regulator @@ -45,6 +56,16 @@ properties: reg: maxItems: 1 =20 + clocks: + items: + - description: Core reference clock + - description: AHB interface clock + + clock-names: + items: + - const: core + - const: hclk + required: - compatible - reg --=20 2.34.1 From nobody Mon Jun 8 03:20:21 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 31BF93B8BCC for ; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-36dd91f1affsm2154028a91.11.2026.06.02.02.22.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 02:22:13 -0700 (PDT) From: Kathiravan Thirumoorthy Date: Tue, 02 Jun 2026 14:52:00 +0530 Subject: [PATCH 2/2] regulator: qcom-refgen: add support for the IPQ9650 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260602-ipq9650_refgen-v1-2-55e2afa5ff64@oss.qualcomm.com> References: <20260602-ipq9650_refgen-v1-0-55e2afa5ff64@oss.qualcomm.com> In-Reply-To: <20260602-ipq9650_refgen-v1-0-55e2afa5ff64@oss.qualcomm.com> To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Kathiravan Thirumoorthy X-Mailer: b4 0.15.2 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjAyMDA4NyBTYWx0ZWRfX1X9RFbKqRonD s0+6w//66b9beEJiv6EOh2g2kJt48Xe4Ap4igIgyVhawV1eSAO6phqWtxVyS7EXATB3VqYtZg0l IEbVTSRpd9xhaSaai9+5naod9P5AgrX7dU7GMNr1FsfRxZ6Kg3qirzB6fmuQD1YkZzwqKkdGtSz obht3TS+s2Kh/c8PkgwOBp0OwjVxK0tGOxcqLsy45pg5tDf8bA9hUv7KEhK/wtqB2jpk7WjR0lE n79HauoW3r6TmXu6crO/mOwp45+6/lpV8PmZ9GXPFNg5fepS+zSVS6GHwIFsZKgqLHeYLfkS9yl SZVHJnZUDxWcNzU+l5xa/08UmyG7HhmojwG5+Q6EsfmopoJSHRTZtl1ftKzB3N+MZPFD+hqxO4X TJWSg/zyQyUjQh7ey01v5XiX/igCQpOsuryifCwXQGjUdzY8zO8i8vAfJt1mVlGf0JgE6U94ZKd xNOhSewxEg1bkX+aarQ== X-Authority-Analysis: v=2.4 cv=d5nFDxjE c=1 sm=1 tr=0 ts=6a1ea0c6 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=mehsi33qI3AhlkpvdBkA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-ORIG-GUID: RH19z4pdSXdxoFSiFCiQSEuZ1cwlFAQN X-Proofpoint-GUID: RH19z4pdSXdxoFSiFCiQSEuZ1cwlFAQN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-01_07,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 malwarescore=0 clxscore=1015 adultscore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606020087 IPQ9650 SoC has 2 REFGEN blocks providing the reference current to the PCIe and USB, UNIPHY PHYs. For the other SoCs, clocks for this block is enabled on power up but that's not the case for IPQ9650 and we have to enable those clocks explicitly to bring up the PHYs properly. As per the design team, REFGEN block provides the reference current. Hence marked the regulator type as REGULATOR_CURRENT. Signed-off-by: Kathiravan Thirumoorthy --- drivers/regulator/qcom-refgen-regulator.c | 94 +++++++++++++++++++++++++++= ++-- 1 file changed, 90 insertions(+), 4 deletions(-) diff --git a/drivers/regulator/qcom-refgen-regulator.c b/drivers/regulator/= qcom-refgen-regulator.c index 299ac3c8c3bc..2858792acba8 100644 --- a/drivers/regulator/qcom-refgen-regulator.c +++ b/drivers/regulator/qcom-refgen-regulator.c @@ -3,6 +3,7 @@ // Copyright (c) 2023, Linaro Limited =20 #include +#include #include #include #include @@ -10,6 +11,7 @@ #include #include #include +#include =20 #define REFGEN_REG_BIAS_EN 0x08 #define REFGEN_BIAS_EN_MASK GENMASK(2, 0) @@ -25,6 +27,17 @@ #define REFGEN_PWRDWN_CTRL5_MASK BIT(0) #define REFGEN_PWRDWN_CTRL5_ENABLE 0x1 =20 +struct qcom_refgen_regulator_data { + const struct regulator_desc *rdesc; + bool has_clocks; +}; + +struct qcom_refgen_drvdata { + struct clk_bulk_data *clks; + int num_clks; + unsigned int enable_count; +}; + static int qcom_sdm845_refgen_enable(struct regulator_dev *rdev) { regmap_update_bits(rdev->regmap, REFGEN_REG_BG_CTRL, REFGEN_BG_CTRL_MASK, @@ -62,6 +75,49 @@ static int qcom_sdm845_refgen_is_enabled(struct regulato= r_dev *rdev) return 1; } =20 +static int qcom_ipq9650_refgen_enable(struct regulator_dev *rdev) +{ + struct qcom_refgen_drvdata *drvdata =3D rdev_get_drvdata(rdev); + int ret; + + ret =3D clk_bulk_prepare_enable(drvdata->num_clks, drvdata->clks); + if (ret) + return ret; + + drvdata->enable_count++; + + return 0; +} + +static int qcom_ipq9650_refgen_disable(struct regulator_dev *rdev) +{ + struct qcom_refgen_drvdata *drvdata =3D rdev_get_drvdata(rdev); + + clk_bulk_disable_unprepare(drvdata->num_clks, drvdata->clks); + drvdata->enable_count--; + + return 0; +} + +static int qcom_ipq9650_refgen_is_enabled(struct regulator_dev *rdev) +{ + struct qcom_refgen_drvdata *drvdata =3D rdev_get_drvdata(rdev); + + return drvdata->enable_count > 0; +} + +static const struct regulator_desc ipq9650_refgen_desc =3D { + .enable_time =3D 5, + .name =3D "refgen", + .owner =3D THIS_MODULE, + .type =3D REGULATOR_CURRENT, + .ops =3D &(const struct regulator_ops) { + .enable =3D qcom_ipq9650_refgen_enable, + .disable =3D qcom_ipq9650_refgen_disable, + .is_enabled =3D qcom_ipq9650_refgen_is_enabled, + }, +}; + static const struct regulator_desc sdm845_refgen_desc =3D { .enable_time =3D 5, .name =3D "refgen", @@ -90,6 +146,19 @@ static const struct regulator_desc sm8250_refgen_desc = =3D { }, }; =20 +static const struct qcom_refgen_regulator_data ipq9650_data =3D { + .rdesc =3D &ipq9650_refgen_desc, + .has_clocks =3D true, +}; + +static const struct qcom_refgen_regulator_data sdm845_data =3D { + .rdesc =3D &sdm845_refgen_desc, +}; + +static const struct qcom_refgen_regulator_data sm8250_data =3D { + .rdesc =3D &sm8250_refgen_desc, +}; + static const struct regmap_config qcom_refgen_regmap_config =3D { .reg_bits =3D 32, .reg_stride =3D 4, @@ -98,6 +167,8 @@ static const struct regmap_config qcom_refgen_regmap_con= fig =3D { =20 static int qcom_refgen_probe(struct platform_device *pdev) { + const struct qcom_refgen_regulator_data *data; + struct qcom_refgen_drvdata *drvdata =3D NULL; struct regulator_init_data *init_data; struct regulator_config config =3D {}; const struct regulator_desc *rdesc; @@ -106,10 +177,23 @@ static int qcom_refgen_probe(struct platform_device *= pdev) struct regmap *regmap; void __iomem *base; =20 - rdesc =3D of_device_get_match_data(dev); - if (!rdesc) + data =3D of_device_get_match_data(dev); + if (!data) return -ENODATA; =20 + if (data->has_clocks) { + drvdata =3D devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + drvdata->num_clks =3D devm_clk_bulk_get_all(dev, &drvdata->clks); + if (drvdata->num_clks < 0) + return dev_err_probe(dev, drvdata->num_clks, + "failed to get clocks\n"); + } + + rdesc =3D data->rdesc; + base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) return PTR_ERR(base); @@ -126,6 +210,7 @@ static int qcom_refgen_probe(struct platform_device *pd= ev) config.init_data =3D init_data; config.of_node =3D dev->of_node; config.regmap =3D regmap; + config.driver_data =3D drvdata; =20 rdev =3D devm_regulator_register(dev, rdesc, &config); if (IS_ERR(rdev)) @@ -135,8 +220,9 @@ static int qcom_refgen_probe(struct platform_device *pd= ev) } =20 static const struct of_device_id qcom_refgen_match_table[] =3D { - { .compatible =3D "qcom,sdm845-refgen-regulator", .data =3D &sdm845_refge= n_desc }, - { .compatible =3D "qcom,sm8250-refgen-regulator", .data =3D &sm8250_refge= n_desc }, + { .compatible =3D "qcom,ipq9650-refgen-regulator", .data =3D &ipq9650_dat= a }, + { .compatible =3D "qcom,sdm845-refgen-regulator", .data =3D &sdm845_data = }, + { .compatible =3D "qcom,sm8250-refgen-regulator", .data =3D &sm8250_data = }, { } }; MODULE_DEVICE_TABLE(of, qcom_refgen_match_table); --=20 2.34.1