From nobody Mon Jun 8 04:25:37 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 358CD3D25D2 for ; Tue, 2 Jun 2026 09:11:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780391489; cv=none; b=Un0RfBm8Oj5mwyvv6f4n/u/INduhmxezzeFkHsbQiMspFAbNx8yDR7Ix0nJukVk0q7YlBIlFi5i11MuPA8uTLJPMhhC2qPdsezOoEpfhw8+N0NHE9OhM6VfDc9U5VC1qFkieFG/Bj5af50jXQjU/NhSaodM0opZNK6fc+3gba/M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780391489; c=relaxed/simple; bh=Uq7SV6Ep5ActlglyrkOIZMDwSsOOyS7xf6CtI/ZDDWI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mQyKGGyJe0ekUqP8ThHscIJTHLKuvw9qOSokJ0aiWMpcNSO8UuMkv19y3AdS46e1yG9V1/6B0QOHKYKMtlrDfbJY6aTBLaaRghfoPYKvHEYOhJ7gD1Mu474Z9HxeKxRwN3BwlCJF/fiectpVRTW52z0ZvpwJ0A10vUsm54y2BV0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=jAa/bHTx; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=eHGXRfC/; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="jAa/bHTx"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="eHGXRfC/" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 6526MdaB2767325 for ; Tue, 2 Jun 2026 09:11:27 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= wRMlDIbqB0uP0ea/ic+hhlybUOF+IemcZoAacOc4Yzg=; b=jAa/bHTxyqCQXBs1 yQDG+SVE9IDIFm7FrpOJs//K7f/LJmAZSpJe42cBkeQFA/6kmimuKdh18Bei2Jbh 9l4NaOt/lR4U8tHekAEtFrn1qHrxDs8CKiO50sUlPGsL9nYmIHyHc0UwDbGcCFnd 2q/t0Qwell9fcCh+P6dYn6Uw+dI3TKBJ+rY4Lci5dCYwAiWpu3wiltqZFwfm0Vat zyZhOtD+Namg1MT3NtQD/0lg5VFJTRAcMXW7QYnYlH6pRN2/py694K1XEtKuvHAq 5chqPFVCJ+XQGvikxB+wxlIeFlQssnUcsel3CIFzYNOQnMaYiEeKxt1vchoy/acJ 06J17w== Received: from mail-qt1-f200.google.com (mail-qt1-f200.google.com [209.85.160.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ehsus0pnu-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 02 Jun 2026 09:11:27 +0000 (GMT) Received: by mail-qt1-f200.google.com with SMTP id d75a77b69052e-51766317074so18311621cf.3 for ; Tue, 02 Jun 2026 02:11:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1780391486; x=1780996286; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=wRMlDIbqB0uP0ea/ic+hhlybUOF+IemcZoAacOc4Yzg=; b=eHGXRfC/t5Zsc0BbTQrtwIm2JsMHSR36fGLMM2tmvO1/8P4SoAkjhW0+PHJG/vXmyk vlMsjqRcr2S9XHZ2JhQfJSR0c3vt4vvDds6WOk3Uv2d1W7Oqw2wBFYmuCtkFxuWZK3tk ySOhcvzxwXUow0982uhhBGoiNMY7qMEPYqFWgqpgdjRFv4KkPvlGgBWhBLE7/76ks3hg zmMEdVl5BM8Zw4JXOMOCjGzFEDfBOV5MfglceqagsApBJ0kyslSxA/ifnUSV64lsoJDB PiS+L2cN1Ah4Txbo6Vnyyif12LZE62fffAiFHn0BK3JurddrelKZG/JlD2ohMtDR3PJj W6FQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1780391486; x=1780996286; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=wRMlDIbqB0uP0ea/ic+hhlybUOF+IemcZoAacOc4Yzg=; b=lqo+/Z5dxQuHfJIuelwEcXFFSuqZG9/kNu+IDjvQIawXk9wtp3LTGGgO4DVSV5yRPI JQ9IsT49SNuTD8xR3eu5dn7okRoj91RPe9OhlAHwo12+MS6ZmHUMxMNWZ9gqqQS2c1E3 lsdAasMHtp0cO1aq0RO53Fc20d50JDamd/JUlk4x4cVUyTwwzcofZckB5MhqTLahLsjV PQTJXEMsE/1s5rIkvATz7ld9YmEuylulAaUQ0R3SsyC2AFchNVE2A+lLo8pxZ//bOHID UAL26sFZ18a1J4WpoEJXN6EMQuObsGVsL5f9HDctQr6ce7kKtryu+BL0E7yu+Q6isWJi t0sg== X-Forwarded-Encrypted: i=1; AFNElJ8QE8wR3j5R4ay8Wfb04a6lJTmwTh6Sjsxhy8tQcEo/4FmDoidK9S1dsm9fu3QmwVMzncxcSsIEPv36zts=@vger.kernel.org X-Gm-Message-State: AOJu0Yy/tww48eMY/0N+ZFYt/HWCWaqRw4ZmJIsYsMJOudNDgHRxFUGL TRrEZRLE4jTb6/PM80od2aogPN9PnQ1EiNKS6gwN02QEGdixqDJ5xGexqf76iM1lEhIKLHERQjN 73ogRC12vr0R2IBwXZW+6PN3s7pjsCyymQvhXO71lMh2VlkhN3KRG1mb7jX3IwBiWEjQ= X-Gm-Gg: Acq92OHe0RMx08s4faBWkMUcz61M4NL+u+/bxKGp8HTkUi5JU+6Z0JFw0ReHqlgzvkk GRKqF6zk4hNWcCcfpQFPN/23kboCObdMPZZPQmfYs3RVjH3W3wZTZpsruTBqxDZl/3qH4Rytrvw V+tFZuAmAFA5AZmyGqZdbL4HbbR4+v7U6lgDRzS3NHJmW9HE6m1p6g4ILPO1X84ynR/dvL3IpTi g8ziNm5hIijcVjBBtVvcWvKp19KEScAO16CNp6HUmCpk7CZ6mhkTZ8Dabh9ZopwRwXlIxDvOWOc lPx9RhbHpie4z9vrUknQSx7u/u83zHfqiOzW+QjzFxd1Q+vP5bg8/QNGHFbXUWX+8g8NuN6PD/e WdwNcRH3CFCpWpCcbO4hTpIx7WgGgfurMogOhpkogODMfBOqAr5wzd5rxlnaevk1uehuIQ1nLUh WeiOCpQOcQuWnIK31cFA== X-Received: by 2002:a05:622a:248e:b0:517:146d:185b with SMTP id d75a77b69052e-5173a7eefe3mr214883321cf.30.1780391486272; Tue, 02 Jun 2026 02:11:26 -0700 (PDT) X-Received: by 2002:a05:622a:248e:b0:517:146d:185b with SMTP id d75a77b69052e-5173a7eefe3mr214882921cf.30.1780391485816; Tue, 02 Jun 2026 02:11:25 -0700 (PDT) Received: from yongmou2.ap.qualcomm.com (Global_NAT1_IAD_FW.qualcomm.com. [129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-51768c76e53sm12480851cf.4.2026.06.02.02.11.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 02:11:25 -0700 (PDT) From: Yongxing Mou Date: Tue, 02 Jun 2026 17:11:13 +0800 Subject: [PATCH v6 01/15] drm/msm/dp: remove cached drm_edid from panel Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260602-dp_mstclean-v6-1-2c17ff40a9b2@oss.qualcomm.com> References: <20260602-dp_mstclean-v6-0-2c17ff40a9b2@oss.qualcomm.com> In-Reply-To: <20260602-dp_mstclean-v6-0-2c17ff40a9b2@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Dmitry Baryshkov X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780391476; l=9216; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=Uq7SV6Ep5ActlglyrkOIZMDwSsOOyS7xf6CtI/ZDDWI=; b=fUnbdJv/ZWAzCaS1RzEOOyudGpMeIUlUFolnSLteOUGHSpMdp0AP9VtJtyEkw3pinEG4pZv6F jkqx0LVYcHsBqMVYMcIg1ckbF1bAusrET2Po1lGS7y/es7yqvfVPs8i X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-ORIG-GUID: SF75i1zpQkEzPaJn8zoQGeXgBmdeG1NM X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjAyMDA4NSBTYWx0ZWRfX6UloMMWpsLeR oXi1kpbc7owrNcXcwn/xegZeRqhD3KFCjB5UUEqNOGkq1Qj8POz0t+bFO0CUM9pnGlxAZ+81hQz esDe6c0NaONx1lNUco0+wusFr4Z+kZSlBLUlFaFSbC+/o9WPy2mCv6xFgONcLclH9Fo4lHcoCXK grse6D5AkW63cZ+c0eCaM17MDz1+IzR8AHKTKm0QWcT8NrFS4hQcTGVTvfZgxbNbn9xaejgu065 nexxX1jBq7ZhBCYUgvgU15t5KFjHwBEHXQwVEb44JilSJRB/2mpbaa6wSxVpgXO4CGRFl6lPIYb lIZYBPsVcl0WLA6MJVbar3cQ1/4CTSME0f3xK8JsWdUqYYycmvzOw5KnywniQeW2bl9xqYraH/s 8F/qLIid7+psSfDn1L6sHK//KEXl885ebvkH13Juyorxxdi8gF+IGKaXhq7sSfRVd8zSbMBVutF jOTO8a4BZ/bwIcw1v8g== X-Authority-Analysis: v=2.4 cv=ZYAt8MVA c=1 sm=1 tr=0 ts=6a1e9e3f cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=yBxTOPed86Cp7mhl67IA:9 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-GUID: SF75i1zpQkEzPaJn8zoQGeXgBmdeG1NM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-01_07,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 clxscore=1015 adultscore=0 impostorscore=0 spamscore=0 phishscore=0 suspectscore=0 malwarescore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606020085 The cached drm_edid seems unnecessary here. Use the drm_edid pointer directly in the plug stage instead of caching it. Remove the cached drm_edid and the corresponding oneliner to simplify the code. Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_display.c | 28 +++++++++++------- drivers/gpu/drm/msm/dp/dp_panel.c | 57 ++++-----------------------------= ---- drivers/gpu/drm/msm/dp/dp_panel.h | 13 +++------ 3 files changed, 27 insertions(+), 71 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 6800c628adb4..e3682c4d6077 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -269,6 +269,7 @@ static int msm_dp_display_process_hpd_high(struct msm_d= p_display_private *dp) const struct drm_display_info *info =3D &connector->display_info; int rc =3D 0; u8 dpcd[DP_RECEIVER_CAP_SIZE]; + const struct drm_edid *drm_edid =3D NULL; =20 rc =3D drm_dp_read_dpcd_caps(dp->aux, dpcd); if (rc) @@ -276,10 +277,20 @@ static int msm_dp_display_process_hpd_high(struct msm= _dp_display_private *dp) =20 dp->link->lttpr_count =3D msm_dp_display_lttpr_init(dp, dpcd); =20 - rc =3D msm_dp_panel_read_sink_caps(dp->panel, connector); + rc =3D msm_dp_panel_read_link_caps(dp->panel, connector); if (rc) goto end; =20 + drm_edid =3D drm_edid_read_ddc(connector, &dp->aux->ddc); + drm_edid_connector_update(connector, drm_edid); + + if (!drm_edid) { + DRM_ERROR("panel edid read failed\n"); + /* check edid read fail is due to unplug */ + if (!msm_dp_aux_is_link_connected(dp->aux)) + return -ETIMEDOUT; + } + msm_dp_link_process_request(dp->link); =20 if (!dp->msm_dp_display.is_edp) @@ -291,7 +302,7 @@ static int msm_dp_display_process_hpd_high(struct msm_d= p_display_private *dp) dp->msm_dp_display.psr_supported =3D dp->panel->psr_cap.version && psr_en= abled; =20 dp->audio_supported =3D info->has_audio; - msm_dp_panel_handle_sink_request(dp->panel); + msm_dp_panel_handle_sink_request(dp->panel, drm_edid); =20 /* * set sink to normal operation mode -- D0 @@ -302,6 +313,7 @@ static int msm_dp_display_process_hpd_high(struct msm_d= p_display_private *dp) msm_dp_link_reset_phy_params_vx_px(dp->link); =20 end: + drm_edid_free(drm_edid); return rc; } =20 @@ -453,7 +465,7 @@ static int msm_dp_hpd_unplug_handle(struct msm_dp_displ= ay_private *dp) =20 /* Don't forget modes for eDP */ if (!dp->msm_dp_display.is_edp) - msm_dp_panel_unplugged(dp->panel, dp->msm_dp_display.connector); + drm_edid_connector_update(dp->msm_dp_display.connector, NULL); =20 /* triggered by irq_hdp with sink_count =3D 0 */ if (dp->link->sink_count =3D=3D 0) @@ -515,7 +527,6 @@ static int msm_dp_irq_hpd_handle(struct msm_dp_display_= private *dp) static void msm_dp_display_deinit_sub_modules(struct msm_dp_display_privat= e *dp) { msm_dp_audio_put(dp->audio); - msm_dp_panel_put(dp->panel); msm_dp_aux_put(dp->aux); } =20 @@ -566,7 +577,7 @@ static int msm_dp_init_sub_modules(struct msm_dp_displa= y_private *dp) rc =3D PTR_ERR(dp->ctrl); DRM_ERROR("failed to initialize ctrl, rc =3D %d\n", rc); dp->ctrl =3D NULL; - goto error_ctrl; + goto error_link; } =20 dp->audio =3D msm_dp_audio_get(dp->msm_dp_display.pdev, dp->link_base); @@ -574,13 +585,11 @@ static int msm_dp_init_sub_modules(struct msm_dp_disp= lay_private *dp) rc =3D PTR_ERR(dp->audio); pr_err("failed to initialize audio, rc =3D %d\n", rc); dp->audio =3D NULL; - goto error_ctrl; + goto error_link; } =20 return rc; =20 -error_ctrl: - msm_dp_panel_put(dp->panel); error_link: msm_dp_aux_put(dp->aux); error: @@ -744,8 +753,7 @@ int msm_dp_display_get_modes(struct msm_dp *dp) =20 msm_dp_display =3D container_of(dp, struct msm_dp_display_private, msm_dp= _display); =20 - return msm_dp_panel_get_modes(msm_dp_display->panel, - dp->connector); + return drm_edid_connector_add_modes(msm_dp_display->panel->connector); } =20 bool msm_dp_display_check_video_test(struct msm_dp *dp) diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_= panel.c index 6bb021820d7c..bde4a772d22c 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -232,8 +232,8 @@ static u32 msm_dp_panel_get_supported_bpp(struct msm_dp= _panel *msm_dp_panel, return min_supported_bpp; } =20 -int msm_dp_panel_read_sink_caps(struct msm_dp_panel *msm_dp_panel, - struct drm_connector *connector) +int msm_dp_panel_read_link_caps(struct msm_dp_panel *msm_dp_panel, + struct drm_connector *connector) { int rc, bw_code; int count; @@ -271,36 +271,9 @@ int msm_dp_panel_read_sink_caps(struct msm_dp_panel *m= sm_dp_panel, =20 rc =3D drm_dp_read_downstream_info(panel->aux, msm_dp_panel->dpcd, msm_dp_panel->downstream_ports); - if (rc) - return rc; - - drm_edid_free(msm_dp_panel->drm_edid); - - msm_dp_panel->drm_edid =3D drm_edid_read_ddc(connector, &panel->aux->ddc); - - drm_edid_connector_update(connector, msm_dp_panel->drm_edid); - - if (!msm_dp_panel->drm_edid) { - DRM_ERROR("panel edid read failed\n"); - /* check edid read fail is due to unplug */ - if (!msm_dp_aux_is_link_connected(panel->aux)) { - rc =3D -ETIMEDOUT; - goto end; - } - } - -end: return rc; } =20 -void msm_dp_panel_unplugged(struct msm_dp_panel *msm_dp_panel, - struct drm_connector *connector) -{ - drm_edid_connector_update(connector, NULL); - drm_edid_free(msm_dp_panel->drm_edid); - msm_dp_panel->drm_edid =3D NULL; -} - u32 msm_dp_panel_get_mode_bpp(struct msm_dp_panel *msm_dp_panel, u32 mode_edid_bpp, u32 mode_pclk_khz) { @@ -324,20 +297,6 @@ u32 msm_dp_panel_get_mode_bpp(struct msm_dp_panel *msm= _dp_panel, return bpp; } =20 -int msm_dp_panel_get_modes(struct msm_dp_panel *msm_dp_panel, - struct drm_connector *connector) -{ - if (!msm_dp_panel) { - DRM_ERROR("invalid input\n"); - return -EINVAL; - } - - if (msm_dp_panel->drm_edid) - return drm_edid_connector_add_modes(connector); - - return 0; -} - static u8 msm_dp_panel_get_edid_checksum(const struct edid *edid) { edid +=3D edid->extensions; @@ -345,7 +304,8 @@ static u8 msm_dp_panel_get_edid_checksum(const struct e= did *edid) return edid->checksum; } =20 -void msm_dp_panel_handle_sink_request(struct msm_dp_panel *msm_dp_panel) +void msm_dp_panel_handle_sink_request(struct msm_dp_panel *msm_dp_panel, + const struct drm_edid *drm_edid) { struct msm_dp_panel_private *panel; =20 @@ -358,7 +318,7 @@ void msm_dp_panel_handle_sink_request(struct msm_dp_pan= el *msm_dp_panel) =20 if (panel->link->sink_request & DP_TEST_LINK_EDID_READ) { /* FIXME: get rid of drm_edid_raw() */ - const struct edid *edid =3D drm_edid_raw(msm_dp_panel->drm_edid); + const struct edid *edid =3D drm_edid_raw(drm_edid); u8 checksum; =20 if (edid) @@ -755,10 +715,3 @@ struct msm_dp_panel *msm_dp_panel_get(struct device *d= ev, struct drm_dp_aux *aux return msm_dp_panel; } =20 -void msm_dp_panel_put(struct msm_dp_panel *msm_dp_panel) -{ - if (!msm_dp_panel) - return; - - drm_edid_free(msm_dp_panel->drm_edid); -} diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_= panel.h index 9173e90a5053..53b7b4463551 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -33,7 +33,6 @@ struct msm_dp_panel { u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; =20 struct msm_dp_link_info link_info; - const struct drm_edid *drm_edid; struct drm_connector *connector; struct msm_dp_display_mode msm_dp_mode; struct msm_dp_panel_psr psr_cap; @@ -47,15 +46,12 @@ struct msm_dp_panel { int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel); int msm_dp_panel_deinit(struct msm_dp_panel *msm_dp_panel); int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_b= us_en); -int msm_dp_panel_read_sink_caps(struct msm_dp_panel *msm_dp_panel, - struct drm_connector *connector); -void msm_dp_panel_unplugged(struct msm_dp_panel *msm_dp_panel, - struct drm_connector *connector); +int msm_dp_panel_read_link_caps(struct msm_dp_panel *msm_dp_panel, + struct drm_connector *connector); u32 msm_dp_panel_get_mode_bpp(struct msm_dp_panel *msm_dp_panel, u32 mode_= max_bpp, u32 mode_pclk_khz); -int msm_dp_panel_get_modes(struct msm_dp_panel *msm_dp_panel, - struct drm_connector *connector); -void msm_dp_panel_handle_sink_request(struct msm_dp_panel *msm_dp_panel); +void msm_dp_panel_handle_sink_request(struct msm_dp_panel *msm_dp_panel, + const struct drm_edid *drm_edid); void msm_dp_panel_tpg_config(struct msm_dp_panel *msm_dp_panel, bool enabl= e); =20 void msm_dp_panel_clear_dsc_dto(struct msm_dp_panel *msm_dp_panel); @@ -94,5 +90,4 @@ struct msm_dp_panel *msm_dp_panel_get(struct device *dev,= struct drm_dp_aux *aux struct msm_dp_link *link, void __iomem *link_base, void __iomem *p0_base); -void msm_dp_panel_put(struct msm_dp_panel *msm_dp_panel); #endif /* _DP_PANEL_H_ */ --=20 2.43.0 From nobody Mon Jun 8 04:25:37 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC0CA3D333F for ; Tue, 2 Jun 2026 09:11:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780391494; cv=none; b=rjTUExiplrYyEdQPjnDhMrQcw9T2u64588qn2YD6lKEdUiglcpOK2r+Hl9hcoAObYkXMXSPc5X1exvYX8yuvTI75pW4/fYGVxcoU8yij+nG1SNjKD/p+eONygUIHbjQ0yHdswWYa/tapHPiZUIg7uPK4cXx/bPs6Zt2ETYdDhww= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780391494; c=relaxed/simple; bh=HuWHEfgETeqeFInaSeDlkVr7MomHzKqKAmZIdQ6wMSs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pdnhp9+klWW+9+1B6UqeQ/Iudegm+/blDDtSuR/Fn+dFjXggqkNZQmZz8SbIp9EzBnlSJburf6FZVITY+ldXxvHxtp4CgMqIvXk8n+rXd1ZnaVRNcchrP1NORhPB54Qz6MXl4v5x1SN02FhdO/ZXMHOkAszmiKvcmgYtx4FJgOs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=IZ1PcfUf; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=HFYXhU6y; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="IZ1PcfUf"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="HFYXhU6y" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 6525tWw44012409 for ; Tue, 2 Jun 2026 09:11:32 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= Duf46m0jTOVOH0fYjqS+1d3N2OndiCBozOdXn5npkR4=; b=IZ1PcfUf1rl4SRr4 0rrKO0ahjDhHtkN4zmWWZNwz2Hh8hzBIPGJrMd3/vrFgYtefoDwwWuzc7q4YPcSk MlwnHnirbmvQpxgWv4E6bZ0xPkcoa3Ys4bvCviaH97lmv2vgS/a21g1GPhSo8lh/ 78deG6a495TavcqK74fKfY2r8+ZBSG02bP1xdV9LEf1Sh/afoVYtqi8Tgnbc2X9h VbZ5cvnHJ9JlFF0APRMfW447B9jlfKdPLshHtcP7JtIDiP18kQubcqSEk//ibDLK iDCQjbs0ZR0NfrssWWX7WlvtZXCG7h67B9cU9tjDhpSg+ANxeYzovFQsVHRZpLiW mZGLPA== Received: from mail-qt1-f199.google.com (mail-qt1-f199.google.com [209.85.160.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ehsf4gt8p-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 02 Jun 2026 09:11:32 +0000 (GMT) Received: by mail-qt1-f199.google.com with SMTP id d75a77b69052e-5174a236220so48857411cf.3 for ; Tue, 02 Jun 2026 02:11:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1780391491; x=1780996291; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Duf46m0jTOVOH0fYjqS+1d3N2OndiCBozOdXn5npkR4=; b=HFYXhU6yRIb9LePZyFiWgMYipWUM6xLh03HQ/7nsFFVvkt5wHlwp6MbWQ27WjwDxbL NHNSC4im8uSxMQispLTsMadB3jkaqJrlosq7RFx7M6s41YGWZlkP1api29Sx4q+e/jpl slSKU5/BIExaHf/MpBf8OulFKd+rmSBKIoJqVhmMvoH7QRLlwB4bQ/Uy/EW1H1xnDmAg feDRRtsBIk8T+J2/0J1O37VM8uoAR1lBWwLlEobevxjsNHht2qvmUMgJ5JSnHgn6+ADn bnrZCNb7hGs6dv4zAkvLArgvjBz6c7YVOQK3l9a3DTF79GOHKElLJzzmIZ1bO6S/OnpV YVkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1780391491; x=1780996291; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=Duf46m0jTOVOH0fYjqS+1d3N2OndiCBozOdXn5npkR4=; b=ZnEWFbI8NkssfPA8PhlU9AqZKFGF2ylztxvC1AHvEcXwz6R5LHN7IZiWy6U4lilmdC +aeZZWp53doq6Rel4WBEgCEDtuWv7FD6r7xGwDtq22OTjH9P9aJEeiD/arYFmUnB5EmY J6oc+szOWVEBkph+/saC/9L9ayf/f0j6I6BL71QzF5xJuG/3JVXEwWb/ksmgyWcy16lx DGZ4eDLJxC6ivSkWJFXCEsl1fIGr7Sky4f6UCAU0aLPMtYQ1cubZ8w3d9AQaDZXNTG2P znAoTQJOu5+W/aG8da4EWsxaMrB6TV7MwWhDLstLTBEMeEtStPYdImdkrXB7QGwxKPPF aBJQ== X-Forwarded-Encrypted: i=1; AFNElJ+InyF2vva3bowHjdTW19xQvnm+LsjLbHjWvNIxZaWI3/RwWRCLH2j/DjkjC0fjQn+4S9dcDLuKQNccr6w=@vger.kernel.org X-Gm-Message-State: AOJu0Yzx3Y+if8rWK8x+6hy6kALFJyYVsMh1lTtZjIofwGDctR9+ukcZ 2ABaN0PwMFvqovHFSsABKrJ1PuQkz/2fwrszKBR2Lo+71KsltOchMSf1W9pEbpVZtA75Wn1iR38 0bXIjapto51F6LvIKO2LFKKbUnDVeomd/JkhgAkkStMAWCg6bKLCoc/LML7r+agqxg2k= X-Gm-Gg: Acq92OEIpbQp5lXazroiijOeG7ILfHN+eDd7YrGFhYHJn/8Qk8N/oDQ9h6YLarozRu8 k4/H/zxqlZvzFR89vizooF9549N6XCZaZRsjMoWDSBdrnJ/gmuOrPNSGlLw5jtpnEkR/H4HKDhT co8BUr3a349f/Wi+LWot44u6QHqxMdCp9Dp+7yrGsY9Nwlf3lKTA/z2JCRmnoOjBY3j1R1NI9Yt ZsFxQfs7KcVBc3tJAD5vEpGYOaY88lDKu7JvdDQs0h8xyQlFhh/zqEkc030wANSj7tayYUleP6o xbJir5cLnqogeheq43QmfNbclbO310Cp2TAKq+dW8dW49gC7ykuILFe/2l4xU8jUqFksnSDZR6N PL2xiNlWSbKM20pXa0YCbbvunwj8egOGSKZikqtUJr/877YuT1IkP/+ijLXGkJLX+48tfz+xBYr QUkTs+IDOPJQHdM8r3HA== X-Received: by 2002:a05:622a:284:b0:517:6ef7:f6ea with SMTP id d75a77b69052e-5176ef7fb5fmr10989181cf.11.1780391491182; Tue, 02 Jun 2026 02:11:31 -0700 (PDT) X-Received: by 2002:a05:622a:284:b0:517:6ef7:f6ea with SMTP id d75a77b69052e-5176ef7fb5fmr10988731cf.11.1780391490741; Tue, 02 Jun 2026 02:11:30 -0700 (PDT) Received: from yongmou2.ap.qualcomm.com (Global_NAT1_IAD_FW.qualcomm.com. [129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-51768c76e53sm12480851cf.4.2026.06.02.02.11.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 02:11:30 -0700 (PDT) From: Yongxing Mou Date: Tue, 02 Jun 2026 17:11:14 +0800 Subject: [PATCH v6 02/15] drm/msm/dp: drop deprecated .mode_set() and use .atomic_enable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260602-dp_mstclean-v6-2-2c17ff40a9b2@oss.qualcomm.com> References: <20260602-dp_mstclean-v6-0-2c17ff40a9b2@oss.qualcomm.com> In-Reply-To: <20260602-dp_mstclean-v6-0-2c17ff40a9b2@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Abhinav Kumar , Dmitry Baryshkov X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780391476; l=8155; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=HuWHEfgETeqeFInaSeDlkVr7MomHzKqKAmZIdQ6wMSs=; b=M69pZb0hXor2OgwRt9PIzLikRSelckTn7Ng1DDuYG7f7f/Lg6xBo4UBuvTKsw1Z4oTMeB9wT7 Kp42JM4BCdGDqLlk4eDsjSgkqlc0A3YhqxTW3kIZ7iebQa6reK19O/2 X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjAyMDA4NSBTYWx0ZWRfXx5kQtGrZTjfy p/+lDBfKo9m5zBqMpPo9MeTWFqP6vCtBEEMdKVWSxV/X+RRvKLjMJcM8nrNJpUZpVZlN8YatULu B54NHgblIvLFqr413rSrEx17FUNVrsRJAUr1pl7nytfAubhCdZDh0ECACfmBuexZbCJs2EgSsih 7q7PGJC6VqnBgmj8QyIhRK/EnB7skPGFBX9DLjq8vw06Q0pzasbeYouUv7bFZ6/oQd1hg5aCUhW XU+Pv1akHkN1qQwnMm+WC9KA+/uVNalxhn25IZbmRATjl7mJ1BQ6A9fHgjl3b+oXlJ/U25/bX9C KPdwiuw/yn1sVtJZ37zgM2ncZbnfWUKVOsDQz1goO4Dh1kcXaCUdT5sedBTOXanVEu7Mpkas1ga H/n5ql+u7Pvxgn1muKB5JBLhc+lGCQw/uWT+bjsNyDAiec65Jb5EMA0Z9zcQlTVUsSd+d1X21gL gFzIIgUQugIHlUdt6BQ== X-Proofpoint-GUID: xywmjie6d_vl--gvPsmeGzP-1oLTyvlW X-Authority-Analysis: v=2.4 cv=AJZ7LEvz c=1 sm=1 tr=0 ts=6a1e9e44 cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=ohAeICWEHyx3i1rom8gA:9 a=QEXdDO2ut3YA:10 a=kacYvNCVWA4VmyqE58fU:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: xywmjie6d_vl--gvPsmeGzP-1oLTyvlW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-01_07,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 suspectscore=0 malwarescore=0 phishscore=0 bulkscore=0 impostorscore=0 clxscore=1015 lowpriorityscore=0 spamscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606020085 The bridge .mode_set() callback is deprecated. Remove it and move all mode setup logic to .atomic_enable(), where the adjusted_mode is available from the atomic CRTC state. Drop msm_dp_mode from msm_dp_display_private and store the mode directly in the panel, as it was only used as a temporary cache. Both changes are limited to msm_dp_display_set_mode and are kept in a single patch. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_display.c | 81 ++++++++++++++-------------------= ---- drivers/gpu/drm/msm/dp/dp_drm.c | 2 - drivers/gpu/drm/msm/dp/dp_drm.h | 3 -- 3 files changed, 31 insertions(+), 55 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index e3682c4d6077..181d238addfc 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -63,7 +63,6 @@ struct msm_dp_display_private { struct msm_dp_panel *panel; struct msm_dp_ctrl *ctrl; =20 - struct msm_dp_display_mode msm_dp_mode; struct msm_dp msm_dp_display; =20 /* wait for audio signaling */ @@ -597,16 +596,33 @@ static int msm_dp_init_sub_modules(struct msm_dp_disp= lay_private *dp) } =20 static int msm_dp_display_set_mode(struct msm_dp *msm_dp_display, - struct msm_dp_display_mode *mode) + const struct drm_display_mode *adjusted_mode, + struct msm_dp_panel *msm_dp_panel) { struct msm_dp_display_private *dp; + u32 bpp; =20 dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 - drm_mode_copy(&dp->panel->msm_dp_mode.drm_mode, &mode->drm_mode); - dp->panel->msm_dp_mode.bpp =3D mode->bpp; - dp->panel->msm_dp_mode.out_fmt_is_yuv_420 =3D mode->out_fmt_is_yuv_420; - msm_dp_panel_init_panel_info(dp->panel); + drm_mode_copy(&msm_dp_panel->msm_dp_mode.drm_mode, adjusted_mode); + if (msm_dp_display_check_video_test(msm_dp_display)) + bpp =3D msm_dp_display_get_test_bpp(msm_dp_display); + else + bpp =3D msm_dp_panel->connector->display_info.bpc * 3; + + msm_dp_panel->msm_dp_mode.bpp =3D bpp ? bpp : 24; /* Default bpp */ + msm_dp_panel->msm_dp_mode.v_active_low =3D + !!(adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC); + msm_dp_panel->msm_dp_mode.h_active_low =3D + !!(adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC); + msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420 =3D + drm_mode_is_420_only(&msm_dp_panel->connector->display_info, adjusted_mo= de) && + msm_dp_panel->vsc_sdp_supported; + msm_dp_panel_init_panel_info(msm_dp_panel); + + /* populate wide_bus_support to different layers */ + dp->ctrl->wide_bus_en =3D + msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420 ? false : dp->wide_bus_supp= orted; return 0; } =20 @@ -1309,7 +1325,7 @@ bool msm_dp_wide_bus_available(const struct msm_dp *m= sm_dp_display) =20 dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 - if (dp->msm_dp_mode.out_fmt_is_yuv_420) + if (dp->panel->msm_dp_mode.out_fmt_is_yuv_420) return false; =20 return dp->wide_bus_supported; @@ -1365,15 +1381,19 @@ void msm_dp_bridge_atomic_enable(struct drm_bridge = *drm_bridge, { struct msm_dp_bridge *msm_dp_bridge =3D to_dp_bridge(drm_bridge); struct msm_dp *dp =3D msm_dp_bridge->msm_dp_display; + struct drm_crtc *crtc; + struct drm_crtc_state *crtc_state; int rc =3D 0; struct msm_dp_display_private *msm_dp_display; bool force_link_train =3D false; =20 msm_dp_display =3D container_of(dp, struct msm_dp_display_private, msm_dp= _display); - if (!msm_dp_display->msm_dp_mode.drm_mode.clock) { - DRM_ERROR("invalid params\n"); + + crtc =3D drm_atomic_get_new_crtc_for_encoder(state, + drm_bridge->encoder); + if (!crtc) return; - } + crtc_state =3D drm_atomic_get_new_crtc_state(state, crtc); =20 if (dp->is_edp) msm_dp_hpd_plug_handle(msm_dp_display); @@ -1386,7 +1406,7 @@ void msm_dp_bridge_atomic_enable(struct drm_bridge *d= rm_bridge, if (msm_dp_display->link->sink_count =3D=3D 0) return; =20 - rc =3D msm_dp_display_set_mode(dp, &msm_dp_display->msm_dp_mode); + rc =3D msm_dp_display_set_mode(dp, &crtc_state->adjusted_mode, msm_dp_dis= play->panel); if (rc) { DRM_ERROR("Failed to perform a mode set, rc=3D%d\n", rc); return; @@ -1446,45 +1466,6 @@ void msm_dp_bridge_atomic_post_disable(struct drm_br= idge *drm_bridge, pm_runtime_put_sync(&dp->pdev->dev); } =20 -void msm_dp_bridge_mode_set(struct drm_bridge *drm_bridge, - const struct drm_display_mode *mode, - const struct drm_display_mode *adjusted_mode) -{ - struct msm_dp_bridge *msm_dp_bridge =3D to_dp_bridge(drm_bridge); - struct msm_dp *dp =3D msm_dp_bridge->msm_dp_display; - struct msm_dp_display_private *msm_dp_display; - struct msm_dp_panel *msm_dp_panel; - - msm_dp_display =3D container_of(dp, struct msm_dp_display_private, msm_dp= _display); - msm_dp_panel =3D msm_dp_display->panel; - - memset(&msm_dp_display->msm_dp_mode, 0x0, sizeof(struct msm_dp_display_mo= de)); - - if (msm_dp_display_check_video_test(dp)) - msm_dp_display->msm_dp_mode.bpp =3D msm_dp_display_get_test_bpp(dp); - else /* Default num_components per pixel =3D 3 */ - msm_dp_display->msm_dp_mode.bpp =3D dp->connector->display_info.bpc * 3; - - if (!msm_dp_display->msm_dp_mode.bpp) - msm_dp_display->msm_dp_mode.bpp =3D 24; /* Default bpp */ - - drm_mode_copy(&msm_dp_display->msm_dp_mode.drm_mode, adjusted_mode); - - msm_dp_display->msm_dp_mode.v_active_low =3D - !!(msm_dp_display->msm_dp_mode.drm_mode.flags & DRM_MODE_FLAG_NVSYNC); - - msm_dp_display->msm_dp_mode.h_active_low =3D - !!(msm_dp_display->msm_dp_mode.drm_mode.flags & DRM_MODE_FLAG_NHSYNC); - - msm_dp_display->msm_dp_mode.out_fmt_is_yuv_420 =3D - drm_mode_is_420_only(&dp->connector->display_info, adjusted_mode) && - msm_dp_panel->vsc_sdp_supported; - - /* populate wide_bus_support to different layers */ - msm_dp_display->ctrl->wide_bus_en =3D - msm_dp_display->msm_dp_mode.out_fmt_is_yuv_420 ? false : msm_dp_display-= >wide_bus_supported; -} - void msm_dp_bridge_hpd_enable(struct drm_bridge *bridge) { struct msm_dp_bridge *msm_dp_bridge =3D to_dp_bridge(bridge); diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_dr= m.c index b659d22f5f28..6ac5bac903d9 100644 --- a/drivers/gpu/drm/msm/dp/dp_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_drm.c @@ -56,7 +56,6 @@ static const struct drm_bridge_funcs msm_dp_bridge_ops = =3D { .atomic_enable =3D msm_dp_bridge_atomic_enable, .atomic_disable =3D msm_dp_bridge_atomic_disable, .atomic_post_disable =3D msm_dp_bridge_atomic_post_disable, - .mode_set =3D msm_dp_bridge_mode_set, .mode_valid =3D msm_dp_bridge_mode_valid, .get_modes =3D msm_dp_bridge_get_modes, .detect =3D msm_dp_bridge_detect, @@ -233,7 +232,6 @@ static const struct drm_bridge_funcs msm_edp_bridge_ops= =3D { .atomic_enable =3D msm_edp_bridge_atomic_enable, .atomic_disable =3D msm_edp_bridge_atomic_disable, .atomic_post_disable =3D msm_edp_bridge_atomic_post_disable, - .mode_set =3D msm_dp_bridge_mode_set, .mode_valid =3D msm_edp_bridge_mode_valid, .atomic_reset =3D drm_atomic_helper_bridge_reset, .atomic_duplicate_state =3D drm_atomic_helper_bridge_duplicate_state, diff --git a/drivers/gpu/drm/msm/dp/dp_drm.h b/drivers/gpu/drm/msm/dp/dp_dr= m.h index 041aa026ae2e..4bd788ea05d5 100644 --- a/drivers/gpu/drm/msm/dp/dp_drm.h +++ b/drivers/gpu/drm/msm/dp/dp_drm.h @@ -36,9 +36,6 @@ void msm_dp_bridge_atomic_post_disable(struct drm_bridge = *drm_bridge, enum drm_mode_status msm_dp_bridge_mode_valid(struct drm_bridge *bridge, const struct drm_display_info *info, const struct drm_display_mode *mode); -void msm_dp_bridge_mode_set(struct drm_bridge *drm_bridge, - const struct drm_display_mode *mode, - const struct drm_display_mode *adjusted_mode); void msm_dp_bridge_hpd_enable(struct drm_bridge *bridge); void msm_dp_bridge_hpd_disable(struct drm_bridge *bridge); void msm_dp_bridge_hpd_notify(struct drm_bridge *bridge, --=20 2.43.0 From nobody Mon Jun 8 04:25:37 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B21003D3D0E for ; Tue, 2 Jun 2026 09:11:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780391498; cv=none; b=VMER5lNs42JMQu95jyhpGBwsHYszlePOI9M1voiwfslKoLPmnm2mW0wn/qV9BjGD4aaL6fzrRbmwsV/HGq+05GyR5PzY66m/axpGG2ueSo2B1LohAnmaAdWGazPBdzt/xZ2XOKDpqeqjFkdB/fJ4zaCZDqN+LFxjC7fYmucnPQI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780391498; c=relaxed/simple; bh=utX2rWcnEK7sp26OqAqarcDBJ0uE50FzNeV/RPRB27I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=HAjtvTptcAmDdwqT18ws0jYozT7GfP+isr6c5q1HRSYTyBcKXCMGuQuYD1abddPEzfvVgOOwOYKpqXzlaI4tk7zLDnHY5RaDqaTElthbTPIjMYQ0iowfDpkFPk00XIU8zeR6VkR09f9rNz2VkX1XbK9PdYQzIyPuQ+c9Aj2f+nU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=NhQ+nnwF; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=N+ocnsdk; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="NhQ+nnwF"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="N+ocnsdk" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 65245gHF2691969 for ; Tue, 2 Jun 2026 09:11:37 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= gsb2m0YYMxi0oazQhslfYqgxjuHbp4QxtyHnC/SdYhY=; b=NhQ+nnwFQIqLvsxK usM8NbLj3GXXjVo4WCpjg0VtXp6DyrpbRjRjtqzFR5HD0J0TiCOiyr1LjeS4tK+n g/Ia/ZNvBh4qkVaYkgfU+nzH72IDBZZ7FwCZh74q0cvyL4rN5xLYb3B6Z1FytBK3 hRwCQGtoQjD2NLeV6i8dmg/5uOOkaxEXSaE0yJk2bJxnBfFyalolAbFFvATM4u+7 LP2sq846VdAkUYYme4Xc+Y8xrJIWoAXorNuu6yj5plyWkT5qSB8PYTYzQH4U3LVP gwAOE1EeUw3dFHHkhZvqz/ClPvjDx00ccsOa0UFZoZ/v3SRyAiFxQ8NPdWlMbVsm JzkZCQ== Received: from mail-qt1-f198.google.com (mail-qt1-f198.google.com [209.85.160.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ehqumh6e5-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 02 Jun 2026 09:11:37 +0000 (GMT) Received: by mail-qt1-f198.google.com with SMTP id d75a77b69052e-516d13328dcso225032351cf.1 for ; Tue, 02 Jun 2026 02:11:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1780391496; x=1780996296; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=gsb2m0YYMxi0oazQhslfYqgxjuHbp4QxtyHnC/SdYhY=; b=N+ocnsdkedZvhwMsYMfvKk1gIeaVgVp/o+LM7Ijp0qZQEoCNwekEiU7eLiwL0HhRMS CKEgChT8A11+MXe7PY+jrXgx/iDQyUirfjkw6pYSjYerMKVdkp/Mqp+kw2Plp3s+WsBk bGHBvTHfLvcj5ZI4ajeF8GQHz1rETC2h33nycLSvjwiP//UDErxlByqUfK661zgAlmKQ 4StqH30nzcWjB6w8T7s8CzFOSBox267bTUvf0ggXna8u6IUZH/g8hlwGeW3gn154Urpu UuE+Da1Dj9KbWUE92ZCl320ytXczieo7LuhE2mRrAplzSY95fQebLFN7IvFaImLGqpyB 0cbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1780391496; x=1780996296; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=gsb2m0YYMxi0oazQhslfYqgxjuHbp4QxtyHnC/SdYhY=; b=o2ztxzosxRHeJCT9ALXK7H2LH7ZjNbkQu/msUcFpdaPO1TVMnAnd3scTiMTI40VTfi i8XZ6GMkLSqkRRS/1o1EdK9ZefP68zYDix9/O1uhrtolobPj6mSwf1TylKPxvnXTIlqb GeCBCcRHsQ7kUt/ZrcLgLMcXWZfbhXs0b0g0ZoxNJMYx5dAEt5pBlXQCljQ2LMSYuz8r bPMIbo9QMZ2HjKo9PSbqvEEPb9lmQtcIgNWzk7X1IR1M91LdMN1CqK3Vud57CTlVk0aw yjhHzYM2uZr6Vvw94ik++pRyoMsS0LJipULuXW4UsItZE/hIjGelpTvCivyg7wdXhBmh 80tw== X-Forwarded-Encrypted: i=1; AFNElJ8j8okyKRKtuIpCxHdcB5twxQcLl417vxzYRRVS8YIE4Jhfmoz1cRdp0rTBtVbQFAP1o3AGnnsAE7QMfqk=@vger.kernel.org X-Gm-Message-State: AOJu0YyeQZIndgojodzfW7kxEaqx/YlPHtxb8C6dmSfvyjO7b2hRrN7c o5QizpHHWqOTITENQosGsxO7Pvv61tSvybQ9uktI3aDawXg+zb21r/tJ48wmNmyyNHve+xDGMIz J9SBg88e9iBgrWe2ItNHaOPBWynK4Y0Y3xhuezJn3uHqRdW5EdcC5+ar5fd/jnNc4P7okJCGxLv hv6Q== X-Gm-Gg: Acq92OGfWZB2C+dorCt457IKOKX7Y7G0IOLVe2w0wjpOFx8GoMX1ELCX3oIWXJzClBz YPC6mWV6x8TF7WVbIKLGG2osbg9lJOqFYRJ0pA2z6buB6cfGr55KJ4WRghJfVbb+3vKHWt4TVAl dsImy6vvgkjUheVDDcVgZPdAkEfY/E38XumRQgeem/lT50eohx/bbQT5Jb8FhwjrOaZeDsTfX6i yagxhUqPJl/sjvmi+R30ynhMIoFhDZB70uuziBH3f792I68zcpkX1Ru7nBQKnxSOr+RQoXtJQv2 EyQvEGjqVYq8qwq7yrFRp/y6IhWZBYHtMkFyg8OB/2V7caTxv59uQcD/++fVILBRXyXLe8Eis2a qZVdfk0XJE/cuUCsaBWFsCBMNS/Eo6nMYps2ei05Q8xaDewwLx9MWhIqVOCAdB+3DhT8nWspXZb 4ecF8i7mWBquLkwDqUrQ== X-Received: by 2002:a05:622a:1802:b0:516:d84a:9f54 with SMTP id d75a77b69052e-5173a92542dmr191551891cf.38.1780391495870; Tue, 02 Jun 2026 02:11:35 -0700 (PDT) X-Received: by 2002:a05:622a:1802:b0:516:d84a:9f54 with SMTP id d75a77b69052e-5173a92542dmr191551491cf.38.1780391495356; Tue, 02 Jun 2026 02:11:35 -0700 (PDT) Received: from yongmou2.ap.qualcomm.com (Global_NAT1_IAD_FW.qualcomm.com. [129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-51768c76e53sm12480851cf.4.2026.06.02.02.11.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 02:11:35 -0700 (PDT) From: Yongxing Mou Date: Tue, 02 Jun 2026 17:11:15 +0800 Subject: [PATCH v6 03/15] drm/msm/dp: move mode setup into msm_dp_panel_init_panel_info() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260602-dp_mstclean-v6-3-2c17ff40a9b2@oss.qualcomm.com> References: <20260602-dp_mstclean-v6-0-2c17ff40a9b2@oss.qualcomm.com> In-Reply-To: <20260602-dp_mstclean-v6-0-2c17ff40a9b2@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Dmitry Baryshkov X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780391476; l=4086; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=utX2rWcnEK7sp26OqAqarcDBJ0uE50FzNeV/RPRB27I=; b=ag5SVemMbeu4yqDiCnBBxzstPdazchSBZyEVVnFxjr7GQDKrJBa+ZSo/vkMKzp4XCF+WVC/Es 9Onj1rVceKHA+PvOr+gcCfs9ZoABWs6BqlU59zD+QW9fHZGn0M09lev X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjAyMDA4NiBTYWx0ZWRfX9K2tDKCCshYW mgTcjuNGJWzWx3/Fk9UFV0B8Cp2q53JApeXBVeB5jwQ+eZjKbNpDeaRRL90Fi1UIqM2jmFdg3YI 0tZgJF1LT1QYnCI+xH4L0m66Y08FP8/RZzBFyZsHv/KzGTNXeu7qahmXqidEwLnzRUq0reAu10h AV+a56TlDsmwdQIP+8LOYZG711BKR/HBVZ13hkJIfERVoC5GUSy8Xlcq/xRK5DGCU2s7foySDnP CZCiU/xfvCoUWzQiy5Mp1ZCUNLz8Fu/AOHYkGjHMMlY02lEiZVE3u3le27d+C37Akc4Ho3JcrGs oSJEojZ8Cj/7TJJxSvB1iH+ULmEQewV5Ow69eB2caYpt/JjhUU7gym5WWkLxov6m0do5ScwQ5El oxvvICVh3vR5yLFggDtGHezjM/rng/sf1AxuQdB2zsD/DLu/7rc4FDxwwYMpnwwgmdN64yO37Rz y0nEDUOANRKQgl6fxlA== X-Proofpoint-ORIG-GUID: rv24SAMZo2mmojKOpayRsgYa_9Jy675C X-Proofpoint-GUID: rv24SAMZo2mmojKOpayRsgYa_9Jy675C X-Authority-Analysis: v=2.4 cv=Rrv16imK c=1 sm=1 tr=0 ts=6a1e9e49 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=RRF978PcF5p4qF5CYGQA:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-01_07,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 spamscore=0 suspectscore=0 impostorscore=0 phishscore=0 priorityscore=1501 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606020086 The display layer directly assigns msm_dp_panel mode fields (bpp, sync polarity, yuv420 flag) instead of letting the panel manage its own state. Pass adjusted_mode and bpp as parameters to msm_dp_panel_init_panel_info() and move the assignments inside it. Suggested-by: Dmitry Baryshkov Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_display.c | 11 +---------- drivers/gpu/drm/msm/dp/dp_panel.c | 18 +++++++++++++++--- drivers/gpu/drm/msm/dp/dp_panel.h | 4 +++- 3 files changed, 19 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 181d238addfc..f33c754b83c3 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -604,21 +604,12 @@ static int msm_dp_display_set_mode(struct msm_dp *msm= _dp_display, =20 dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 - drm_mode_copy(&msm_dp_panel->msm_dp_mode.drm_mode, adjusted_mode); if (msm_dp_display_check_video_test(msm_dp_display)) bpp =3D msm_dp_display_get_test_bpp(msm_dp_display); else bpp =3D msm_dp_panel->connector->display_info.bpc * 3; =20 - msm_dp_panel->msm_dp_mode.bpp =3D bpp ? bpp : 24; /* Default bpp */ - msm_dp_panel->msm_dp_mode.v_active_low =3D - !!(adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC); - msm_dp_panel->msm_dp_mode.h_active_low =3D - !!(adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC); - msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420 =3D - drm_mode_is_420_only(&msm_dp_panel->connector->display_info, adjusted_mo= de) && - msm_dp_panel->vsc_sdp_supported; - msm_dp_panel_init_panel_info(msm_dp_panel); + msm_dp_panel_init_panel_info(msm_dp_panel, adjusted_mode, bpp ? bpp : 24); =20 /* populate wide_bus_support to different layers */ dp->ctrl->wide_bus_en =3D diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_= panel.c index bde4a772d22c..e76dad0f6663 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -647,15 +647,27 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_= dp_panel, bool wide_bus_en) return 0; } =20 -int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel) +int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel, + const struct drm_display_mode *adjusted_mode, + u32 bpp) { struct drm_display_mode *drm_mode; struct msm_dp_panel_private *panel; =20 - drm_mode =3D &msm_dp_panel->msm_dp_mode.drm_mode; - panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_= panel); =20 + drm_mode_copy(&msm_dp_panel->msm_dp_mode.drm_mode, adjusted_mode); + msm_dp_panel->msm_dp_mode.bpp =3D bpp; + msm_dp_panel->msm_dp_mode.v_active_low =3D + !!(adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC); + msm_dp_panel->msm_dp_mode.h_active_low =3D + !!(adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC); + msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420 =3D + drm_mode_is_420_only(&msm_dp_panel->connector->display_info, adjusted_mo= de) && + msm_dp_panel->vsc_sdp_supported; + + drm_mode =3D &msm_dp_panel->msm_dp_mode.drm_mode; + /* * print resolution info as this is a result * of user initiated action of cable connection diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_= panel.h index 53b7b4463551..4519ac374220 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -43,7 +43,9 @@ struct msm_dp_panel { u32 max_bw_code; }; =20 -int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel); +int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel, + const struct drm_display_mode *adjusted_mode, + u32 bpp); int msm_dp_panel_deinit(struct msm_dp_panel *msm_dp_panel); int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_b= us_en); int msm_dp_panel_read_link_caps(struct msm_dp_panel *msm_dp_panel, --=20 2.43.0 From nobody Mon Jun 8 04:25:37 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 350963D410E for ; Tue, 2 Jun 2026 09:11:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780391503; cv=none; b=qVJU6/DywQzUQLV4aVLlP7LTOqkhVsillkksw4veeEFkMtWsJuz+lEVZhGhQwdBmBnJB8vA/XSPolluk2EfKX2GeU1gmUldJbXIf8TmX1wXkepa8FKsaXApNqvKkfvvYDsEzfsFERTcCp3+CP1Mz+BXa8BqwQmxzxjDl70CHwdE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780391503; c=relaxed/simple; bh=z27Brjfd33j73HBw/hhLe9oIAiCr/9OyTLQ9EZGX168=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CUIzBjCcZYW6oNFkpDyEO1CJeCftQTfswtDD8dA4rdmXSJk3sH3xo/8lQoP+acK6pRId4QcAFE85cFFtjABG+/EKJQktG1i1kwrgpLN8GWH4Lm6vT+HLpM0TzgIOoj990y2zggJ5xnYvA12jpYEaevIcCoRCdEvH+cdkO8pUtjg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=EzxHiug/; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=CQ/sKWcM; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="EzxHiug/"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="CQ/sKWcM" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 6525tZsf4012485 for ; Tue, 2 Jun 2026 09:11:41 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= TUh1BC9Oa2lMbBLcFslL+DmIKNezCTsWlDxQwL1V7Js=; b=EzxHiug/T2yqpblh T6Nik2VYn7E+V6F3Ea9nIb7z/K0HRPuf6J2A53ZgNESkuwh+LQ9DAcE6TqyIFlxR vmp5ySgaT+eAzo3Sw2u2fSlX4j3lwnPhYs4cWmYPw+6S7Tz8fu+j7HaD/SIfQrvp pzIxUJGkrL9a8U18fRV2qKW5FGjNoOngjNdq1Wi2NmG9mx2KmGqgP6JTYLgCMrgh /kFNuR8f9NL9N18LCoUwXBc30Q3l7UxTfJ+LVHWPjERDB/TXPNweFKDjmKQ5Hkc/ Ng9z0YEY+S3C9d8LAlYmssp466uVxzn509T/CnzqAQeVaPzkLkhi1CTiH7VvbFDX 0D/WIA== Received: from mail-qt1-f197.google.com (mail-qt1-f197.google.com [209.85.160.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ehsf4gt9h-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 02 Jun 2026 09:11:41 +0000 (GMT) Received: by mail-qt1-f197.google.com with SMTP id d75a77b69052e-5175bf22b1bso20848941cf.3 for ; Tue, 02 Jun 2026 02:11:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1780391500; x=1780996300; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=TUh1BC9Oa2lMbBLcFslL+DmIKNezCTsWlDxQwL1V7Js=; b=CQ/sKWcMhoiBD2ZxeofF9vzQeDkLb9rz7xDf0k2JN2yCjKkKV2+dZwueuGt7l0cdLR T7kAvJkprGgazZA9iP0plZWaAK3JSU9DdYpJ9M58jL3Io/to3uj3Mmnes59X8Eqot0Qv Ul2AmsN0RcYruNXm/TgjdzsgYPk3YW4vEMsrclBXq68noYqXC1U2+KvvzLkaHJ8BXwGg eRydt6ofDUBA8HwBaT9bRqMASRI+TV3D1bTKjNivATod7I/F6dwJjsG9Nhvaxrv7CuQ5 5GEMjMKdogZPbqGiW7LICrh2Ym4XGWoZ5MQwYSAYOBcDw8ZM6vCx/PZHfhwKQfbn10z4 eY3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1780391500; x=1780996300; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=TUh1BC9Oa2lMbBLcFslL+DmIKNezCTsWlDxQwL1V7Js=; b=jM4YuWmuH8MbwdJhEBImQOfqn78jSsItVqGfIUye5qgHMohxSDzRbUvf7NRZEWk+8D wMO0Qk4TFh/aZzf3cB6u1Weqc7K9oERL1BSyv4r2knoyIPFHb4UiEYf+J9JD5Lh+weVT 2dnsP23XYFt05A4rmV53gkXJwZ1XjUEHQ9g2QO286LT2vJW6OZXOGR9bOo7FW7acUbld YvxUiWN0+t31Kwz4BJcNIzuq9HNoYItqBfrmi2NfsH2gHWPyHgn/9UXhYiHVxKEm14Eg EnV2rzgfIZuueTM43zn+AcZezSsHgGbTD0fQRhWnHN//tWkiiYbjQMthczf5dt7JJokY M9ig== X-Forwarded-Encrypted: i=1; AFNElJ/c9AnhBFDa43GbJIT4xUxooQlmuVJxYIpXhuc0CdGtaG3g+1w7uAlO7C9xuTJmqq+Gzo054/fWa8OOpBU=@vger.kernel.org X-Gm-Message-State: AOJu0YyYK2jI2buGhCNu2cmCdRZV+iiTMtgdAyiXV5RmMtBE/MO7ozKk zj+tvZmdUMmN1aXxO5cneIM131s7709FYw0BXW1p3oKoHcOOoV423v6Y3U3U2UPYsgVa26EZpeg YT3zufvhpq/XNT5qWz/u9S6fTNErDXyrI9ZBfcapVHSi1Ut+ws2nLkswSUApGv3vpdcc= X-Gm-Gg: Acq92OEILUKfzkZyRb9F1dpjJlptASx8rzEibRMrRHm534LcAT4NcjJmuVrkUdnXb7l ivliKwlUJdpEI0a3/dCUbojj9tW1edj7IU8cDAhVlJvtLqWgI59FMBariw1VIyBYGqRghgbarX8 LTQ1bahLVz4NTiC3ha0pTyuuf68EjmyWDS0DGfxUCUymPeJiXZpjKye7c3LyQxb3QIy2+yaCRV2 LnyHK0yBlfYsRmzT6UfuFXdmzJ2kE1s9A/TlbK0SGLz0NkKdE5akKSs8pPd0mxzbHV5OWd8xD0h i9NV6aFLooDUL3CrIKdHNPWQDqTeqtpKywmXxoFCMPoCaWcauwzhBIsGsw3IyGteOFRMnkcwc5M bxlWrBEmBYhWRmE4cZfeZZi4GH0oLKMSJ79HPHBynmjXyOdyfxYv90c2+JsZc22JZwsK000ELT3 cE/t4QaRaPHnMZtokF4Q== X-Received: by 2002:a05:622a:5c16:b0:516:d955:ea6 with SMTP id d75a77b69052e-5173a67b6d9mr228727221cf.14.1780391500516; Tue, 02 Jun 2026 02:11:40 -0700 (PDT) X-Received: by 2002:a05:622a:5c16:b0:516:d955:ea6 with SMTP id d75a77b69052e-5173a67b6d9mr228726891cf.14.1780391500074; Tue, 02 Jun 2026 02:11:40 -0700 (PDT) Received: from yongmou2.ap.qualcomm.com (Global_NAT1_IAD_FW.qualcomm.com. [129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-51768c76e53sm12480851cf.4.2026.06.02.02.11.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 02:11:39 -0700 (PDT) From: Yongxing Mou Date: Tue, 02 Jun 2026 17:11:16 +0800 Subject: [PATCH v6 04/15] drm/msm/dp: split msm_dp_ctrl_config_ctrl() into link parts and stream parts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260602-dp_mstclean-v6-4-2c17ff40a9b2@oss.qualcomm.com> References: <20260602-dp_mstclean-v6-0-2c17ff40a9b2@oss.qualcomm.com> In-Reply-To: <20260602-dp_mstclean-v6-0-2c17ff40a9b2@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780391476; l=3766; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=z27Brjfd33j73HBw/hhLe9oIAiCr/9OyTLQ9EZGX168=; b=uh/2vuvwZi4NPWvxpb0HLAMWnkDC3My/HP9tdgGNJh4egce6glFrjfSqF6g0pTqElE5gtP5J4 iyXlaYzrJ2UAeVeEOMv+hP2Hf/EGB2wils/8eUs9M1JQyfosEXeYeqG X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjAyMDA4NiBTYWx0ZWRfX/4MwuHM84pFK 0YwEZ3351O3WMwIrvumvIXFyHKo5mbIIfg5lzQLI/6+IRWMGu49xZT0sJdZUqL3OliwTpCAKJgF hvQIL6bFatvAefhTjRcKSR3eR+P7Qn2KDMN1fz7deqf+dOZxsMDfYjYP/AZf20l8kYnhQpO4/5P NBsDN3J73EPlcFbZsOysSbHCginicwhz2t465gtaIQdR77BaLIHMjxsyZbMqkyHDerY/hKQ8boV TN3aqxQybQVAk1xjYjZ8MkqxIUtGC2TK0KnUM7oURwUTgpwNmOZWxQJyEKcvu1vXzn9OP1YLRh9 Tba9gsZtRtvqbFbCZBOQZ9XlRLbHOCWf8Ruuw6r1uHrgrMznHsfJAFeCLK5d/tpHcrfnwdAqUgE mtbZI6rpop25ektG2MCn4fUHVkWZV3kzoY2AF1Q4fOmx9DtpLneBVMxY9NKHrgWHyMfFxKeKF9K lTy4VUR3YBZ6g63JPZw== X-Proofpoint-GUID: 1wWvEV-Oy4beiptp8N5CXZen3jc4Ap5l X-Authority-Analysis: v=2.4 cv=AJZ7LEvz c=1 sm=1 tr=0 ts=6a1e9e4d cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=N4WGanfLxQUAwF0MUGsA:9 a=QEXdDO2ut3YA:10 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-ORIG-GUID: 1wWvEV-Oy4beiptp8N5CXZen3jc4Ap5l X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-01_07,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 suspectscore=0 malwarescore=0 phishscore=0 bulkscore=0 impostorscore=0 clxscore=1015 lowpriorityscore=0 spamscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606020086 The DP_CONFIGURATION_CTRL register contains both link-level and stream-specific fields. Currently, msm_dp_ctrl_config_ctrl() configures all of them together. Separate the configuration into link parts and stream parts to support MST. Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 46 +++++++++++++++++++++++++++---------= ---- 1 file changed, 31 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 86ef8c89ad44..ed2ba47881fd 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -388,26 +388,44 @@ void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp= _ctrl) drm_dbg_dp(ctrl->drm_dev, "mainlink off\n"); } =20 -static void msm_dp_ctrl_config_ctrl(struct msm_dp_ctrl_private *ctrl) +static void msm_dp_ctrl_config_ctrl_streams(struct msm_dp_ctrl_private *ct= rl, + struct msm_dp_panel *msm_dp_panel) { u32 config =3D 0, tbd; + + /* + * RMW: Called from atomic_enable(). Serialized by the DRM atomic framewo= rk. + */ + config =3D msm_dp_read_link(ctrl, REG_DP_CONFIGURATION_CTRL); + + if (msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420) + config |=3D DP_CONFIGURATION_CTRL_RGB_YUV; /* YUV420 */ + + tbd =3D msm_dp_link_get_test_bits_depth(ctrl->link, + msm_dp_panel->msm_dp_mode.bpp); + + config |=3D tbd << DP_CONFIGURATION_CTRL_BPC_SHIFT; + + if (msm_dp_panel->psr_cap.version) + config |=3D DP_CONFIGURATION_CTRL_SEND_VSC; + + drm_dbg_dp(ctrl->drm_dev, "stream DP_CONFIGURATION_CTRL=3D0x%x\n", config= ); + + msm_dp_write_link(ctrl, REG_DP_CONFIGURATION_CTRL, config); +} + +static void msm_dp_ctrl_config_ctrl_link(struct msm_dp_ctrl_private *ctrl) +{ + u32 config =3D 0; const u8 *dpcd =3D ctrl->panel->dpcd; =20 /* Default-> LSCLK DIV: 1/4 LCLK */ config |=3D (2 << DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT); =20 - if (ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420) - config |=3D DP_CONFIGURATION_CTRL_RGB_YUV; /* YUV420 */ - /* Scrambler reset enable */ if (drm_dp_alternate_scrambler_reset_cap(dpcd)) config |=3D DP_CONFIGURATION_CTRL_ASSR; =20 - tbd =3D msm_dp_link_get_test_bits_depth(ctrl->link, - ctrl->panel->msm_dp_mode.bpp); - - config |=3D tbd << DP_CONFIGURATION_CTRL_BPC_SHIFT; - /* Num of Lanes */ config |=3D ((ctrl->link->link_params.num_lanes - 1) << DP_CONFIGURATION_CTRL_NUM_OF_LANES_SHIFT); @@ -421,10 +439,7 @@ static void msm_dp_ctrl_config_ctrl(struct msm_dp_ctrl= _private *ctrl) config |=3D DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN; config |=3D DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK; =20 - if (ctrl->panel->psr_cap.version) - config |=3D DP_CONFIGURATION_CTRL_SEND_VSC; - - drm_dbg_dp(ctrl->drm_dev, "DP_CONFIGURATION_CTRL=3D0x%x\n", config); + drm_dbg_dp(ctrl->drm_dev, "link DP_CONFIGURATION_CTRL=3D0x%x\n", config); =20 msm_dp_write_link(ctrl, REG_DP_CONFIGURATION_CTRL, config); } @@ -450,7 +465,8 @@ static void msm_dp_ctrl_configure_source_params(struct = msm_dp_ctrl_private *ctrl msm_dp_ctrl_lane_mapping(ctrl); msm_dp_setup_peripheral_flush(ctrl); =20 - msm_dp_ctrl_config_ctrl(ctrl); + msm_dp_ctrl_config_ctrl_link(ctrl); + msm_dp_ctrl_config_ctrl_streams(ctrl, ctrl->panel); =20 test_bits_depth =3D msm_dp_link_get_test_bits_depth(ctrl->link, ctrl->pan= el->msm_dp_mode.bpp); colorimetry_cfg =3D msm_dp_link_get_colorimetry_config(ctrl->link); @@ -1628,7 +1644,7 @@ static int msm_dp_ctrl_link_train(struct msm_dp_ctrl_= private *ctrl, u8 assr; struct msm_dp_link_info link_info =3D {0}; =20 - msm_dp_ctrl_config_ctrl(ctrl); + msm_dp_ctrl_config_ctrl_link(ctrl); =20 link_info.num_lanes =3D ctrl->link->link_params.num_lanes; link_info.rate =3D ctrl->link->link_params.rate; --=20 2.43.0 From nobody Mon Jun 8 04:25:37 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 16EFA3CBE73 for ; Tue, 2 Jun 2026 09:11:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780391508; cv=none; b=IOYz2qW/YprthjIFhwZFRfeZ1FiDfn0Z43fYzoPHaSIV33RT/DO9vqjKNeqIh8oaljamsXJ4+fdD1mDg9ZC6NIkHOi+Eya9wcb50YFCEI/cdVE1QqUIFueeudlTTmFx4OdkUVvL5ALFGonxeI13I4FOjXamsKuBw8nHFgBt7cac= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780391508; c=relaxed/simple; bh=k2Fff3upCougTurRhx1qk32jaQDI5eLSE+rUossKmgQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=T8i8omwMlu3VKSPXBzLoLIv5FIDybxHgpg758NT7W2x4wfExv1UYAJKcTUmObsx3Vd6t6pl4hpkR0MWg922kch1ulxKNybHeLL/P28DejIccJThri8aw5LyDTrLi2IapvPWwAkRnQmhUbJRBDSh1ovg4bKJNEtlR/k5IiFuFDJY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=JUufF27A; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=inWsgx1V; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="JUufF27A"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="inWsgx1V" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 6525tokT1855124 for ; Tue, 2 Jun 2026 09:11:46 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= w64aJR4GsiijIIC+qw1V7Ljp4DhfTK7YqGC8ys2CQuk=; b=JUufF27AjkSwlUqw Insnk7c+Z+YHrWCvAUts5brdKPfLi7qWo9keD74aDxhLFgg7sOpsIO+qKHt5WYhd 5J2P4W2IJpiR98MjtgazuuHkCCoY8dg9p5y8Rfq/Qye6D1H1OzO8JJKOloRAI9wO rvaCZnnGLtV+8wOJm5sksgEmMeZz1B4B7pbU04cCLGKv1CbPcSFugsUcylk+u603 4TwhqbUQooCWlT2zH8iC/6Of6dpWIVLGx57+uwQEBkl7bBPlRW7LYZN5q8WCerlm VCMDqh7IVNrO7Wq2RHklDgIzGwBKzZ+r+gMl8akkwX8aEAd/QPltqaOxfIkygtk7 Rwnk3A== Received: from mail-qt1-f199.google.com (mail-qt1-f199.google.com [209.85.160.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ehsf78svg-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 02 Jun 2026 09:11:46 +0000 (GMT) Received: by mail-qt1-f199.google.com with SMTP id d75a77b69052e-5175842d1abso38453151cf.1 for ; Tue, 02 Jun 2026 02:11:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1780391505; x=1780996305; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=w64aJR4GsiijIIC+qw1V7Ljp4DhfTK7YqGC8ys2CQuk=; b=inWsgx1VHk2ZAHZ+x9EhHUD65EDzcRHsi6EEfrq4+JhtvWUB4Yk0jeaVBzPyAy9B0W t3A1Zduf1sdyLIwSocKPBo6KorV0qgmt+q7c45UfyceR1JR1yTOyoR3Gbc7Xct8ruL4w MuPO6zeqsCNl9R6O00mtdtEryI5tLqMhvcKaGupymTl7pM9LC/u0EYdQdX7mAHLGbZ7Z gTDTXmlClR8i7Xcdw+Q/VwD07zvr5xD194gDWJ9xWwGJtOfnHdKQN0CNkN6k4Tnpo2YT s8J11mywr0yzYywoejXKxMSKWSd2m1hovZ8zoKK3oZ+TWqBqQTKNFgbI6TQurPorVdqC yIMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1780391505; x=1780996305; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=w64aJR4GsiijIIC+qw1V7Ljp4DhfTK7YqGC8ys2CQuk=; b=n827vmRJLqbFltkNSypHHiewhFahYl/tSJoMTm7CSdFDEXiZPdEjZvLk5vGbsi3s95 F4E5ym1mxZtd31qvVJmHrhDDcpfzKHTUaj0A3SKGwYsfbq/rzT+zqD7DN8196uqW1GMr v4U3fWWMOpnHw6Dt0+deuT/Jgq/fu78GHYdxI8IUgfofZ98DuJhQPJ0eNYBybMGEewPU 6xWRnXx0q4gJh9PG6Ytj9yt4iBmhGeH7XZ7ytoLqj/wh69oMr02QavDZPWbHYSkvOUix +BJsfQOSA2f+IhUUzIScphB56JZev554p8PyFz7tM22mh68c6EQ137ngON8qPRqSiQt2 +c/g== X-Forwarded-Encrypted: i=1; AFNElJ9OmNZUuzAExWS6fZK2LtbkdKfXtvtfPaFhOU07W7OUcNt0iQynTO4U0bJkmxjKJPLSEpAOquw5zB9lUT8=@vger.kernel.org X-Gm-Message-State: AOJu0Ywg2CJuYOz2Fesmvxbr+rUXGK3FoJC5hvS2SDTguKkIa8QDD0bf WIbiqwTS+I51djOJNakAnuNT1OsCHCN/RTTSt/rU0ldF+kDTW2M1oAAeSecWy4+/kgoEPcCvA4T PTa4RHEG0Aorlz/pcoCa/Swx46oTsF+iD26fcE6VYPFtdfikboypgl186+XEndNsU+QY= X-Gm-Gg: Acq92OF+hyWbOejhejhfGVMyypVrJFuYBKn0ocUzKx9f0Pd9vMfJ15DnTPqrXze4XdN KjPdVwCluKIE4CFFEYVS7HcilbV9ZfXMXeLGPG8Kgn3itehPxEPx+Yy+RbynqCwjv1OuuuZVLSd GwreVuoZYPRh7fbQeo4VClbu+U4bE0baBeCT1i0SSUe8YZgdffbRuQ6PSR8il1Fr79EDyxkcDsZ HTF6HcIl7xsoegpGF5MG3J7P09OkxH4U3Cj8hrmKbHQy1PvikqRY7CPSl8cm8lZnc14gp4Lf6lA yjjD26mcHJ9jfJsKGh5vAW3t+FdjxmxUQCSY79w2F5RbI8qsFHmMKGQpXOxbh32S95OmrKcoWpV QykJHTPlaI0MZc0mmTIcftAJB2W7kV1KKdI9gK4TGh/9bp3SRyBGGiP4m9Xpuo82c2A21D0Hyuw hHwN3Bacjk3Dv2E8C/LQ== X-Received: by 2002:a05:622a:1812:b0:50f:c9a2:1643 with SMTP id d75a77b69052e-517662835efmr36172971cf.11.1780391505063; Tue, 02 Jun 2026 02:11:45 -0700 (PDT) X-Received: by 2002:a05:622a:1812:b0:50f:c9a2:1643 with SMTP id d75a77b69052e-517662835efmr36172701cf.11.1780391504654; Tue, 02 Jun 2026 02:11:44 -0700 (PDT) Received: from yongmou2.ap.qualcomm.com (Global_NAT1_IAD_FW.qualcomm.com. [129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-51768c76e53sm12480851cf.4.2026.06.02.02.11.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 02:11:44 -0700 (PDT) From: Yongxing Mou Date: Tue, 02 Jun 2026 17:11:17 +0800 Subject: [PATCH v6 05/15] drm/msm/dp: extract MISC1_MISC0 configuration into a separate function Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260602-dp_mstclean-v6-5-2c17ff40a9b2@oss.qualcomm.com> References: <20260602-dp_mstclean-v6-0-2c17ff40a9b2@oss.qualcomm.com> In-Reply-To: <20260602-dp_mstclean-v6-0-2c17ff40a9b2@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Dmitry Baryshkov X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780391476; l=2097; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=k2Fff3upCougTurRhx1qk32jaQDI5eLSE+rUossKmgQ=; b=i05DXxqApSBHDn24Y/faO64tUx0fwhQhNrJN23hr3yxu0q6ThLoselo9pXKhvx2pg3MCF6Xpc uOM/uL5oVQKBuNBbQTbinDYz8cOaqbhcNVc6RquNhHROUM7d9+u9qWU X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Authority-Analysis: v=2.4 cv=WKRPmHsR c=1 sm=1 tr=0 ts=6a1e9e52 cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=TC1OlXllJ9dbkp4NpB8A:9 a=QEXdDO2ut3YA:10 a=kacYvNCVWA4VmyqE58fU:22 X-Proofpoint-GUID: EE6ccH6bBGDRkS3Hu-JYTk2g_P1H_ULl X-Proofpoint-ORIG-GUID: EE6ccH6bBGDRkS3Hu-JYTk2g_P1H_ULl X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjAyMDA4NiBTYWx0ZWRfX8BpZRRkx8p1d YcD3gt1BNvLclA/kCgm1vJ3H0NrZfevVO3sj2sscQZTATp1vVkUtweHlLnK4D/pI0r79KYUQoXC qjcAI5VbvBDwNAiJcnf2Bsrv3DzKp99eY+jSN/pcywP03y7VIp24W0CQECNRKWhfEKTWwBBXW9S R+B3vMixaC93XFJnsQjjB1KmSRBzNFG+eK//j+vKXac2sdgbPFAxL2tlR8a1mg3lpieCacdoQYh bk7EAz/8298Yp2Kk5XDL5h26gisYluCaYiMzEaZwASoMDjxippOt93pPoZ3bdleL/aOb9J2RiW8 x28zWIzHvnWXkgXgjFotvOSfDPOUlSRg+M3eHvAofq3O3QEsZ4HTSByMzJU4omNdWZLlSWhRdfJ j4i+WFT4+BUqeiEoJLYaLSvpn4y4oQqRnMCPu+t/+THUbexbp5q9FTeLzhxQHpTGmYhe5FwjIl+ cw1juZzi4bNnAW4RpnA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-01_07,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 suspectscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 phishscore=0 priorityscore=1501 clxscore=1015 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606020086 Refactor the MISC1_MISC0 register configuration into a standalone helper function to support MST. Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index ed2ba47881fd..71d45b2c4daf 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -458,17 +458,13 @@ static void msm_dp_ctrl_lane_mapping(struct msm_dp_ct= rl_private *ctrl) ln_mapping); } =20 -static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private= *ctrl) +static void msm_dp_ctrl_config_misc1_misc0(struct msm_dp_ctrl_private *ctr= l, + struct msm_dp_panel *msm_dp_panel) { u32 colorimetry_cfg, test_bits_depth, misc_val; =20 - msm_dp_ctrl_lane_mapping(ctrl); - msm_dp_setup_peripheral_flush(ctrl); - - msm_dp_ctrl_config_ctrl_link(ctrl); - msm_dp_ctrl_config_ctrl_streams(ctrl, ctrl->panel); - - test_bits_depth =3D msm_dp_link_get_test_bits_depth(ctrl->link, ctrl->pan= el->msm_dp_mode.bpp); + test_bits_depth =3D msm_dp_link_get_test_bits_depth(ctrl->link, + msm_dp_panel->msm_dp_mode.bpp); colorimetry_cfg =3D msm_dp_link_get_colorimetry_config(ctrl->link); =20 misc_val =3D msm_dp_read_link(ctrl, REG_DP_MISC1_MISC0); @@ -482,6 +478,17 @@ static void msm_dp_ctrl_configure_source_params(struct= msm_dp_ctrl_private *ctrl =20 drm_dbg_dp(ctrl->drm_dev, "misc settings =3D 0x%x\n", misc_val); msm_dp_write_link(ctrl, REG_DP_MISC1_MISC0, misc_val); +} + +static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private= *ctrl) +{ + msm_dp_ctrl_lane_mapping(ctrl); + msm_dp_setup_peripheral_flush(ctrl); + + msm_dp_ctrl_config_ctrl_link(ctrl); + msm_dp_ctrl_config_ctrl_streams(ctrl, ctrl->panel); + + msm_dp_ctrl_config_misc1_misc0(ctrl, ctrl->panel); =20 msm_dp_panel_timing_cfg(ctrl->panel, ctrl->msm_dp_ctrl.wide_bus_en); } --=20 2.43.0 From nobody Mon Jun 8 04:25:38 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 73BD73D47A1 for ; Tue, 2 Jun 2026 09:11:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780391513; cv=none; b=KI+12cuDgxZt5/QZcuRU3Fo4/k5HlOhfef2MVT07SGJyAPahg6oDppElcSyObafV5ORFbpfF3Dugs2dBIbPriQ9XlKBGMcGNhgMraR1EuYDloeyqKo4afgekAi+/VGcSVWRVY4FMQoBju4JkrOWKbGD8QigWR/Qa8eX8H3InIOs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780391513; c=relaxed/simple; bh=ixgmYJIVCgIesw8IPUX+/UcnW6cdOBjM+XPZmes1+Eo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YHd17TEEDOqlZQFU30NTbjiAwGVPRP7/J8VS7u1elbtIs4/wWfK/HLqkh2qI5ml6uDh9URRooBeHowvDU7l+DRv0L2HihSY1AkjS1hxUGC6jc2IWTG9ivAeEQZHdLt+g2sjyPLNoxTsy5IsHwWkc3nZpOc5CcWxzgaqkqOIZc58= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=nRB5h+VL; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=JFUlGSPt; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="nRB5h+VL"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="JFUlGSPt" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 6528WprO3430318 for ; Tue, 2 Jun 2026 09:11:50 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= IovUpKpDFwGWZaF4DLWER239PrNpT7oEBKFqXm1bx5A=; b=nRB5h+VLOnyb7b5H MzBxDkXq2aDo6Ver+IH7SW1QClrIB3SACFd4T9J+1+TZtZasYhREa4K7kS8OXacF /JiRFxZUq35P3Q/xIiEw5JQjAsZo/lyW28OL4eU0kxYyYfJMVQZOb3pgyEMAMuPu nK5NzkXQPz2SjTPsnZGXRrJSfrXFAx2F7VE5O6SLYd/r6Lnbk8caXOws+JYOH8ze x/H8u7QvIUWGcNDxXqnfzLqLf5v4S2JK+7FFImBMsMV3afIzbGbQTFlZTVts+m7l 7oc/6bxsubZ6Nw9d/3JGxxPrt7GyRT1hL2Yl5clhtIKAdx561giMHGbIZAb3i5/K FW5xLA== Received: from mail-qt1-f197.google.com (mail-qt1-f197.google.com [209.85.160.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ehn8mhq2u-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 02 Jun 2026 09:11:50 +0000 (GMT) Received: by mail-qt1-f197.google.com with SMTP id d75a77b69052e-51771d41426so4623941cf.2 for ; Tue, 02 Jun 2026 02:11:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1780391510; x=1780996310; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=IovUpKpDFwGWZaF4DLWER239PrNpT7oEBKFqXm1bx5A=; b=JFUlGSPtLDYE3RmjVCtEqRUNo+GNA/PkhlGFI47t+JIfmVHcRPp3jtm/c+XZB8wX5Q HFXxBqA+y3jpghNcjOgcI0Dw083JAl3QExdZIUrl4ESOnyR3JpExZpQDvCYXlmMMBhHt Du8J7yZJRMR5tJ6Wq5ShPfKSsJQZG/Noj9Bm7l9+6ki2aSAmlib61x6Vd4EVAuvbOKet yBxPx2QKk8UWpKRfzJvN2C0PplBiUulq+rAtiaxEztW5JFe8KiWbEhuwXYpw+b9kay7v QJXn4eR1Be03zff1Kt68hBx/NeQ++qF5aCp93tImifrTHR6M+f1DCjS6Ll6xLFfU9rCM vU4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1780391510; x=1780996310; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=IovUpKpDFwGWZaF4DLWER239PrNpT7oEBKFqXm1bx5A=; b=Xlv4e8XgB25pnumbHIvgZEVc4OG3BPYpnNUaAiM2aFjURRvu77IISpc9xQAG9plx91 /TuCKl4QeMwrvl0w4z1FBr1q/pqAqND1TUzSnT4e+D0k2LNHptuoOay/Xj0FRBq81wI+ B9tAvXCrd2jS/bEFzA3iIsurHnjiQt+Wy5dCPdn6fSn/0Q4mJrEAi2/jj8JbEmYKhOFL 2nDy4W5Egoc3TdH0uXUH17Y2DuV0VEMywlgIGZQ+i9fRGhcGGiQzt6ijR+l/xXVHKm1V msQO62FDVJ2EMlQhP3sq+/EeRH4sUqMwf4H0GEVqulLKmEcGCN5VKsupgKGUup/GAWgd p/nw== X-Forwarded-Encrypted: i=1; AFNElJ+GX5tfxtDpga18Oa7h1xDUQIAbyeB24GGcE5kAzdcAsW5KI9Gu5ed7guDve83RsTAwUQrQgAUedWb5IdE=@vger.kernel.org X-Gm-Message-State: AOJu0YzlnPEHYCMUrMiAXkAqLrsbqHw8Q4zzcsjObauI7dmOtl7YVA+I jJlpRU1W2hR3DqsutUZpHdG+muUHzfY1L1rj9TqM5v3r7cRVgB7fHoMikv1il9ChuHatvmKuVYC 4g7DQG0p7EWApAhPiq7QWOHhtcdhT9HqDHXEjb4Vc9rEbNPxt70i1qBy7fnHSJuyewtg= X-Gm-Gg: Acq92OFjabepKbolfVJqA3ltBImMj6fvxah9mRJVSwb910nftBH2M7l4IQZdffA8Boy jIeEB2QGgin4U8KFszxw/wVIJoZgpGTHH3e338mKclpBYX5gdbRoMFAu8Smru2MZHH6cdwd9W7x zbrGQmW+nG1DGSBZxKjlrAdLAshoqgHlOUIvIwed3rZDHuOaxAmNZWsm3OR/sze/r4VZdNT4IOM mqIjDpeM8YLNQxhcbANaxW37RN7v2EQZekwXXvaXxPJmviqzUQ0VU+i7llAEpr3amEeTfeVhlP9 C6k9deE50hIHsmKvldTGr/pscdWTr9FueU1E2aKsLZ1DYHzW0fAeWhJGN0EfJ6rlujUE2nild6+ OuMNnJ1BR9pvzmyfjNc95+BavKb6P7T+fph6447WfBMZUx3z0U3bhj04rSchtgS7JMskInCDr/g VH/HFlzv6am7qG7eD3nw== X-Received: by 2002:a05:622a:5588:b0:516:d4b1:48cc with SMTP id d75a77b69052e-5173a5b4efbmr215685781cf.8.1780391509712; Tue, 02 Jun 2026 02:11:49 -0700 (PDT) X-Received: by 2002:a05:622a:5588:b0:516:d4b1:48cc with SMTP id d75a77b69052e-5173a5b4efbmr215685341cf.8.1780391509319; Tue, 02 Jun 2026 02:11:49 -0700 (PDT) Received: from yongmou2.ap.qualcomm.com (Global_NAT1_IAD_FW.qualcomm.com. [129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-51768c76e53sm12480851cf.4.2026.06.02.02.11.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 02:11:49 -0700 (PDT) From: Yongxing Mou Date: Tue, 02 Jun 2026 17:11:18 +0800 Subject: [PATCH v6 06/15] drm/msm/dp: split link setup from source params Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260602-dp_mstclean-v6-6-2c17ff40a9b2@oss.qualcomm.com> References: <20260602-dp_mstclean-v6-0-2c17ff40a9b2@oss.qualcomm.com> In-Reply-To: <20260602-dp_mstclean-v6-0-2c17ff40a9b2@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Dmitry Baryshkov X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780391476; l=1402; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=ixgmYJIVCgIesw8IPUX+/UcnW6cdOBjM+XPZmes1+Eo=; b=wQzA1NrqLbrqIbng1TSRR2q9hmwp+iEZEBvdcs8FrTVsSEdAZMPKBB4tatmzXucFn4wiG3Qc6 4279BVHj7IKCpFz2/1YLNZLLtl56qWVDUllMS4Cim1r5nPqnBWg2OO6 X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjAyMDA4NiBTYWx0ZWRfX9bqwuMWXir+t UJWGxvQHviI8M9RKCTyAFAvw6JNlPkC6rWHsmE3KOwBpe1zKxS1Zlvlly5lybYLVkw8U3oVtolA Y1d90l3QOiCa6l6+MWw4JE7Di6Dm6PTVfnkpfnKkuX+wG8euvaK96ahlHY7WfO7SnM2LwC5NF+c 7a7LBYDUcazTCaqt70hMTu/P6orAnxNynRZ3ozUYMJ2/n4ylXKpdeTF2sR+i0UKy8o2gUMKiyli JH0CHgi4t04C55ETNC1Ld9RKwR1+UQrbbOIrfJCmk6ui88SisnCO9sCB9AwMsW8Ube3s7ZYwu7k Ddk3yAMV15PmBoB5ZOAYFOoQRXaoUrVgw7387PzHkgl8IFstv3keySvn8NBL4cHPV4S6aatEO1p mW6FAcNO5YrIz5JA5YUipK6fFinIPMepZPVbpd7YZ+QNrfaO++WVdQcoz6M3gQJgTQDjG4TrM4q JYC+gQj8ioWpneTPyQg== X-Authority-Analysis: v=2.4 cv=d5nFDxjE c=1 sm=1 tr=0 ts=6a1e9e56 cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=saXSvH3Ee-fMY4W8qR0A:9 a=QEXdDO2ut3YA:10 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-ORIG-GUID: C-hzCGktyI3448MqhGOjgYMChaTLr0bC X-Proofpoint-GUID: C-hzCGktyI3448MqhGOjgYMChaTLr0bC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-01_07,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 malwarescore=0 clxscore=1015 adultscore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606020086 msm_dp_ctrl_configure_source_params() should only handle stream-related configuration. Move the link setup out of it so MST can program link and stream settings separately. Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 71d45b2c4daf..1c2eccec6ec6 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -482,10 +482,6 @@ static void msm_dp_ctrl_config_misc1_misc0(struct msm_= dp_ctrl_private *ctrl, =20 static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private= *ctrl) { - msm_dp_ctrl_lane_mapping(ctrl); - msm_dp_setup_peripheral_flush(ctrl); - - msm_dp_ctrl_config_ctrl_link(ctrl); msm_dp_ctrl_config_ctrl_streams(ctrl, ctrl->panel); =20 msm_dp_ctrl_config_misc1_misc0(ctrl, ctrl->panel); @@ -2551,6 +2547,10 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp= _ctrl, bool force_link_train */ reinit_completion(&ctrl->video_comp); =20 + msm_dp_ctrl_lane_mapping(ctrl); + msm_dp_setup_peripheral_flush(ctrl); + msm_dp_ctrl_config_ctrl_link(ctrl); + msm_dp_ctrl_configure_source_params(ctrl); =20 msm_dp_ctrl_config_msa(ctrl, --=20 2.43.0 From nobody Mon Jun 8 04:25:38 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9573D3CC7D1 for ; Tue, 2 Jun 2026 09:11:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780391518; cv=none; b=suhD3cvgC4gt47Y5Y7mgesoVTJLBFGPVGzBjllNYvrtjHVDC8yeDmMr1WdOZ6vxcCxnZwKxvK1zUiNO+XqZvvO8Ij70UBqyMvnxaIaVgV8eSlIATY4Cdur8iJd/RNViq8tGgL3+QOqoax5wZPQq7PLh5Mu9CEfsQW+l5T+a+FVQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780391518; c=relaxed/simple; bh=UaT/1/E05CYDg064KZ/+/vx3fX/KlDmWiJULn3OKuWU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mgetHflnKIjQaK0PAmg5E4HKaikA+uRrzrD7uA39j/p5EoZEATABmpV0FG8U6O2TW7DLWr3wbGrail5soEhJtA+qV5d/JAvSXK+LV+gPPruTDIWtCbAehubanQRruTMKcYds1GKMr1YvLqiBlOWOVjoyZq2AEBYJD6oCTs23+Vk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=YXY4wOTK; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=hNYAaSrB; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="YXY4wOTK"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="hNYAaSrB" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 6527gsnC1638562 for ; Tue, 2 Jun 2026 09:11:56 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= NaE5h732hDoKExFZJ0IFYAnF1/2ly5i/KuKrn899XBU=; b=YXY4wOTKfWxUh3MX G0pk5pl33KEHGfFtIcs7sX1dFl0nMLvLEP6E+3buRHZq9vyzG77Jbyk0uFGI7Tcl IwbxIshdHa+FOWjJd2kzFUuWF/mRDuUPe5mbyZXYVM76i4fIrfufMecfRnJ5+v/h goUfoTUGk4qMCikDNlRzrw3RIDohZjD2vb6lwvubeCYZMLfUZ7wkMZ8SXAy/+I4T CZGIVj2wOfvpi7IcKH4DbmbIJe2zlvz8BabPrG7i2sLsSogBsoA7fBo9ETbs6E/N SR7bmAYiBBgjtsw5VqLuk5uK0lkZCFFPVG2GV68PmmGNKT1UNBBjkVW1MK8muRy7 aVKi0g== Received: from mail-qt1-f197.google.com (mail-qt1-f197.google.com [209.85.160.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ehu1cgc3r-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 02 Jun 2026 09:11:56 +0000 (GMT) Received: by mail-qt1-f197.google.com with SMTP id d75a77b69052e-516d191f2ccso241449951cf.2 for ; Tue, 02 Jun 2026 02:11:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1780391516; x=1780996316; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=NaE5h732hDoKExFZJ0IFYAnF1/2ly5i/KuKrn899XBU=; b=hNYAaSrBC37Zt/BJEFmiC9Y4hUtl5Xxe0yzRKbfzvFpWynqaL5I0B6UdSLtrIkmUb8 JBjzBjLpQfg+UChiTFNmBjmJ7Uk/vgWqXJESKg5GufsD13emA8VfhmsRSQ+1qXWoc5kv Cara5uB6Ghe4z/MIka6uiNbrRkDCR00CElDkPVDLwAYbFCJRE4BOxS57V1dYkDmk7cRT A0wPhbpRlvGzflVmHSJQcVLEQbT1wEi0YwmCIJkSHU1JTsruNT8xB44TunNyUsBYdTM8 U75g++N7MoF0I/zedHyolevSXgcAtOgn9L3YuPyjdt9HRwiTSWRIz9cnHrL/pOMX6895 o9Sw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1780391516; x=1780996316; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=NaE5h732hDoKExFZJ0IFYAnF1/2ly5i/KuKrn899XBU=; b=aoUUAIGdz1xY/9ePnp37qt0wPg1QfeH+M3n48f+qhoCSslMAfmrj3bG9A3gsdXvd5m /iRp3T0VehJYx521/XV6EGJTqQ0gHRv9TsfqMLczPO2eS1h38Ff+9xbaLCzHSKI8W09A r9Qe3TdkjQUe6sKHkFm9mRreleSLF1ZTZpez1qgkk7xr1gkWxnx/zPYzlhZIikYax/hU GerbKroYZYHNL0gGReLclO7MxOFIXJpbl+2/xI/NNyX5eOQtol1odVpy9oxJ+FGK++Dv 9QNpAn1ZXaw9/aEUOhT3tE05HUkaAxS6SG1js89Dblr7ziAkSkGPf5+1jNTBYmIkHlmK E7zg== X-Forwarded-Encrypted: i=1; AFNElJ9KrYpH53XsCeINf3zLucJt0IKMMmFeQuE0swl9QOPNb7hzk2hYdu8MfQldRe1ncYo5M8N/tj3sA+sxF5w=@vger.kernel.org X-Gm-Message-State: AOJu0Yyk7YgarUuW5rUv7dE7bNRmcXIhoWYPIfoEYRoPLjnRibjCqVUy 9Rmy10yCh5jG+nYM6scQ8JtWfICRd3z4rrvCh/nm41qBSYI19j6pWctMWbh4JCaPLThbv+OzKTk 8W8JWz4oB2mjYm3uKHKcNaHyz5NqGx5RiH3dDnBeNGEUm0RcHNdeIWpLc1W/eN6IIESE= X-Gm-Gg: Acq92OEwmiv7LJE99SL1VpfcxucBxJYL4VHqj+ZH/AgInnYwI6yngiVuflfEh/FofBR cc19LVXPgCzAZHEMFhX0xn6woxML2Dc4SuZM9HNvxNBNbbImyXNr3HWyHcKWUhblMjw7PwHRah1 yiMaZnAnHUaaZ7shkEydbiMn03Y0TmVPUrkg0jp6xYgup46iYRAnY23zuqmI72e8Z6nY4xF2q7B nHsLtNg0joC7nbDBeBQDXKn6vZ8Dnzz4gGV9J0Kjl7MYMK/SeAkckkteuFYJby6/XbnDJd0JXRT lbWyGZ7tQ0tDWO5ynhlvk9+mF0KgvNATftglkU6ZJcxFk5dc+yRjmfmQo9a7VsFBokEYlzdm4f7 AiYOZNtj4GxSVg+eGXyaKF980rtdlLzwQtz3p+QdT+CzmXkfFVM7zLNg8QsupA0bhR5ZfK0IJf2 nRSYj2D4s+rwvyP9crKw== X-Received: by 2002:a05:622a:5c16:b0:516:d955:ea6 with SMTP id d75a77b69052e-5173a67b6d9mr228736961cf.14.1780391514650; Tue, 02 Jun 2026 02:11:54 -0700 (PDT) X-Received: by 2002:a05:622a:5c16:b0:516:d955:ea6 with SMTP id d75a77b69052e-5173a67b6d9mr228736671cf.14.1780391514240; Tue, 02 Jun 2026 02:11:54 -0700 (PDT) Received: from yongmou2.ap.qualcomm.com (Global_NAT1_IAD_FW.qualcomm.com. [129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-51768c76e53sm12480851cf.4.2026.06.02.02.11.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 02:11:53 -0700 (PDT) From: Yongxing Mou Date: Tue, 02 Jun 2026 17:11:19 +0800 Subject: [PATCH v6 07/15] drm/msm/dp: move the pixel clock control to its own API Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260602-dp_mstclean-v6-7-2c17ff40a9b2@oss.qualcomm.com> References: <20260602-dp_mstclean-v6-0-2c17ff40a9b2@oss.qualcomm.com> In-Reply-To: <20260602-dp_mstclean-v6-0-2c17ff40a9b2@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Abhinav Kumar , Dmitry Baryshkov X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780391476; l=4116; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=UaT/1/E05CYDg064KZ/+/vx3fX/KlDmWiJULn3OKuWU=; b=pXXnr4sV6x3w0BqHmYpCW0puPOY9afsmy+fiq1U7KJCeiclrWdmD+o0hAUYlVFWTfxehgqSSl 7HVICWYZPaEDMXk262IaFXRvQb44qsL3sPNCBIBMB/VVmzEtnAYNNbL X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-ORIG-GUID: luZc3BlaGb1BoiYIoBQsNPAcdsNFUXyH X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjAyMDA4NiBTYWx0ZWRfXxRoUoQHXnjMX WSW0gPhL0As5IQSjApWog9vq5y90OQh4/P6tsONs4OCYJJEhnK6uWQ0NKjtmbdTUnKBv5ZzybT7 m5eceJq8/7WBrvsiihOUyslBN5jMbi5WADNSM3qPYc51lJxkNaAzRLZ6ERJADOovLzpWrnA/Ujl 78KgBd+12xN59OMezwr8D2c5lwrAiGMHK6FMl8bvHMqtz0ZNkpy9L+qTKNr37WjYeR35CAE4Un6 OgcdoKj5+HFYVPC4NKn/pjdz3KbkNlVvoen4qk+ZyFVnhXL6xl3bD7s6+yqgnQp9+fg0k4191ed U+iwCQOncv7nphR2jiiyX38ItwAqfpUnPJYIWodRPLUdj22tNFzF62ytfA2FikvnuIN4phWSb1g OnHMCyXavvd3Ld32rOQQrfqMma17vUJn85iayi36ralQnM1Fvx4TL+wUNl6e69NWlDnirEMy4Bs ztVo+/AGv0zNkkLqZ4g== X-Proofpoint-GUID: luZc3BlaGb1BoiYIoBQsNPAcdsNFUXyH X-Authority-Analysis: v=2.4 cv=O6IJeh9W c=1 sm=1 tr=0 ts=6a1e9e5c cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=FjMX0bmgnFGAle5WrLgA:9 a=QEXdDO2ut3YA:10 a=a_PwQJl-kcHnX1M80qC6:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-01_07,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 bulkscore=0 malwarescore=0 lowpriorityscore=0 impostorscore=0 spamscore=0 adultscore=0 phishscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606020086 Enable/Disable of DP pixel clock happens in multiple code paths leading to code duplication. Move it into individual helpers so that the helpers can be called wherever necessary. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 81 +++++++++++++++++++++---------------= ---- 1 file changed, 42 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 1c2eccec6ec6..ac0a2c387f03 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -2171,6 +2171,42 @@ static bool msm_dp_ctrl_send_phy_test_pattern(struct= msm_dp_ctrl_private *ctrl) return success; } =20 +static int msm_dp_ctrl_on_pixel_clk(struct msm_dp_ctrl_private *ctrl, unsi= gned long pixel_rate) +{ + int ret; + + ret =3D clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); + if (ret) { + DRM_ERROR("Failed to set pixel clock rate. ret=3D%d\n", ret); + return ret; + } + + if (ctrl->stream_clks_on) { + drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n"); + } else { + ret =3D clk_prepare_enable(ctrl->pixel_clk); + if (ret) { + DRM_ERROR("Failed to start pixel clocks. ret=3D%d\n", ret); + return ret; + } + ctrl->stream_clks_on =3D true; + } + + return ret; +} + +static void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl) +{ + struct msm_dp_ctrl_private *ctrl; + + ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); + + if (ctrl->stream_clks_on) { + clk_disable_unprepare(ctrl->pixel_clk); + ctrl->stream_clks_on =3D false; + } +} + static int msm_dp_ctrl_process_phy_test_request(struct msm_dp_ctrl_private= *ctrl) { int ret; @@ -2196,22 +2232,7 @@ static int msm_dp_ctrl_process_phy_test_request(stru= ct msm_dp_ctrl_private *ctrl } =20 pixel_rate =3D ctrl->panel->msm_dp_mode.drm_mode.clock; - ret =3D clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); - if (ret) { - DRM_ERROR("Failed to set pixel clock rate. ret=3D%d\n", ret); - return ret; - } - - if (ctrl->stream_clks_on) { - drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n"); - } else { - ret =3D clk_prepare_enable(ctrl->pixel_clk); - if (ret) { - DRM_ERROR("Failed to start pixel clocks. ret=3D%d\n", ret); - return ret; - } - ctrl->stream_clks_on =3D true; - } + ret =3D msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate); =20 msm_dp_ctrl_send_phy_test_pattern(ctrl); =20 @@ -2514,26 +2535,13 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_d= p_ctrl, bool force_link_train ret =3D msm_dp_ctrl_enable_mainlink_clocks(ctrl); if (ret) { DRM_ERROR("Failed to start link clocks. ret=3D%d\n", ret); - goto end; + return ret; } } =20 - ret =3D clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); - if (ret) { - DRM_ERROR("Failed to set pixel clock rate. ret=3D%d\n", ret); - goto end; - } - - if (ctrl->stream_clks_on) { - drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n"); - } else { - ret =3D clk_prepare_enable(ctrl->pixel_clk); - if (ret) { - DRM_ERROR("Failed to start pixel clocks. ret=3D%d\n", ret); - goto end; - } - ctrl->stream_clks_on =3D true; - } + ret =3D msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate); + if (ret) + return ret; =20 if (force_link_train || !msm_dp_ctrl_channel_eq_ok(ctrl)) msm_dp_ctrl_link_retrain(ctrl); @@ -2572,7 +2580,6 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_= ctrl, bool force_link_train drm_dbg_dp(ctrl->drm_dev, "mainlink %s\n", mainlink_ready ? "READY" : "NOT READY"); =20 -end: return ret; } =20 @@ -2620,11 +2627,7 @@ void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl) =20 msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl); =20 - if (ctrl->stream_clks_on) { - clk_disable_unprepare(ctrl->pixel_clk); - ctrl->stream_clks_on =3D false; - } - + msm_dp_ctrl_off_pixel_clk(msm_dp_ctrl); dev_pm_opp_set_rate(ctrl->dev, 0); msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); =20 --=20 2.43.0 From nobody Mon Jun 8 04:25:38 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 438F13D566F for ; Tue, 2 Jun 2026 09:12:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780391523; cv=none; b=Z08aqVCjRVQGgZaNDs3xm1r4PdZfFrxRgxxX3j3adBVs2XBon65Ez5olBTRI/R/JyKLxTUuAUcIvhB0uowRAmQ2TiVsYFuk92oqvXtGyk+Urb9uqYXJUQ+sJRKIJZgtQizs3VHQA1pUDUiChHDhfwjD4KquWX7yqCK6xf8CjFdY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780391523; c=relaxed/simple; bh=zSnGi0bbdZ/VVEDgF7ym6Btkt+/Uv5gTh8caBZqhP6A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=N2RXNynP7tpVNuU7KAY0rBUKSnIOOuSdNGZa+Y7RBO1awjkvXT1F4MuJw35ILpG9PxUIkwgzhD5FmQIFjD+13fX1XE8S0V4sIAKOvbQEQzJzuAVTK4C1icr9LSkAqYy8DOsSdd/5siR22MboKRnd7rciY2ea0cJEsY4zE2/W4Zk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=QlnGAwf3; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=GIjsS9G4; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="QlnGAwf3"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="GIjsS9G4" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 65245lQD2692219 for ; Tue, 2 Jun 2026 09:12:01 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= lGiqHAGb2wqxVw+z1FvZ2fyaog25rtaM9glu7hrHjmw=; b=QlnGAwf3uxb+yD4c tPdSciT9tBVT7mcxDTq5WyxFz9IYG/sSEfSuD+0jAstHKTUYhgtvDKN72Pc++q0w F7Pe/dy5BFwv6aYlgM/tkGIJ9/OesnjcEzPXMfgLfyLJW8FuPZXk+mgwMXZDXb/q KrEWpVbxVRayQSseTLwvjuGtMb9j2G8VqUT7NR6SKO5jaGkhc2kVYJegOMWQGifP GRWW7/04R5ZMTUmEvXWmTHHpyQE/NFI49THr/HgKAbZo/W3tQrmrT3/mLrdppNqW wzys3VpR0EHw7IGz2ZYaKyqtG3+Ib826z3sZk8jDCyUkbXBfvHPaLbEqDPBBOlqi i0GUaQ== Received: from mail-qt1-f200.google.com (mail-qt1-f200.google.com [209.85.160.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ehqumh6gj-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 02 Jun 2026 09:12:01 +0000 (GMT) Received: by mail-qt1-f200.google.com with SMTP id d75a77b69052e-5176cc5bf2aso5260621cf.1 for ; Tue, 02 Jun 2026 02:12:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1780391521; x=1780996321; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=lGiqHAGb2wqxVw+z1FvZ2fyaog25rtaM9glu7hrHjmw=; b=GIjsS9G4TCTJ6pfIeiZYm+n1URdLKHDjlWq2xG036kSdZVINWWv/bR8QZFnJEX9jfE hUB5GjyGM8bQIJT8HVuQX+iJqnVizFIfxGbyNBNGSdXDoSPu3p021ZDcPrjrizsu7Vpn Gn6WPpbSoBpEqzUkKvfloXGkwkU7G+TYAc2sTr9qEzlR8QWHZSgLbB4/4m4GsPm15sMF 0h9jGAhQChh0Al7yGB3mngsRoNrehvA6qN4HWbLboWBti82AiwTHXHL3KQqtBhooYgqc GAxe+p3BRNBTJ7qtzse2I/MePKqllzBHawA0tRAKL9cwZQ4Nl5+EEw5udtjzY7gqMFOL 9P/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1780391521; x=1780996321; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=lGiqHAGb2wqxVw+z1FvZ2fyaog25rtaM9glu7hrHjmw=; b=B+6wzpv7ilGyp7xGmJ75SqudWd10AyPP5DpYnHQsLW7ajE9dNpo8m97RrkEKyuFlj/ GSZI/z5uKI6m9Hw3UtNnKG3LALzjXScmgHpW8eRVcH8jW63jepJ91fKQIj4476PESfnX lEjwxzB+o2KMbUsMlsTn0pQFLwODV4Qg0VXsFxZUEwQEv2+0uEStb5JbrS2SnnbFZVhM yc3/rUxhZCSpu/Q2fEJWzm6bidF0JM87wMWr0VKVPRS1b2rEx+r8usN0AUMvcK+sFeBX lWdVlW6iac6g3dfDOAhvMuPXEv3+WSh2kQi4MJI/1zbSNL/zYUz2n2wI/pZt/2L88HJG TKHw== X-Forwarded-Encrypted: i=1; AFNElJ9Wmvv+fgzhdjkRLrgIEVO6Jva/VoFbqhhITjS99ZGpeCPAzB1sH3ei7xzfIwJcgYyYab2gIjQNPNuzXuQ=@vger.kernel.org X-Gm-Message-State: AOJu0Yxzyn8ky1Bx/j/eOCgL7mtKwsjo7QgkpWy6pEdSUeRKscFv15QI cgyqY1z4D8PFjII+S4D54n3hpVJbFcXvJa2258+ao/60H6lJ7enTth5/aKG26MZXy4adiyvbOM+ Ied4/Vso3UQpJAsMCdcWBWJ1HfH8h5CH2wWzurg7pMqclpdUiEgg9pvebONly24P+Ing= X-Gm-Gg: Acq92OEa9Nn2sU88H66tvwB+caKy0pjFlaQtYhAR5zZ8+/hdjWuyLc+yqncUBHx1uUi jpbTuDKX4UCM1z4FUV6mIOQHNugT+9NQUQZeqxW6Q9zloXrZdvbXBAnEIHxwdBmzgizeCoIEf8p 2zDomgXiZc3Nu3dnkI4Fwp1+49L7BWp8wHLd87wFyVnwkgWDmMLbcjNjW7l3XjqfxkmoJgjlRgB bfcHjFlYYsodgSYH1KKzsoqwkkNQWDsNFyt0qzR22a9sQQnKIptalbb8UsxN75Sh5+DAH4LT/Wn lzpRxA//NqvKyMSt2f53XjO2pyU9rYWG/N9pED6IDxJuNQwybt18y2Zk2JqSYw0ihRlThT8yYDd EDrPxP9gNh6k0daYZ8ZmlPNvQtpNs9LpyGXaai19xAfVjSbKeqJof45kgp1DluXPIXuW0lMtMbY sojHIWZV0O9/z+iiEFgQ== X-Received: by 2002:ac8:7d8a:0:b0:517:5f04:f249 with SMTP id d75a77b69052e-5175f04f4camr73862301cf.39.1780391520480; Tue, 02 Jun 2026 02:12:00 -0700 (PDT) X-Received: by 2002:ac8:7d8a:0:b0:517:5f04:f249 with SMTP id d75a77b69052e-5175f04f4camr73861961cf.39.1780391519896; Tue, 02 Jun 2026 02:11:59 -0700 (PDT) Received: from yongmou2.ap.qualcomm.com (Global_NAT1_IAD_FW.qualcomm.com. [129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-51768c76e53sm12480851cf.4.2026.06.02.02.11.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 02:11:59 -0700 (PDT) From: Yongxing Mou Date: Tue, 02 Jun 2026 17:11:20 +0800 Subject: [PATCH v6 08/15] drm/msm/dp: break up dp_display_enable into two parts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260602-dp_mstclean-v6-8-2c17ff40a9b2@oss.qualcomm.com> References: <20260602-dp_mstclean-v6-0-2c17ff40a9b2@oss.qualcomm.com> In-Reply-To: <20260602-dp_mstclean-v6-0-2c17ff40a9b2@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Abhinav Kumar , Dmitry Baryshkov X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780391476; l=10300; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=pS/y0SrXTUOv0Ui2vWFTX1frKGlvknXRwKnhZSdJ1dc=; b=nNNdk9vAl2rLvgitc8pIMpxCZM+1qjxYucU+cu5Y7OWkclDZ/6mb6ksXeipvwejGlfOvTGMgB wQeyDCrVbrfAoedqEeq6D5QcBvAuL4+8T9JfD5LicUEMroNe2/XkqvJ X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjAyMDA4NiBTYWx0ZWRfX4YklqlmubDZu QuRWIWTh2W19cYDu+ixkT2dvmHxq4ezdrebG4bLPF9ypSiXckDnbHRmsrZtESnsfe8Ko4uKd92H 7vvXufyKKtc4Juw2PWIVGT2voVsR1OIb2kpI7KFJTSYJKqxkE1ofiquoAz4CCSl+gWodf71E7CL Ehj0ueWSIhJ/Pdx7QN7Iby4LJStaAODpiAbHWAca/Je4+WOBPSTIiLd4m1ubjleS+IDJbMdZvQ5 +CLFpeHTQ0VlZncrDnApkapER/WsFbwQSqRq3+XsF7XJ5/nN0TUJXqdDltRiA9ROU6OmD19BGp9 VczTE1l/F2n5i8UDFHXWkA8CKqtRl2WxMztPfIZF7tUZ112ODvi4hjTQe+sdISOxl1HeJ1F0Mt9 tJ/yhcqVwxZvpDOuZHrK5sBwLriXUDcerIiE83sVV5SFlvXnhaRhwK+dNWtUr1DLcScLh30S1j/ B7HuDK/MFuD6oXhtYIg== X-Proofpoint-ORIG-GUID: 7CabzVM0RKTPHBU-6yyoMEzdfHuySleK X-Proofpoint-GUID: 7CabzVM0RKTPHBU-6yyoMEzdfHuySleK X-Authority-Analysis: v=2.4 cv=Rrv16imK c=1 sm=1 tr=0 ts=6a1e9e61 cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=yY1IV_0HXbUsaRqM5MUA:9 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-01_07,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 spamscore=0 suspectscore=0 impostorscore=0 phishscore=0 priorityscore=1501 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606020086 From: Abhinav Kumar dp_display_enable() currently re-trains the link if needed and then enables the pixel clock, programs the controller to start sending the pixel stream. Split these two parts into prepare/enable APIs, to support MST bridges_enable insert the MST payloads funcs between enable stream_clks and program register. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 48 +++++++++++------ drivers/gpu/drm/msm/dp/dp_ctrl.h | 3 +- drivers/gpu/drm/msm/dp/dp_display.c | 105 +++++++++++++++++++++++---------= ---- 3 files changed, 102 insertions(+), 54 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index ac0a2c387f03..002141a02073 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -2505,27 +2505,19 @@ static void msm_dp_ctrl_config_msa(struct msm_dp_ct= rl_private *ctrl, msm_dp_write_link(ctrl, REG_DP_SOFTWARE_NVID, nvid); } =20 -int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, bool force_link= _train) +int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool fo= rce_link_train) { int ret =3D 0; - bool mainlink_ready =3D false; struct msm_dp_ctrl_private *ctrl; - unsigned long pixel_rate; - unsigned long pixel_rate_orig; =20 if (!msm_dp_ctrl) return -EINVAL; =20 ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); =20 - pixel_rate =3D pixel_rate_orig =3D ctrl->panel->msm_dp_mode.drm_mode.cloc= k; - - if (msm_dp_ctrl->wide_bus_en || ctrl->panel->msm_dp_mode.out_fmt_is_yuv_4= 20) - pixel_rate >>=3D 1; - - drm_dbg_dp(ctrl->drm_dev, "rate=3D%d, num_lanes=3D%d, pixel_rate=3D%lu\n", - ctrl->link->link_params.rate, - ctrl->link->link_params.num_lanes, pixel_rate); + drm_dbg_dp(ctrl->drm_dev, "rate=3D%d, num_lanes=3D%d\n", + ctrl->link->link_params.rate, + ctrl->link->link_params.num_lanes); =20 drm_dbg_dp(ctrl->drm_dev, "core_clk_on=3D%d link_clk_on=3D%d stream_clk_on=3D%d\n", @@ -2539,16 +2531,40 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_d= p_ctrl, bool force_link_train } } =20 - ret =3D msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate); - if (ret) - return ret; - if (force_link_train || !msm_dp_ctrl_channel_eq_ok(ctrl)) msm_dp_ctrl_link_retrain(ctrl); =20 /* stop txing train pattern to end link training */ msm_dp_ctrl_clear_training_pattern(ctrl, DP_PHY_DPRX); =20 + return ret; +} + +int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl) +{ + int ret =3D 0; + bool mainlink_ready =3D false; + struct msm_dp_ctrl_private *ctrl; + unsigned long pixel_rate; + unsigned long pixel_rate_orig; + + if (!msm_dp_ctrl) + return -EINVAL; + + ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); + + pixel_rate_orig =3D ctrl->panel->msm_dp_mode.drm_mode.clock; + pixel_rate =3D pixel_rate_orig; + + if (msm_dp_ctrl->wide_bus_en || ctrl->panel->msm_dp_mode.out_fmt_is_yuv_4= 20) + pixel_rate >>=3D 1; + + drm_dbg_dp(ctrl->drm_dev, "pixel_rate=3D%lu\n", pixel_rate); + + ret =3D msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate); + if (ret) + return ret; + /* * Set up transfer unit values and set controller state to send * video. diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_c= trl.h index f68bee62713f..1497f1a8fc2f 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -17,7 +17,8 @@ struct msm_dp_ctrl { struct phy; =20 int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl); -int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, bool force_link= _train); +int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl); +int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool fo= rce_link_train); void msm_dp_ctrl_off_link_stream(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl); diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index f33c754b83c3..cf859f880943 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -617,7 +617,40 @@ static int msm_dp_display_set_mode(struct msm_dp *msm_= dp_display, return 0; } =20 -static int msm_dp_display_enable(struct msm_dp_display_private *dp, bool f= orce_link_train) +static int msm_dp_display_prepare_link(struct msm_dp_display_private *dp) +{ + struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; + int rc =3D 0; + bool force_link_train =3D false; + + drm_dbg_dp(dp->drm_dev, "sink_count=3D%d\n", dp->link->sink_count); + + if (msm_dp_display->is_edp) + msm_dp_hpd_plug_handle(dp); + + rc =3D pm_runtime_resume_and_get(&msm_dp_display->pdev->dev); + if (rc) { + DRM_ERROR("failed to pm_runtime_resume\n"); + return rc; + } + + if (dp->link->sink_count =3D=3D 0) + return rc; + + if (!msm_dp_display->power_on) { + msm_dp_display_host_phy_init(dp); + force_link_train =3D true; + } + + rc =3D msm_dp_ctrl_on_link(dp->ctrl); + if (rc) + DRM_ERROR("Failed link training (rc=3D%d)\n", rc); + // TODO: schedule drm_connector_set_link_status_property() + + return msm_dp_ctrl_prepare_stream_on(dp->ctrl, force_link_train); +} + +static int msm_dp_display_enable(struct msm_dp_display_private *dp) { int rc =3D 0; struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; @@ -628,7 +661,7 @@ static int msm_dp_display_enable(struct msm_dp_display_= private *dp, bool force_l return 0; } =20 - rc =3D msm_dp_ctrl_on_stream(dp->ctrl, force_link_train); + rc =3D msm_dp_ctrl_on_stream(dp->ctrl); if (!rc) msm_dp_display->power_on =3D true; =20 @@ -658,13 +691,10 @@ static int msm_dp_display_post_enable(struct msm_dp *= msm_dp_display) return 0; } =20 -static int msm_dp_display_disable(struct msm_dp_display_private *dp) +static void msm_dp_display_audio_notify_disable(struct msm_dp_display_priv= ate *dp) { struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; =20 - if (!msm_dp_display->power_on) - return 0; - /* wait only if audio was enabled */ if (msm_dp_display->audio_enabled) { /* signal the disconnect event */ @@ -675,6 +705,14 @@ static int msm_dp_display_disable(struct msm_dp_displa= y_private *dp) } =20 msm_dp_display->audio_enabled =3D false; +} + +static int msm_dp_display_disable(struct msm_dp_display_private *dp) +{ + struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; + + if (!msm_dp_display->power_on) + return 0; =20 if (dp->link->sink_count =3D=3D 0) { /* @@ -1371,14 +1409,13 @@ void msm_dp_bridge_atomic_enable(struct drm_bridge = *drm_bridge, struct drm_atomic_commit *state) { struct msm_dp_bridge *msm_dp_bridge =3D to_dp_bridge(drm_bridge); - struct msm_dp *dp =3D msm_dp_bridge->msm_dp_display; + struct msm_dp *msm_dp_display =3D msm_dp_bridge->msm_dp_display; struct drm_crtc *crtc; struct drm_crtc_state *crtc_state; int rc =3D 0; - struct msm_dp_display_private *msm_dp_display; - bool force_link_train =3D false; + struct msm_dp_display_private *dp; =20 - msm_dp_display =3D container_of(dp, struct msm_dp_display_private, msm_dp= _display); + dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 crtc =3D drm_atomic_get_new_crtc_for_encoder(state, drm_bridge->encoder); @@ -1386,44 +1423,29 @@ void msm_dp_bridge_atomic_enable(struct drm_bridge = *drm_bridge, return; crtc_state =3D drm_atomic_get_new_crtc_state(state, crtc); =20 - if (dp->is_edp) - msm_dp_hpd_plug_handle(msm_dp_display); - - if (pm_runtime_resume_and_get(&dp->pdev->dev)) { - DRM_ERROR("failed to pm_runtime_resume\n"); - return; - } - - if (msm_dp_display->link->sink_count =3D=3D 0) - return; - - rc =3D msm_dp_display_set_mode(dp, &crtc_state->adjusted_mode, msm_dp_dis= play->panel); + rc =3D msm_dp_display_set_mode(msm_dp_display, &crtc_state->adjusted_mode= , dp->panel); if (rc) { DRM_ERROR("Failed to perform a mode set, rc=3D%d\n", rc); return; } =20 - if (!dp->power_on) { - msm_dp_display_host_phy_init(msm_dp_display); - force_link_train =3D true; - } - - rc =3D msm_dp_ctrl_on_link(msm_dp_display->ctrl); + rc =3D msm_dp_display_prepare_link(dp); if (rc) { - DRM_ERROR("Failed link training (rc=3D%d)\n", rc); - // TODO: schedule drm_connector_set_link_status_property() + DRM_ERROR("DP display prepare failed, rc=3D%d\n", rc); return; } =20 - msm_dp_display_enable(msm_dp_display, force_link_train); + rc =3D msm_dp_display_enable(dp); + if (rc) + DRM_ERROR("DP display enable failed, rc=3D%d\n", rc); =20 - rc =3D msm_dp_display_post_enable(dp); + rc =3D msm_dp_display_post_enable(msm_dp_display); if (rc) { DRM_ERROR("DP display post enable failed, rc=3D%d\n", rc); - msm_dp_display_disable(msm_dp_display); + msm_dp_display_disable(dp); } =20 - drm_dbg_dp(dp->drm_dev, "type=3D%d Done\n", dp->connector_type); + drm_dbg_dp(msm_dp_display->drm_dev, "type=3D%d Done\n", msm_dp_display->c= onnector_type); } =20 void msm_dp_bridge_atomic_disable(struct drm_bridge *drm_bridge, @@ -1438,6 +1460,15 @@ void msm_dp_bridge_atomic_disable(struct drm_bridge = *drm_bridge, msm_dp_ctrl_push_idle(msm_dp_display->ctrl); } =20 +static void msm_dp_display_unprepare(struct msm_dp_display_private *dp) +{ + struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; + + pm_runtime_put_sync(&msm_dp_display->pdev->dev); + + drm_dbg_dp(dp->drm_dev, "type=3D%d Done\n", msm_dp_display->connector_typ= e); +} + void msm_dp_bridge_atomic_post_disable(struct drm_bridge *drm_bridge, struct drm_atomic_commit *state) { @@ -1450,11 +1481,11 @@ void msm_dp_bridge_atomic_post_disable(struct drm_b= ridge *drm_bridge, if (dp->is_edp) msm_dp_hpd_unplug_handle(msm_dp_display); =20 - msm_dp_display_disable(msm_dp_display); + msm_dp_display_audio_notify_disable(msm_dp_display); =20 - drm_dbg_dp(dp->drm_dev, "type=3D%d Done\n", dp->connector_type); + msm_dp_display_disable(msm_dp_display); =20 - pm_runtime_put_sync(&dp->pdev->dev); + msm_dp_display_unprepare(msm_dp_display); } =20 void msm_dp_bridge_hpd_enable(struct drm_bridge *bridge) --=20 2.43.0 From nobody Mon Jun 8 04:25:38 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6343C3D5C1D for ; Tue, 2 Jun 2026 09:12:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780391528; cv=none; b=gbB3w59Wy3HzRhPaW/CwCQKnzXDgQjT66Wtmga7C2DWbVFgfPeeC1hZ1pxlU0f7ssznFO8FW0VK+f5OHZzGzXg3E83p7WzQpr+vMfH616NVjl3NomRn6OrcAuO7NBo0nMXAD39f3B7yYgT7XGUOfUyg9ElqrGySN0WfADYKjHlg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780391528; c=relaxed/simple; bh=k+fjd0uAzZi7jcHsWm9CXjVJSBGmbgcOCLEymAHwJvg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=IqVvV7PzNJ+7JKye2NHr/k/3DMiiJPUaQOQWHO7wZAwFYaDrJAhf+0JwfY9gE4wrh18au26+25kXHTse8/zJoj3ZKh3DFIzXhi57Xvp3mbK1h+DqqfeATe29QOxPKmlp638XaWyNh3OzSzEQ6mznTnb5L4pzp535+eUcURef28A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=Nc6DvaV6; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=P9yZfLoH; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="Nc6DvaV6"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="P9yZfLoH" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 65245kBJ2692148 for ; Tue, 2 Jun 2026 09:12:06 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= Re9bQbGzhFUu/DwhaF7px31nxHQNbIQ8lgyi807eAgQ=; b=Nc6DvaV6tvosR4JA oYrChKsp58rejt9+eaHJ0rJ2iCgrOF33GM4I0Bv+z1OmU7e/sTSDIwDug/yw5u7i TTXi6qJoKf440aE0AjBzsLr4xT6epgHORMcHZjP6JFm4pmOrv7oyYsgg8ae4+f1s fjWkHnwnkTTrSHE4+KL219MhkrufEpodNXSI6OyBHJ+dTZccRXbuzZzIaYikUd6m 8paOO1b5y0tCkx9bHzbIcHMeUst330fhjUUK0QBf+iajXJ4i8nTAu0lqrZ5v83xs U5KZ/REABHG8Xj8MJzCjAH5EU2ISSY0K+e034u/bbSscPPTa/Amz4EcDd6Zhny2m EXKlCA== Received: from mail-qt1-f198.google.com (mail-qt1-f198.google.com [209.85.160.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ehqumh6h5-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 02 Jun 2026 09:12:06 +0000 (GMT) Received: by mail-qt1-f198.google.com with SMTP id d75a77b69052e-516d19f68acso223408181cf.2 for ; Tue, 02 Jun 2026 02:12:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1780391526; x=1780996326; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Re9bQbGzhFUu/DwhaF7px31nxHQNbIQ8lgyi807eAgQ=; b=P9yZfLoHV0OdKIgmEa0MHVhht2IaeTKxyY7IM1MJybbG8G2a+w/dwhVa1z1vI63QbT fNZ09YpsoXxtuZPbJD+GKyJ73Mfmt7RDFucYUAGzeVJVYcsrzWAdOjieoOLLNiQ6TD5D fOCh9+RcFP5NksoOkBxE0scCAENA9iFBJtHY2IXI1bRhHFK9/2sbRmr0cgxQImjGB12A txdYkaXopzFla5ua//RTg5gX5rxqEL8sc+Rhmgih+Cxt4QAh1wu+HPahBqTbOpgJMTMG xRD7okIM8f+ZmxEc2GlhtvjSECQW+r42HqwAQOB17nbdCsuNHrV9VNtCBrZyFiu+qC6n WSog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1780391526; x=1780996326; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=Re9bQbGzhFUu/DwhaF7px31nxHQNbIQ8lgyi807eAgQ=; b=sar4AT6uvmnQnapoHCutBrpBjEQkXMVPlQgjiEMW7+ZKaV3n0+S+ACNInNboXNZJ8w RrYsQMuY2oQ9ac6vmxqGYJ6gmbeo1NkntRYMkr8FaVGJTjxFmu0GbBFPWvtWGZD6IBY2 MS9I1CRH8K48yz/l4TB6RTNmOh/lGZ+ecpmLrKy6GCJRGaRogiEof5PzZG+YI4vdYKqy PBEhW+FZI8p05PT5G0mtUvhJUDyRRcFyAn08YWGQu16o61Kz74AZteeHA319qS2t8GEk mOPCoQaSvGq9WJRyR6Z6eZMeRl2y5u5VWZwdgJ2XeaCmcZE+1Y/3dUi9qxkrCOC481KF Fxrg== X-Forwarded-Encrypted: i=1; AFNElJ/so2zZrMMJTeUfQE8M+BpvSWzfq4/8FV6HxGq6NsHrl8PlhZBQciE9ykaqiPfNtYuzpZruthvwSTA1XNs=@vger.kernel.org X-Gm-Message-State: AOJu0YzMCLN9YKefasJp7MI/zqAJgPsxBtMpP6ckwk813HYNJYtdQBih Fq0plHO2y7oz9tP1XDhI8E3oau5r87N8GEHZ09yoylyuKkn1yhdk19HF24x4Kz/Ah8SB3v3SxLp UsjMutTkjuOFakKGY4nt6T8ZOg43F2qAzR7t7jrAHbqr0Yu4RmNqrUF4T0IebmvKxFCY= X-Gm-Gg: Acq92OFqovyODi14XMBMUj2rCYM8plDymQaSzIp4kfp94nTxntWus248JmMUnPVrzEG jpSJasvit1750CEtNGKq5x2fKYFU40nQXetAeI1HgB4iLblIWZHJbQK20aGwi7spyKI8FUumi0p lyO3fY27PxkCzbeHok1cjW0STHlGT26PJZybdwHsBaGUZLRt5pqZQ5zmD46pKCAL/IMBJ39LElj i3eG5qIxxyhw3Ngs682pjBnagBm2mfCENkTz3g4nbzQebQswsUdtYeeKuvYXpRtQlnW/jnw/iIY qPDnEUdb1Sb74m+0itrgYMdUQr5Hd1RySmh658umaH/IXfmmEf+z/T9l4D1WIz5i9/mzdQj5HJr wM2olxzJmC/QocwlLvEXJh5qhBE9FBwxVOYu3YbalCUUZTRU9p0B4IAL0C+tNNOJ5MKypwIs18O nBCQgOSllueWC05qak2Q== X-Received: by 2002:a05:622a:2a99:b0:516:ea30:8756 with SMTP id d75a77b69052e-5173a817bf7mr147694351cf.36.1780391525585; Tue, 02 Jun 2026 02:12:05 -0700 (PDT) X-Received: by 2002:a05:622a:2a99:b0:516:ea30:8756 with SMTP id d75a77b69052e-5173a817bf7mr147694191cf.36.1780391525127; Tue, 02 Jun 2026 02:12:05 -0700 (PDT) Received: from yongmou2.ap.qualcomm.com (Global_NAT1_IAD_FW.qualcomm.com. [129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-51768c76e53sm12480851cf.4.2026.06.02.02.12.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 02:12:04 -0700 (PDT) From: Yongxing Mou Date: Tue, 02 Jun 2026 17:11:21 +0800 Subject: [PATCH v6 09/15] drm/msm/dp: re-arrange dp_display_disable() into functional parts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260602-dp_mstclean-v6-9-2c17ff40a9b2@oss.qualcomm.com> References: <20260602-dp_mstclean-v6-0-2c17ff40a9b2@oss.qualcomm.com> In-Reply-To: <20260602-dp_mstclean-v6-0-2c17ff40a9b2@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Abhinav Kumar , Dmitry Baryshkov X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780391476; l=3890; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=4Wm5dEjIlmt2dcJEpToKqMf/8eYUPZtjPLztPMLreZM=; b=q9czTavEj55EDD0AC9Z/pXgndqDGASyPrB0KPxwVGUMSDYpltbQSYpgN4VQ52U3vd4U83sncs RnAAe8Hddw3BAlPxYuDw4b+ZzuwYkZXgka4Ug2HDZ4cKBumqFN7Lib/ X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjAyMDA4NiBTYWx0ZWRfX/qXhWGiHoABf rlF9IFAUZ/nehWYMx8msvojG2JfteYG7/T2NXSzwyIA9L8FQVUk1BDUKMPMjMPgz9k/RFBgBRdb CIN8uHw0znYAJJdgH9Z9ngZMFL/IaVaGa9anHcj1KBQ/N28lCdixOEeg5/O9I93J2d5qt/vrGnE upjTGtRVQOcbmfe0kgubNny8UCYUdImcB7uQWRz/Rwr8jVFo8SR5HbZLNF0PP+yzdTXSDzBD4HP RS/yUPQUxpKSnqGUvOJD+zf7tYiTOf84sgvwkZqAXfObPrkjCQ9KDNIA8S3jHz02hRGDO0cx89M t8XUscX/GRIh04oS9mZTrsZ5kisIMy/5o46omsaeATzGnQuaxJcELb6+dCwTBwUk+195hZuaMBd 3hto8/v4Crr6dQ0qFo8ZsJvYtunMQn0/VXN2K/H290Fa103tTvCHLHh11Bzlw4nfqua7LkMEW6n 3jAe0ZOCxr3xw6wOsgQ== X-Proofpoint-ORIG-GUID: LTkTsGSvRpwkdqezf7zZ9-TmAZNUFl1m X-Proofpoint-GUID: LTkTsGSvRpwkdqezf7zZ9-TmAZNUFl1m X-Authority-Analysis: v=2.4 cv=Rrv16imK c=1 sm=1 tr=0 ts=6a1e9e66 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=7LH33tsxRIP6uNRhSrAA:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-01_07,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 spamscore=0 suspectscore=0 impostorscore=0 phishscore=0 priorityscore=1501 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606020086 From: Abhinav Kumar dp_display_disable() handles special case of when monitor is disconnected from the dongle while the dongle stays connected thereby needing a separate function dp_ctrl_off_link_stream() for this. However with a slight rework this can still be handled by keeping common paths same for regular and special case. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 19 +------------------ drivers/gpu/drm/msm/dp/dp_ctrl.h | 2 +- drivers/gpu/drm/msm/dp/dp_display.c | 10 +++++++++- 3 files changed, 11 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 002141a02073..d0c5ffb907e5 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -2599,7 +2599,7 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_= ctrl) return ret; } =20 -void msm_dp_ctrl_off_link_stream(struct msm_dp_ctrl *msm_dp_ctrl) +void msm_dp_ctrl_reinit_phy(struct msm_dp_ctrl *msm_dp_ctrl) { struct msm_dp_ctrl_private *ctrl; struct phy *phy; @@ -2607,23 +2607,6 @@ void msm_dp_ctrl_off_link_stream(struct msm_dp_ctrl = *msm_dp_ctrl) ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); phy =3D ctrl->phy; =20 - msm_dp_panel_disable_vsc_sdp(ctrl->panel); - - /* set dongle to D3 (power off) mode */ - msm_dp_link_psm_config(ctrl->link, &ctrl->panel->link_info, true); - - msm_dp_ctrl_mainlink_disable(ctrl); - - if (ctrl->stream_clks_on) { - clk_disable_unprepare(ctrl->pixel_clk); - ctrl->stream_clks_on =3D false; - } - - dev_pm_opp_set_rate(ctrl->dev, 0); - msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); - - phy_power_off(phy); - /* aux channel down, reinit phy */ phy_exit(phy); phy_init(phy); diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_c= trl.h index 1497f1a8fc2f..5d615f50d13b 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -19,7 +19,6 @@ struct phy; int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl); int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl); int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool fo= rce_link_train); -void msm_dp_ctrl_off_link_stream(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl); irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_dp_ctrl); @@ -46,4 +45,5 @@ void msm_dp_ctrl_core_clk_disable(struct msm_dp_ctrl *msm= _dp_ctrl); void msm_dp_ctrl_enable_irq(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_disable_irq(struct msm_dp_ctrl *msm_dp_ctrl); =20 +void msm_dp_ctrl_reinit_phy(struct msm_dp_ctrl *msm_dp_ctrl); #endif /* _DP_CTRL_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index cf859f880943..b8dab3f8a7c2 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -714,12 +714,20 @@ static int msm_dp_display_disable(struct msm_dp_displ= ay_private *dp) if (!msm_dp_display->power_on) return 0; =20 + msm_dp_panel_disable_vsc_sdp(dp->panel); + + /* dongle is still connected but sinks are disconnected */ if (dp->link->sink_count =3D=3D 0) { /* * irq_hpd with sink_count =3D 0 * hdmi unplugged out of dongle */ - msm_dp_ctrl_off_link_stream(dp->ctrl); + + /* set dongle to D3 (power off) mode */ + msm_dp_link_psm_config(dp->link, &dp->panel->link_info, true); + msm_dp_ctrl_off(dp->ctrl); + /* re-init the PHY so that we can listen to Dongle disconnect */ + msm_dp_ctrl_reinit_phy(dp->ctrl); } else { /* * unplugged interrupt --=20 2.43.0 From nobody Mon Jun 8 04:25:38 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 551283D6498 for ; Tue, 2 Jun 2026 09:12:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780391540; cv=none; b=C8Vz7XFlj6Lohy+TF/mi8Nat9MEIOBKwte1GX6aTm51KjAsPczdKXc94j+hUckXmmiK4R83u5eJ4UAqtiPokfMkRPZu6hkxDEVIDj3P0EGbbMwdfgVfg3ykUWq4Jk9fsg8JkL0OylcqZ/Fe67/NgBjpintsNznDzqZv4W03m/wQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780391540; c=relaxed/simple; bh=cQKBO8WPNa3xIXe5TRbVPZj9lDh46gX9A9WoSmvPXGg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=p5BFJpd+MSjtffG1hwGTsOHA6+kR4a7qm3Es5lr7/Oarv7hXvRQ2sxrIK7QhhOcrSerzT27iOYlUvsOKW7jsZOKuHZql28CuA04LU8L7V/iHk8W2wfsYgeEJA353LOduvhPSQ7TDn/PYsO7w5VLuF8zBomH3CApqDlVr4psOxLo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=cQUCxNQG; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=TBQWZ07n; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="cQUCxNQG"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="TBQWZ07n" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 65262JMf2687965 for ; Tue, 2 Jun 2026 09:12:12 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= VmZT1gSX0SYi9K0NfM0grDl/MdLFvJ3fRETebuBTp1g=; b=cQUCxNQGvvAzBL7a YPXhQt3l+qQPkXvq4QSJOLQWhsjlXwDloIYF6NvJyTLa2EqZgewmStEeAhzD2z/D 6ssOJO2coEOpFo89UzU/vATzlFWv82faP7g2J21GzzOrJywCePFNciqTFxq1nZKW TsuAtnwIuxQ8VWZBIzxlaiHhVy/Vcshn6d+SKypEa6fOyqQJiDRD1APXGL8E+i1O cNlWGvArJT9gmPwEdfBqLEDD/Y+Qb5hdvhkWM4KKTH1QF4MqdO8ep7GJ6i+s1RMh +/d0nsnGmT5F/TAhtjNq98aQim+dgEFZlqdMrs6SwnnGAB2IQf2ULzL968yGoAug 9fh/vw== Received: from mail-qt1-f198.google.com (mail-qt1-f198.google.com [209.85.160.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ehsja8rmf-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 02 Jun 2026 09:12:12 +0000 (GMT) Received: by mail-qt1-f198.google.com with SMTP id d75a77b69052e-516d4b3f3a1so222127141cf.1 for ; Tue, 02 Jun 2026 02:12:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1780391531; x=1780996331; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=VmZT1gSX0SYi9K0NfM0grDl/MdLFvJ3fRETebuBTp1g=; b=TBQWZ07nt9ZLNdw6DWhl9g/rPOPTJI90Yi+rbEpuLKyED7MjqeX704295Rt6pz/FQx N+i1s7f0kQT0/D1N0MGj7+ZalHYQh5HXuIqYDr3BRpYlUO4b3Y6PyPT1brsZlS+XmWr0 pfqigVIklTpDQb95rpYR5U2XN3m2r89aJn0O9/zLJaUJULzaU9dRnn3JRopkIMq+8SLA C3IhKkpSMxkHmIWFO5cFCfe3Lgz+d9PvM9+tB/EYO8A8Ygtr0F02C5tXB6JtKXTTfpxc zd+WhlZMw/dTIEkh6LePTcVSzuubDtOAAKXXGzkvIYt0ddIZviyG1CzTvopzH5+E7dJx H4gA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1780391531; x=1780996331; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=VmZT1gSX0SYi9K0NfM0grDl/MdLFvJ3fRETebuBTp1g=; b=cCthzmzOOtTmmERz+sdZVavmbVADH3JRgQTqwfiIpdJOQiBw7J/9Z358gRDfkyDYcO 9pAU1+nxoEPSypAgkIgMX0fQqB/4734nR3AagJvCVNJ5ajOQsojhUDYexOwn67PwyIOt lEZ0xw0dsWN/HZ8gIkSk9cyE3GZ2r1T/rAL8fvHVAq8HOEFpwZCo9AJlDYCAS2wpKk5L Ep3r1g/rtUuJ+n6N2uSMebCurJI3OKoxlMKYkptYJWxyo1tvsWeElRavvw47oTvKA9Zm mwnmL1u/HadPSh6377n8GlIX0soK5AMyNJZ00LXdk3RBzEcDqrxBdsN61+2f+80MiKcB i3Mg== X-Forwarded-Encrypted: i=1; AFNElJ9FKEcaFCWG2Bz4UsJb0mILvkc49vgY4Lt+unahr0/wlxjobrw/d65Et/Uj5upFH2KL7ksFeVonKuk3fWY=@vger.kernel.org X-Gm-Message-State: AOJu0YyPlSYn/gDPCW5EdFpdkydltThPWKmMkc3D65O199NRZt8CVlx+ 8WzO5IXTi2A8BRe1pXrsdf0p7jZEy+0XCikm8m0x1N1q7lTxo0fkTWyHVQC67i3d/g9uqxRW7jr ODtx9Ql7a+E8fC0UKyLAcmNFsKzQvGoSABSK+RTKNSQN+mr+1P9sV4eK6hoXdnwFu62Y= X-Gm-Gg: Acq92OH2yUWyY7NNUrOoUirJ0LTan9sDMikU2kd0KpIYpoJqbMUIMbJPUx4Cp3EQ58g x8RtLrEN64QyMmtlj+ZQSBZnahPPYQprXFUsOXvkutTZljrGIf0hqXd+xSRlJt1V82nXsn2bd8g 5o9AK5gf5cyxFMkW9h4Dy2U0WEkhEz9mPW4tYl3SUh+rkaNZPl2rQDCn6hGHIxpjIKs3rx+Ntlo qRHiw0TMU3EoWohjoaSWGe0hUSxkk+bdqAm4Zt30VTnhiM9VG9nf0LTOx31xf7vfkuS10ploDU0 sFGOv1UUyiub38Tv6PfKTzVuc2Q2tYs46pRWsZ9EPqgJU6KRtFBBGakhsxyQRSRfJ+VMOTawkKf u3izrw9hr86SzyU6mx3EVMpB2HP51CbhxmDWGId/oD3aMdrkT26qVCoPVywfYqYX+X5nFDq2qka hNo2Emgrq5tOMiuy/f7A== X-Received: by 2002:a05:622a:199d:b0:517:7246:8781 with SMTP id d75a77b69052e-51772468aafmr993371cf.8.1780391531131; Tue, 02 Jun 2026 02:12:11 -0700 (PDT) X-Received: by 2002:a05:622a:199d:b0:517:7246:8781 with SMTP id d75a77b69052e-51772468aafmr992911cf.8.1780391530535; Tue, 02 Jun 2026 02:12:10 -0700 (PDT) Received: from yongmou2.ap.qualcomm.com (Global_NAT1_IAD_FW.qualcomm.com. [129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-51768c76e53sm12480851cf.4.2026.06.02.02.12.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 02:12:10 -0700 (PDT) From: Yongxing Mou Date: Tue, 02 Jun 2026 17:11:22 +0800 Subject: [PATCH v6 10/15] drm/msm/dp: allow dp_ctrl stream APIs to use any panel passed to it Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260602-dp_mstclean-v6-10-2c17ff40a9b2@oss.qualcomm.com> References: <20260602-dp_mstclean-v6-0-2c17ff40a9b2@oss.qualcomm.com> In-Reply-To: <20260602-dp_mstclean-v6-0-2c17ff40a9b2@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Abhinav Kumar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780391476; l=32290; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=0/xJup617qd9RHy62Q62tgv+NCDfsSbiBTKALpu4TLA=; b=PvCJvZ3XBMWjWDWjL4M8ORF4no4nuilzQctn5deU+XL5/rJsXgvui/l51NMdyocuvxytamxJL RYKPjUHgZWqD/5iBvKnL/4GOpCEkrrQurrTwB3+UImlN/WLaezpw28e X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjAyMDA4NiBTYWx0ZWRfX0buO40ozY/cE a2zlgTp/7PO8U44j80/6MHYdwsII/rfJmbtxljpJY5QehOLToNdT4JtfSJ7gvJFHM52OGinNPFX vSzpfgPx35AETD0uYPStH3ah+YTK4f8hsToyCeFtDtu5jz9pkLgBGPmxCXWRckLNpcrwOmz8Syl lZRzLdGT1sODK/vm0otDQGIL0D4XgmHatmS0jwoMIUsb3CU8oohM4VkM1Tg9EQjdO+j2zY4Aa59 7PEY6os9dLJI4Us8DfI+qZaZgd5BEoz+mnM6eqOoR9lIt2FsJb8yTIIs9eLg/kSKrJiMZKCZjcs gtaPzcev7Zos6tdsciSun4z8NvptDM2v9DFbZcCtkgX2EZgiAfy+XSU+e7pOcG1MNc+fAf1BAMq Hx73KQtMNZA9FdyBnW25ZKfCvAk/yek7zMF5hnblnmwq9IgSHDrVFcUva6tV0El1NmiOhUaUdov 6euXxTNymJkM22hTD7A== X-Authority-Analysis: v=2.4 cv=Ld4MLDfi c=1 sm=1 tr=0 ts=6a1e9e6c cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=531mWe0hPKX_9nM1v_MA:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: xbMopxY0zbhvMBw1OzQI8bK2eF6X6ajg X-Proofpoint-ORIG-GUID: xbMopxY0zbhvMBw1OzQI8bK2eF6X6ajg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-01_07,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 adultscore=0 clxscore=1015 impostorscore=0 phishscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606020086 From: Abhinav Kumar With MST, multiple sinks share a single DP controller, so a cached panel in msm_dp_ctrl_private can no longer represent the per-stream sink. Drop the cache and pass panel explicitly to all stream-related dp_ctrl APIs. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 196 ++++++++++++++++++++------------= ---- drivers/gpu/drm/msm/dp/dp_ctrl.h | 28 ++++-- drivers/gpu/drm/msm/dp/dp_display.c | 24 ++--- 3 files changed, 140 insertions(+), 108 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index d0c5ffb907e5..902a6f5d181d 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -114,7 +114,6 @@ struct msm_dp_ctrl_private { struct drm_device *drm_dev; struct device *dev; struct drm_dp_aux *aux; - struct msm_dp_panel *panel; struct msm_dp_link *link; void __iomem *ahb_base; void __iomem *link_base; @@ -202,7 +201,8 @@ static int msm_dp_aux_link_configure(struct drm_dp_aux = *aux, /* * NOTE: resetting DP controller will also clear any pending HPD related i= nterrupts */ -void msm_dp_ctrl_reset(struct msm_dp_ctrl *msm_dp_ctrl) +void msm_dp_ctrl_reset(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *panel) { struct msm_dp_ctrl_private *ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); @@ -219,7 +219,7 @@ void msm_dp_ctrl_reset(struct msm_dp_ctrl *msm_dp_ctrl) =20 if (!ctrl->hw_revision) { ctrl->hw_revision =3D msm_dp_read_ahb(ctrl, REG_DP_HW_VERSION); - ctrl->panel->hw_revision =3D ctrl->hw_revision; + panel->hw_revision =3D ctrl->hw_revision; } } =20 @@ -414,10 +414,11 @@ static void msm_dp_ctrl_config_ctrl_streams(struct ms= m_dp_ctrl_private *ctrl, msm_dp_write_link(ctrl, REG_DP_CONFIGURATION_CTRL, config); } =20 -static void msm_dp_ctrl_config_ctrl_link(struct msm_dp_ctrl_private *ctrl) +static void msm_dp_ctrl_config_ctrl_link(struct msm_dp_ctrl_private *ctrl, + struct msm_dp_panel *panel) { u32 config =3D 0; - const u8 *dpcd =3D ctrl->panel->dpcd; + const u8 *dpcd =3D panel->dpcd; =20 /* Default-> LSCLK DIV: 1/4 LCLK */ config |=3D (2 << DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT); @@ -480,13 +481,14 @@ static void msm_dp_ctrl_config_misc1_misc0(struct msm= _dp_ctrl_private *ctrl, msm_dp_write_link(ctrl, REG_DP_MISC1_MISC0, misc_val); } =20 -static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private= *ctrl) +static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private= *ctrl, + struct msm_dp_panel *panel) { - msm_dp_ctrl_config_ctrl_streams(ctrl, ctrl->panel); + msm_dp_ctrl_config_ctrl_streams(ctrl, panel); =20 - msm_dp_ctrl_config_misc1_misc0(ctrl, ctrl->panel); + msm_dp_ctrl_config_misc1_misc0(ctrl, panel); =20 - msm_dp_panel_timing_cfg(ctrl->panel, ctrl->msm_dp_ctrl.wide_bus_en); + msm_dp_panel_timing_cfg(panel, ctrl->msm_dp_ctrl.wide_bus_en); } =20 /* @@ -1256,20 +1258,21 @@ static void _dp_ctrl_calc_tu(struct msm_dp_ctrl_pri= vate *ctrl, } =20 static void msm_dp_ctrl_calc_tu_parameters(struct msm_dp_ctrl_private *ctr= l, + struct msm_dp_panel *panel, struct msm_dp_vc_tu_mapping_table *tu_table) { struct msm_dp_tu_calc_input in; - struct drm_display_mode *drm_mode; + const struct drm_display_mode *drm_mode; =20 - drm_mode =3D &ctrl->panel->msm_dp_mode.drm_mode; + drm_mode =3D &panel->msm_dp_mode.drm_mode; =20 in.lclk =3D ctrl->link->link_params.rate / 1000; in.pclk_khz =3D drm_mode->clock; in.hactive =3D drm_mode->hdisplay; in.hporch =3D drm_mode->htotal - drm_mode->hdisplay; in.nlanes =3D ctrl->link->link_params.num_lanes; - in.bpp =3D ctrl->panel->msm_dp_mode.bpp; - in.pixel_enc =3D ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420 ? 420 : 444; + in.bpp =3D panel->msm_dp_mode.bpp; + in.pixel_enc =3D panel->msm_dp_mode.out_fmt_is_yuv_420 ? 420 : 444; in.dsc_en =3D 0; in.async_en =3D 0; in.fec_en =3D 0; @@ -1279,14 +1282,15 @@ static void msm_dp_ctrl_calc_tu_parameters(struct m= sm_dp_ctrl_private *ctrl, _dp_ctrl_calc_tu(ctrl, &in, tu_table); } =20 -static void msm_dp_ctrl_setup_tr_unit(struct msm_dp_ctrl_private *ctrl) +static void msm_dp_ctrl_setup_tr_unit(struct msm_dp_ctrl_private *ctrl, + struct msm_dp_panel *panel) { u32 msm_dp_tu =3D 0x0; u32 valid_boundary =3D 0x0; u32 valid_boundary2 =3D 0x0; struct msm_dp_vc_tu_mapping_table tu_calc_table; =20 - msm_dp_ctrl_calc_tu_parameters(ctrl, &tu_calc_table); + msm_dp_ctrl_calc_tu_parameters(ctrl, panel, &tu_calc_table); =20 msm_dp_tu |=3D tu_calc_table.tu_size_minus1; valid_boundary |=3D tu_calc_table.valid_boundary_link; @@ -1438,6 +1442,7 @@ static int msm_dp_ctrl_set_pattern_state_bit(struct m= sm_dp_ctrl_private *ctrl, } =20 static int msm_dp_ctrl_link_train_1(struct msm_dp_ctrl_private *ctrl, + struct msm_dp_panel *panel, int *training_step, enum drm_dp_phy dp_phy) { int delay_us; @@ -1446,7 +1451,7 @@ static int msm_dp_ctrl_link_train_1(struct msm_dp_ctr= l_private *ctrl, int const maximum_retries =3D 4; =20 delay_us =3D drm_dp_read_clock_recovery_delay(ctrl->aux, - ctrl->panel->dpcd, dp_phy, false); + panel->dpcd, dp_phy, false); =20 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); =20 @@ -1532,14 +1537,15 @@ static int msm_dp_ctrl_link_rate_down_shift(struct = msm_dp_ctrl_private *ctrl) return ret; } =20 -static int msm_dp_ctrl_link_lane_down_shift(struct msm_dp_ctrl_private *ct= rl) +static int msm_dp_ctrl_link_lane_down_shift(struct msm_dp_ctrl_private *ct= rl, + struct msm_dp_panel *panel) { =20 if (ctrl->link->link_params.num_lanes =3D=3D 1) return -1; =20 ctrl->link->link_params.num_lanes /=3D 2; - ctrl->link->link_params.rate =3D ctrl->panel->link_info.rate; + ctrl->link->link_params.rate =3D panel->link_info.rate; =20 ctrl->link->phy_params.p_level =3D 0; ctrl->link->phy_params.v_level =3D 0; @@ -1548,6 +1554,7 @@ static int msm_dp_ctrl_link_lane_down_shift(struct ms= m_dp_ctrl_private *ctrl) } =20 static void msm_dp_ctrl_clear_training_pattern(struct msm_dp_ctrl_private = *ctrl, + struct msm_dp_panel *panel, enum drm_dp_phy dp_phy) { int delay_us; @@ -1555,11 +1562,12 @@ static void msm_dp_ctrl_clear_training_pattern(stru= ct msm_dp_ctrl_private *ctrl, msm_dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_DISABLE, dp_phy); =20 delay_us =3D drm_dp_read_channel_eq_delay(ctrl->aux, - ctrl->panel->dpcd, dp_phy, false); + panel->dpcd, dp_phy, false); fsleep(delay_us); } =20 static int msm_dp_ctrl_link_train_2(struct msm_dp_ctrl_private *ctrl, + struct msm_dp_panel *panel, int *training_step, enum drm_dp_phy dp_phy) { int delay_us; @@ -1570,16 +1578,16 @@ static int msm_dp_ctrl_link_train_2(struct msm_dp_c= trl_private *ctrl, u8 link_status[DP_LINK_STATUS_SIZE]; =20 delay_us =3D drm_dp_read_channel_eq_delay(ctrl->aux, - ctrl->panel->dpcd, dp_phy, false); + panel->dpcd, dp_phy, false); =20 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); =20 *training_step =3D DP_TRAINING_2; =20 - if (drm_dp_tps4_supported(ctrl->panel->dpcd)) { + if (drm_dp_tps4_supported(panel->dpcd)) { pattern =3D DP_TRAINING_PATTERN_4; state_ctrl_bit =3D 4; - } else if (drm_dp_tps3_supported(ctrl->panel->dpcd)) { + } else if (drm_dp_tps3_supported(panel->dpcd)) { pattern =3D DP_TRAINING_PATTERN_3; state_ctrl_bit =3D 3; } else { @@ -1616,18 +1624,19 @@ static int msm_dp_ctrl_link_train_2(struct msm_dp_c= trl_private *ctrl, } =20 static int msm_dp_ctrl_link_train_1_2(struct msm_dp_ctrl_private *ctrl, + struct msm_dp_panel *panel, int *training_step, enum drm_dp_phy dp_phy) { int ret; =20 - ret =3D msm_dp_ctrl_link_train_1(ctrl, training_step, dp_phy); + ret =3D msm_dp_ctrl_link_train_1(ctrl, panel, training_step, dp_phy); if (ret) { DRM_ERROR("link training #1 on phy %d failed. ret=3D%d\n", dp_phy, ret); return ret; } drm_dbg_dp(ctrl->drm_dev, "link training #1 on phy %d successful\n", dp_p= hy); =20 - ret =3D msm_dp_ctrl_link_train_2(ctrl, training_step, dp_phy); + ret =3D msm_dp_ctrl_link_train_2(ctrl, panel, training_step, dp_phy); if (ret) { DRM_ERROR("link training #2 on phy %d failed. ret=3D%d\n", dp_phy, ret); return ret; @@ -1638,16 +1647,17 @@ static int msm_dp_ctrl_link_train_1_2(struct msm_dp= _ctrl_private *ctrl, } =20 static int msm_dp_ctrl_link_train(struct msm_dp_ctrl_private *ctrl, + struct msm_dp_panel *panel, int *training_step) { int i; int ret =3D 0; - const u8 *dpcd =3D ctrl->panel->dpcd; + const u8 *dpcd =3D panel->dpcd; u8 encoding[] =3D { 0, DP_SET_ANSI_8B10B }; u8 assr; struct msm_dp_link_info link_info =3D {0}; =20 - msm_dp_ctrl_config_ctrl_link(ctrl); + msm_dp_ctrl_config_ctrl_link(ctrl, panel); =20 link_info.num_lanes =3D ctrl->link->link_params.num_lanes; link_info.rate =3D ctrl->link->link_params.rate; @@ -1670,8 +1680,8 @@ static int msm_dp_ctrl_link_train(struct msm_dp_ctrl_= private *ctrl, for (i =3D ctrl->link->lttpr_count - 1; i >=3D 0; i--) { enum drm_dp_phy dp_phy =3D DP_PHY_LTTPR(i); =20 - ret =3D msm_dp_ctrl_link_train_1_2(ctrl, training_step, dp_phy); - msm_dp_ctrl_clear_training_pattern(ctrl, dp_phy); + ret =3D msm_dp_ctrl_link_train_1_2(ctrl, panel, training_step, dp_phy); + msm_dp_ctrl_clear_training_pattern(ctrl, panel, dp_phy); =20 if (ret) break; @@ -1682,7 +1692,7 @@ static int msm_dp_ctrl_link_train(struct msm_dp_ctrl_= private *ctrl, goto end; } =20 - ret =3D msm_dp_ctrl_link_train_1_2(ctrl, training_step, DP_PHY_DPRX); + ret =3D msm_dp_ctrl_link_train_1_2(ctrl, panel, training_step, DP_PHY_DPR= X); if (ret) { DRM_ERROR("link training on sink failed. ret=3D%d\n", ret); goto end; @@ -1695,6 +1705,7 @@ static int msm_dp_ctrl_link_train(struct msm_dp_ctrl_= private *ctrl, } =20 static int msm_dp_ctrl_setup_main_link(struct msm_dp_ctrl_private *ctrl, + struct msm_dp_panel *panel, int *training_step) { int ret =3D 0; @@ -1710,7 +1721,7 @@ static int msm_dp_ctrl_setup_main_link(struct msm_dp_= ctrl_private *ctrl, * a link training pattern, we have to first do soft reset. */ =20 - ret =3D msm_dp_ctrl_link_train(ctrl, training_step); + ret =3D msm_dp_ctrl_link_train(ctrl, panel, training_step); =20 return ret; } @@ -1809,11 +1820,12 @@ static void msm_dp_ctrl_link_clk_disable(struct msm= _dp_ctrl *msm_dp_ctrl) str_on_off(ctrl->core_clks_on)); } =20 -static int msm_dp_ctrl_enable_mainlink_clocks(struct msm_dp_ctrl_private *= ctrl) +static int msm_dp_ctrl_enable_mainlink_clocks(struct msm_dp_ctrl_private *= ctrl, + struct msm_dp_panel *panel) { int ret =3D 0; struct phy *phy =3D ctrl->phy; - const u8 *dpcd =3D ctrl->panel->dpcd; + const u8 *dpcd =3D panel->dpcd; =20 ctrl->phy_opts.dp.lanes =3D ctrl->link->link_params.num_lanes; ctrl->phy_opts.dp.link_rate =3D ctrl->link->link_params.rate / 100; @@ -1865,13 +1877,14 @@ static void msm_dp_ctrl_psr_exit(struct msm_dp_ctrl= _private *ctrl) msm_dp_write_link(ctrl, REG_PSR_CMD, cmd); } =20 -void msm_dp_ctrl_config_psr(struct msm_dp_ctrl *msm_dp_ctrl) +void msm_dp_ctrl_config_psr(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *panel) { struct msm_dp_ctrl_private *ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); u32 cfg; =20 - if (!ctrl->panel->psr_cap.version) + if (!panel->psr_cap.version) return; =20 /* enable PSR1 function */ @@ -1886,12 +1899,13 @@ void msm_dp_ctrl_config_psr(struct msm_dp_ctrl *msm= _dp_ctrl) drm_dp_dpcd_write(ctrl->aux, DP_PSR_EN_CFG, &cfg, 1); } =20 -void msm_dp_ctrl_set_psr(struct msm_dp_ctrl *msm_dp_ctrl, bool enter) +void msm_dp_ctrl_set_psr(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *panel, bool enter) { struct msm_dp_ctrl_private *ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); =20 - if (!ctrl->panel->psr_cap.version) + if (!panel->psr_cap.version) return; =20 /* @@ -1961,7 +1975,8 @@ void msm_dp_ctrl_phy_exit(struct msm_dp_ctrl *msm_dp_= ctrl) phy_exit(phy); } =20 -static int msm_dp_ctrl_reinitialize_mainlink(struct msm_dp_ctrl_private *c= trl) +static int msm_dp_ctrl_reinitialize_mainlink(struct msm_dp_ctrl_private *c= trl, + struct msm_dp_panel *panel) { struct phy *phy =3D ctrl->phy; int ret =3D 0; @@ -1982,7 +1997,7 @@ static int msm_dp_ctrl_reinitialize_mainlink(struct m= sm_dp_ctrl_private *ctrl) /* hw recommended delay before re-enabling clocks */ msleep(20); =20 - ret =3D msm_dp_ctrl_enable_mainlink_clocks(ctrl); + ret =3D msm_dp_ctrl_enable_mainlink_clocks(ctrl, panel); if (ret) { DRM_ERROR("Failed to enable mainlink clks. ret=3D%d\n", ret); return ret; @@ -1991,7 +2006,8 @@ static int msm_dp_ctrl_reinitialize_mainlink(struct m= sm_dp_ctrl_private *ctrl) return ret; } =20 -static int msm_dp_ctrl_deinitialize_mainlink(struct msm_dp_ctrl_private *c= trl) +static int msm_dp_ctrl_deinitialize_mainlink(struct msm_dp_ctrl_private *c= trl, + struct msm_dp_panel *panel) { struct phy *phy; =20 @@ -1999,7 +2015,7 @@ static int msm_dp_ctrl_deinitialize_mainlink(struct m= sm_dp_ctrl_private *ctrl) =20 msm_dp_ctrl_mainlink_disable(ctrl); =20 - msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl); + msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl, panel); =20 dev_pm_opp_set_rate(ctrl->dev, 0); msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); @@ -2013,7 +2029,8 @@ static int msm_dp_ctrl_deinitialize_mainlink(struct m= sm_dp_ctrl_private *ctrl) return 0; } =20 -static int msm_dp_ctrl_link_maintenance(struct msm_dp_ctrl_private *ctrl) +static int msm_dp_ctrl_link_maintenance(struct msm_dp_ctrl_private *ctrl, + struct msm_dp_panel *panel) { int ret =3D 0; int training_step =3D DP_TRAINING_NONE; @@ -2023,11 +2040,11 @@ static int msm_dp_ctrl_link_maintenance(struct msm_= dp_ctrl_private *ctrl) ctrl->link->phy_params.p_level =3D 0; ctrl->link->phy_params.v_level =3D 0; =20 - ret =3D msm_dp_ctrl_setup_main_link(ctrl, &training_step); + ret =3D msm_dp_ctrl_setup_main_link(ctrl, panel, &training_step); if (ret) goto end; =20 - msm_dp_ctrl_clear_training_pattern(ctrl, DP_PHY_DPRX); + msm_dp_ctrl_clear_training_pattern(ctrl, panel, DP_PHY_DPRX); =20 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); =20 @@ -2207,7 +2224,8 @@ static void msm_dp_ctrl_off_pixel_clk(struct msm_dp_c= trl *msm_dp_ctrl) } } =20 -static int msm_dp_ctrl_process_phy_test_request(struct msm_dp_ctrl_private= *ctrl) +static int msm_dp_ctrl_process_phy_test_request(struct msm_dp_ctrl_private= *ctrl, + struct msm_dp_panel *panel) { int ret; unsigned long pixel_rate; @@ -2223,15 +2241,15 @@ static int msm_dp_ctrl_process_phy_test_request(str= uct msm_dp_ctrl_private *ctrl * running. Add the global reset just before disabling the * link clocks and core clocks. */ - msm_dp_ctrl_off(&ctrl->msm_dp_ctrl); + msm_dp_ctrl_off(&ctrl->msm_dp_ctrl, panel); =20 - ret =3D msm_dp_ctrl_on_link(&ctrl->msm_dp_ctrl); + ret =3D msm_dp_ctrl_on_link(&ctrl->msm_dp_ctrl, panel); if (ret) { DRM_ERROR("failed to enable DP link controller\n"); return ret; } =20 - pixel_rate =3D ctrl->panel->msm_dp_mode.drm_mode.clock; + pixel_rate =3D panel->msm_dp_mode.drm_mode.clock; ret =3D msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate); =20 msm_dp_ctrl_send_phy_test_pattern(ctrl); @@ -2239,7 +2257,8 @@ static int msm_dp_ctrl_process_phy_test_request(struc= t msm_dp_ctrl_private *ctrl return 0; } =20 -void msm_dp_ctrl_handle_sink_request(struct msm_dp_ctrl *msm_dp_ctrl) +void msm_dp_ctrl_handle_sink_request(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *panel) { struct msm_dp_ctrl_private *ctrl; u32 sink_request =3D 0x0; @@ -2254,14 +2273,14 @@ void msm_dp_ctrl_handle_sink_request(struct msm_dp_= ctrl *msm_dp_ctrl) =20 if (sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) { drm_dbg_dp(ctrl->drm_dev, "PHY_TEST_PATTERN request\n"); - if (msm_dp_ctrl_process_phy_test_request(ctrl)) { + if (msm_dp_ctrl_process_phy_test_request(ctrl, panel)) { DRM_ERROR("process phy_test_req failed\n"); return; } } =20 if (sink_request & DP_LINK_STATUS_UPDATED) { - if (msm_dp_ctrl_link_maintenance(ctrl)) { + if (msm_dp_ctrl_link_maintenance(ctrl, panel)) { DRM_ERROR("LM failed: TEST_LINK_TRAINING\n"); return; } @@ -2269,7 +2288,7 @@ void msm_dp_ctrl_handle_sink_request(struct msm_dp_ct= rl *msm_dp_ctrl) =20 if (sink_request & DP_TEST_LINK_TRAINING) { msm_dp_link_send_test_response(ctrl->link); - if (msm_dp_ctrl_link_maintenance(ctrl)) { + if (msm_dp_ctrl_link_maintenance(ctrl, panel)) { DRM_ERROR("LM failed: TEST_LINK_TRAINING\n"); return; } @@ -2305,7 +2324,8 @@ static bool msm_dp_ctrl_channel_eq_ok(struct msm_dp_c= trl_private *ctrl) return drm_dp_channel_eq_ok(link_status, num_lanes); } =20 -int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl) +int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *panel) { int rc =3D 0; struct msm_dp_ctrl_private *ctrl; @@ -2321,8 +2341,8 @@ int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ct= rl) =20 ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); =20 - rate =3D ctrl->panel->link_info.rate; - pixel_rate =3D ctrl->panel->msm_dp_mode.drm_mode.clock; + rate =3D panel->link_info.rate; + pixel_rate =3D panel->msm_dp_mode.drm_mode.clock; =20 msm_dp_ctrl_core_clk_enable(&ctrl->msm_dp_ctrl); =20 @@ -2334,8 +2354,8 @@ int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ct= rl) } else { ctrl->link->link_params.rate =3D rate; ctrl->link->link_params.num_lanes =3D - ctrl->panel->link_info.num_lanes; - if (ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420) + panel->link_info.num_lanes; + if (panel->msm_dp_mode.out_fmt_is_yuv_420) pixel_rate >>=3D 1; } =20 @@ -2343,13 +2363,13 @@ int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_= ctrl) ctrl->link->link_params.rate, ctrl->link->link_params.num_lanes, pixel_rate); =20 - rc =3D msm_dp_ctrl_enable_mainlink_clocks(ctrl); + rc =3D msm_dp_ctrl_enable_mainlink_clocks(ctrl, panel); if (rc) return rc; =20 while (--link_train_max_retries) { training_step =3D DP_TRAINING_NONE; - rc =3D msm_dp_ctrl_setup_main_link(ctrl, &training_step); + rc =3D msm_dp_ctrl_setup_main_link(ctrl, panel, &training_step); if (rc =3D=3D 0) { /* training completed successfully */ break; @@ -2368,7 +2388,7 @@ int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ct= rl) * some lanes are ready, * reduce lane number */ - rc =3D msm_dp_ctrl_link_lane_down_shift(ctrl); + rc =3D msm_dp_ctrl_link_lane_down_shift(ctrl, panel); if (rc < 0) { /* lane =3D=3D 1 already */ /* end with failure */ break; @@ -2389,7 +2409,7 @@ int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ct= rl) ctrl->link->link_params.num_lanes)) rc =3D msm_dp_ctrl_link_rate_down_shift(ctrl); else - rc =3D msm_dp_ctrl_link_lane_down_shift(ctrl); + rc =3D msm_dp_ctrl_link_lane_down_shift(ctrl, panel); =20 if (rc < 0) { /* end with failure */ @@ -2397,10 +2417,10 @@ int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_= ctrl) } =20 /* stop link training before start re training */ - msm_dp_ctrl_clear_training_pattern(ctrl, DP_PHY_DPRX); + msm_dp_ctrl_clear_training_pattern(ctrl, panel, DP_PHY_DPRX); } =20 - rc =3D msm_dp_ctrl_reinitialize_mainlink(ctrl); + rc =3D msm_dp_ctrl_reinitialize_mainlink(ctrl, panel); if (rc) { DRM_ERROR("Failed to reinitialize mainlink. rc=3D%d\n", rc); break; @@ -2421,20 +2441,21 @@ int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_= ctrl) * link training failed * end txing train pattern here */ - msm_dp_ctrl_clear_training_pattern(ctrl, DP_PHY_DPRX); + msm_dp_ctrl_clear_training_pattern(ctrl, panel, DP_PHY_DPRX); =20 - msm_dp_ctrl_deinitialize_mainlink(ctrl); + msm_dp_ctrl_deinitialize_mainlink(ctrl, panel); rc =3D -ECONNRESET; } =20 return rc; } =20 -static int msm_dp_ctrl_link_retrain(struct msm_dp_ctrl_private *ctrl) +static int msm_dp_ctrl_link_retrain(struct msm_dp_ctrl_private *ctrl, + struct msm_dp_panel *panel) { int training_step =3D DP_TRAINING_NONE; =20 - return msm_dp_ctrl_setup_main_link(ctrl, &training_step); + return msm_dp_ctrl_setup_main_link(ctrl, panel, &training_step); } =20 static void msm_dp_ctrl_config_msa(struct msm_dp_ctrl_private *ctrl, @@ -2505,7 +2526,9 @@ static void msm_dp_ctrl_config_msa(struct msm_dp_ctrl= _private *ctrl, msm_dp_write_link(ctrl, REG_DP_SOFTWARE_NVID, nvid); } =20 -int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool fo= rce_link_train) +int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *panel, + bool force_link_train) { int ret =3D 0; struct msm_dp_ctrl_private *ctrl; @@ -2524,7 +2547,7 @@ int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl = *msm_dp_ctrl, bool force_li ctrl->core_clks_on, ctrl->link_clks_on, ctrl->stream_clks_on); =20 if (!ctrl->link_clks_on) { /* link clk is off */ - ret =3D msm_dp_ctrl_enable_mainlink_clocks(ctrl); + ret =3D msm_dp_ctrl_enable_mainlink_clocks(ctrl, panel); if (ret) { DRM_ERROR("Failed to start link clocks. ret=3D%d\n", ret); return ret; @@ -2532,15 +2555,15 @@ int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctr= l *msm_dp_ctrl, bool force_li } =20 if (force_link_train || !msm_dp_ctrl_channel_eq_ok(ctrl)) - msm_dp_ctrl_link_retrain(ctrl); + msm_dp_ctrl_link_retrain(ctrl, panel); =20 /* stop txing train pattern to end link training */ - msm_dp_ctrl_clear_training_pattern(ctrl, DP_PHY_DPRX); + msm_dp_ctrl_clear_training_pattern(ctrl, panel, DP_PHY_DPRX); =20 return ret; } =20 -int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl) +int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_p= anel *panel) { int ret =3D 0; bool mainlink_ready =3D false; @@ -2553,10 +2576,10 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_d= p_ctrl) =20 ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); =20 - pixel_rate_orig =3D ctrl->panel->msm_dp_mode.drm_mode.clock; + pixel_rate_orig =3D panel->msm_dp_mode.drm_mode.clock; pixel_rate =3D pixel_rate_orig; =20 - if (msm_dp_ctrl->wide_bus_en || ctrl->panel->msm_dp_mode.out_fmt_is_yuv_4= 20) + if (msm_dp_ctrl->wide_bus_en || panel->msm_dp_mode.out_fmt_is_yuv_420) pixel_rate >>=3D 1; =20 drm_dbg_dp(ctrl->drm_dev, "pixel_rate=3D%lu\n", pixel_rate); @@ -2573,18 +2596,18 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_d= p_ctrl) =20 msm_dp_ctrl_lane_mapping(ctrl); msm_dp_setup_peripheral_flush(ctrl); - msm_dp_ctrl_config_ctrl_link(ctrl); + msm_dp_ctrl_config_ctrl_link(ctrl, panel); =20 - msm_dp_ctrl_configure_source_params(ctrl); + msm_dp_ctrl_configure_source_params(ctrl, panel); =20 msm_dp_ctrl_config_msa(ctrl, ctrl->link->link_params.rate, pixel_rate_orig, - ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420); + panel->msm_dp_mode.out_fmt_is_yuv_420); =20 - msm_dp_panel_clear_dsc_dto(ctrl->panel); + msm_dp_panel_clear_dsc_dto(panel); =20 - msm_dp_ctrl_setup_tr_unit(ctrl); + msm_dp_ctrl_setup_tr_unit(ctrl, panel); =20 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); =20 @@ -2612,7 +2635,8 @@ void msm_dp_ctrl_reinit_phy(struct msm_dp_ctrl *msm_d= p_ctrl) phy_init(phy); } =20 -void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl) +void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *panel) { struct msm_dp_ctrl_private *ctrl; struct phy *phy; @@ -2620,11 +2644,11 @@ void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctr= l) ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); phy =3D ctrl->phy; =20 - msm_dp_panel_disable_vsc_sdp(ctrl->panel); + msm_dp_panel_disable_vsc_sdp(panel); =20 msm_dp_ctrl_mainlink_disable(ctrl); =20 - msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl); + msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl, panel); =20 msm_dp_ctrl_off_pixel_clk(msm_dp_ctrl); dev_pm_opp_set_rate(ctrl->dev, 0); @@ -2633,7 +2657,8 @@ void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl) phy_power_off(phy); } =20 -irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_dp_ctrl) +irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *panel) { struct msm_dp_ctrl_private *ctrl; u32 isr; @@ -2644,7 +2669,7 @@ irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_d= p_ctrl) =20 ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); =20 - if (ctrl->panel->psr_cap.version) { + if (panel->psr_cap.version) { isr =3D msm_dp_ctrl_get_psr_interrupt(ctrl); =20 if (isr) @@ -2733,7 +2758,7 @@ static int msm_dp_ctrl_clk_init(struct msm_dp_ctrl *m= sm_dp_ctrl) } =20 struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct msm_dp_link= *link, - struct msm_dp_panel *panel, struct drm_dp_aux *aux, + struct drm_dp_aux *aux, struct phy *phy, void __iomem *ahb_base, void __iomem *link_base) @@ -2741,7 +2766,7 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *de= v, struct msm_dp_link *link struct msm_dp_ctrl_private *ctrl; int ret; =20 - if (!dev || !panel || !aux || !link) { + if (!dev || !aux || !link) { DRM_ERROR("invalid input\n"); return ERR_PTR(-EINVAL); } @@ -2769,7 +2794,6 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *de= v, struct msm_dp_link *link init_completion(&ctrl->video_comp); =20 /* in parameters */ - ctrl->panel =3D panel; ctrl->aux =3D aux; ctrl->link =3D link; ctrl->dev =3D dev; diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_c= trl.h index 5d615f50d13b..00b430392a52 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -16,28 +16,36 @@ struct msm_dp_ctrl { =20 struct phy; =20 -int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl); -int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl); -int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool fo= rce_link_train); -void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl); +int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *panel); +int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_p= anel *panel); +int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *panel, + bool force_link_train); +void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *panel); void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl); -irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_dp_ctrl); -void msm_dp_ctrl_handle_sink_request(struct msm_dp_ctrl *msm_dp_ctrl); +irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *panel); +void msm_dp_ctrl_handle_sink_request(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *panel); struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct msm_dp_link *link, - struct msm_dp_panel *panel, struct drm_dp_aux *aux, struct phy *phy, void __iomem *ahb_base, void __iomem *link_base); =20 -void msm_dp_ctrl_reset(struct msm_dp_ctrl *msm_dp_ctrl); +void msm_dp_ctrl_reset(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *panel); void msm_dp_ctrl_phy_init(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_phy_exit(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_irq_phy_exit(struct msm_dp_ctrl *msm_dp_ctrl); =20 -void msm_dp_ctrl_set_psr(struct msm_dp_ctrl *msm_dp_ctrl, bool enable); -void msm_dp_ctrl_config_psr(struct msm_dp_ctrl *msm_dp_ctrl); +void msm_dp_ctrl_set_psr(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *panel, bool enable); +void msm_dp_ctrl_config_psr(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *panel); =20 int msm_dp_ctrl_core_clk_enable(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_core_clk_disable(struct msm_dp_ctrl *msm_dp_ctrl); diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index b8dab3f8a7c2..230e14615a23 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -359,7 +359,7 @@ static void msm_dp_display_host_init(struct msm_dp_disp= lay_private *dp) dp->phy_initialized); =20 msm_dp_ctrl_core_clk_enable(dp->ctrl); - msm_dp_ctrl_reset(dp->ctrl); + msm_dp_ctrl_reset(dp->ctrl, dp->panel); msm_dp_ctrl_enable_irq(dp->ctrl); msm_dp_aux_init(dp->aux); dp->core_initialized =3D true; @@ -371,7 +371,7 @@ static void msm_dp_display_host_deinit(struct msm_dp_di= splay_private *dp) dp->msm_dp_display.connector_type, dp->core_initialized, dp->phy_initialized); =20 - msm_dp_ctrl_reset(dp->ctrl); + msm_dp_ctrl_reset(dp->ctrl, dp->panel); msm_dp_ctrl_disable_irq(dp->ctrl); msm_dp_aux_deinit(dp->aux); msm_dp_ctrl_core_clk_disable(dp->ctrl); @@ -392,7 +392,7 @@ static int msm_dp_display_handle_irq_hpd(struct msm_dp_= display_private *dp) =20 drm_dbg_dp(dp->drm_dev, "%d\n", sink_request); =20 - msm_dp_ctrl_handle_sink_request(dp->ctrl); + msm_dp_ctrl_handle_sink_request(dp->ctrl, dp->panel); =20 if (sink_request & DP_TEST_LINK_VIDEO_PATTERN) msm_dp_display_handle_video_request(dp); @@ -570,7 +570,7 @@ static int msm_dp_init_sub_modules(struct msm_dp_displa= y_private *dp) goto error_link; } =20 - dp->ctrl =3D msm_dp_ctrl_get(dev, dp->link, dp->panel, dp->aux, + dp->ctrl =3D msm_dp_ctrl_get(dev, dp->link, dp->aux, phy, dp->ahb_base, dp->link_base); if (IS_ERR(dp->ctrl)) { rc =3D PTR_ERR(dp->ctrl); @@ -642,12 +642,12 @@ static int msm_dp_display_prepare_link(struct msm_dp_= display_private *dp) force_link_train =3D true; } =20 - rc =3D msm_dp_ctrl_on_link(dp->ctrl); + rc =3D msm_dp_ctrl_on_link(dp->ctrl, dp->panel); if (rc) DRM_ERROR("Failed link training (rc=3D%d)\n", rc); // TODO: schedule drm_connector_set_link_status_property() =20 - return msm_dp_ctrl_prepare_stream_on(dp->ctrl, force_link_train); + return msm_dp_ctrl_prepare_stream_on(dp->ctrl, dp->panel, force_link_trai= n); } =20 static int msm_dp_display_enable(struct msm_dp_display_private *dp) @@ -661,7 +661,7 @@ static int msm_dp_display_enable(struct msm_dp_display_= private *dp) return 0; } =20 - rc =3D msm_dp_ctrl_on_stream(dp->ctrl); + rc =3D msm_dp_ctrl_on_stream(dp->ctrl, dp->panel); if (!rc) msm_dp_display->power_on =3D true; =20 @@ -686,7 +686,7 @@ static int msm_dp_display_post_enable(struct msm_dp *ms= m_dp_display) msm_dp_display_handle_plugged_change(msm_dp_display, true); =20 if (msm_dp_display->psr_supported) - msm_dp_ctrl_config_psr(dp->ctrl); + msm_dp_ctrl_config_psr(dp->ctrl, dp->panel); =20 return 0; } @@ -725,7 +725,7 @@ static int msm_dp_display_disable(struct msm_dp_display= _private *dp) =20 /* set dongle to D3 (power off) mode */ msm_dp_link_psm_config(dp->link, &dp->panel->link_info, true); - msm_dp_ctrl_off(dp->ctrl); + msm_dp_ctrl_off(dp->ctrl, dp->panel); /* re-init the PHY so that we can listen to Dongle disconnect */ msm_dp_ctrl_reinit_phy(dp->ctrl); } else { @@ -733,7 +733,7 @@ static int msm_dp_display_disable(struct msm_dp_display= _private *dp) * unplugged interrupt * dongle unplugged out of DUT */ - msm_dp_ctrl_off(dp->ctrl); + msm_dp_ctrl_off(dp->ctrl, dp->panel); msm_dp_display_host_phy_exit(dp); } =20 @@ -869,7 +869,7 @@ void msm_dp_display_set_psr(struct msm_dp *msm_dp_displ= ay, bool enter) } =20 dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); - msm_dp_ctrl_set_psr(dp->ctrl, enter); + msm_dp_ctrl_set_psr(dp->ctrl, dp->panel, enter); } =20 /** @@ -979,7 +979,7 @@ static irqreturn_t msm_dp_display_irq_handler(int irq, = void *dev_id) } =20 /* DP controller isr */ - ret |=3D msm_dp_ctrl_isr(dp->ctrl); + ret |=3D msm_dp_ctrl_isr(dp->ctrl, dp->panel); =20 return ret; } --=20 2.43.0 From nobody Mon Jun 8 04:25:38 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 84519284B29 for ; Tue, 2 Jun 2026 09:12:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780391547; cv=none; b=ZV8TZJGC2yhLqFtTg23by9xZxOemTeVvA9HO4p4cMWjS6cK4nw02WgQiGeVjJJPCttxZ1ClD580oWZxdnsKQwLEPpWVEXeuQQV5nAWowKq4cQXz/ay+sUrDPcAhwX13ULxMDrTncmRK9A7C4kQBK8v1hAROahSMB7M2Py0EcCns= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780391547; c=relaxed/simple; bh=7y/nuSMlRJXRRb/ms/qQ1O6YqSZDBnwjUaF6ovcvrkQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=WM5jWnc/xbDL7M0cd5cvtKwMXFwzEW8RPNiv74BK/jgZycOxoIaYgLMWnDuxFYuTrN6odUkLegYo4qbd8oNplEUwc7hL4RFy/a+XoFLO5rXxK9QL5apaEJbGc00ewixvqaRfTF8IQ359eLmvrg2teEGmrR/An5IcPwe6Msnxzj8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=KNRyBhCc; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=KPZR9EH4; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="KNRyBhCc"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="KPZR9EH4" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 6525tdck4012510 for ; Tue, 2 Jun 2026 09:12:23 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= pP/YEN94t1y4drOH5CzH4TOHLceSrZCrc4auNY99UvY=; b=KNRyBhCcoQIcRgf/ bgTKaLmkKeNVAz/EMC848Wawi0l9agrXxpDz9G7i/sifTAmf+ybTGJyAIkSOSxID bL+pvBzgchsLgM+WZzzEyLB6cxNkfv3MuIgHcqThcBaDM6JAT+/qWCEgqqVUcMYk Ou71Wby4zlbTi6H9N8I82BCRf5qxbCzUZUPcVXUn/iE2n5n2yun/sdqCSrijKKeo C249KjHkdyYbycGG2Q3/ul3DlDH9i3QgxwnJP+IjTB4XFX3iITo07bdZltP7Wpif 6RR5nqvnwQ4GuVCywJdu2Agg5O4geo1EfrHevqX6oKvFHUFm1d+OthcftEGW7Kxb /QN0Xg== Received: from mail-qt1-f197.google.com (mail-qt1-f197.google.com [209.85.160.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ehsf4gtce-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 02 Jun 2026 09:12:21 +0000 (GMT) Received: by mail-qt1-f197.google.com with SMTP id d75a77b69052e-51766317074so18321891cf.3 for ; Tue, 02 Jun 2026 02:12:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1780391536; x=1780996336; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=pP/YEN94t1y4drOH5CzH4TOHLceSrZCrc4auNY99UvY=; b=KPZR9EH4SF3VwUcSNhW6xkaaJR97EVR6h1TFO5HlkJqly4GWKJnB9fADSPopYTr3U2 SHlde7tvT+cx2jQTRwbESSdjeo/xcrHbMSIsQ3IGddvERnXRvBmYCJykg65DwQPjW54p bN2pBSo5bZH4A1yxqx2O/ZgHv0g8lYZj2P4KGIWsGfFgZFGjsSseD16zRcjw2XMoAxsQ 9wrSOENFvvhuwn13thxBD/wBvjT0mz/LmS2o2ygbQpvqy2UwKtUAbDQXABp5D1rPn7Na FF4DQS1XhEMdmpcafL+Y5yLHqsF+R1dKEeZn0InLzkPgZnqVOI+LdOSrEiGhmxXxgAIA VP6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1780391536; x=1780996336; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=pP/YEN94t1y4drOH5CzH4TOHLceSrZCrc4auNY99UvY=; b=nrRxns2S6TsoRWlAgY0i2TvJef/j0rvv9VhkhyejwTgYchRtXyMFGrG+gV8Iqv/PCK gnq96s3WMucwuFdVMHLJNg68rLZ8x436cWKnzL6tdtrC5X+/FWbN07ZFdpcU826Yv4v0 Xcqma4G/Z6KwCLyF2dPB432lSjOD2WBBEIfPpLHgvuOw5LdvQ/Cisv3j2uFlfIfCW5sr bgnqyRUOY4VfgWbHy2fr6214jQtPlT0fTfGx8CToQV0P6LN8YhGMAJzZT+G26rMemEkz gAJMTAPbVTMj792EUJ9RqBsb3JorIbKVqjMR6VOsibD9Ei6qd5cddhH9Pa7XJH0b6bXC ER4g== X-Forwarded-Encrypted: i=1; AFNElJ+bplXFRM6GMOFywCgp4Pkt98KZ1gr6R2Y5DSf/+rvqbeCLFyRduGJrlckL2A+H1VrGRA2Ir9iwHhXnO2I=@vger.kernel.org X-Gm-Message-State: AOJu0YwDwwy4TUU+6nFU21V9nbmQNJCcVZeNC3O35N4hotft6WnBy1tY hSYu9lRUmAxvBNLhruOeiRceJRc15GYcC2PX/ebg1Z+lt0ToxzfA+9gRZw8iL8Tdm9S7E15F0ZP PfHBLPaa2YUFrwQ5C2LZV7RGh3BOZji7n2gLUPXWB/tKbi3MZwuMfbc4b1MvwmeQi48o= X-Gm-Gg: Acq92OG2sQ94MoocKYb8G+MlL7EaG9VY225ZE7957lYQ+1ETucQvZ+qJK2mRpqSpIZD KBECJErYdRcfcUq3dSudmiWrB9VyI7+vi9whrb2tib683Nk+dfiVrFtL6hMgspYbrmBH3M2XAPG sKuqjAbGkkOvtRLYFYh2eSWRhyKmwVRsZFrsEA0+QtZi2ZNkDHeiCX2vHzMsM0UU3AyOQiben+L WnmGmJdBg3ve0Ke9PC8H447NhPUJ7zjgOdSMFH/hXbV8IO+W+Xlmq0t8EZ8c0RCdthL20AF20nd Ahn+Tc+dRN5rZcCMLSYeCDMSt8LVqAUnjRM/8uMvoap5/+yOK0/9mFZoOOBrldvd3dVXIiTwLbu k/SYHBp+DROOJZAaemd20aDxH4VAG5Eh+ivrIBbX4y6PDIO2Hr8/1X84VwynSOPtSFGO7JuhkQD Tjj66anyncssCA+dxH+g== X-Received: by 2002:a05:622a:8f1b:b0:516:e10f:b1fa with SMTP id d75a77b69052e-5173a6336d6mr167602121cf.2.1780391535937; Tue, 02 Jun 2026 02:12:15 -0700 (PDT) X-Received: by 2002:a05:622a:8f1b:b0:516:e10f:b1fa with SMTP id d75a77b69052e-5173a6336d6mr167601781cf.2.1780391535411; Tue, 02 Jun 2026 02:12:15 -0700 (PDT) Received: from yongmou2.ap.qualcomm.com (Global_NAT1_IAD_FW.qualcomm.com. [129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-51768c76e53sm12480851cf.4.2026.06.02.02.12.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 02:12:15 -0700 (PDT) From: Yongxing Mou Date: Tue, 02 Jun 2026 17:11:23 +0800 Subject: [PATCH v6 11/15] drm/msm/dp: split dp_ctrl_off() into stream and link parts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260602-dp_mstclean-v6-11-2c17ff40a9b2@oss.qualcomm.com> References: <20260602-dp_mstclean-v6-0-2c17ff40a9b2@oss.qualcomm.com> In-Reply-To: <20260602-dp_mstclean-v6-0-2c17ff40a9b2@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Abhinav Kumar , Dmitry Baryshkov X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780391476; l=3896; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=yXTeHtGoeumB61qfMSu4s70qnNcHeimTgjHJ10HGZIA=; b=4CiVna5IhAqn8eXmUh3DDUaDP1YSx7SFCAhVi5jOL0G9RpUkR379l+6FAU2Wnz2Ze+wWoQ0vU oJ7UZfFNxEeCLAoXayag36/4ZK5b23E3cJHFhZz6xUdkZWKSSTVkwHu X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjAyMDA4NiBTYWx0ZWRfX1/EUgzWdcPsx 2yFHBqIR23pQdOvueQJs1s11v+hvpKRWRBxVqcuRFM8Sut9zhVWD1GdZnE6a1bfTmdosSaG568Y OWnoqXiPjK5NaqzNUBvrHtPz+LjgSf6B4Sw5Czrha2D4K/lQp22VT9uyKBTyVlxmGiSIeoY8DEt dE4K53aRE0ph0vDKJBeLheeoXJ3SHMktDAjc+Yoz+1L8885770kLIQubRDSty5mlSB7mdAlnF3o 6Im4P1ruM1yJ6qZCAoV/dT8LioL66lnEaHLZ0z5Up9Tbk/gtz4uuUC4MmsiROb2WNJmV376iZk2 4mIYZWuMqluq7SIjVBthI3vQyhCOIwjTDTBhiy7WieAxxAa6uzeGV0YRXQCq3R3BwFv2O7w9yse g0tXHFvdb5dzuKrbLLHwZmx23+JGmjyrFnzsKRCPVYtAMgRKLfQFwCSYgNWrPVaI1P3IZVoPMIc wKV/PdmPUIW+B9WYSqg== X-Proofpoint-GUID: KNztbWPi_oQB4CgirQ9pbBSe-yHSPuS6 X-Authority-Analysis: v=2.4 cv=AJZ7LEvz c=1 sm=1 tr=0 ts=6a1e9e77 cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=2kxiPxfbkJi5fZIrDGYA:9 a=QEXdDO2ut3YA:10 a=a_PwQJl-kcHnX1M80qC6:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: KNztbWPi_oQB4CgirQ9pbBSe-yHSPuS6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-01_07,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 suspectscore=0 malwarescore=0 phishscore=0 bulkscore=0 impostorscore=0 clxscore=1015 lowpriorityscore=0 spamscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606020086 From: Abhinav Kumar Split dp_ctrl_off() into stream and link parts so that for MST cases we can control the link and pixel parts separately. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 10 +++++----- drivers/gpu/drm/msm/dp/dp_ctrl.h | 5 +++-- drivers/gpu/drm/msm/dp/dp_display.c | 7 ++++--- 3 files changed, 12 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 902a6f5d181d..c88929d1fbab 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -2212,7 +2212,7 @@ static int msm_dp_ctrl_on_pixel_clk(struct msm_dp_ctr= l_private *ctrl, unsigned l return ret; } =20 -static void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl) +void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl) { struct msm_dp_ctrl_private *ctrl; =20 @@ -2241,7 +2241,8 @@ static int msm_dp_ctrl_process_phy_test_request(struc= t msm_dp_ctrl_private *ctrl * running. Add the global reset just before disabling the * link clocks and core clocks. */ - msm_dp_ctrl_off(&ctrl->msm_dp_ctrl, panel); + msm_dp_ctrl_off_pixel_clk(&ctrl->msm_dp_ctrl); + msm_dp_ctrl_off_link(&ctrl->msm_dp_ctrl, panel); =20 ret =3D msm_dp_ctrl_on_link(&ctrl->msm_dp_ctrl, panel); if (ret) { @@ -2635,8 +2636,8 @@ void msm_dp_ctrl_reinit_phy(struct msm_dp_ctrl *msm_d= p_ctrl) phy_init(phy); } =20 -void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl, - struct msm_dp_panel *panel) +void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *panel) { struct msm_dp_ctrl_private *ctrl; struct phy *phy; @@ -2650,7 +2651,6 @@ void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl, =20 msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl, panel); =20 - msm_dp_ctrl_off_pixel_clk(msm_dp_ctrl); dev_pm_opp_set_rate(ctrl->dev, 0); msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); =20 diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_c= trl.h index 00b430392a52..5902cf7e746a 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -22,8 +22,9 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl= , struct msm_dp_panel * int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel *panel, bool force_link_train); -void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl, - struct msm_dp_panel *panel); +void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *panel); +void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl); irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel *panel); diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 230e14615a23..8f472633da82 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -725,15 +725,16 @@ static int msm_dp_display_disable(struct msm_dp_displ= ay_private *dp) =20 /* set dongle to D3 (power off) mode */ msm_dp_link_psm_config(dp->link, &dp->panel->link_info, true); - msm_dp_ctrl_off(dp->ctrl, dp->panel); - /* re-init the PHY so that we can listen to Dongle disconnect */ + msm_dp_ctrl_off_pixel_clk(dp->ctrl); + msm_dp_ctrl_off_link(dp->ctrl, dp->panel); msm_dp_ctrl_reinit_phy(dp->ctrl); } else { /* * unplugged interrupt * dongle unplugged out of DUT */ - msm_dp_ctrl_off(dp->ctrl, dp->panel); + msm_dp_ctrl_off_pixel_clk(dp->ctrl); + msm_dp_ctrl_off_link(dp->ctrl, dp->panel); msm_dp_display_host_phy_exit(dp); } =20 --=20 2.43.0 From nobody Mon Jun 8 04:25:38 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7ABC13D6465 for ; Tue, 2 Jun 2026 09:12:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780391545; cv=none; b=j19pUiGoL31Lw3pi62WXXDNjqzrr+W7R3nYGkI3bLU0PHIU17qogdKQhP0ELb3nCDv+/dLmNHQwQhyAVKskjzXBStwoS0NfGTGRsmJc9ZAjNCJbeR6CW3wQ9GkWBCbB0J3n0iplwdixgxEnvlaVHYW8T+83BVmZI+e+uGRsHLiY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780391545; c=relaxed/simple; bh=4TJKG8RTz4R+dv3UNXgRl/mjeEf45SUuZJzked/IkbU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=kzL6v1iZMLDEQIlTlAhbBhIKAhAcyRMdwBgG6UhTsUR3Kh3ESmHF3BZh0MeU6+XK+xkmgMP5X7kx2AkPPq9KkgrTC83qwCj/fdKO7Hz5pVDAcierEqEgmJ5mrorEEWAU7D5gCR6M4wtPZdnQqwiZBclLkDR17gdN9CYf67+bY3U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=hohob0sA; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=hdqCW9jJ; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="hohob0sA"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="hdqCW9jJ" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 6528QnYc3430226 for ; Tue, 2 Jun 2026 09:12:21 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= sRjgMQtRt4M0KMMF63fnqZRXOOmmbwogwYrfMYQ8brA=; b=hohob0sAycBvqqdr cpqG86dXz2IaSY+iEs6Fq9x3tkF8+NOvcQuM/5nPzi+lQY3Uiy/JVmBR4uvuLowP hyT75i07ImJtfhKJ7W2xOHEQITteMr72bs6QYvQbWxvxY5PjvQ0t87Gql+9n1Vvh MvF9dijyx66cC42mwVHXfviM44ZLijS1nGnFBYd3WVmFEf7jEYCaxFAGhPXVQzE+ 0SLEM/wQMg9eDB4MoLOjEr1XNlZfo3Kn3fDZiuPgAGu1TMr7v1utOU17ztDdEIxP BecNJPXC7JiKiqaFHBbsa1dDhL/MblZCozL3+iUea+MdOU0tI3GIFu6uGW/R11h3 D9oFzg== Received: from mail-qt1-f197.google.com (mail-qt1-f197.google.com [209.85.160.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ehn8mhq55-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 02 Jun 2026 09:12:21 +0000 (GMT) Received: by mail-qt1-f197.google.com with SMTP id d75a77b69052e-51771d41426so4631991cf.2 for ; Tue, 02 Jun 2026 02:12:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1780391540; x=1780996340; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=sRjgMQtRt4M0KMMF63fnqZRXOOmmbwogwYrfMYQ8brA=; b=hdqCW9jJSmRrCezIhE+1P2qSDosgT1uOHCrilm3ztj1SB0t0N5+w/hzu5SA1xYAb6H doFg9rcS9h1SzVaabWvfpRZuLsxNDCzToB62zv5wxamSKXk+zLoodkxVQeD52RCvBgvJ +40oymd0RJHStgxWOTdTmaIVqXB/LbQNfAdjZBweknQvVYGwckuxKvKkhPSGeW4HabKM xAhiPH/hLEvS/wtMYc3sJojJ+n6cdFElFR8fQ/H2eebdls6TvfWWuTA1E5sDBi+YX+WD 8vDu61+A774OsAdJQfk+Yc/3IuZ9uWgFgDJWS+ibwuCIN84b9FDlxiIScDPmak9j1mH0 XV8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1780391540; x=1780996340; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=sRjgMQtRt4M0KMMF63fnqZRXOOmmbwogwYrfMYQ8brA=; b=cbghNH/jnaq8jGe9mEpacAExlrRXBieeZbF2pYmDlIdK78cHtdtk2SLry4AZKXTU1B BJa5uJfqbfC3aBGUJkUzaceMobe6LStm1kTdw+625pfAYvWxZs3+wnfeWmSoYIA5eMjo VShbVnBL17QCshE2XrTUvFsuyGq1YJ99ndP7bh0eGqmzshXHjQrLDcJxDSslJy1PipZI 8RWnpmeCgGYabXa0DZEN8tEHgNimU5oniUK9wkwbm8jnXuemThn7JGb5H8BVgRow39bZ ZpSD0TU7PnlKiQFX2k/nYNC56eVtJFW++xGPzTlzyz2igoqAZ3TmMimKRKHEpkqKNbKg txSw== X-Forwarded-Encrypted: i=1; AFNElJ9ZgbxdscwhYpoQgaDD67p19a/E1XnUZmKK2UPQXbya1Xz6tM8IsGkb4RWXz3Y5ixKjlb4jrDwgqGY6PKU=@vger.kernel.org X-Gm-Message-State: AOJu0YzrY0Ws5EeJOwu+ShI8hzvd+f1Ffdy9ZNqPZUCEBYd0jOV+oKNQ 2+UozwKcHnACaFVZjNwy09Zmtr/deixHuKHq/lvierUzKTGdcMWFPIHLacnQi2R+HAy1TvJC0y+ IpdhXxSdgbSAAP/tI/FVoQ+P6Y/Fp8JTZ+sYAgic8s6Xp3y4sD7yXyapnFAoiDR/ohK4= X-Gm-Gg: Acq92OEPJH3JPcmgL4G1nP5Lf+V/sJOVgz+C5Jf+1Nv7SM54mM1bK4d/b0/TdDQw+1g G/7FLBsFF1YBT+ZW0W79jsfxLS5OlORoHGE7EiB0VPR1HcD/xYL8r1wfM629CNHQdpuBcE+ieKE xGQB2rpMLKDzEvWhK7fMMcPo2x+H/3uPfLZon8EgMG/5YOxaLm/Alp09NROzF6q47Vn4ZoYhYUt 1Z0QvgypYfutgi5kJW0f1Uc0aLo3OqRL4QaliR2Hi+iAZ96IGiWFuIBsqlBIiOnSXtPEMGRISoq t0DeGIkx2stnUeCKViJC6SYrjS1qFMAgOZ8bpjFSD1EY+zgIxdZIOjgqKAle34Q6RrvtUsvYvvx dY95LbuszLYAf0N9eN+wsbOKYS+B5kgOO++/yJb3V1F/DL1sJf5R1uuSH/7+5Y2qvyXyiviGuMV /MYfdukRa+wkr1rUwlOw== X-Received: by 2002:a05:622a:5588:b0:516:d4b1:48cc with SMTP id d75a77b69052e-5173a5b4efbmr215705171cf.8.1780391540620; Tue, 02 Jun 2026 02:12:20 -0700 (PDT) X-Received: by 2002:a05:622a:5588:b0:516:d4b1:48cc with SMTP id d75a77b69052e-5173a5b4efbmr215704941cf.8.1780391540253; Tue, 02 Jun 2026 02:12:20 -0700 (PDT) Received: from yongmou2.ap.qualcomm.com (Global_NAT1_IAD_FW.qualcomm.com. [129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-51768c76e53sm12480851cf.4.2026.06.02.02.12.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 02:12:19 -0700 (PDT) From: Yongxing Mou Date: Tue, 02 Jun 2026 17:11:24 +0800 Subject: [PATCH v6 12/15] drm/msm/dp: simplify link and clock disable sequence Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260602-dp_mstclean-v6-12-2c17ff40a9b2@oss.qualcomm.com> References: <20260602-dp_mstclean-v6-0-2c17ff40a9b2@oss.qualcomm.com> In-Reply-To: <20260602-dp_mstclean-v6-0-2c17ff40a9b2@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Dmitry Baryshkov X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780391476; l=1745; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=4TJKG8RTz4R+dv3UNXgRl/mjeEf45SUuZJzked/IkbU=; b=ox1G7nychJ7oiBzA35Qma6lzidQKD+nkk6+TZgyPQArcq3cOd+PwVMakMQT4j5LHOjZb+smiV 9CGT1edwi8UCq2Zn53qsPUrVFxLMT3ox/KsmqBNE7QmpzHyHPCKA4pc X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjAyMDA4NiBTYWx0ZWRfX7jVU1ceXFjwl WwzpyVKYSXdaZTYw3QLzkKtxRaa9HVAHai4UUH78MNYwuJoJ09T+BpyTiFpI1FZs+a7evT7oRk+ AuqynWQQ9QH9Oswt2G0y3ZEpwn52ipz/BmBjUYnhnm3x6ruCowerugvSkWlMYcFNcjUVqUffqi+ bEKeuAFRUutbQkQcc38ikWishmB4Lk+fU8ja6lw9G8KR56xEhMQGoToNKLKSXR5xU/YYd6W6HSa indWGqZA+B3XhSe15R9dEZx5t0nB33SJelxxA9ZDOCG25YLDkuwL6g1QTD+wnEroxokRcwXp6ZG ++H/flV0oNSagk7wSiowkhoAq27xjVoCnUhaDHpcEClnCMVqbYaqGv54+fyPKFAmUxLcaYh5/cN 6ZegnVysmWRclXP7qPgORqWXi/gINZwIQEfv4yXw5iVdAXiMJUg2f/t7xFVHLbEWQvvdghgdZUw NABjeNhQfq1gMGneQsA== X-Authority-Analysis: v=2.4 cv=d5nFDxjE c=1 sm=1 tr=0 ts=6a1e9e75 cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=W1j8KJVysGQzs9t885kA:9 a=QEXdDO2ut3YA:10 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-ORIG-GUID: 28fyyF6h85XRg1Rly_VIqBbXjc9i170u X-Proofpoint-GUID: 28fyyF6h85XRg1Rly_VIqBbXjc9i170u X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-01_07,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 malwarescore=0 clxscore=1015 adultscore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606020086 Move the common disable steps out of the sink_count check to make the flow easier to follow. No functional change intended. Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_display.c | 26 +++++++++----------------- 1 file changed, 9 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 8f472633da82..63e5b191f95c 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -716,27 +716,19 @@ static int msm_dp_display_disable(struct msm_dp_displ= ay_private *dp) =20 msm_dp_panel_disable_vsc_sdp(dp->panel); =20 - /* dongle is still connected but sinks are disconnected */ - if (dp->link->sink_count =3D=3D 0) { - /* - * irq_hpd with sink_count =3D 0 - * hdmi unplugged out of dongle - */ + msm_dp_ctrl_off_pixel_clk(dp->ctrl); =20 - /* set dongle to D3 (power off) mode */ + /* dongle is still connected but sinks are disconnected */ + if (dp->link->sink_count =3D=3D 0) msm_dp_link_psm_config(dp->link, &dp->panel->link_info, true); - msm_dp_ctrl_off_pixel_clk(dp->ctrl); - msm_dp_ctrl_off_link(dp->ctrl, dp->panel); + + msm_dp_ctrl_off_link(dp->ctrl, dp->panel); + + if (dp->link->sink_count =3D=3D 0) + /* re-init the PHY so that we can listen to Dongle disconnect */ msm_dp_ctrl_reinit_phy(dp->ctrl); - } else { - /* - * unplugged interrupt - * dongle unplugged out of DUT - */ - msm_dp_ctrl_off_pixel_clk(dp->ctrl); - msm_dp_ctrl_off_link(dp->ctrl, dp->panel); + else msm_dp_display_host_phy_exit(dp); - } =20 msm_dp_display->power_on =3D false; =20 --=20 2.43.0 From nobody Mon Jun 8 04:25:38 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7338B3D25B4 for ; Tue, 2 Jun 2026 09:12:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780391549; cv=none; b=IlPfnHcaAA22gw+zL+oRLZ902e9zxmQpnwaYHrH7Ukfp0k0ilhf2hQd3iaR0YyTGdZH80+yFD1cun9xatyadx+VKfs8GGGyR6iIXGRXXBJcPP265wL+lFOSMwTxYI1PXeX85SMU34Ogu6JeIZJcAMeK1Zln1Edd2BXUg1vJIm+w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780391549; c=relaxed/simple; bh=rHOJ/Tfly+p+zzltozyn9wJCqcj0lLLdlbTm8fgeIJ0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=br2pNuZ7gd2KT5OViKJcRgC9z4SiZ3RN8Mdv9QOMkP3bP0FPSv1VyklGucYC4J6Y0dYg1hEyPCUtRP/T7UIvE/xUDJKlFW0bV9Os/pn5tjihw7IUGsOc1jK7vXRW2r5KPQKK7YAmZ3Eq10T9Dd7VnlCVIVo+ibQG+5OIENDuOhM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=P41Qh0UB; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=DVkTJDM4; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="P41Qh0UB"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="DVkTJDM4" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 6525iosH1316218 for ; Tue, 2 Jun 2026 09:12:27 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= PrpKel4Av768jUzNR25shjZmFALdbmxo17UJsOuCq8E=; b=P41Qh0UBJwUMVqAH +WeQYemVTDFeIzz70XPe1rSvikEx0j/H2iFo6Ncy+IO0JtUewsvD7tNMbuDjd2D0 gpd0IlJ8zQil0/eGAXTnpgDVz2Z+MQhUeAPCczBco/XY6N3W2Okskto2F3ZnCGLt hUfYM2XCv/x4HbOWeXOWlsb2xfd02x3145thAjy1dj3E6tQVsOFKhBRB/OAxHVX/ j1l5qGd/7XSrWuIrAf/WVAaevTXfUysvc+dbei5zyPaqeXMZAnObYovvjFlBXfBj +ZQ2SOUHgZvrl9cTRcGTD2tJeOuDGgTt5013+LJzcA+QJctay9/qgDj6pggtqpQ4 mSNiWg== Received: from mail-qt1-f198.google.com (mail-qt1-f198.google.com [209.85.160.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ehs9vruh0-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 02 Jun 2026 09:12:26 +0000 (GMT) Received: by mail-qt1-f198.google.com with SMTP id d75a77b69052e-516d6cf547bso48394391cf.3 for ; Tue, 02 Jun 2026 02:12:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1780391546; x=1780996346; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=PrpKel4Av768jUzNR25shjZmFALdbmxo17UJsOuCq8E=; b=DVkTJDM4KGaRzbLOUIkOdL/ugYAp7TNLYiiRVjOpokDO3Uui3mbyoAbqyyW+ZxCEB/ UPZaqh2tytYcXd7e9CSU3QxcaZtXuCg9TDRPeHPwh4U0+6fXsg9jIyuPb5gZbnWmNizI sILdPWFBhTDRYkBCTSsaio4jDPiKcMmOy9TW428WFctIEGJlzJAP7deRa6TB2pNEOGZt piMdjOXZ2ZGB0RTsVDgE6+TxFHny21xgFbbcwy7ushd7QeYoRQgH20BO8aD9WeqSXx8x +VG25ZGTP03hjpT3RypevC9xlLsov9s3aqoWzr1d6uSKkdLOQ6UfmiNzC4kdU4LrF1MG 25GA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1780391546; x=1780996346; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=PrpKel4Av768jUzNR25shjZmFALdbmxo17UJsOuCq8E=; b=iF4JOWWOG5me8lrW/585K2JBfzDM0lJUm1JTmsVJK+xC/yDouj+zu2A7cCtszFzjqN rsY3KjqaWZCViL+k1sABuFBOOmp1Zn9tZA02GwoJZBhccx/NlS3YGmDthSyFMZZIaVX0 AL/cG0iShpH3x7bq5cJmrRG520TodzumvjZBRw4YnmzRMvbLPgYqUCCBQwrAJWr6AJg9 1bHaUAoJLoRm7hcZy8t4yPh8/O8M5cNSTkom/5+ep3cNeRQWTtEgqgceWMK9yV/LfImi 21y/CPiaIn6ZHaoabLQodJBe2dWl8rPs3agrDt2guYyMFmYMW30NiNSaZcSVjxPQpzC2 YllQ== X-Forwarded-Encrypted: i=1; AFNElJ9R7tPb9/q3VeQ+lXXvFcc/yNbLKJ95KXEHMpKAK/U1OL4Z81jfGZSMbBrhj3gEH7paBWFzj3acl8dqQnk=@vger.kernel.org X-Gm-Message-State: AOJu0Yzl7MyoMKk6R9ifzxWRkRTOHHlFEtAWfwQw7UGFN7FUKSk20Imb LL2MIZGFywvH3pjlA5eSWOxkHowYUDH4aV7ljVtVYOwAKhmFRZF4AHQ1K6JXc0yZMiv2VRf1PRc bC8zuWETde+pJ5+l7U8CfVOBtvCBE5CIvhZUBYuJEiNAvrg5mY5s17oLVayD4KlSHKG0= X-Gm-Gg: Acq92OHKlp6V3+dB2/pCo3pXfVmyIqLangPBkhPfznfkwMFmmVQQtTHgmSc7GKKMTVY CUve7+6ZcysFmhHZZs0dfBt9CmOU+hTAfoUZL5jyVA1YNZ/e4lr4LP+G51jo8lEkA+5Wrkn2aak aumkHBFNqOdlc06MO25zjDRFiQAUtqoPg/JwtC6Rs6qK2k4SRbLhpGSJkr7jpL3eTJJkqItCHg+ a+jEZP0b4l7wJJqbzB79uqatBl4gwkellCs9aDRSowlxjwVcU0os0G8RYJj19zySYG2hTU8miOF Nmb5lwhES3Q9Z0ywr1cfBSA/H9+QYHKXQrIa2+FYjiRS1sn0x4w+7ZYtYx+YvBs92ZwAUQSMNoz DhOQUKl6hdhYGvstrC8Rmt1faEJ2bD0fodjOzivUE18vpHuXRxrY0y1tHNeiEQwggRw2RqDPTHr 1Wo1XnzeM1XY6oHFB1lw== X-Received: by 2002:a05:622a:418a:b0:516:c8ec:5f67 with SMTP id d75a77b69052e-5173a84a3f1mr198592631cf.56.1780391545631; Tue, 02 Jun 2026 02:12:25 -0700 (PDT) X-Received: by 2002:a05:622a:418a:b0:516:c8ec:5f67 with SMTP id d75a77b69052e-5173a84a3f1mr198592131cf.56.1780391545156; Tue, 02 Jun 2026 02:12:25 -0700 (PDT) Received: from yongmou2.ap.qualcomm.com (Global_NAT1_IAD_FW.qualcomm.com. [129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-51768c76e53sm12480851cf.4.2026.06.02.02.12.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 02:12:24 -0700 (PDT) From: Yongxing Mou Date: Tue, 02 Jun 2026 17:11:25 +0800 Subject: [PATCH v6 13/15] drm/msm/dp: make bridge helpers use dp_display to allow re-use Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260602-dp_mstclean-v6-13-2c17ff40a9b2@oss.qualcomm.com> References: <20260602-dp_mstclean-v6-0-2c17ff40a9b2@oss.qualcomm.com> In-Reply-To: <20260602-dp_mstclean-v6-0-2c17ff40a9b2@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Abhinav Kumar , Dmitry Baryshkov X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780391476; l=8509; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=js7Ds0kDP3MA2PA3qJwTal/QoxqVBRyKdoKt/vuLT7c=; b=ZIKUZVz4daNTz0P7bthYlY4nnsEdqpv9D4FX1PiLsqSkdPb+Ap4IAbCOx2h0GKWct4PCbB+Eg gACCsLNcWNdCcbNqO9aJtUKjhurRfJLyZAEGoCcgEQSArxbs8jLgRgi X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-GUID: PDSWFNEWKeRC6_qQeYgGN2wRYDFFm1JY X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjAyMDA4NiBTYWx0ZWRfX8KDVYsWEZ6EF dzwq3n2Aqjwu9RA/b7WhBWuhBZPe5DmTSkIIsyaJoZxVHwLs3bkcKMLRfqsXwoDn25+m9TP//Q1 hSZwprYfplwZaWpm2gn8DAZ9Eq9JsKnQJmVhbv4+w08UOfSQKhUa4ZWahfjym7ENHJUDtMWNbYx WMKnY3VY5iK3OId6nHEtwMGqcnoohV09Nthu8NGODaZuJsR3KvpvmmBY3nqUUwEPy+xdV8FmaMd 9nOyhIm7VJBb4jzeSYY0oVKq4tQq+9JiyR6h4Sp94yNKZIIGQuxEIF+eYa98kybr0sKA1HGbK60 cCh6hFDuls/8GE/5VXMzbS/kG2aJLpd6h/PqaX+MoIqF4vMctKiO/TR1TaeKbx617xOE3WeW89I rsFsETjy4luKH5FdpLNTdTAKULD6nT9zbKWwuUG6d94KO6NP8GNDeNjZ34Qjysftf1mEz925TnX xmQn3j4Jx8C/H0xJ9Zw== X-Authority-Analysis: v=2.4 cv=NYfWEWD4 c=1 sm=1 tr=0 ts=6a1e9e7a cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=LmD7BKvqrCyCckpIDn8A:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: PDSWFNEWKeRC6_qQeYgGN2wRYDFFm1JY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-01_07,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 clxscore=1015 suspectscore=0 priorityscore=1501 phishscore=0 impostorscore=0 bulkscore=0 lowpriorityscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606020086 From: Abhinav Kumar dp_bridge helpers take drm_bridge as an input and extract the dp_display object to be used in the dp_display module. Rather than doing it in a roundabout way, directly pass the dp_display object to these helpers so that the MST bridge can also re-use the same helpers. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_display.c | 29 +++++++++------------------ drivers/gpu/drm/msm/dp/dp_display.h | 7 +++++++ drivers/gpu/drm/msm/dp/dp_drm.c | 39 +++++++++++++++++++++++++++++++++= +++- drivers/gpu/drm/msm/dp/dp_drm.h | 9 --------- 4 files changed, 54 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 63e5b191f95c..2d5ef087648c 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -738,24 +738,21 @@ static int msm_dp_display_disable(struct msm_dp_displ= ay_private *dp) =20 /** * msm_dp_bridge_mode_valid - callback to determine if specified mode is v= alid - * @bridge: Pointer to drm bridge structure + * @dp: Pointer to dp display structure * @info: display info * @mode: Pointer to drm mode structure * Returns: Validity status for specified mode */ -enum drm_mode_status msm_dp_bridge_mode_valid(struct drm_bridge *bridge, - const struct drm_display_info *info, - const struct drm_display_mode *mode) +enum drm_mode_status msm_dp_display_mode_valid(struct msm_dp *dp, + const struct drm_display_info *info, + const struct drm_display_mode *mode) { const u32 num_components =3D 3, default_bpp =3D 24; struct msm_dp_display_private *msm_dp_display; struct msm_dp_link_info *link_info; u32 mode_rate_khz =3D 0, supported_rate_khz =3D 0, mode_bpp =3D 0; - struct msm_dp *dp; int mode_pclk_khz =3D mode->clock; =20 - dp =3D to_dp_bridge(bridge)->msm_dp_display; - if (!dp || !mode_pclk_khz || !dp->connector) { DRM_ERROR("invalid params\n"); return -EINVAL; @@ -1406,11 +1403,9 @@ int msm_dp_modeset_init(struct msm_dp *msm_dp_displa= y, struct drm_device *dev, return 0; } =20 -void msm_dp_bridge_atomic_enable(struct drm_bridge *drm_bridge, - struct drm_atomic_commit *state) +void msm_dp_display_atomic_enable(struct msm_dp *msm_dp_display, + struct drm_atomic_commit *state) { - struct msm_dp_bridge *msm_dp_bridge =3D to_dp_bridge(drm_bridge); - struct msm_dp *msm_dp_display =3D msm_dp_bridge->msm_dp_display; struct drm_crtc *crtc; struct drm_crtc_state *crtc_state; int rc =3D 0; @@ -1419,7 +1414,7 @@ void msm_dp_bridge_atomic_enable(struct drm_bridge *d= rm_bridge, dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 crtc =3D drm_atomic_get_new_crtc_for_encoder(state, - drm_bridge->encoder); + msm_dp_display->bridge->encoder); if (!crtc) return; crtc_state =3D drm_atomic_get_new_crtc_state(state, crtc); @@ -1449,11 +1444,8 @@ void msm_dp_bridge_atomic_enable(struct drm_bridge *= drm_bridge, drm_dbg_dp(msm_dp_display->drm_dev, "type=3D%d Done\n", msm_dp_display->c= onnector_type); } =20 -void msm_dp_bridge_atomic_disable(struct drm_bridge *drm_bridge, - struct drm_atomic_commit *state) +void msm_dp_display_atomic_disable(struct msm_dp *dp) { - struct msm_dp_bridge *msm_dp_bridge =3D to_dp_bridge(drm_bridge); - struct msm_dp *dp =3D msm_dp_bridge->msm_dp_display; struct msm_dp_display_private *msm_dp_display; =20 msm_dp_display =3D container_of(dp, struct msm_dp_display_private, msm_dp= _display); @@ -1470,11 +1462,8 @@ static void msm_dp_display_unprepare(struct msm_dp_d= isplay_private *dp) drm_dbg_dp(dp->drm_dev, "type=3D%d Done\n", msm_dp_display->connector_typ= e); } =20 -void msm_dp_bridge_atomic_post_disable(struct drm_bridge *drm_bridge, - struct drm_atomic_commit *state) +void msm_dp_display_atomic_post_disable(struct msm_dp *dp) { - struct msm_dp_bridge *msm_dp_bridge =3D to_dp_bridge(drm_bridge); - struct msm_dp *dp =3D msm_dp_bridge->msm_dp_display; struct msm_dp_display_private *msm_dp_display; =20 msm_dp_display =3D container_of(dp, struct msm_dp_display_private, msm_dp= _display); diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/d= p_display.h index 0b65e16c790d..5116f7bbbd02 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -33,5 +33,12 @@ void msm_dp_display_signal_audio_start(struct msm_dp *ms= m_dp_display); void msm_dp_display_signal_audio_complete(struct msm_dp *msm_dp_display); void msm_dp_display_set_psr(struct msm_dp *dp, bool enter); void msm_dp_display_debugfs_init(struct msm_dp *msm_dp_display, struct den= try *dentry, bool is_edp); +void msm_dp_display_atomic_post_disable(struct msm_dp *dp_display); +void msm_dp_display_atomic_disable(struct msm_dp *dp_display); +void msm_dp_display_atomic_enable(struct msm_dp *dp_display, + struct drm_atomic_commit *state); +enum drm_mode_status msm_dp_display_mode_valid(struct msm_dp *dp, + const struct drm_display_info *info, + const struct drm_display_mode *mode); =20 #endif /* _DP_DISPLAY_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_dr= m.c index 6ac5bac903d9..6b8923d9dff4 100644 --- a/drivers/gpu/drm/msm/dp/dp_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_drm.c @@ -49,6 +49,43 @@ static void msm_dp_bridge_debugfs_init(struct drm_bridge= *bridge, struct dentry msm_dp_display_debugfs_init(dp, root, false); } =20 +static void msm_dp_bridge_atomic_enable(struct drm_bridge *drm_bridge, + struct drm_atomic_commit *state) +{ + struct msm_dp_bridge *dp_bridge =3D to_dp_bridge(drm_bridge); + struct msm_dp *dp =3D dp_bridge->msm_dp_display; + + msm_dp_display_atomic_enable(dp, state); +} + +static void msm_dp_bridge_atomic_disable(struct drm_bridge *drm_bridge, + struct drm_atomic_commit *state) +{ + struct msm_dp_bridge *dp_bridge =3D to_dp_bridge(drm_bridge); + struct msm_dp *dp =3D dp_bridge->msm_dp_display; + + msm_dp_display_atomic_disable(dp); +} + +static void msm_dp_bridge_atomic_post_disable(struct drm_bridge *drm_bridg= e, + struct drm_atomic_commit *state) +{ + struct msm_dp_bridge *dp_bridge =3D to_dp_bridge(drm_bridge); + struct msm_dp *dp =3D dp_bridge->msm_dp_display; + + msm_dp_display_atomic_post_disable(dp); +} + +static enum drm_mode_status msm_dp_bridge_mode_valid(struct drm_bridge *dr= m_bridge, + const struct drm_display_info *info, + const struct drm_display_mode *mode) +{ + struct msm_dp_bridge *dp_bridge =3D to_dp_bridge(drm_bridge); + struct msm_dp *dp =3D dp_bridge->msm_dp_display; + + return msm_dp_display_mode_valid(dp, info, mode); +} + static const struct drm_bridge_funcs msm_dp_bridge_ops =3D { .atomic_duplicate_state =3D drm_atomic_helper_bridge_duplicate_state, .atomic_destroy_state =3D drm_atomic_helper_bridge_destroy_state, @@ -115,7 +152,7 @@ static void msm_edp_bridge_atomic_enable(struct drm_bri= dge *drm_bridge, return; } =20 - msm_dp_bridge_atomic_enable(drm_bridge, state); + msm_dp_display_atomic_enable(dp, state); } =20 static void msm_edp_bridge_atomic_disable(struct drm_bridge *drm_bridge, diff --git a/drivers/gpu/drm/msm/dp/dp_drm.h b/drivers/gpu/drm/msm/dp/dp_dr= m.h index 4bd788ea05d5..da412c788503 100644 --- a/drivers/gpu/drm/msm/dp/dp_drm.h +++ b/drivers/gpu/drm/msm/dp/dp_drm.h @@ -27,15 +27,6 @@ int msm_dp_bridge_init(struct msm_dp *msm_dp_display, st= ruct drm_device *dev, =20 enum drm_connector_status msm_dp_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector); -void msm_dp_bridge_atomic_enable(struct drm_bridge *drm_bridge, - struct drm_atomic_commit *state); -void msm_dp_bridge_atomic_disable(struct drm_bridge *drm_bridge, - struct drm_atomic_commit *state); -void msm_dp_bridge_atomic_post_disable(struct drm_bridge *drm_bridge, - struct drm_atomic_commit *state); -enum drm_mode_status msm_dp_bridge_mode_valid(struct drm_bridge *bridge, - const struct drm_display_info *info, - const struct drm_display_mode *mode); void msm_dp_bridge_hpd_enable(struct drm_bridge *bridge); void msm_dp_bridge_hpd_disable(struct drm_bridge *bridge); void msm_dp_bridge_hpd_notify(struct drm_bridge *bridge, --=20 2.43.0 From nobody Mon Jun 8 04:25:38 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A7743D16F9 for ; Tue, 2 Jun 2026 09:12:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780391554; cv=none; b=jkMXqMYph1Sf4zxuRYofpyx8i1J3+sEJH7dmSUPGfIlbhpQZKECrMtlABKH3mxVV3sESLu1sMrHWnkicDiHSEm1esz82peAZXnvfTRmg4ayRFO+Q3HqRK82rUpoL0Me4YYN2Vmgu9+oPThRexGu5nDH25jRQwZAxZe7muwxXo08= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780391554; c=relaxed/simple; bh=da4DiLmkH54vMKs4+UHrFXYyvX9aCG9OfWIw37ym+Ew=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=leDcSxsx61G7E5z/+bjQLpSg/utEqlRRQHHTNai8O8Q9W08XkqpBIpA3DfBdCGyrc8uJ+7xR1l+62P+2EfxC6b8lazxPB/+sluFHyGtjmvtVgzdjzHxzcQSuxsdsMZ9PlCffrvCh5hkLyLs5SARPeJfepBjyzq4u/r7+yA/gvi8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=eBhbMY4a; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=bQ7xDYtO; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="eBhbMY4a"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="bQ7xDYtO" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 6527gi4k1638282 for ; Tue, 2 Jun 2026 09:12:32 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 4GLG60vKqqPhXSK9u7LFSK5eRlVCZiWpAvGD6R5I4zI=; b=eBhbMY4aeciroODC ciMEQgeG4o3hgcWsdrGbIzXENThOO9YJVvnDQqAo0ezoGf8S8Md1UWnacr/w4jWo JQTJG5So91z1K7YR3Vgp+J2wmP5KYffqRPQ9OYOoRJh8tkaFU7+O/TYNKA0ENib4 h47hzLobhlqUw3xR0nKc3kxqKTaEubVPNhtXQifhskY/Pb2K/gI7kh9dDYZ35Bxe kCnIuaKO4xU0ItxsSVquH5ISRmr0s5yxht8bpVDsBxrKvNetcYiZqohwLECJaDpd +1XbNTeZMysXuCR9qCeoUdpVpbaH/YCgJCOuPYSzPWXG4dotl7znhhivOiMCtGQF sfEz1w== Received: from mail-qv1-f69.google.com (mail-qv1-f69.google.com [209.85.219.69]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ehu1cgc6a-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 02 Jun 2026 09:12:32 +0000 (GMT) Received: by mail-qv1-f69.google.com with SMTP id 6a1803df08f44-8ccf62978bfso71249256d6.1 for ; Tue, 02 Jun 2026 02:12:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1780391551; x=1780996351; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=4GLG60vKqqPhXSK9u7LFSK5eRlVCZiWpAvGD6R5I4zI=; b=bQ7xDYtOu4e0DmdGrFc4XrABzx4QQ3E7+yJb1L7rN5QjaSBTF5PJuNZwzQtV6QSGdZ 6LKx3/Vyj+RzepqaElNjLCskJzM57VNCHeGfCPpaLgGyH+XPMAzel05q0SuPzUraagIc XuK/Ii5aClvI/1uIKMRXgrEGd5mllAayyPRAxBTa1AvH1gWMaFdnY9+zxAdQd2l4BPQx 6RDASSCnXFTJO+o8CLUfiD9GfVTC0p3aHsubcVoOHpTBNRi1gUPlfBNDHqYWFL+serBy nASDDkLM6PuMEQqRbq6UqenRF5Ge5pDOlukmPnwVsVuohgmeZVCM3YkCaemP8Y7Ya954 Yquw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1780391551; x=1780996351; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=4GLG60vKqqPhXSK9u7LFSK5eRlVCZiWpAvGD6R5I4zI=; b=liUCE6u8oQ6V/bwE+KNEc71FFAA4jKOKRE7FTv9Fyzs02DvI8yzmp1tQGUm6IJ4qih fAYCfUgaCBu6PN/YYz4zOez0gTWn+ztmruvPVN5VAhekjKfZlZMaIf09Ok5bXB0CBZn/ r2XpCVyGax83BTFuBi6B9QP/GrD9gJMPKNJswWbLPZfs2xTs5W19W6wiRY0X8GoKWbZi VfwJzfc80XiRxp9Bm+8EWy1ms46Gpp5ZBVAHYmWQFOkk5wZVkacPA7jIwNoabfNX40WB merP4fclPHQ47zuwt3hazUOGpV7D6+rg6H2cbFu/9aLE1u7sSa78xenSdu4RUZt6FE0Q ruMQ== X-Forwarded-Encrypted: i=1; AFNElJ/D4OS6QHTTq/8d/ygYwAmiTpb0xuLHs3CJEPsfoVOMoxFopxtg369ShUAEPNOff60TiIbmlxy0sCYOmv0=@vger.kernel.org X-Gm-Message-State: AOJu0YyLA+Ykw7q8iJcaUhveuFQMHsqjdPnbQ1WB8/T8zMuWw3nHUlWZ PPGyY9YHAObi+kcfrSIx/fQIjQ1zLIIhKfVx3gkaBGwZyQz27+KOd9uIl5Nbm4JH5IEt4aOeSS+ AOaxfGMu2w3lE0TJMcQEuXOPCVPd94eMn4BAkSmDybW8BhUmczhGFyEMIFgaXNY5cfJI= X-Gm-Gg: Acq92OF7MYX1LlU+j1p6Smotj8jmYsvKu3W546ekH8dDLxr1hijVvGaTdMMM2iHS9qU QztWXfLJW7wJxlGLxMcfuzDcpyJRnEazwp/NYqjgsplLgoAGkabB1kS5eF1BmJqf8pAaR4raZ6M qVgxFOxBw5aBzXQJOrtOA5K34T/0LPf769gQ6XIwMrp+WrBhDW+DNsdmJZV8AjiR+mTP+HyeCmM mLUL2nlRiz+Tz/mhnJ+o7V6mXd+m5Sh/fkjY8T6+I5KFoNYBKp+VtXcVFURzUxDQsO2C2GrrkX3 /PTCXK0UiZ2Qnbdxqa//rhLRmO4QTXJed+q3Yw6mKb+O9wwUaAGMeo+ViaQzR2qpIFRhwpmCvmt NsnPrrEVK77Q59lWSxu59fJPfmFnQOCxaF25MGEbb7Vq93QaEvoB1b56uJTJrtix1NHlvqICSyN WC30jo7vE4nqunn/qg4Q== X-Received: by 2002:a05:622a:a6d5:b0:516:de98:b670 with SMTP id d75a77b69052e-5173a935333mr173922381cf.39.1780391551279; Tue, 02 Jun 2026 02:12:31 -0700 (PDT) X-Received: by 2002:a05:622a:a6d5:b0:516:de98:b670 with SMTP id d75a77b69052e-5173a935333mr173922081cf.39.1780391550806; Tue, 02 Jun 2026 02:12:30 -0700 (PDT) Received: from yongmou2.ap.qualcomm.com (Global_NAT1_IAD_FW.qualcomm.com. [129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-51768c76e53sm12480851cf.4.2026.06.02.02.12.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 02:12:30 -0700 (PDT) From: Yongxing Mou Date: Tue, 02 Jun 2026 17:11:26 +0800 Subject: [PATCH v6 14/15] drm/msm/dp: separate dp_display_prepare() into its own API Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260602-dp_mstclean-v6-14-2c17ff40a9b2@oss.qualcomm.com> References: <20260602-dp_mstclean-v6-0-2c17ff40a9b2@oss.qualcomm.com> In-Reply-To: <20260602-dp_mstclean-v6-0-2c17ff40a9b2@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Abhinav Kumar , Dmitry Baryshkov X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780391476; l=3743; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=PejPis5lPUmTa0t10X2rGcGnHfGkWszn1oUEuwhLLv0=; b=I+18ZOiJ7T4ONemocEPsWLpHYt0H8WenXnbhVc6cN2xPFnXd5W9vUP4XU5Q4tlH8EdE14UKkY WrAY17QYSsIBRzi2C83dmPZfd1OI9JGrW1Z8NpFjKazrt8mnysyNXsD X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-ORIG-GUID: q4NpRDzwQD6fO6080qkY5MI3OU6oYXd- X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjAyMDA4NiBTYWx0ZWRfX74Omy9n9vJOQ eN7ye4xhaZBFxQh0by+HA5tQNOp1dqGaxrqAaZTbmqF9yG/CmBRqoKjlNmS8tT/IJ5fwapjUDnx nR38bnawKvriX4c2PIZencEkY5ZsDstBnZqfYP76zfqXBSX0nO2YLIV0O1wPuRHoiTJg/s1lG0T u9DKRPUO7iDg1rU4IJzOUwEmKrX2UNmOWkMgtFbe6aLUie4hxjt/2tfWN2QLo6WQdFCQsPnjVY2 6Zk5WCcDYqmXYg8FMRGpWFfrQsHpvG9ZN8OKLuAhrVQ/xNylVmUrNxON3x9wVBAlrHredhhQ1Br Pe+yv6O+D/qPVkXAduFHx2+SLrYkVCpcjsrHqOx+HQQw/vdRo6r9PAswloxuZ2Uu6T4lfYhra/l zmzte3r9+X02c9ssbxsYK5XqJ1y/Y83McqHhgnPWOXzpnb/q61RxSKHhXtgfzHKxpi0Lr+0XoG/ wSBZqhydCj2B/RR5TRQ== X-Proofpoint-GUID: q4NpRDzwQD6fO6080qkY5MI3OU6oYXd- X-Authority-Analysis: v=2.4 cv=O6IJeh9W c=1 sm=1 tr=0 ts=6a1e9e80 cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=rHTcTV9uYuKpyGuOXCsA:9 a=QEXdDO2ut3YA:10 a=OIgjcC2v60KrkQgK7BGD:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-01_07,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 bulkscore=0 malwarescore=0 lowpriorityscore=0 impostorscore=0 spamscore=0 adultscore=0 phishscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606020086 From: Abhinav Kumar For MST, the link setup should only be done once when multiple sinks are enabled, while stream setup may run multiple times for each sink. Split the link-related preparation out of msm_dp_display_atomic_enable() so it can be called separately before the per-stream enable path. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_display.c | 16 +++++++++++----- drivers/gpu/drm/msm/dp/dp_display.h | 5 +++-- drivers/gpu/drm/msm/dp/dp_drm.c | 6 ++++-- 3 files changed, 18 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 2d5ef087648c..cd1f2899b733 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -1403,8 +1403,8 @@ int msm_dp_modeset_init(struct msm_dp *msm_dp_display= , struct drm_device *dev, return 0; } =20 -void msm_dp_display_atomic_enable(struct msm_dp *msm_dp_display, - struct drm_atomic_commit *state) +void msm_dp_display_atomic_prepare(struct msm_dp *msm_dp_display, + struct drm_atomic_commit *state) { struct drm_crtc *crtc; struct drm_crtc_state *crtc_state; @@ -1426,10 +1426,16 @@ void msm_dp_display_atomic_enable(struct msm_dp *ms= m_dp_display, } =20 rc =3D msm_dp_display_prepare_link(dp); - if (rc) { + if (rc) DRM_ERROR("DP display prepare failed, rc=3D%d\n", rc); - return; - } +} + +void msm_dp_display_atomic_enable(struct msm_dp *msm_dp_display) +{ + struct msm_dp_display_private *dp; + int rc =3D 0; + + dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 rc =3D msm_dp_display_enable(dp); if (rc) diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/d= p_display.h index 5116f7bbbd02..43ed79093e24 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -35,8 +35,9 @@ void msm_dp_display_set_psr(struct msm_dp *dp, bool enter= ); void msm_dp_display_debugfs_init(struct msm_dp *msm_dp_display, struct den= try *dentry, bool is_edp); void msm_dp_display_atomic_post_disable(struct msm_dp *dp_display); void msm_dp_display_atomic_disable(struct msm_dp *dp_display); -void msm_dp_display_atomic_enable(struct msm_dp *dp_display, - struct drm_atomic_commit *state); +void msm_dp_display_atomic_prepare(struct msm_dp *dp_display, + struct drm_atomic_commit *state); +void msm_dp_display_atomic_enable(struct msm_dp *dp_display); enum drm_mode_status msm_dp_display_mode_valid(struct msm_dp *dp, const struct drm_display_info *info, const struct drm_display_mode *mode); diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_dr= m.c index 6b8923d9dff4..4bf1a5b7c3f9 100644 --- a/drivers/gpu/drm/msm/dp/dp_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_drm.c @@ -55,7 +55,8 @@ static void msm_dp_bridge_atomic_enable(struct drm_bridge= *drm_bridge, struct msm_dp_bridge *dp_bridge =3D to_dp_bridge(drm_bridge); struct msm_dp *dp =3D dp_bridge->msm_dp_display; =20 - msm_dp_display_atomic_enable(dp, state); + msm_dp_display_atomic_prepare(dp, state); + msm_dp_display_atomic_enable(dp); } =20 static void msm_dp_bridge_atomic_disable(struct drm_bridge *drm_bridge, @@ -152,7 +153,8 @@ static void msm_edp_bridge_atomic_enable(struct drm_bri= dge *drm_bridge, return; } =20 - msm_dp_display_atomic_enable(dp, state); + msm_dp_display_atomic_prepare(dp, state); + msm_dp_display_atomic_enable(dp); } =20 static void msm_edp_bridge_atomic_disable(struct drm_bridge *drm_bridge, --=20 2.43.0 From nobody Mon Jun 8 04:25:38 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA1363D75A9 for ; Tue, 2 Jun 2026 09:12:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780391560; cv=none; b=KUCU6P7GtLynUuPi7MRZteXxFwZYL6q6ue7nrKs48kDx1z4NuiyHURog65lxsf72db6Cb5kytbDutQU73F8QSOHivvQ4/kyB4p6Ey1X8O/+GZ4usDL0Fl4la31SA5ZtpOmxUwPp4awqV1n02cMTd0gpQ799hzAL5Zy9CCZdAk6c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780391560; c=relaxed/simple; bh=VMCb+gh78a5tyRp4ocOtlXR3WU+MH0tKL5IrymVyK/Y=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=The0hRoMSpaQhQGMk7lTPVsFu4uLQ6oq0tvVf0A0PIxskM4+G6QYrmkOdyistUYvqvn6la/6n/6mgXJnXsGQJbl9zQ9GBiTp18sPFkgF1rt7PGJRSXr7fr4tky8zaoSGpCwn7iL3kxj/vY4ehkaLVyejIxedxnalOXvdB1mpTi4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=Fc1CDxdd; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=UMRZQPVq; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="Fc1CDxdd"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="UMRZQPVq" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 6527gSFu3302622 for ; Tue, 2 Jun 2026 09:12:36 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= CnGOml6KRNLCf8LNyNsT22xgMpxrnwiDol3PAO0B0Jw=; b=Fc1CDxddIHANP11x cRrB39iSWkuTIMR6zfUHAGGw4SrivL1gbg7MXGwYB9lWcSTyngO38iFuTZxKrhJL 5FSpCRhIIpJTN2k8v6J9266YJGA2uPEHImiBO2N3GnIvMxJiLAD4qcPYXpqcfBTd dXwhgvvYdCHe1lxgTnUAa5qmTauzhTPTPSxuEI5qLaIOvEelcrD31ADv9AfKQPhx 02OaSNPJ68clP+exldURvgZHYjx/w1iz7KrkLZi0GieEGIj19sgRx91XM3W20LVi OK2+aXg64y7DKgbO/O4j/TlzlRTNPKyvDh9fg2ovvSPaM4Vb6DynK9y0zOs7SLFr VnG8mQ== Received: from mail-qt1-f198.google.com (mail-qt1-f198.google.com [209.85.160.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ehu18gck0-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 02 Jun 2026 09:12:36 +0000 (GMT) Received: by mail-qt1-f198.google.com with SMTP id d75a77b69052e-5174e8642f5so48328621cf.1 for ; Tue, 02 Jun 2026 02:12:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1780391556; x=1780996356; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=CnGOml6KRNLCf8LNyNsT22xgMpxrnwiDol3PAO0B0Jw=; b=UMRZQPVqAquKSYT57tBLK5vi4RWjIR1eYUpERGeNspgaaARe2bsU6glzHLkcD0NIsn 6GfJc6G5VQqxHI7jURdV9sYH5GmlqiZSlZrPXb63IbUY3Bs2XDjCzmnRGHRCNu3Tl4jr X+6EJ4Ciah8lNxtMKI5l1eohTE7eNmFCytR4gqGvEXuhKpfRO5K6TLSstNy3F3S/YqHO 8e/3CcRIznmBKUt0VH6+wADHBlDnzqZKbRda1Ve+0z8E5BmWJZWn7cGIzIgTeD88GK5v tb0/nQGWXRlmt+gd1yEwfB3gTDYBNW7QuO1XROboUv3pWzxWGNRuy+fOMplUUW3fKTRC WB/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1780391556; x=1780996356; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=CnGOml6KRNLCf8LNyNsT22xgMpxrnwiDol3PAO0B0Jw=; b=GgapIGRlWIIwmusN0fbi0n7USMuC85T3gLEBw5IhBYBtx1kW9PcbrEduqIQQjWuv6l pqUSm+ZWp4Thwzdg98w9MpCaLH6Q78SdQYU9syXQH3Z49DxJpr/+o9+r7F9iGASVtEBK gqfMwysA6bB3jiJL/YYnkUX+MYjBdAT/+nonYRj6v7zFjGYxvv1OEWR8ntezpqRu6fME 5/IuGevo3kvUPBe1OUW9ralSCsnry86CB81zU0RCjb7aPAZagicy7EIM94dQE93Oh+U6 iRAGv22SRCghZQnYSB5fvd73pSZsHTeR4s+InXq9cwq6wq4M2eCqz9VkeMaSOfp+R+bo BTSQ== X-Forwarded-Encrypted: i=1; AFNElJ+eG0y7ET+zDVe9xzyCDNmnf4d+0qewWLfI2Fph4f58Abq8VuqWLcpKGtf73Ne+4v/RO/WaVGaCB5dpYk0=@vger.kernel.org X-Gm-Message-State: AOJu0YwecUXaOS960T9sf30n+lPozQRCLjEPt9T52dQA1bhTNdH+qpVJ M77wWAVq6TEFkTUeT3pqEFraz2dr0Af9rpm85gyiKwvTkHCQXYDKtw6C/0wFymAgwyB43c8D6oN Eoc0YIUstgFybdWSFpEmDyqlwLVQKKrOWzqEjod753kcF3o8I2SDtx/3mIQbmZfTiwCk= X-Gm-Gg: Acq92OG9MV3ufUhJfd3eNvdkG4bZP2fhumBAgpvid8qQazs1UUdYhNgiF59rR1ncQ+I sxBuTRMeJcG94rJdhyUj/yzfxOeRIF1dqBZPSGgs4M/4j9ww6CJnM41DIAufa5iD/x0Q9ZYApV/ a+xO7AaKdp+p9RQgdTyG5moLAmrC0wld3rP65270MKvKmY66tUpjeXKGpSYNNRF2dFaGTIEfYh3 uK0pVyQknwa2XNTKBKW00I+honORkVhxSTRdhjbO0OtqLSIRIjmcrpKlM/8cT7c3w78AdpWHOER Bc2QjVjl+sbMKYBOUNW+OUy7G0cez3ALNNlMlw0P5j2Qdi1ZNmmFVj8Beu8Q7xiBYmzaCYi65hk SZ/bCQGP71mhWPELoHNbFPzqRRxHGjCtpTrHj1eQCDw3QMxKUzORQWc4mfIb/dR9taXZxGvGVP4 DPIXOnYcUOVptSOy4IZg== X-Received: by 2002:ac8:5fc8:0:b0:517:7277:9362 with SMTP id d75a77b69052e-51772779863mr836901cf.48.1780391555979; Tue, 02 Jun 2026 02:12:35 -0700 (PDT) X-Received: by 2002:ac8:5fc8:0:b0:517:7277:9362 with SMTP id d75a77b69052e-51772779863mr836571cf.48.1780391555611; Tue, 02 Jun 2026 02:12:35 -0700 (PDT) Received: from yongmou2.ap.qualcomm.com (Global_NAT1_IAD_FW.qualcomm.com. [129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-51768c76e53sm12480851cf.4.2026.06.02.02.12.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 02:12:35 -0700 (PDT) From: Yongxing Mou Date: Tue, 02 Jun 2026 17:11:27 +0800 Subject: [PATCH v6 15/15] drm/msm/dp: pass panel to display enable/disable helpers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260602-dp_mstclean-v6-15-2c17ff40a9b2@oss.qualcomm.com> References: <20260602-dp_mstclean-v6-0-2c17ff40a9b2@oss.qualcomm.com> In-Reply-To: <20260602-dp_mstclean-v6-0-2c17ff40a9b2@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Dmitry Baryshkov X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780391476; l=3118; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=VMCb+gh78a5tyRp4ocOtlXR3WU+MH0tKL5IrymVyK/Y=; b=+MxUWsyBnARoL5Z62MZhRAt4ecZNYa9xBG7vgztbTLl60v1elrbRh/WmVoBaLvyQOPEGYmlxT oJC7G1JLVSwC58blLYJYerJpyqtOgCMZPtAfv7p4fQtZmrgohyS1pj1 X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Authority-Analysis: v=2.4 cv=POA/P/qC c=1 sm=1 tr=0 ts=6a1e9e84 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=wgkWW237A_BUGFCT6doA:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjAyMDA4NiBTYWx0ZWRfXxnxie+oxTiR9 3uM8whhZilxXpGssE2IvU07eJOwThPFS9LOwcTMuXZuFnO/gSFp2e7v4vjMkB8sQFlYZdVAb/wg XPw6fESACKmWjYdEY3QHkbSgp9LkfLfw9HWqMmpY6rmnqdYZ52fYrrA0g1I8dcssm9tfMEp0+kV 0VfNlBHvCnFIsaNOhkuJgyGyjpWK3PwUYWsMY379aheA6rtiDgrMufrQx0y/58T+VA46Z85WWbU QzFsSgJ+ZNNjpjGVOib91Ry6vmXGPSJXdWYOZ9DcvXgV+EG9n10p550LvkBxTXFIV52sn0Cbsnf 5t5P1ix7ACvQTj14VCaz/RHbwDqIlupkbDv3X5h+PyqGAD4p4FGNRMFNuTDN5CoIlKtcWmnNnsZ V8ucbmsYLB+sHOyrAVl7fWiH+3P/0tawmUV9fZUV6h1tvkptKcQ6zQQzb15BAs7LWajFj4bxWIT tF2Ezfs4HQljB6wNyqA== X-Proofpoint-GUID: 9UvDeudL6oB0BZKAQl1zvx-MJHS6dZLM X-Proofpoint-ORIG-GUID: 9UvDeudL6oB0BZKAQl1zvx-MJHS6dZLM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-01_07,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 spamscore=0 bulkscore=0 adultscore=0 phishscore=0 impostorscore=0 clxscore=1015 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606020086 Pass struct msm_dp_panel to the display enable/disable helpers to make them easier to reuse for MST stream handling. Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_display.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index cd1f2899b733..bea5bfb22967 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -650,7 +650,8 @@ static int msm_dp_display_prepare_link(struct msm_dp_di= splay_private *dp) return msm_dp_ctrl_prepare_stream_on(dp->ctrl, dp->panel, force_link_trai= n); } =20 -static int msm_dp_display_enable(struct msm_dp_display_private *dp) +static int msm_dp_display_enable(struct msm_dp_display_private *dp, + struct msm_dp_panel *msm_dp_panel) { int rc =3D 0; struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; @@ -661,7 +662,7 @@ static int msm_dp_display_enable(struct msm_dp_display_= private *dp) return 0; } =20 - rc =3D msm_dp_ctrl_on_stream(dp->ctrl, dp->panel); + rc =3D msm_dp_ctrl_on_stream(dp->ctrl, msm_dp_panel); if (!rc) msm_dp_display->power_on =3D true; =20 @@ -707,20 +708,21 @@ static void msm_dp_display_audio_notify_disable(struc= t msm_dp_display_private *d msm_dp_display->audio_enabled =3D false; } =20 -static int msm_dp_display_disable(struct msm_dp_display_private *dp) +static int msm_dp_display_disable(struct msm_dp_display_private *dp, + struct msm_dp_panel *msm_dp_panel) { struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; =20 if (!msm_dp_display->power_on) return 0; =20 - msm_dp_panel_disable_vsc_sdp(dp->panel); + msm_dp_panel_disable_vsc_sdp(msm_dp_panel); =20 msm_dp_ctrl_off_pixel_clk(dp->ctrl); =20 /* dongle is still connected but sinks are disconnected */ if (dp->link->sink_count =3D=3D 0) - msm_dp_link_psm_config(dp->link, &dp->panel->link_info, true); + msm_dp_link_psm_config(dp->link, &msm_dp_panel->link_info, true); =20 msm_dp_ctrl_off_link(dp->ctrl, dp->panel); =20 @@ -1437,14 +1439,14 @@ void msm_dp_display_atomic_enable(struct msm_dp *ms= m_dp_display) =20 dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 - rc =3D msm_dp_display_enable(dp); + rc =3D msm_dp_display_enable(dp, dp->panel); if (rc) DRM_ERROR("DP display enable failed, rc=3D%d\n", rc); =20 rc =3D msm_dp_display_post_enable(msm_dp_display); if (rc) { DRM_ERROR("DP display post enable failed, rc=3D%d\n", rc); - msm_dp_display_disable(dp); + msm_dp_display_disable(dp, dp->panel); } =20 drm_dbg_dp(msm_dp_display->drm_dev, "type=3D%d Done\n", msm_dp_display->c= onnector_type); @@ -1479,7 +1481,7 @@ void msm_dp_display_atomic_post_disable(struct msm_dp= *dp) =20 msm_dp_display_audio_notify_disable(msm_dp_display); =20 - msm_dp_display_disable(msm_dp_display); + msm_dp_display_disable(msm_dp_display, msm_dp_display->panel); =20 msm_dp_display_unprepare(msm_dp_display); } --=20 2.43.0