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Mon, 01 Jun 2026 16:15:46 -0700 (PDT) From: Oliver White To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thinh Nguyen , Bjorn Andersson , Konrad Dybcio Cc: Felipe Balbi , Oliver White , linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/3] dt-bindings: usb: dwc3: document snps,reinit-phy-on-resume Date: Tue, 2 Jun 2026 11:12:34 +1200 Message-ID: <20260601231236.20402-2-oliverjwhite07@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260601231236.20402-1-oliverjwhite07@gmail.com> References: <20260601231236.20402-1-oliverjwhite07@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the documentation for the 'snps,reinit-phy-on-resume' boolean property. When set, the DWC3 core will perform a full phy_exit() + phy_init() cycle on each USB2 PHY during the host-mode fast resume path. This is needed on platforms where the USB2 PHY power domain is gated during deep sleep even when device_may_wakeup is true. Signed-off-by: Oliver White --- .../devicetree/bindings/usb/snps,dwc3-common.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml b/= Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml index 6c0b8b653824..d12f6ae81ab8 100644 --- a/Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml +++ b/Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml @@ -212,6 +212,16 @@ properties: When set, run the SOF/ITP counter based on ref_clk. type: boolean =20 + snps,reinit-phy-on-resume: + description: + When set, the DWC3 will re-initialize the USB2 PHYs during the + host-mode fast resume path (device_may_wakeup). Some platforms + cut PHY power during deep sleep even when USB wake is enabled, + and the standard PHY runtime PM resume is insufficient to restore + the PHY register state. This quirk forces a full phy_exit() + + phy_init() cycle on each USB2 PHY. + type: boolean + snps,resume-hs-terminations: description: Fix the issue of HS terminations CRC error on resume by enabling this --=20 2.53.0 From nobody Mon Jun 8 06:22:35 2026 Received: from mail-pl1-f175.google.com (mail-pl1-f175.google.com [209.85.214.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 567E9384CEF for ; Mon, 1 Jun 2026 23:15:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780355759; cv=none; b=H2PGXeGZ94w6cee2jZRxF/kfdCBZFYm0ssME1KS8swWJtNWScHbuC5ZpDppzMdFd4dbSVs8b4YVYqeUc4/SXAlDv9+pKSw5lxmT7oISlW6H7Jc+tko0LMV/s3uAVICteeb5ibFI/d68YEkQVzUQyO4Lll7+I9LFxIDV+Dn0GmBQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780355759; 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Mon, 01 Jun 2026 16:15:57 -0700 (PDT) From: Oliver White To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thinh Nguyen , Bjorn Andersson , Konrad Dybcio Cc: Felipe Balbi , Oliver White , linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/3] usb: dwc3: add reinit-phy-on-resume quirk Date: Tue, 2 Jun 2026 11:12:35 +1200 Message-ID: <20260601231236.20402-3-oliverjwhite07@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260601231236.20402-1-oliverjwhite07@gmail.com> References: <20260601231236.20402-1-oliverjwhite07@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some platforms gate the USB2 PHY power domain during deep sleep (S3) even when device_may_wakeup is set, which causes the PHY register state to be lost. The DWC3 fast resume path (taken when device_may_wakeup is true) relies on phy_pm_runtime_get_sync() to restore the PHY, but this is a no-op for PHY drivers that do not implement runtime PM (e.g. the Qualcomm eUSB2 driver). Add a new boolean quirk 'snps,reinit-phy-on-resume' that, when set, forces a full phy_exit() + phy_init() cycle on each USB2 PHY during the host-mode fast resume path. This ensures the PHY registers are properly re-programmed after power loss. Signed-off-by: Oliver White --- drivers/usb/dwc3/core.c | 25 +++++++++++++++++++++++++ drivers/usb/dwc3/core.h | 1 + 2 files changed, 26 insertions(+) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 161a4d58b2ce..82baaab0d1d1 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -1854,6 +1854,8 @@ static void dwc3_get_properties(struct dwc3 *dwc) =20 dwc->dis_split_quirk =3D device_property_read_bool(dev, "snps,dis-split-quirk"); + dwc->reinit_phy_on_resume =3D device_property_read_bool(dev, + "snps,reinit-phy-on-resume"); =20 dwc->lpm_nyet_threshold =3D lpm_nyet_threshold; dwc->tx_de_emphasis =3D tx_de_emphasis; @@ -2561,6 +2563,29 @@ static int dwc3_resume_common(struct dwc3 *dwc, pm_m= essage_t msg) dwc3_writel(dwc, DWC3_GUSB2PHYCFG(i), reg); } =20 + /* + * Some platforms gate USB2 PHY power during deep sleep even + * when device_may_wakeup is true, causing register state to be + * lost. Re-initialize the PHY to ensure clean signalling. + */ + if (dwc->reinit_phy_on_resume && !PMSG_IS_AUTO(msg)) { + for (i =3D 0; i < dwc->num_usb2_ports; i++) { + int ret; + + ret =3D phy_exit(dwc->usb2_generic_phy[i]); + if (ret) + dev_warn_ratelimited(dwc->dev, + "failed to exit usb2 phy %d: %d\n", + i, ret); + + ret =3D phy_init(dwc->usb2_generic_phy[i]); + if (ret) + dev_warn_ratelimited(dwc->dev, + "failed to init usb2 phy %d: %d\n", + i, ret); + } + } + for (i =3D 0; i < dwc->num_usb2_ports; i++) phy_pm_runtime_get_sync(dwc->usb2_generic_phy[i]); for (i =3D 0; i < dwc->num_usb3_ports; i++) diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index a35b3db1f9f3..f64cf709e194 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -1403,6 +1403,7 @@ struct dwc3 { unsigned dis_metastability_quirk:1; =20 unsigned dis_split_quirk:1; + unsigned reinit_phy_on_resume:1; unsigned async_callbacks:1; unsigned sys_wakeup:1; unsigned wakeup_configured:1; --=20 2.53.0 From nobody Mon Jun 8 06:22:35 2026 Received: from mail-pl1-f175.google.com (mail-pl1-f175.google.com [209.85.214.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8AA54349CFE for ; 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charset="utf-8" The Surface Laptop 7 gates the USB2 PHY power domain during deep sleep, cau= sing the PHY register state to be lost. When the DWC3 multi-port controller= resumes via the fast path (device_may_wakeup), the PHY is not re-initializ= ed and USB2 devices (such as the wired keyboard on the USB-A port) may exhi= bit corrupted signalling, e.g. stuck modifier key reports. Enable the 'snps,reinit-phy-on-resume' quirk to force a full PHY re-initial= ization cycle on resume. --- arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi b/arc= h/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi index 4356cb88e2bd..2de244ffb54d 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi @@ -1731,6 +1731,10 @@ &usb_mp { status =3D "okay"; }; =20 +&usb_mp_dwc3 { + snps,reinit-phy-on-resume; +}; + &usb_mp_hsphy0 { vdd-supply =3D <&vreg_l2e>; vdda12-supply =3D <&vreg_l2j>; --=20 2.53.0