From nobody Mon Jun 8 05:26:08 2026 Received: from mail-pl1-f169.google.com (mail-pl1-f169.google.com [209.85.214.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A8212E8E09 for ; Mon, 1 Jun 2026 16:22:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780330925; cv=none; b=tbY+RJrTlD8JSxooDJJ3wakt8lP9+q0Bze6flneoQVMcj0qJd/cdxCM/rYvlINPQneDPiXcVtd45R4iypgwy+PMXJeJHXYHP+CVpqw6gdrWFT5k85KESZpmz8aDT4g5JqqES8U0J9b/q8kRUBOKYIk+VzbQTN3LK8G8TwdnArzo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780330925; c=relaxed/simple; bh=AlIbcBhxQY5tdoRA+xhInIDubeZASOSXqAsfI1siQbs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=t1UTsi9CBP4LEh7OVKAW/zahHcS63KhjMFVKLx3bHK6/sN1VbVr2/k5W1XJS6wAe0QZnGEzxJEY1OIa/YgCS/hacWm6LSu6ao5nJQBrwQ+zDQSVlBhQnwaIMYrMQOFNJ8SXm/xEl3rS+0lwrEbEi7tx51YfguDC9IWh4zTJEPXw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=kf1b0GpM; arc=none smtp.client-ip=209.85.214.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="kf1b0GpM" Received: by mail-pl1-f169.google.com with SMTP id d9443c01a7336-2c0c35980fdso16348265ad.2 for ; Mon, 01 Jun 2026 09:22:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1780330923; x=1780935723; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NFYhV629aCcMh6n03w8fB9pu9Qir4aq6dz+7Wpy2WIQ=; b=kf1b0GpMiVliT4l+tKLugYKfGlNn1jSomyPPFWN+/HN87spNVB65F36UYr0AbVXyyn wyv2k/Vx3+zdiP+gc6NsmWKhWSGcNCUPgEVKnycZksLPHD0K7RE7wPCLUqmiGhFxn6Qk 39iOVlVWbcfWFffcxhQBQrAlxlGjkmY4Q15AE3IYYSy03acG0FlgHKO5zAdExCjLC7Wg iWrdwzZsF6KIQ9R2m3toJ7CUJovvZcNk7+gYn5UDtk6kOdszc6Zijv69unl2mwSmf2ef UnipRu9Q7nd9oie6z5vG/IPwkrbIo5KgFlSKYZckmcREum2hzUfUGJSxYF9atOSljfN8 qMOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1780330923; x=1780935723; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=NFYhV629aCcMh6n03w8fB9pu9Qir4aq6dz+7Wpy2WIQ=; b=Iox9+t39fz5D4Vi/OxkxmUAvmIEoTcMP561FMTryHRJMV3FM0A6Wqv0Ouawzdwt4Su KmrFvsJBugQZwnweMV8LIaioFPJJyxkakOiGd1Ru98TY+rMTg9dC3agBguB6Yd8r0Qw4 ezq6KIrtaz2ECnJaH/g5+oI1S9zYXV+BCp2LVM7v7hG1PzJinQG/GJXmBh4Q8Tc1JMms rG/8SiHKV3VPqlyRpPcOMlNOAxydmgzgyzdvWkkQ021GZl6OHoavEkFhhYpCs5nV0ySk 5H3i8pu6ztzjfnqNb+QW83PXLtslBzyH3o5+tMvwGOtzNnR4OCzsO9Emo+FP89fr0bkZ laBQ== X-Forwarded-Encrypted: i=1; AFNElJ/kIG8b9/39KD6pa6/DJ+by+mtrP91VNnGO6lBvhvbDMsTL0l4Lt9IluuHX1Y1Kmn47S8fQS4mGMQVGdlw=@vger.kernel.org X-Gm-Message-State: AOJu0YyAXzsuARgXFfnv6EZ+difS9IZnBFIiYoA4hEvWSMA0N1lS2aUX LIzIFupCAfc2GpUl57baodCtCjFe8jdtJbzSnHRqtzxgm93OoaDHMJEZ X-Gm-Gg: Acq92OHQMav7RyK6Nlcs78Zh/ZlP7jWVh65n9mzaj5T0mLK2I6Zv/6wvGTRYpF+oHYM 5uedRXZEQuO0tv+k99VOFxqqgGlQvkh9hSGK3V7eIilu8fviLUqw8IBvjx51/O+1cbLIfeyygiD UC8p2utIMRYgTKRq/hSpePWsZFRy/CBX2WUr70AhnwMG2RU0h27I5oh4I4VORPRrNA//CY84Gkx Kw/AmWoJVUuXO1Y55xBzhtuho873VCo3IbkJaRtZUyTg9XaeWWym17tZVXPj4J+o5Pxje0+v9Nf 01kkCIulOVzTHcyxW3vXrJOp/WEH2nRW+OYBLj/7kzFvVPhFKdiQHsOFJTOZH+5MBR7e+TYNtfV jOM5yyBzzDpUwJrQXwcgWcgBlrb7pMWgWLBN3HKemoxnn6CpHsbzvbG231boek6B7RnagBTDSvN 9InZAiHoh305sLnTRhwET5WUNLul5aeQ/rYzKwDSZ5 X-Received: by 2002:a17:903:2311:b0:2c0:cb90:1dfc with SMTP id d9443c01a7336-2c0cb902165mr76599465ad.12.1780330923397; Mon, 01 Jun 2026 09:22:03 -0700 (PDT) Received: from i386.168.1.127 ([2402:a00:163:2ce9:9c6f:e28:3da8:7980]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2bf239e5d83sm116647455ad.8.2026.06.01.09.21.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jun 2026 09:22:02 -0700 (PDT) From: Hrushiraj Gandhi To: Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Hrushiraj Gandhi Subject: [PATCH v6 1/3] dt-bindings: vendor-prefixes: add vicharak Date: Mon, 1 Jun 2026 21:51:40 +0530 Message-ID: <20260601162143.170030-2-hrushirajg23@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260601162143.170030-1-hrushirajg23@gmail.com> References: <20260601162143.170030-1-hrushirajg23@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the vendor prefix for Vicharak Computers Pvt. Ltd. Signed-off-by: Hrushiraj Gandhi --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index 28784d66ae7b..504a691a33b9 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1791,6 +1791,8 @@ patternProperties: description: VIA Technologies, Inc. "^vialab,.*": description: VIA Labs, Inc. + "^vicharak,.*": + description: Vicharak Computers Pvt. Ltd. "^vicor,.*": description: Vicor Corporation "^videostrong,.*": --=20 2.47.3 From nobody Mon Jun 8 05:26:08 2026 Received: from mail-pl1-f173.google.com (mail-pl1-f173.google.com [209.85.214.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3542E2F2914 for ; Mon, 1 Jun 2026 16:22:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780330931; cv=none; b=X9WCUObLe7WA3qgXEIAKlV+V0EH82F5MUha0wp0Vl/KN7M7ioEbVU4gBGHweJWbulqrUhjfoLk0ouibCWj4h+ZIHnsiaYncl4mZFFjF953L6S9UUNAtmIN08b55mgjYrJa/1NrOw/n3LiSFLLQ8/ZJAfSY0KbZ0EgLUr1FmVANs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780330931; c=relaxed/simple; bh=PPWvaKyXHBKw3dRbdQICjaYQ5ch3ydY/WU7J8dzT2PE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZfjDZ7i400oKxtq33GGNpZCl9lmJ7pieQRSjOB0HnCIL/e19gr9BXinJtFCyfmfFtC7pzQJW0oYPCKS5r0KbxFxbYpLBdxye5VkVuVcON5TG0HRKivXE4CLtlYGRBH5Y1xyCY8ItwcJUFwOqvm7HX9GgzkRlsmyaEHCTi0dIrO0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=F89rBvZW; arc=none smtp.client-ip=209.85.214.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="F89rBvZW" Received: by mail-pl1-f173.google.com with SMTP id d9443c01a7336-2bf36a6905cso15946115ad.3 for ; Mon, 01 Jun 2026 09:22:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1780330928; x=1780935728; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YU2lR4C6HulA/xumBMwgTiZI291rJPzss3O8OSIe4FI=; b=F89rBvZWXwHTVMPWuUbWj422CeVsX7rK+i8wR++Y7lod9FDRVxyWPubwPUro/sy7JX VKksdxww6r7nwOCQ4MHKjts45SYYO85Ggn0hM9e+RBjZLbcmhzlLdCFtrkGXA4fOjInD HAjiLBJRbpFfBe80s3L1r782GyAPBKG4HlrnpwmSwzCPGKu7dUOytmVHbpmAQAre/avx XKimuhZ2Q7jPjECczVm9nrYYxUOE5uAh33u58/SQ/Kd0qQwa896BH2pcU86Kxd5RSPSW GQAYBXjzXQaST/zHnpFh0vXUlWUWNW9+VGb1eDoGTEQn0wfyLPBHlIzNeKFjmvgShDPd +f/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1780330928; x=1780935728; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=YU2lR4C6HulA/xumBMwgTiZI291rJPzss3O8OSIe4FI=; b=pOQ5F/15idWB/utslPEZvJQsTgiXlnsEau3HyYE4Q73uCSzYHlsCCb0f1YG449WxkL r7Xcl9TA0PV8P2+33Y7szyrryq4rgXzkaiCXn9cd//2VGhu1IYuhRoRX1S0hc39VpLuB UTP/cj8KCdCAC2v5bDSUayU2ETMnnqfDUk6nhyux/n9qtw5To3RisGD7zNo6vRgtVZnJ 9NorAbq8jyDtHTgsdXHwCM0eJm1WPHAatnQckHYPc8oJVeSQQpwul01rZ3lzMfAgx/zw +SNx62NENqjoCCcl4rr+N74SDGZEaepkH+QJ7HCqcehkOtQJLwX4VlNMM/9OjUVt4TLn zmOQ== X-Forwarded-Encrypted: i=1; AFNElJ+FhzjI4veY6a/3tUcELgWtdILw3lPh6QMRe3CeT8Im1+vTITvwnOlsTiaSwsESCeONlT72UOEaSXweiIs=@vger.kernel.org X-Gm-Message-State: AOJu0YwW8njQIq8aqYpd00JsNrDi84pjkxO0NGTQNM53HAnRGgr5k/CZ 2RazILf+dqZcmtp49B1AwCb4jzTF2F7EM11defuyDuxN1FoG5JMLuHhEfcc+H7Krws8= X-Gm-Gg: Acq92OF14KPHykQ6cj2fxmwe+sDoViDQuQeSoUAfTzYF6W11TW8jN5egu40B831Y6ia nAUBB8reMfZ+SzAuJ8JmB7ocVfipgel3K5CT1iN61qpz3651MF8MKN23ev/Z1a4x72nqWCQY2rm vjEtMDw6v99+g2XcY7gtx74gmNYW6XnRl870ZLXzzSNpubtJBnBiawGQm4g+zjnabORpewgmzGU SCVcZDuldyMwwNCxLi5SquSTtm6powdupX7/vw7fq4gqYXjMYnhbbJR3H4uTVWoJ/6l8r0oOj1m D5CHjSQkwRGeGkOYAuwJqXsdcUeBS4StWTnBbMH6MQf25YaukyADoomyl87S/lM/5g5jE8UQjN7 pwkJJc4wRuazV6/keqwfFKDQYE1BMCwNVtq283paNypPZYp1CdMcf+9TGpjHt8eMjMjfJWF+R7a Hlu3CI/QHRKso5S7OS0SpYRAOZtc7zF1Sq2clgAUmM X-Received: by 2002:a17:903:2344:b0:2c0:aef8:23dd with SMTP id d9443c01a7336-2c0aef82687mr112227805ad.22.1780330928509; Mon, 01 Jun 2026 09:22:08 -0700 (PDT) Received: from i386.168.1.127 ([2402:a00:163:2ce9:9c6f:e28:3da8:7980]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2bf239e5d83sm116647455ad.8.2026.06.01.09.22.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jun 2026 09:22:07 -0700 (PDT) From: Hrushiraj Gandhi To: Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Hrushiraj Gandhi Subject: [PATCH v6 2/3] dt-bindings: arm: rockchip: add Vicharak Axon board Date: Mon, 1 Jun 2026 21:51:41 +0530 Message-ID: <20260601162143.170030-3-hrushirajg23@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260601162143.170030-1-hrushirajg23@gmail.com> References: <20260601162143.170030-1-hrushirajg23@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the device tree binding for the Vicharak Axon single-board computer based on the Rockchip RK3588 SoC. Signed-off-by: Hrushiraj Gandhi --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index 1a9dde18626d..b023d4cc9842 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -1306,6 +1306,11 @@ properties: - const: turing,rk1 - const: rockchip,rk3588 =20 + - description: Vicharak Axon + items: + - const: vicharak,axon + - const: rockchip,rk3588 + - description: WolfVision PF5 mainboard items: - const: wolfvision,rk3568-pf5 --=20 2.47.3 From nobody Mon Jun 8 05:26:08 2026 Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F31FD2FFDE1 for ; Mon, 1 Jun 2026 16:22:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780330936; cv=none; b=YPpoPxrtroycW8sSXHEAzDzXE21alztIzRK0aJCdhymyvElA5PFPvIIKCXiOVtrNyNzxrz/rWZncA1xMuF+LlLS5aAed+6vKISuenJEdEtD5LcpSPtC7+WowLobsgDAQxFabcm8bxO1FuSVtRViQHCSGHv5wRzft3k019Of0PeA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780330936; c=relaxed/simple; bh=jOwZYDfaH2HJceF4IKa23BLbjQXEd5YH511Z1xMw00M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cypYvJR2CFm0hrAbbYMLHfDZzkQPlhfFF3Ws7B0ffeJ70kwCeoV1pf9yIzPtJ5gM8KqLs4wotlFm9nqp/m4XzJvDZzCkLHf41ZjKGEbIlmz5ylIKkZCLGk3Xa4wRMIjt675sSfHHy7CoNvfEH3YMQeHuxkySWyqzJ7tfEo64wHo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=rN1GOTCJ; arc=none smtp.client-ip=209.85.214.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="rN1GOTCJ" Received: by mail-pl1-f179.google.com with SMTP id d9443c01a7336-2c0c2a68d01so10318335ad.1 for ; Mon, 01 Jun 2026 09:22:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1780330933; x=1780935733; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hLqSjNA5WaTN9zMcFad6exF0rd+hjiZYKyYXSLxTOP4=; b=rN1GOTCJpNK9Pu3RF9G4sZz9NB6GVGV1dPeB/F4aib5nJATUmP8T7FsgEx5saNCeky ngc8KSt6TSBey29jJHfjeL8VUBS/HBXE694/5xYIdrcSnNH4YdYsIc7LSk8EfTlFs3Yz gGiJWMqWXdPiTLNtpn3JiALH9UScHEiAr7VzWmovCSBoCoYbQ4OmS/UtzU7VOiTK5mJD cubqtn+URSV7vf/5mjp7dVbhsX89tW+ZeErGEP2i6QOKDUt/GEy0tG4Wr/UUrPDVuMeZ 5oiBBfqXz1G3UTZfUYoHKh5EGHOp/UVkXS4xTsuyzsQN8VPrzB1y6ZNDauWoZE53/+vM b3zQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1780330933; x=1780935733; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=hLqSjNA5WaTN9zMcFad6exF0rd+hjiZYKyYXSLxTOP4=; b=s0xzNRvwuuh0Mn177AvnIQ179P4R8FJ8qsuAqKxpBfq6Do/n5ufMnVK6fWLQuID+ro r09otPsOBduX5BDUeMA6ivImp264RVaqMSm8Phf0n76T+0KeY3AmqzlKzTpaQscp6n3V Qumuk0ySWbDwsIP45dnGsiBCd5y+n4MewZaYXBkFmvB3phcAPsQNGZubmkk++97DoJ+j q9f/csGOhHwyn9zgvAeF6iEEGPW9dIP23QM7znAFxsnFgMDNHltuywxi6WXEFKneT6Df wpa2ROxxhKGewIfbv3pWtyVAOpIostVfPfaMxk0WocZ0+vhvDD1pFMTBrMIRlJ40WUjs S5Jg== X-Forwarded-Encrypted: i=1; AFNElJ+suE7WftAUU301QS2OOO1tWWBbyUNUrO8VQYuKwJZhw5dN2LZCdyCOSwHQ2PuWI+BUvf+XB3AwbXubbpc=@vger.kernel.org X-Gm-Message-State: AOJu0YxXPomc3clmzxfJILIUpkfG5mRWUknKQdiBaUFGzOd/YhFQL+Op JOCjI4sURUpb3CkJOhmp+KCeG/2wBjPJLEL+13uY6N+UrkGcfW8vZkKn X-Gm-Gg: Acq92OFNxJRJRn5CfnRyjceE4NZQ8X1JLR9tyU6tsMLKgvMyQwWN+wREq83luSqpTFH u8TsCslkTv4WNkcEqF/05ErcqAmUzgwUae4cVrLHhHJKyjx2X4PidrE9bKNIZ9r6OWLrYDfFhI+ BfeC3pCmqjXUFIoHFGzKtSD43UPbAtICYD+o6Bb4beBO5XhEbhzXSMXnNt0XgNUtEq2hjriv2bS n55Xn+h5vDgHtoXT+rwK9S2EUwCmCiNoeDmW2x70EmoEREeKsx635Lg0Xx6I7G9HoblCjm28KBZ FmlOL0Ak8+ZuOScDZJuHIicWCvyNCwqWlHL13TD1nGMbP8a47Km3Y4f+j34y59y45GQWYkxQq1k H9O3dnciLyiJgA8NuWRg4ZKA90xECi40F/gk4ywdi5dyJb5DMlsev4d1TknUj8ABAp62X2+dx75 k/jBOc6iFFb6cfA5hwSXmNBSntQZEe5UELVZziei5n X-Received: by 2002:a17:902:d2c9:b0:2b2:67ca:5ff9 with SMTP id d9443c01a7336-2bf36377925mr125746895ad.0.1780330932995; Mon, 01 Jun 2026 09:22:12 -0700 (PDT) Received: from i386.168.1.127 ([2402:a00:163:2ce9:9c6f:e28:3da8:7980]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2bf239e5d83sm116647455ad.8.2026.06.01.09.22.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jun 2026 09:22:12 -0700 (PDT) From: Hrushiraj Gandhi To: Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Hrushiraj Gandhi Subject: [PATCH v6 3/3] arm64: dts: rockchip: add Vicharak Axon board Date: Mon, 1 Jun 2026 21:51:42 +0530 Message-ID: <20260601162143.170030-4-hrushirajg23@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260601162143.170030-1-hrushirajg23@gmail.com> References: <20260601162143.170030-1-hrushirajg23@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add initial support for the Vicharak Axon single-board computer based on the Rockchip RK3588 SoC. The board supports: - eMMC storage - microSD card - Gigabit Ethernet - HDMI output (dual HDMI) - HDMI input - USB 2.0 host ports - PCIe 2.0 slots - PCIe 3.0 x4 slot - SATA - RTC - Status LEDs The board uses an RK806 PMIC and provides the regulators required by the RK3588 SoC. Signed-off-by: Hrushiraj Gandhi --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/rk3588-vicharak-axon.dts | 991 ++++++++++++++++++ 2 files changed, 992 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-vicharak-axon.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index cb55c6b70d0e..b10c6d80c5cc 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -211,6 +211,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-tiger-haikou.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-tiger-haikou-video-demo.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-toybrick-x0.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-turing-rk1.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-vicharak-axon.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588s-coolpi-4b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588s-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588s-gameforce-ace.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vicharak-axon.dts b/arch/a= rm64/boot/dts/rockchip/rk3588-vicharak-axon.dts new file mode 100644 index 000000000000..4d7fafd76c16 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-vicharak-axon.dts @@ -0,0 +1,991 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include "rk3588.dtsi" + +/ { + model =3D "Vicharak Axon"; + compatible =3D "vicharak,axon", "rockchip,rk3588"; + + aliases { + mmc0 =3D &sdmmc; + mmc1 =3D &sdhci; + mmc2 =3D &sdio; + serial2 =3D &uart2; + }; + + chosen { + stdout-path =3D "serial2:1500000n8"; + }; + + hdmi0-con { + compatible =3D "hdmi-connector"; + type =3D "a"; + + port { + hdmi0_con_in: endpoint { + remote-endpoint =3D <&hdmi0_out_con>; + }; + }; + }; + + hdmi1-con { + compatible =3D "hdmi-connector"; + type =3D "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint =3D <&hdmi1_out_con>; + }; + }; + }; + + leds { + compatible =3D "gpio-leds"; + status =3D "okay"; + + power_led: power-led { + color =3D ; + function =3D LED_FUNCTION_STATUS; + gpios =3D <&pca9554 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + }; + + status_led: status-led { + color =3D ; + function =3D LED_FUNCTION_STATUS; + gpios =3D <&pca9554 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "none"; + }; + }; + + pcie20_avdd0v85: regulator-pcie20-avdd0v85 { + compatible =3D "regulator-fixed"; + regulator-name =3D "pcie20_avdd0v85"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + vin-supply =3D <&vdd_0v85_s0>; + }; + + pcie20_avdd1v8: regulator-pcie20-avdd1v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "pcie20_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: regulator-pcie30-avdd0v75 { + compatible =3D "regulator-fixed"; + regulator-name =3D "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + vin-supply =3D <&vdd_0v75_s0>; + }; + + pcie30_avdd1v8: regulator-pcie30-avdd1v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&avcc_1v8_s0>; + }; + + sata_vcc_5v0: regulator-sata-vcc-5v0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "sata_vcc_5v0"; + startup-delay-us =3D <5000>; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc12v_dcin>; + }; + vcc0_4v0: vcc4v0_sys: regulator-vcc0-4v0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc0_4v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <4000000>; + regulator-max-microvolt =3D <4000000>; + vin-supply =3D <&vcc12v_dcin>; + }; + + vcc12v_dcin: regulator-vcc12v-dcin { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + }; + + vcc3v3_io_expander: regulator-vcc3v3-io-expander { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_io_expander"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + + vcc3v3_pcie20_sata30: regulator-vcc3v3-pcie20-sata30 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_pcie20_sata30"; + regulator-boot-on; + regulator-always-on; + enable-active-high; + gpios =3D <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + vin-supply =3D <&vcc12v_dcin>; + }; + + vcc3v3_pcie30: regulator-vcc3v3-pcie30 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_pcie30"; + regulator-boot-on; + regulator-always-on; + enable-active-high; + gpios =3D <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc12v_dcin>; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc12v_dcin>; + }; + + vcc5v0_usb20_host: regulator-vcc5v0-usb20-host { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_usb20_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc5v0_sys>; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + vin-supply =3D <&vcc5v0_sys>; + }; + +}; + + +&combphy0_ps { + status =3D "okay"; +}; + +&combphy1_ps { + status =3D "okay"; +}; + +&combphy2_psu { + status =3D "okay"; +}; + +&cpu_b0 { + cpu-supply =3D <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply =3D <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply =3D <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply =3D <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&gmac1 { + clock_in_out =3D "output"; + phy-handle =3D <&rgmii_phy>; + phy-mode =3D "rgmii-rxid"; + phy-supply =3D <&vcc_3v3_s3>; + pinctrl-0 =3D <&gmac1_rgmii_bus + &gmac1_rgmii_clk + &gmac1_rx_bus2 + &gmac1_tx_bus2 + &gmac1_miim>; + pinctrl-names =3D "default"; + snps,reset-active-low; + snps,reset-delays-us =3D <0 20000 100000>; + snps,reset-gpio =3D <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + rx_delay =3D <0x00>; + tx_delay =3D <0x43>; + status =3D "okay"; +}; + +&gpu { + mali-supply =3D <&vdd_gpu_s0>; + status =3D "okay"; +}; + +&hdmi0 { + status =3D "okay"; +}; + +&hdmi0_in { + hdmi0_in_vp0: endpoint { + remote-endpoint =3D <&vp0_out_hdmi0>; + }; +}; + +&hdmi0_out { + hdmi0_out_con: endpoint { + remote-endpoint =3D <&hdmi0_con_in>; + }; +}; + +&hdmi0_sound { + status =3D "okay"; +}; + +&hdmi1 { + status =3D "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp1: endpoint { + remote-endpoint =3D <&vp1_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint =3D <&hdmi1_con_in>; + }; +}; + +&hdmi1_sound { + status =3D "okay"; +}; + +&hdmi_receiver { + pinctrl-0 =3D <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_= sda &hdmirx_hpd>; + pinctrl-names =3D "default"; + hpd-gpios =3D <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>; + status =3D "okay"; +}; + +&hdmi_receiver_cma { + status =3D "okay"; +}; + +&hdptxphy0 { + status =3D "okay"; +}; + +&hdptxphy1 { + status =3D "okay"; +}; + +&i2c0 { + pinctrl-0 =3D <&i2c0m2_xfer>; + pinctrl-names =3D "default"; + status =3D "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible =3D "rockchip,rk8602"; + fcs,suspend-voltage-selector =3D <1>; + reg =3D <0x42>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <1050000>; + regulator-min-microvolt =3D <550000>; + regulator-name =3D "vdd_cpu_big0_s0"; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible =3D "rockchip,rk8603", "rockchip,rk8602"; + fcs,suspend-voltage-selector =3D <1>; + reg =3D <0x43>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <1050000>; + regulator-min-microvolt =3D <550000>; + regulator-name =3D "vdd_cpu_big1_s0"; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + hym8563: rtc@51 { + compatible =3D "haoyu,hym8563"; + reg =3D <0x51>; + #clock-cells =3D <0>; + clock-output-names =3D "hym8563"; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rtc_int>; + wakeup-source; + status =3D "okay"; + }; +}; + +&i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c1m2_xfer>; + status =3D "okay"; + + vdd_npu_s0: regulator@42 { + compatible =3D "rockchip,rk8602"; + reg =3D <0x42>; + fcs,suspend-voltage-selector =3D <1>; + regulator-name =3D "vdd_npu_s0"; + regulator-boot-on; + regulator-enable-ramp-delay =3D <500>; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c6 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c6m0_xfer>; + status =3D "okay"; + + pca9554: gpio@24 { + compatible =3D "nxp,pca9554"; + #gpio-cells =3D <2>; + gpio-controller; + reg =3D <0x24>; + vcc-supply =3D <&vcc3v3_io_expander>; + status =3D "okay"; + }; +}; + +&i2s5_8ch { + status =3D "okay"; +}; + +&i2s6_8ch { + status =3D "okay"; +}; + +&sdhci { + bus-width =3D <8>; + full-pwr-cycle-in-suspend; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sd; + no-sdio; + non-removable; + vmmc-supply =3D <&vcc_3v3_s3>; + vqmmc-supply =3D <&vcc_1v8_s3>; + status =3D "okay"; +}; + +&sdmmc { + bus-width =3D <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios =3D <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency =3D <200000000>; + no-mmc; + no-sdio; + sd-uhs-sdr104; + vmmc-supply =3D <&vcc_3v3_s3>; + vqmmc-supply =3D <&vccio_sd_s0>; + status =3D "okay"; +}; + +&spi2 { + assigned-clock-rates =3D <200000000>; + assigned-clocks =3D <&cru CLK_SPI2>; + num-cs =3D <1>; + pinctrl-0 =3D <&spi2m2_cs0 &spi2m2_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmic@0 { + reg =3D <0>; + compatible =3D "rockchip,rk806"; + #gpio-cells =3D <2>; + gpio-controller; + interrupt-parent =3D <&gpio0>; + interrupts =3D <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names =3D "default", "pmic-power-off"; + pinctrl-0 =3D <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + pinctrl-1 =3D <&rk806_dvs1_pwrdn>; + spi-max-frequency =3D <1000000>; + + vcc1-supply =3D <&vcc5v0_sys>; + vcc2-supply =3D <&vcc5v0_sys>; + vcc3-supply =3D <&vcc5v0_sys>; + vcc4-supply =3D <&vcc5v0_sys>; + vcc5-supply =3D <&vcc5v0_sys>; + vcc6-supply =3D <&vcc5v0_sys>; + vcc7-supply =3D <&vcc5v0_sys>; + vcc8-supply =3D <&vcc5v0_sys>; + vcc9-supply =3D <&vcc5v0_sys>; + vcc10-supply =3D <&vcc5v0_sys>; + vcc11-supply =3D <&vcc_2v0_pldo_s3>; + vcc12-supply =3D <&vcc5v0_sys>; + vcc13-supply =3D <&vcc_1v1_nldo_s3>; + vcc14-supply =3D <&vcc_1v1_nldo_s3>; + vcca-supply =3D <&vcc5v0_sys>; + + rk806_dvs1_null: rk806_dvs1_null { + pins =3D "gpio_pwrctrl1"; + function =3D "pin_fun0"; + }; + + rk806_dvs1_slp: rk806_dvs1_slp { + pins =3D "gpio_pwrctrl1"; + function =3D "pin_fun1"; + }; + + rk806_dvs1_pwrdn: rk806_dvs1_pwrdn { + pins =3D "gpio_pwrctrl1"; + function =3D "pin_fun2"; + }; + + rk806_dvs1_rst: rk806_dvs1_rst { + pins =3D "gpio_pwrctrl1"; + function =3D "pin_fun3"; + }; + + rk806_dvs2_null: rk806_dvs2_null { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun0"; + }; + + rk806_dvs2_slp: rk806_dvs2_slp { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun1"; + }; + + rk806_dvs2_pwrdn: rk806_dvs2_pwrdn { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun2"; + }; + + rk806_dvs2_rst: rk806_dvs2_rst { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun3"; + }; + + rk806_dvs2_dvs: rk806_dvs2_dvs { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun4"; + }; + + rk806_dvs2_gpio: rk806_dvs2_gpio { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun5"; + }; + + rk806_dvs3_null: rk806_dvs3_null { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun0"; + }; + + rk806_dvs3_slp: rk806_dvs3_slp { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun1"; + }; + + rk806_dvs3_pwrdn: rk806_dvs3_pwrdn { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun2"; + }; + + rk806_dvs3_rst: rk806_dvs3_rst { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun3"; + }; + + rk806_dvs3_dvs: rk806_dvs3_dvs { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun4"; + }; + + rk806_dvs3_gpio: rk806_dvs3_gpio { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun5"; + }; + + regulators { + vdd_gpu_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_gpu_s0"; + regulator-enable-ramp-delay =3D <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <750000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <750000>; + }; + }; + + vdd_vdenc_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <900000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name =3D "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <2000000>; + regulator-max-microvolt =3D <2000000>; + regulator-name =3D "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name =3D "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-name =3D "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + regulator-name =3D "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-name =3D "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <837500>; + regulator-max-microvolt =3D <837500>; + regulator-name =3D "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-name =3D "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + regulator-name =3D "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&mdio1 { + rgmii_phy: phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0x1>; + }; +}; + +&pcie2x1l0 { + reset-gpios =3D <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie2_0_rst>; + vpcie3v3-supply =3D <&vcc3v3_pcie20_sata30>; + status =3D "okay"; +}; + +&pcie2x1l1 { + reset-gpios =3D <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie2_1_rst>; + vpcie3v3-supply =3D <&vcc3v3_pcie20_sata30>; + status =3D "okay"; +}; + +&pcie2x1l2 { + status =3D "disabled"; +}; + +&pcie30phy { + status =3D "okay"; +}; + +&pcie3x4 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie3_reset>; + reset-gpios =3D <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc3v3_pcie30>; + status =3D "okay"; +}; + +&pinctrl { + + hdmirx { + hdmirx_hpd: hdmirx-5v-detection { + rockchip,pins =3D <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + + hym8563 { + rtc_int: rtc-int { + rockchip,pins =3D + <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie2 { + pcie2_0_rst: pcie2-0-rst { + rockchip,pins =3D + <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie2_1_rst: pcie2-1-rst { + rockchip,pins =3D + <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie3 { + pcie3_reset: pcie3-reset { + rockchip,pins =3D + <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + +}; + +&saradc { + vref-supply =3D <&avcc_1v8_s0>; + status =3D "okay"; +}; + +&sata0 { + status =3D "okay"; +}; + +&tsadc { + status =3D "okay"; +}; +&u2phy2 { + status =3D "okay"; +}; + +&u2phy2_host { + phy-supply =3D <&vcc5v0_usb20_host>; + status =3D "okay"; +}; + +&u2phy3 { + status =3D "okay"; +}; + +&u2phy3_host { + phy-supply =3D <&vcc5v0_usb20_host>; + status =3D "okay"; +}; + +&uart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart2m0_xfer>; + status =3D "okay"; +}; + +&usb_host0_ehci { + status =3D "okay"; +}; + +&usb_host0_ohci { + status =3D "okay"; +}; + +&usb_host1_ehci { + status =3D "okay"; +}; + +&usb_host1_ohci { + status =3D "okay"; +}; + +&vop { + status =3D "okay"; +}; + +&vop_mmu { + status =3D "okay"; +}; + +&vp0 { + vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg =3D ; + remote-endpoint =3D <&hdmi0_in_vp0>; + }; +}; + +&vp1 { + vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg =3D ; + remote-endpoint =3D <&hdmi1_in_vp1>; + }; +}; --=20 2.47.3