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Mon, 01 Jun 2026 09:06:27 -0700 (PDT) From: Hrushiraj Gandhi To: Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Hrushiraj Gandhi Subject: [PATCH v5 1/3] dt-bindings: vendor-prefixes: add vicharak Date: Mon, 1 Jun 2026 21:36:01 +0530 Message-ID: <20260601160603.167706-2-hrushirajg23@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260601160603.167706-1-hrushirajg23@gmail.com> References: <20260601160603.167706-1-hrushirajg23@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the vendor prefix for Vicharak Computers Pvt. Ltd. Signed-off-by: Hrushiraj Gandhi --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index 28784d66ae7b..504a691a33b9 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1791,6 +1791,8 @@ patternProperties: description: VIA Technologies, Inc. "^vialab,.*": description: VIA Labs, Inc. + "^vicharak,.*": + description: Vicharak Computers Pvt. Ltd. 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Mon, 01 Jun 2026 09:06:33 -0700 (PDT) From: Hrushiraj Gandhi To: Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Hrushiraj Gandhi Subject: [PATCH v5 2/3] dt-bindings: arm: rockchip: add Vicharak Axon board Date: Mon, 1 Jun 2026 21:36:02 +0530 Message-ID: <20260601160603.167706-3-hrushirajg23@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260601160603.167706-1-hrushirajg23@gmail.com> References: <20260601160603.167706-1-hrushirajg23@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the device tree binding for the Vicharak Axon single-board computer based on the Rockchip RK3588 SoC. Signed-off-by: Hrushiraj Gandhi --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index 1a9dde18626d..b023d4cc9842 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -1306,6 +1306,11 @@ properties: - const: turing,rk1 - const: rockchip,rk3588 =20 + - description: Vicharak Axon + items: + - const: vicharak,axon + - const: rockchip,rk3588 + - description: WolfVision PF5 mainboard items: - const: wolfvision,rk3568-pf5 --=20 2.47.3 From nobody Mon Jun 8 05:25:45 2026 Received: from mail-pj1-f42.google.com (mail-pj1-f42.google.com [209.85.216.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B4AB2D0C72 for ; Mon, 1 Jun 2026 16:06:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 01 Jun 2026 09:06:39 -0700 (PDT) Received: from i386.168.1.127 ([2402:a00:163:2ce9:9c6f:e28:3da8:7980]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-36dd9205ddasm64218a91.14.2026.06.01.09.06.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jun 2026 09:06:38 -0700 (PDT) From: Hrushiraj Gandhi To: Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Hrushiraj Gandhi Subject: [PATCH v5 3/3] arm64: dts: rockchip: add Vicharak Axon board Date: Mon, 1 Jun 2026 21:36:03 +0530 Message-ID: <20260601160603.167706-4-hrushirajg23@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260601160603.167706-1-hrushirajg23@gmail.com> References: <20260601160603.167706-1-hrushirajg23@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add initial support for the Vicharak Axon single-board computer based on the Rockchip RK3588 SoC. The board supports: - eMMC storage - microSD card - Gigabit Ethernet - HDMI output (dual HDMI) - HDMI input - USB 2.0 host ports - PCIe 2.0 slots - PCIe 3.0 x4 slot - SATA - RTC - Status LEDs The board uses an RK806 PMIC and provides the regulators required by the RK3588 SoC. Signed-off-by: Hrushiraj Gandhi --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/rk3588-vicharak-axon.dts | 983 ++++++++++++++++++ 2 files changed, 984 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-vicharak-axon.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index cb55c6b70d0e..b10c6d80c5cc 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -211,6 +211,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-tiger-haikou.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-tiger-haikou-video-demo.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-toybrick-x0.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-turing-rk1.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-vicharak-axon.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588s-coolpi-4b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588s-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588s-gameforce-ace.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vicharak-axon.dts b/arch/a= rm64/boot/dts/rockchip/rk3588-vicharak-axon.dts new file mode 100644 index 000000000000..f0ba75a750e8 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-vicharak-axon.dts @@ -0,0 +1,983 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include "rk3588.dtsi" + +/ { + model =3D "Vicharak Axon"; + compatible =3D "vicharak,axon", "rockchip,rk3588"; + + aliases { + mmc0 =3D &sdmmc; + mmc1 =3D &sdhci; + mmc2 =3D &sdio; + serial2 =3D &uart2; + }; + + chosen { + stdout-path =3D "serial2:1500000n8"; + }; + + hdmi0-con { + compatible =3D "hdmi-connector"; + type =3D "a"; + + port { + hdmi0_con_in: endpoint { + remote-endpoint =3D <&hdmi0_out_con>; + }; + }; + }; + + hdmi1-con { + compatible =3D "hdmi-connector"; + type =3D "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint =3D <&hdmi1_out_con>; + }; + }; + }; + + leds { + compatible =3D "gpio-leds"; + status =3D "okay"; + + power_led: power-led { + color =3D ; + function =3D LED_FUNCTION_STATUS; + gpios =3D <&pca9554 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + }; + + status_led: status-led { + color =3D ; + function =3D LED_FUNCTION_STATUS; + gpios =3D <&pca9554 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "none"; + }; + }; + + pcie20_avdd0v85: regulator-pcie20-avdd0v85 { + compatible =3D "regulator-fixed"; + regulator-name =3D "pcie20_avdd0v85"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + vin-supply =3D <&vdd_0v85_s0>; + }; + + pcie20_avdd1v8: regulator-pcie20-avdd1v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "pcie20_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: regulator-pcie30-avdd0v75 { + compatible =3D "regulator-fixed"; + regulator-name =3D "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + vin-supply =3D <&vdd_0v75_s0>; + }; + + pcie30_avdd1v8: regulator-pcie30-avdd1v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&avcc_1v8_s0>; + }; + + sata_vcc_5v0: regulator-sata-vcc-5v0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "sata_vcc_5v0"; + startup-delay-us =3D <5000>; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc12v_dcin>; + }; + vcc0_4v0: vcc4v0_sys: regulator-vcc0-4v0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc0_4v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <4000000>; + regulator-max-microvolt =3D <4000000>; + vin-supply =3D <&vcc12v_dcin>; + }; + + vcc12v_dcin: regulator-vcc12v-dcin { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + }; + + vcc3v3_io_expander: regulator-vcc3v3-io-expander { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_io_expander"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + + vcc3v3_pcie20_sata30: regulator-vcc3v3-pcie20-sata30 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_pcie20_sata30"; + regulator-boot-on; + regulator-always-on; + enable-active-high; + gpios =3D <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + vin-supply =3D <&vcc12v_dcin>; + }; + + vcc3v3_pcie30: regulator-vcc3v3-pcie30 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_pcie30"; + regulator-boot-on; + regulator-always-on; + enable-active-high; + gpios =3D <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc12v_dcin>; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc12v_dcin>; + }; + + vcc5v0_usb20_host: regulator-vcc5v0-usb20-host { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_usb20_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc5v0_sys>; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + vin-supply =3D <&vcc5v0_sys>; + }; + +}; + + +&combphy0_ps { + status =3D "okay"; +}; + +&combphy1_ps { + status =3D "okay"; +}; + +&combphy2_psu { + status =3D "okay"; +}; + +&cpu_b0 { + cpu-supply =3D <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply =3D <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply =3D <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply =3D <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&gmac1 { + clock_in_out =3D "output"; + phy-handle =3D <&rgmii_phy>; + phy-mode =3D "rgmii-rxid"; + phy-supply =3D <&vcc_3v3_s3>; + pinctrl-0 =3D <&gmac1_rgmii_bus + &gmac1_rgmii_clk + &gmac1_rx_bus2 + &gmac1_tx_bus2 + &gmac1_miim>; + pinctrl-names =3D "default"; + snps,reset-active-low; + snps,reset-delays-us =3D <0 20000 100000>; + snps,reset-gpio =3D <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + rx_delay =3D <0x00>; + tx_delay =3D <0x43>; + status =3D "okay"; +}; + +&gpu { + mali-supply =3D <&vdd_gpu_s0>; + status =3D "okay"; +}; + +&hdmi0 { + status =3D "okay"; +}; + +&hdmi0_in { + hdmi0_in_vp0: endpoint { + remote-endpoint =3D <&vp0_out_hdmi0>; + }; +}; + +&hdmi0_out { + hdmi0_out_con: endpoint { + remote-endpoint =3D <&hdmi0_con_in>; + }; +}; + +&hdmi0_sound { + status =3D "okay"; +}; + +&hdmi1 { + status =3D "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp1: endpoint { + remote-endpoint =3D <&vp1_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint =3D <&hdmi1_con_in>; + }; +}; + +&hdmi1_sound { + status =3D "okay"; +}; + +&hdmi_receiver { + pinctrl-0 =3D <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_= sda &hdmirx_hpd>; + pinctrl-names =3D "default"; + hpd-gpios =3D <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>; + status =3D "okay"; +}; + +&hdmi_receiver_cma { + status =3D "okay"; +}; + +&hdptxphy0 { + status =3D "okay"; +}; + +&hdptxphy1 { + status =3D "okay"; +}; + +&i2c0 { + pinctrl-0 =3D <&i2c0m2_xfer>; + pinctrl-names =3D "default"; + status =3D "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible =3D "rockchip,rk8602"; + fcs,suspend-voltage-selector =3D <1>; + reg =3D <0x42>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <1050000>; + regulator-min-microvolt =3D <550000>; + regulator-name =3D "vdd_cpu_big0_s0"; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible =3D "rockchip,rk8603", "rockchip,rk8602"; + fcs,suspend-voltage-selector =3D <1>; + reg =3D <0x43>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <1050000>; + regulator-min-microvolt =3D <550000>; + regulator-name =3D "vdd_cpu_big1_s0"; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + hym8563: rtc@51 { + compatible =3D "haoyu,hym8563"; + reg =3D <0x51>; + #clock-cells =3D <0>; + clock-output-names =3D "hym8563"; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rtc_int>; + wakeup-source; + status =3D "okay"; + }; +}; + +&i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c1m2_xfer>; + status =3D "okay"; + + vdd_npu_s0: regulator@42 { + compatible =3D "rockchip,rk8602"; + reg =3D <0x42>; + fcs,suspend-voltage-selector =3D <1>; + regulator-name =3D "vdd_npu_s0"; + regulator-boot-on; + regulator-enable-ramp-delay =3D <500>; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c6 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c6m0_xfer>; + status =3D "okay"; + + pca9554: gpio@24 { + compatible =3D "nxp,pca9554"; + #gpio-cells =3D <2>; + gpio-controller; + reg =3D <0x24>; + vcc-supply =3D <&vcc3v3_io_expander>; + status =3D "okay"; + }; +}; + +&sdhci { + bus-width =3D <8>; + full-pwr-cycle-in-suspend; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sd; + no-sdio; + non-removable; + vmmc-supply =3D <&vcc_3v3_s3>; + vqmmc-supply =3D <&vcc_1v8_s3>; + status =3D "okay"; +}; + +&sdmmc { + bus-width =3D <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios =3D <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency =3D <200000000>; + no-mmc; + no-sdio; + sd-uhs-sdr104; + vmmc-supply =3D <&vcc_3v3_s3>; + vqmmc-supply =3D <&vccio_sd_s0>; + status =3D "okay"; +}; + +&spi2 { + assigned-clock-rates =3D <200000000>; + assigned-clocks =3D <&cru CLK_SPI2>; + num-cs =3D <1>; + pinctrl-0 =3D <&spi2m2_cs0 &spi2m2_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmic@0 { + reg =3D <0>; + compatible =3D "rockchip,rk806"; + #gpio-cells =3D <2>; + gpio-controller; + interrupt-parent =3D <&gpio0>; + interrupts =3D <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names =3D "default", "pmic-power-off"; + pinctrl-0 =3D <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + pinctrl-1 =3D <&rk806_dvs1_pwrdn>; + spi-max-frequency =3D <1000000>; + + vcc1-supply =3D <&vcc5v0_sys>; + vcc2-supply =3D <&vcc5v0_sys>; + vcc3-supply =3D <&vcc5v0_sys>; + vcc4-supply =3D <&vcc5v0_sys>; + vcc5-supply =3D <&vcc5v0_sys>; + vcc6-supply =3D <&vcc5v0_sys>; + vcc7-supply =3D <&vcc5v0_sys>; + vcc8-supply =3D <&vcc5v0_sys>; + vcc9-supply =3D <&vcc5v0_sys>; + vcc10-supply =3D <&vcc5v0_sys>; + vcc11-supply =3D <&vcc_2v0_pldo_s3>; + vcc12-supply =3D <&vcc5v0_sys>; + vcc13-supply =3D <&vcc_1v1_nldo_s3>; + vcc14-supply =3D <&vcc_1v1_nldo_s3>; + vcca-supply =3D <&vcc5v0_sys>; + + rk806_dvs1_null: rk806_dvs1_null { + pins =3D "gpio_pwrctrl1"; + function =3D "pin_fun0"; + }; + + rk806_dvs1_slp: rk806_dvs1_slp { + pins =3D "gpio_pwrctrl1"; + function =3D "pin_fun1"; + }; + + rk806_dvs1_pwrdn: rk806_dvs1_pwrdn { + pins =3D "gpio_pwrctrl1"; + function =3D "pin_fun2"; + }; + + rk806_dvs1_rst: rk806_dvs1_rst { + pins =3D "gpio_pwrctrl1"; + function =3D "pin_fun3"; + }; + + rk806_dvs2_null: rk806_dvs2_null { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun0"; + }; + + rk806_dvs2_slp: rk806_dvs2_slp { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun1"; + }; + + rk806_dvs2_pwrdn: rk806_dvs2_pwrdn { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun2"; + }; + + rk806_dvs2_rst: rk806_dvs2_rst { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun3"; + }; + + rk806_dvs2_dvs: rk806_dvs2_dvs { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun4"; + }; + + rk806_dvs2_gpio: rk806_dvs2_gpio { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun5"; + }; + + rk806_dvs3_null: rk806_dvs3_null { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun0"; + }; + + rk806_dvs3_slp: rk806_dvs3_slp { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun1"; + }; + + rk806_dvs3_pwrdn: rk806_dvs3_pwrdn { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun2"; + }; + + rk806_dvs3_rst: rk806_dvs3_rst { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun3"; + }; + + rk806_dvs3_dvs: rk806_dvs3_dvs { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun4"; + }; + + rk806_dvs3_gpio: rk806_dvs3_gpio { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun5"; + }; + + regulators { + vdd_gpu_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_gpu_s0"; + regulator-enable-ramp-delay =3D <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <750000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <750000>; + }; + }; + + vdd_vdenc_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <900000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name =3D "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <2000000>; + regulator-max-microvolt =3D <2000000>; + regulator-name =3D "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name =3D "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-name =3D "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + regulator-name =3D "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-name =3D "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <837500>; + regulator-max-microvolt =3D <837500>; + regulator-name =3D "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-name =3D "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + regulator-name =3D "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&mdio1 { + rgmii_phy: phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0x1>; + }; +}; + +&pcie2x1l0 { + reset-gpios =3D <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie2_0_rst>; + vpcie3v3-supply =3D <&vcc3v3_pcie20_sata30>; + status =3D "okay"; +}; + +&pcie2x1l1 { + reset-gpios =3D <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie2_1_rst>; + vpcie3v3-supply =3D <&vcc3v3_pcie20_sata30>; + status =3D "okay"; +}; + +&pcie2x1l2 { + status =3D "disabled"; +}; + +&pcie30phy { + status =3D "okay"; +}; + +&pcie3x4 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie3_reset>; + reset-gpios =3D <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc3v3_pcie30>; + status =3D "okay"; +}; + +&pinctrl { + + hdmirx { + hdmirx_hpd: hdmirx-5v-detection { + rockchip,pins =3D <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + + hym8563 { + rtc_int: rtc-int { + rockchip,pins =3D + <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie2 { + pcie2_0_rst: pcie2-0-rst { + rockchip,pins =3D + <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie2_1_rst: pcie2-1-rst { + rockchip,pins =3D + <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie3 { + pcie3_reset: pcie3-reset { + rockchip,pins =3D + <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + +}; + +&saradc { + vref-supply =3D <&avcc_1v8_s0>; + status =3D "okay"; +}; + +&sata0 { + status =3D "okay"; +}; + +&tsadc { + status =3D "okay"; +}; +&u2phy2 { + status =3D "okay"; +}; + +&u2phy2_host { + phy-supply =3D <&vcc5v0_usb20_host>; + status =3D "okay"; +}; + +&u2phy3 { + status =3D "okay"; +}; + +&u2phy3_host { + phy-supply =3D <&vcc5v0_usb20_host>; + status =3D "okay"; +}; + +&uart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart2m0_xfer>; + status =3D "okay"; +}; + +&usb_host0_ehci { + status =3D "okay"; +}; + +&usb_host0_ohci { + status =3D "okay"; +}; + +&usb_host1_ehci { + status =3D "okay"; +}; + +&usb_host1_ohci { + status =3D "okay"; +}; + +&vop { + status =3D "okay"; +}; + +&vop_mmu { + status =3D "okay"; +}; + +&vp0 { + vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg =3D ; + remote-endpoint =3D <&hdmi0_in_vp0>; + }; +}; + +&vp1 { + vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg =3D ; + remote-endpoint =3D <&hdmi1_in_vp1>; + }; +}; --=20 2.47.3