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Mon, 1 Jun 2026 03:48:48 -0700 From: Ashish Mhetre To: , , , , CC: , , , , Ashish Mhetre Subject: [PATCH v3 1/3] iommu/arm-smmu-v3: Factor out CMDQ batch force-sync conditions Date: Mon, 1 Jun 2026 10:48:43 +0000 Message-ID: <20260601104845.995005-2-amhetre@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260601104845.995005-1-amhetre@nvidia.com> References: <20260601104845.995005-1-amhetre@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023D7:EE_|MN2PR12MB4335:EE_ X-MS-Office365-Filtering-Correlation-Id: 21caffa8-edd4-44f6-e3fa-08debfcb62e8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|376014|36860700016|18002099003|22082099003|56012099006|11063799006; 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charset="utf-8" From: Nicolin Chen arm_smmu_cmdq_batch_add_cmd_p() carries two distinct reasons for flushing the current batch with a CMD_SYNC before appending the new command: - The batch's pre-assigned cmdq does not support the new command. - The Arm erratum 2812531 workaround (ARM_SMMU_OPT_CMDQ_FORCE_SYNC) forces a SYNC at one entry before the batch is full. Lift those checks into a new arm_smmu_cmdq_batch_force_sync() helper so that adding another force-sync condition becomes a one-line addition. No functional change. Signed-off-by: Nicolin Chen Signed-off-by: Ashish Mhetre --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 26 ++++++++++++++++----- 1 file changed, 20 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 9be589d14a3b..4d29bd343460 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -847,16 +847,30 @@ static void arm_smmu_cmdq_batch_init_cmd(struct arm_s= mmu_device *smmu, cmds->cmdq =3D arm_smmu_get_cmdq(smmu, cmd); } =20 +static bool arm_smmu_cmdq_batch_force_sync(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq_batch *cmds, + struct arm_smmu_cmd *cmd) +{ + if (!cmds->num) + return false; + + /* The batch's pre-assigned cmdq doesn't support the new command */ + if (!arm_smmu_cmdq_supports_cmd(cmds->cmdq, cmd)) + return true; + + /* Arm erratum 2812531 */ + if (cmds->num =3D=3D CMDQ_BATCH_ENTRIES - 1 && + (smmu->options & ARM_SMMU_OPT_CMDQ_FORCE_SYNC)) + return true; + + return false; +} + static void arm_smmu_cmdq_batch_add_cmd_p(struct arm_smmu_device *smmu, struct arm_smmu_cmdq_batch *cmds, struct arm_smmu_cmd *cmd) { - bool force_sync =3D (cmds->num =3D=3D CMDQ_BATCH_ENTRIES - 1) && - (smmu->options & ARM_SMMU_OPT_CMDQ_FORCE_SYNC); - bool unsupported_cmd; - - unsupported_cmd =3D !arm_smmu_cmdq_supports_cmd(cmds->cmdq, cmd); - if (force_sync || unsupported_cmd) { + if (arm_smmu_cmdq_batch_force_sync(smmu, cmds, cmd)) { arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmdq, cmds->cmds, cmds->num, true); arm_smmu_cmdq_batch_init_cmd(smmu, cmds, cmd); --=20 2.50.1 From nobody Mon Jun 8 06:36:26 2026 Received: from DM1PR04CU001.outbound.protection.outlook.com (mail-centralusazon11010043.outbound.protection.outlook.com [52.101.61.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EB31E39D3FD; Mon, 1 Jun 2026 10:49:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Tegra264 SMMU is affected by erratum where a TLB entry can survive an invalidation that races with concurrent traffic targeting the same entry. The hardware-recommended software workaround is to issue every CFGI/TLBI command (each followed by CMD_SYNC) twice. The second issue is guaranteed to evict the entry. ATC_INV is not affected and must not be doubled. The erratum is not flagged by any SMMUv3 IDR/IIDR register, so it cannot be detected from hardware ID. Tegra264 boots from device tree only and has no ACPI/IORT support, so detection is through device tree only. Add the ARM_SMMU_OPT_TLBI_TWICE option and set it on instances matching the existing "nvidia,tegra264-smmu" compatible. Also add a static-inline arm_smmu_cmd_needs_tlbi_twice() classifier in arm-smmu-v3.h so that subsequent changes wiring the workaround into the CMDQ submission and iommufd batching paths can share a single predicate. No callers consume the option yet; a subsequent change will wire the workaround into the CMDQ issue paths. Signed-off-by: Ashish Mhetre Reviewed-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 4 ++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 40 +++++++++++++++++++++ 2 files changed, 43 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 4d29bd343460..08684bd40a6d 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -5243,8 +5243,10 @@ static int arm_smmu_device_dt_probe(struct platform_= device *pdev, if (of_dma_is_coherent(dev->of_node)) smmu->features |=3D ARM_SMMU_FEAT_COHERENCY; =20 - if (of_device_is_compatible(dev->of_node, "nvidia,tegra264-smmu")) + if (of_device_is_compatible(dev->of_node, "nvidia,tegra264-smmu")) { tegra_cmdqv_dt_probe(dev->of_node, smmu); + smmu->options |=3D ARM_SMMU_OPT_TLBI_TWICE; + } =20 return ret; } diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 16353596e08a..106034c348a1 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -928,6 +928,14 @@ struct arm_smmu_device { #define ARM_SMMU_OPT_MSIPOLL (1 << 2) #define ARM_SMMU_OPT_CMDQ_FORCE_SYNC (1 << 3) #define ARM_SMMU_OPT_TEGRA241_CMDQV (1 << 4) +/* + * Tegra264 erratum: a TLB entry can survive an invalidation that races + * with concurrent traffic targeting the same entry. The software + * workaround is to issue every CFGI/TLBI command twice, each followed + * by CMD_SYNC. The second issue is guaranteed to evict the entry. + * ATC_INV commands are not affected and must not be doubled. + */ +#define ARM_SMMU_OPT_TLBI_TWICE (1 << 5) u32 options; =20 struct arm_smmu_cmdq cmdq; @@ -1211,6 +1219,38 @@ int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_devi= ce *smmu, struct arm_smmu_cmd *cmds, int n, bool sync); =20 +/* + * Returns true if @cmd is one of the CFGI_* or TLBI_* commands covered + * by the Tegra264 erratum (see ARM_SMMU_OPT_TLBI_TWICE) on an affected + * SMMU instance. + */ +static inline bool arm_smmu_cmd_needs_tlbi_twice(struct arm_smmu_device *s= mmu, + struct arm_smmu_cmd *cmd) +{ + if (!(smmu->options & ARM_SMMU_OPT_TLBI_TWICE)) + return false; + + switch (FIELD_GET(CMDQ_0_OP, cmd->data[0])) { + case CMDQ_OP_CFGI_STE: + case CMDQ_OP_CFGI_ALL: + case CMDQ_OP_CFGI_CD: + case CMDQ_OP_CFGI_CD_ALL: + case CMDQ_OP_TLBI_NH_ALL: + case CMDQ_OP_TLBI_NH_ASID: + case CMDQ_OP_TLBI_NH_VA: + case CMDQ_OP_TLBI_NH_VAA: + case CMDQ_OP_TLBI_EL2_ALL: + case CMDQ_OP_TLBI_EL2_ASID: + case CMDQ_OP_TLBI_EL2_VA: + case CMDQ_OP_TLBI_S12_VMALL: + case CMDQ_OP_TLBI_S2_IPA: + case CMDQ_OP_TLBI_NSNH_ALL: + return true; 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charset="utf-8" Apply the workaround for Tegra264 erratum ARM_SMMU_OPT_TLBI_TWICE by issuing every CFGI/TLBI cmdlist twice on affected SMMU instances, with CMD_SYNC after each. The erratum requires this exact sequencing: TLBI/CFGI ... CMD_SYNC TLBI/CFGI ... CMD_SYNC Rename the existing arm_smmu_cmdq_issue_cmdlist() to __arm_smmu_cmdq_issue_cmdlist() and add a thin wrapper that, on affected SMMUs and when @sync is true, re-issues the same cmdlist a second time when arm_smmu_cmd_needs_tlbi_twice() is true. For the in-tree batching path, register the Tegra264 condition with arm_smmu_cmdq_batch_force_sync() so that a full batch carrying CFGI/TLBI commands flushes with sync=3Dtrue. For iommufd VSMMU path add an arm_vsmmu_can_batch_cmd() predicate that splits the iommufd batch at cmd which doesn't need doubling. Suggested-by: Nicolin Chen Signed-off-by: Ashish Mhetre Reviewed-by: Nicolin Chen --- .../arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 23 +++++++++++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 36 ++++++++++++++++--- 2 files changed, 54 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/= iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index 1e9f7d2de344..78c96a2b652b 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -350,6 +350,26 @@ static int arm_vsmmu_convert_user_cmd(struct arm_vsmmu= *vsmmu, return 0; } =20 +/* + * On Tegra264, arm_smmu_cmdq_issue_cmdlist() doubles every CFGI/TLBI + * submission (see ARM_SMMU_OPT_TLBI_TWICE). The doubling decision is + * taken once per cmdlist based on the first command, so a single + * batch must not mix commands that need doubling with commands that + * do not. Split the iommufd batch whenever the next user command + * crosses that boundary. + */ +static bool arm_vsmmu_can_batch_cmd(struct arm_smmu_device *smmu, + struct arm_vsmmu_invalidation_cmd *last, + struct arm_vsmmu_invalidation_cmd *next) +{ + struct arm_smmu_cmd next_cmd =3D { + .data[0] =3D le64_to_cpu(next->ucmd.cmd[0]), + }; + + return arm_smmu_cmd_needs_tlbi_twice(smmu, &last->cmd) =3D=3D + arm_smmu_cmd_needs_tlbi_twice(smmu, &next_cmd); +} + int arm_vsmmu_cache_invalidate(struct iommufd_viommu *viommu, struct iommu_user_data_array *array) { @@ -382,7 +402,8 @@ int arm_vsmmu_cache_invalidate(struct iommufd_viommu *v= iommu, =20 /* FIXME work in blocks of CMDQ_BATCH_ENTRIES and copy each block? */ cur++; - if (cur !=3D end && (cur - last) !=3D CMDQ_BATCH_ENTRIES - 1) + if (cur !=3D end && (cur - last) !=3D CMDQ_BATCH_ENTRIES - 1 && + arm_vsmmu_can_batch_cmd(smmu, last, cur)) continue; =20 /* FIXME always uses the main cmdq rather than trying to group by type */ diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 08684bd40a6d..f38c21b56f28 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -698,10 +698,10 @@ static void arm_smmu_cmdq_write_entries(struct arm_sm= mu_cmdq *cmdq, * insert their own list of commands then all of the commands from one * CPU will appear before any of the commands from the other CPU. */ -int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, - struct arm_smmu_cmdq *cmdq, - struct arm_smmu_cmd *cmds, int n, - bool sync) +static int __arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq, + struct arm_smmu_cmd *cmds, int n, + bool sync) { struct arm_smmu_cmd cmd_sync; u32 prod; @@ -820,6 +820,26 @@ int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device= *smmu, return ret; } =20 +int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq, + struct arm_smmu_cmd *cmds, int n, + bool sync) +{ + int ret =3D __arm_smmu_cmdq_issue_cmdlist(smmu, cmdq, cmds, n, sync); + + /* + * On Tegra264 (see ARM_SMMU_OPT_TLBI_TWICE) re-issue the same + * cmdlist with another CMD_SYNC to satisfy the erratum. + * Callers must ensure the batch carries a uniform opcode class + * so that checking the first command is enough; the iommufd + * VSMMU path enforces this with arm_vsmmu_can_batch_cmd(). + */ + if (!ret && sync && arm_smmu_cmd_needs_tlbi_twice(smmu, &cmds[0])) + ret =3D __arm_smmu_cmdq_issue_cmdlist(smmu, cmdq, cmds, n, sync); + + return ret; +} + static int arm_smmu_cmdq_issue_cmd_p(struct arm_smmu_device *smmu, struct arm_smmu_cmd *cmd, bool sync) { @@ -863,6 +883,14 @@ static bool arm_smmu_cmdq_batch_force_sync(struct arm_= smmu_device *smmu, (smmu->options & ARM_SMMU_OPT_CMDQ_FORCE_SYNC)) return true; =20 + /* + * Tegra264 erratum (see ARM_SMMU_OPT_TLBI_TWICE). The batch holds + * a uniform opcode class, so checking the first command is enough. + */ + if (cmds->num =3D=3D CMDQ_BATCH_ENTRIES && + arm_smmu_cmd_needs_tlbi_twice(smmu, &cmds->cmds[0])) + return true; + return false; } =20 --=20 2.50.1