From nobody Mon Jun 8 05:29:11 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C9C4B37F002; Mon, 1 Jun 2026 20:36:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780346184; cv=none; b=md5zUaRuX9b3zSe0pBI/nYbcXiLUMutTywpmkqtsTAlXmfmOPJYMq8X1vkWtqjTl/QCx+Upx+af/eaYDPT9khxG8Qt3NNZZpy71jXv/h2U6oPafbE+ylmMdjFQCEH9/+NtaBD9/waZ9alSnv7xjk7i1VX0HsvgT7/TTxDZPSyWQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780346184; c=relaxed/simple; bh=oVWQwUJrVLgt2ds0hOtdw/u3HLWC21FLWSsgjsdIJHo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=OHIVw/hSlow9AcA+vaf/SS40f5X1X/BP0J5RBcvwvc8/mLaMBp+W5en1w6BdB/ZEsxyjcife7ANJ+612lOShTW+0axuff/iRucvUbgGDSZ4syYuFwB95fE3O6QF9qBUhJlEuegEKbWU6LIP4TWq6mPfFaZoVk7dTceoaCIYwe2A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Vu5fMjrP; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Vu5fMjrP" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B8BB91F0089E; Mon, 1 Jun 2026 20:36:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1780346183; bh=srvdFyNcKWrG6UhIb2zhEmit0iT5/TwfHnN+QzKDIL4=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=Vu5fMjrPL7VYm/NMsk+fNiF3uq5/IkU3WA5AHlPBzQfbiMgcVhdNxvtBgtkEa0UZY m2cUjSf6mFXgxr00SFaRZgk2hXmFKuhFhHiw3wF3fgQjuq1PUEX9WqjICXhm+2xx2i alJK209yKLmVdvEdDTzmQKPtIKpdyRjtOIgqLUo0ppBpt2sFin53t351+FVffLpHF7 8abIWTN3Al45EAIc6Az/5+4AeUNy7TBWhWqLEl4RfbY9Hhg5uwx50fJRLyCFGXPYjA JVMKxykKaHpSxUeGGRRBrXjDkFIo0U8/saHHeNYk2WKibfjLYBf2vBgQZ1vf6dsU0F YBTx0X6Noe4dQ== From: Drew Fustini Date: Mon, 01 Jun 2026 13:35:55 -0700 Subject: [PATCH RFC v6 01/18] dt-bindings: riscv: Add Ssqosid extension description Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-1-baf00f50028a@kernel.org> References: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-0-baf00f50028a@kernel.org> In-Reply-To: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-0-baf00f50028a@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , Conor Dooley , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, Gong Shuai , Gong Shuai , liu.qingtao2@zte.com.cn, Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Rob Herring , Conor Dooley , Krzysztof Kozlowski , "Rafael J. Wysocki" , Len Brown , Robert Moore , Sunil V L , Drew Fustini , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Sebastian Andrzej Siewior , Clark Williams , Steven Rostedt , Jonathan Corbet Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org, linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, devicetree@vger.kernel.org, Paul Walmsley , Conor Dooley , linux-rt-devel@lists.linux.dev, linux-doc@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1227; i=fustini@kernel.org; h=from:subject:message-id; bh=oVWQwUJrVLgt2ds0hOtdw/u3HLWC21FLWSsgjsdIJHo=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTJvnWS+l7dmmLiodpjdaLoX/znPxLpDTs/NbouDP55T f5w3MfKjlIWBjEuBlkxRZZNH/IuLPEK/bpg/ottMHNYmUCGMHBxCsBEhGYw/BVkVMk5d8m4M+Cp TZ/FIv2r7/lCtiifuLQ4hGuuV5bRyjkMf6Usfviqzo4MM3SLy/dO/rSueJ/FJdOSK09TNWxU+FT c2QE= X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Document the ratified Supervisor-mode Quality of Service ID (Ssqosid) extension v1.0. Link: https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0 Acked-by: Conor Dooley Signed-off-by: Drew Fustini --- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index 2b0a8a93bb21..1c6f091518d4 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -232,6 +232,12 @@ properties: ratified at commit d70011dde6c2 ("Update to ratified state") of riscv-j-extension. =20 + - const: ssqosid + description: | + The standard Ssqosid extension for Quality of Service ID is + ratified as v1.0 in commit d9c616497fde ("Merge pull + request #7 from ved-rivos/Ratified") of riscv-ssqosid. + - const: ssstateen description: | The standard Ssstateen extension for supervisor-mode view of t= he --=20 2.43.0 From nobody Mon Jun 8 05:29:11 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF01D38AC6A; Mon, 1 Jun 2026 20:36:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780346185; cv=none; b=isnx/5Pb7B1hLId7tBbjsgqSyzkz2N3Z78dEuFhG2x94oBn5ccmvqczxL9VFaXY7w50SRT8l2RFH8IAK5EuB6qtdw4zIcNZpCDRp9BaQ4oNPMfqBDMFTLgunFb5yRo6laz/7Mv4wslvq8+vTXzmpJyX72Zj5CZ+N8CSIw8+RA0A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780346185; c=relaxed/simple; bh=58g1568NRL7/SI4d2HoFSQSOKccqgmn0k03hr3pJQEU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Fzcwff1SuH17pAwJSObigJ7GAejHHe3JtZxF2SuT6lgBfOr4oBL1KUmxCNjUlGok0ORSAbQtS7//9j0vLjTxhpPpV9pzz05o5LZniNqKhyGGBx0jkq+q4SB+Tg4As226akCHXYAScc2jB631+vf63oqcv/hYG4gfWlwVJ3+njUo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GXMOM7Sn; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GXMOM7Sn" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A21FA1F008A3; Mon, 1 Jun 2026 20:36:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1780346184; bh=SoMF0NvEK/nHml8RMjqK0ASTpVqLJvBd+3O6LznwQbI=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=GXMOM7SnhidoV1UMUeJNclAeD8OoXOwUzUM0FxZsmvCRDTWp4Xsl9JxJSUpQiqj2B OL+YZDxxgJvujB6PC547tkvruKBnWjXn5N2kvWJpOFSre96R5K8FmRQJMDb27vTVPd fhMvdvsXx0cezQJWpkjx7i4HunOe+HV38BTi5YyQs4hbx0M9wASblLoWWMzQueFi4f IlfyNYuJGcV7KUuTtkvNx/nX5bTe9r1CjUvMsO2fB15MdmDbIeBGANzU3UG1C8yK06 /h/sfXS1Zwvn/i3LqHIMCY73aQmmakwdVSwKkxj9WmXOG70kmqAqRuC7M+clEp7dfP twwVejwSDmvig== From: Drew Fustini Date: Mon, 01 Jun 2026 13:35:56 -0700 Subject: [PATCH RFC v6 02/18] riscv: detect the Ssqosid extension Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-2-baf00f50028a@kernel.org> References: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-0-baf00f50028a@kernel.org> In-Reply-To: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-0-baf00f50028a@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , Conor Dooley , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, Gong Shuai , Gong Shuai , liu.qingtao2@zte.com.cn, Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Rob Herring , Conor Dooley , Krzysztof Kozlowski , "Rafael J. Wysocki" , Len Brown , Robert Moore , Sunil V L , Drew Fustini , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Sebastian Andrzej Siewior , Clark Williams , Steven Rostedt , Jonathan Corbet Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org, linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, devicetree@vger.kernel.org, Paul Walmsley , Conor Dooley , linux-rt-devel@lists.linux.dev, linux-doc@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1637; i=fustini@kernel.org; h=from:subject:message-id; bh=58g1568NRL7/SI4d2HoFSQSOKccqgmn0k03hr3pJQEU=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTJvnVimy0sp5b18t78Bc8Vli++r7SgZEbCi1fn81/a3 w6LnbGyo6OUhUGMi0FWTJFl04e8C0u8Qr8umP9iG8wcViaQIQxcnAIwkfZ/jAwr7OwO8FQWc02T +Zb1ceVzyTvMN93PteSIO3CpzRDL7+Fk+B9xQ8RvmvLRLU++icV1Bi2NFPjvIZGanTMvqnhvTNB OFg4A X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Ssqosid is the RISC-V Quality-of-Service (QoS) Identifiers specification which defines the Supervisor Resource Management Configuration (srmcfg) register. Link: https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0 Co-developed-by: Kornel Dul=C4=99ba Signed-off-by: Kornel Dul=C4=99ba Signed-off-by: Drew Fustini --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 7ef8e5f55c8d..b83dae5cebb9 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -112,6 +112,7 @@ #define RISCV_ISA_EXT_ZCLSD 103 #define RISCV_ISA_EXT_ZICFILP 104 #define RISCV_ISA_EXT_ZICFISS 105 +#define RISCV_ISA_EXT_SSQOSID 106 =20 #define RISCV_ISA_EXT_XLINUXENVCFG 127 =20 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index f46aa5602d74..668a7e71ff1c 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -582,6 +582,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), __RISCV_ISA_EXT_SUPERSET(ssnpm, RISCV_ISA_EXT_SSNPM, riscv_xlinuxenvcfg_e= xts), + __RISCV_ISA_EXT_DATA(ssqosid, RISCV_ISA_EXT_SSQOSID), __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), __RISCV_ISA_EXT_DATA(svade, RISCV_ISA_EXT_SVADE), __RISCV_ISA_EXT_DATA_VALIDATE(svadu, RISCV_ISA_EXT_SVADU, riscv_ext_svadu= _validate), --=20 2.43.0 From nobody Mon Jun 8 05:29:11 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8EF273F65E0; Mon, 1 Jun 2026 20:36:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780346187; cv=none; b=fj1/UhFBNQWHyeTcmDWGolregj4yF7kdH2f5+0/vBgzll+flJQ91OG8qDvItJ4QKIc4HvrQ9RgsbuK7/p9xqHX92jiQfGa63PFVkcKo1uH9hGnKJElaDARQXTIYNZaFp6wrysPDJ3/wNej3Z6YLO1SfUEp/bZ6u2oW1l7DwCgvk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780346187; c=relaxed/simple; bh=Ru8n+b2Nb9I06Iq/XueF55Kvar2HGUuz3aKE1Dt+uzs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZRQycB1H48skjCgS2YtyUVkXfN6VEibjQqp/w2PGzaueqWfJt4eMtlHeZvEXHxBXEyUOw9YKqoETp/cNJdOTtlo6svNU+qGrZE/ndE9A6bP1+mqytlDuvBRQGCerLaT7vdwzXWHIO+uOJjdBR+Y41dmDrOup1T/hL+Hkv+3QWLY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SetxcZgw; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SetxcZgw" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7ACD21F008A4; Mon, 1 Jun 2026 20:36:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1780346185; bh=jacBUw3TuL0Ul9vWo6PSgvG0qXFvI3P77dpHaOwM/Oo=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=SetxcZgwBa61Znsw/andtsI/wEL/fwV3kb1y0EtGOJQ8fKWx8xDJ4sbQJdm+oiyS1 31O0U/SyMEX/JOv+o3QXPhkdJzoX2iqjsfILoyyDfj/29hyXwcYdVEDwfIt5b7vrQR K6bikkb8b8xFgQ69TUzXG5H33QUFjn+RlJWk0h/FKIAjmkBzSRAect4Mx4SlGu8BA7 oAJJa0kk/fbGSdUi4mpE1xQDU1Q2gt/9SxpiO/ExQ3Xv3RKUO1CuyWYob/Z6Qk8H95 y1g8rqVO8Le6phuvtb+AFU8YqSNxzW9Soe4Hvvow64qyOMpwH/6eAcIVKnzahjWXO7 X7P5czQ/Sp8ow== From: Drew Fustini Date: Mon, 01 Jun 2026 13:35:57 -0700 Subject: [PATCH RFC v6 03/18] riscv: add support for srmcfg CSR from Ssqosid extension Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-3-baf00f50028a@kernel.org> References: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-0-baf00f50028a@kernel.org> In-Reply-To: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-0-baf00f50028a@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , Conor Dooley , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, Gong Shuai , Gong Shuai , liu.qingtao2@zte.com.cn, Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Rob Herring , Conor Dooley , Krzysztof Kozlowski , "Rafael J. Wysocki" , Len Brown , Robert Moore , Sunil V L , Drew Fustini , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Sebastian Andrzej Siewior , Clark Williams , Steven Rostedt , Jonathan Corbet Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org, linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, devicetree@vger.kernel.org, Paul Walmsley , Conor Dooley , linux-rt-devel@lists.linux.dev, linux-doc@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=12220; i=fustini@kernel.org; h=from:subject:message-id; bh=Ru8n+b2Nb9I06Iq/XueF55Kvar2HGUuz3aKE1Dt+uzs=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTJvnWSt55dPK3/TdVB24uTToboBP8X+H5QRf7z1jX7u VWmsBaYdZSyMIhxMciKKbJs+pB3YYlX6NcF819sg5nDygQyhIGLUwAmoqTAyHCZvXbpnqXbZkYd f/sq02nhghW7lv/Uvqv54Eb5A+lNGdbvGBkWOlnKKlc5Nri/0Dl65eCpvOOeG4oE2DtafcMWvK+ Q12QBAA== X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Add support for the srmcfg CSR defined in the Ssqosid ISA extension. The CSR contains two fields: - Resource Control ID (RCID) for resource allocation - Monitoring Counter ID (MCID) for tracking resource usage Requests from a hart to shared resources are tagged with these IDs, allowing resource usage to be associated with the running task. Add a srmcfg field to thread_struct with the same format as the CSR so the scheduler can set the RCID and MCID for each task on context switch. A per-cpu cpu_srmcfg variable mirrors the CSR state to avoid redundant writes. L1D-hot memory access is faster than a CSR read and avoids traps under virtualization. A per-cpu cpu_srmcfg_default holds the default srmcfg for each CPU as set by resctrl CPU group assignment. On context switch, RCID and MCID inherit from the CPU default independently: a task whose thread RCID field is zero takes the CPU default's RCID, and likewise for MCID. Link: https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0 Assisted-by: Claude:claude-opus-4-7 Co-developed-by: Kornel Dul=C4=99ba Signed-off-by: Kornel Dul=C4=99ba Signed-off-by: Drew Fustini --- MAINTAINERS | 8 ++++ arch/riscv/Kconfig | 18 +++++++ arch/riscv/include/asm/csr.h | 5 ++ arch/riscv/include/asm/processor.h | 3 ++ arch/riscv/include/asm/qos.h | 87 +++++++++++++++++++++++++++++++++ arch/riscv/include/asm/switch_to.h | 3 ++ arch/riscv/kernel/Makefile | 2 + arch/riscv/kernel/qos.c | 98 ++++++++++++++++++++++++++++++++++= ++++ 8 files changed, 224 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index c2c6d79275c6..e694fb2a22d2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -23017,6 +23017,14 @@ F: drivers/perf/riscv_pmu.c F: drivers/perf/riscv_pmu_legacy.c F: drivers/perf/riscv_pmu_sbi.c =20 +RISC-V QOS RESCTRL SUPPORT +M: Drew Fustini +R: yunhui cui +L: linux-riscv@lists.infradead.org +S: Supported +F: arch/riscv/include/asm/qos.h +F: arch/riscv/kernel/qos.c + RISC-V RPMI AND MPXY DRIVERS M: Rahul Pathak M: Anup Patel diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index c5754942cf85..6abbb21f3a0d 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -591,6 +591,24 @@ config RISCV_ISA_SVNAPOT =20 If you don't know what to do here, say Y. =20 +config RISCV_ISA_SSQOSID + bool "Ssqosid extension support for supervisor mode Quality of Service ID" + depends on 64BIT + default n + help + Adds support for the Ssqosid ISA extension (Supervisor-mode + Quality of Service ID). + + Ssqosid defines the srmcfg CSR which allows the system to tag the + running process with an RCID (Resource Control ID) and MCID + (Monitoring Counter ID). The RCID is used to determine resource + allocation. The MCID is used to track resource usage in event + counters. + + For example, a cache controller may use the RCID to apply a + cache partitioning scheme and use the MCID to track how much + cache a process, or a group of processes, is using. + config RISCV_ISA_SVPBMT bool "Svpbmt extension support for supervisor mode page-based memory type= s" depends on 64BIT && MMU diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 31b8988f4488..7bce928e5daa 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -84,6 +84,10 @@ #define SATP_ASID_MASK _AC(0xFFFF, UL) #endif =20 +/* SRMCFG fields */ +#define SRMCFG_RCID_MASK GENMASK(11, 0) +#define SRMCFG_MCID_MASK GENMASK(27, 16) + /* Exception cause high bit - is an interrupt if set */ #define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1)) =20 @@ -328,6 +332,7 @@ #define CSR_STVAL 0x143 #define CSR_SIP 0x144 #define CSR_SATP 0x180 +#define CSR_SRMCFG 0x181 =20 #define CSR_STIMECMP 0x14D #define CSR_STIMECMPH 0x15D diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/pr= ocessor.h index 812517b2cec1..49a386d74cd3 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -123,6 +123,9 @@ struct thread_struct { /* A forced icache flush is not needed if migrating to the previous cpu. = */ unsigned int prev_cpu; #endif +#ifdef CONFIG_RISCV_ISA_SSQOSID + u32 srmcfg; +#endif }; =20 /* Whitelist the fstate from the task_struct for hardened usercopy */ diff --git a/arch/riscv/include/asm/qos.h b/arch/riscv/include/asm/qos.h new file mode 100644 index 000000000000..727d438454f3 --- /dev/null +++ b/arch/riscv/include/asm/qos.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_RISCV_QOS_H +#define _ASM_RISCV_QOS_H + +#include + +#ifdef CONFIG_RISCV_ISA_SSQOSID + +#include +#include +#include + +#include +#include +#include + +/* cached value of srmcfg csr for each cpu */ +DECLARE_PER_CPU(u32, cpu_srmcfg); + +/* default srmcfg value for each cpu, set via resctrl cpu assignment */ +DECLARE_PER_CPU(u32, cpu_srmcfg_default); + +static inline void __switch_to_srmcfg(struct task_struct *next) +{ + u32 thread_srmcfg, default_srmcfg; + + thread_srmcfg =3D READ_ONCE(next->thread.srmcfg); + default_srmcfg =3D __this_cpu_read(cpu_srmcfg_default); + + /* + * RCID and MCID inherit from cpu_srmcfg_default independently. + * RESCTRL_RESERVED_CLOSID and RESCTRL_RESERVED_RMID are both 0, + * so a per-field zero means "no task assignment for this + * dimension" and the CPU default supplies that field. Matches + * x86 RDT's __resctrl_sched_in() per-field logic. The fully + * unassigned (thread.srmcfg =3D=3D 0) and fully assigned (both + * fields non-zero) cases short-circuit the field math. + */ + if (thread_srmcfg =3D=3D 0) { + thread_srmcfg =3D default_srmcfg; + } else { + u32 rcid =3D FIELD_GET(SRMCFG_RCID_MASK, thread_srmcfg); + u32 mcid =3D FIELD_GET(SRMCFG_MCID_MASK, thread_srmcfg); + + if (rcid =3D=3D 0 || mcid =3D=3D 0) { + if (rcid =3D=3D 0) + rcid =3D FIELD_GET(SRMCFG_RCID_MASK, default_srmcfg); + if (mcid =3D=3D 0) + mcid =3D FIELD_GET(SRMCFG_MCID_MASK, default_srmcfg); + thread_srmcfg =3D FIELD_PREP(SRMCFG_RCID_MASK, rcid) | + FIELD_PREP(SRMCFG_MCID_MASK, mcid); + } + } + + if (thread_srmcfg !=3D __this_cpu_read(cpu_srmcfg)) { + /* + * Drain stores from the outgoing task before the CSR write + * so they retain the previous RCID/MCID tag at the cache + * interconnect. + */ + RISCV_FENCE(rw, o); + + __this_cpu_write(cpu_srmcfg, thread_srmcfg); + csr_write(CSR_SRMCFG, thread_srmcfg); + /* + * Order the csrw before the new task's loads/stores so they + * pick up the new tag. Zicsr 6.1.1 makes CSR writes weakly + * ordered (device-output) vs memory ops. Ssqosid v1.0 is + * silent so honor the general CSR rule. + */ + RISCV_FENCE(o, rw); + } +} + +static __always_inline bool has_srmcfg(void) +{ + return riscv_has_extension_unlikely(RISCV_ISA_EXT_SSQOSID); +} + +#else /* ! CONFIG_RISCV_ISA_SSQOSID */ + +struct task_struct; +static __always_inline bool has_srmcfg(void) { return false; } +static inline void __switch_to_srmcfg(struct task_struct *next) { } + +#endif /* CONFIG_RISCV_ISA_SSQOSID */ +#endif /* _ASM_RISCV_QOS_H */ diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/sw= itch_to.h index 0e71eb82f920..1c7ea53ec012 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -14,6 +14,7 @@ #include #include #include +#include =20 #ifdef CONFIG_FPU extern void __fstate_save(struct task_struct *save_to); @@ -119,6 +120,8 @@ do { \ __switch_to_fpu(__prev, __next); \ if (has_vector() || has_xtheadvector()) \ __switch_to_vector(__prev, __next); \ + if (has_srmcfg()) \ + __switch_to_srmcfg(__next); \ if (switch_to_should_flush_icache(__next)) \ local_flush_icache_all(); \ __switch_to_envcfg(__next); \ diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index cabb99cadfb6..ebe1c3588177 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -128,3 +128,5 @@ obj-$(CONFIG_ACPI_NUMA) +=3D acpi_numa.o =20 obj-$(CONFIG_GENERIC_CPU_VULNERABILITIES) +=3D bugs.o obj-$(CONFIG_RISCV_USER_CFI) +=3D usercfi.o + +obj-$(CONFIG_RISCV_ISA_SSQOSID) +=3D qos.o diff --git a/arch/riscv/kernel/qos.c b/arch/riscv/kernel/qos.c new file mode 100644 index 000000000000..d18b99b195e7 --- /dev/null +++ b/arch/riscv/kernel/qos.c @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +/* + * Cached value of srmcfg csr for each cpu. Seeded to U32_MAX so the next + * __switch_to_srmcfg() unconditionally writes the CSR; the encoding + * MCID << 16 | RCID with both fields well under 16 bits can never + * produce this sentinel. This covers early-boot context switches that + * happen before riscv_srmcfg_init() runs as an arch_initcall. + */ +DEFINE_PER_CPU(u32, cpu_srmcfg) =3D U32_MAX; + +/* default srmcfg value for each cpu, set via resctrl cpu assignment */ +DEFINE_PER_CPU(u32, cpu_srmcfg_default); + +/* + * Seed the per-CPU srmcfg cache to a sentinel that no real srmcfg encoding + * can produce (MCID << 16 | RCID, both fields well under 16 bits) so the + * next __switch_to_srmcfg() unconditionally writes the CSR. Ssqosid v1.0 + * leaves CSR state across hart stop/start implementation-defined, so the + * cached value cannot be trusted after online. + */ +static int riscv_srmcfg_online(unsigned int cpu) +{ + per_cpu(cpu_srmcfg, cpu) =3D U32_MAX; + return 0; +} + +/* + * Invalidate the cache on offline too. The sentinel persists across the + * offline period, so a CPU brought back online finds the cache already + * invalidated before it is schedulable. This closes the window where a + * task scheduled before riscv_srmcfg_online() runs could match a stale + * cache and skip the CSR write while the hardware CSR was reset across + * hart stop/start. + */ +static int riscv_srmcfg_offline(unsigned int cpu) +{ + per_cpu(cpu_srmcfg, cpu) =3D U32_MAX; + return 0; +} + +/* + * CPU PM notifier: invalidate the cached srmcfg on resume from a deep + * idle / suspend. Ssqosid v1.0 leaves CSR_SRMCFG state across low-power + * transitions implementation-defined, and the boot CPU never goes + * through the cpuhp online callback during system suspend, so without + * this hook __switch_to_srmcfg() would skip the CSR write when the + * outgoing task happens to share its srmcfg with the pre-suspend cache. + */ +static int riscv_srmcfg_pm_notify(struct notifier_block *nb, + unsigned long action, void *unused) +{ + switch (action) { + case CPU_PM_EXIT: + case CPU_PM_ENTER_FAILED: + __this_cpu_write(cpu_srmcfg, U32_MAX); + break; + } + return NOTIFY_OK; +} + +static struct notifier_block riscv_srmcfg_pm_nb =3D { + .notifier_call =3D riscv_srmcfg_pm_notify, +}; + +static int __init riscv_srmcfg_init(void) +{ + int err; + + if (!riscv_has_extension_unlikely(RISCV_ISA_EXT_SSQOSID)) + return 0; + + /* + * cpuhp_setup_state() invokes the startup callback locally on every + * already-online CPU, so no separate seed loop is needed here. + */ + err =3D cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "riscv/srmcfg:online", + riscv_srmcfg_online, riscv_srmcfg_offline); + if (err < 0) { + pr_warn("srmcfg cpuhp registration failed (%d), cpus brought online afte= r boot will not invalidate the CSR_SRMCFG cache\n", + err); + return err; + } + + cpu_pm_register_notifier(&riscv_srmcfg_pm_nb); + return 0; +} +arch_initcall(riscv_srmcfg_init); --=20 2.43.0 From nobody Mon Jun 8 05:29:11 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 310033F6C5A; Mon, 1 Jun 2026 20:36:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780346187; cv=none; b=Ir3qjxlGt5NQS8tCTEeHk8R3TWuQxMOIl8VPfl9sPzsiYJKdlIOO6vYXqnaMpssP0cuHwwrAqXt5pjNL48qCj26Tg/LRG9ykz3j0o21KjfA6KFJmJuXsq5DiYWFpuFa8v0vupY2Rm9EH7i8EMoKM6blsSjepOFDoaPdq4QqSYNk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780346187; c=relaxed/simple; bh=AWRHihJSBi+LIrOoIsOzoxnsBG0+4NVU5YSaIMOxEs8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bZaFi0klSDxeCCpZeU6vEtJL5FWFk9ADQroQ9yNwv2XV06HjBZ3529mxaV8WsDG1+4b+LxBRuiFXYwGwdkS4NSyCUKjASGzxnVJG7fPqTYUDU0xy1Gx3qGq09CfjuH1hvJ5jFUqsbTtK+P/rPma21qgW3I+cAy0zyd3sH3Grfqc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=N4EDcD/4; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="N4EDcD/4" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 509C81F008A2; Mon, 1 Jun 2026 20:36:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1780346186; bh=04z5b3ENFFStDILh5daSgPFr7SyjhKEetoj74bl6s2o=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=N4EDcD/494hQTJe4Z54xn8R31VLX1tGYAWu/wOvCv15H+JZ5j/quW+JmTtNI/6zPT UIG1axiDwdSzkpAizwBy+WWc+N9OhUdlEKFYmcH+hRh9DaqV7e0cn+j+upHN9dR770 VwkMT4qcD3K2H54TgD2cUCKCl8MajpxOdTilhoxUc0BNMxY0j8QXYLB/l0d5oC/W/f 7skH61tjyhUdzxhXDe2acfesYtrQsEypUb8v+0MOFwXE7wBLWNKx5PGNJ1bZOn3TXp LpoCOLqr0/l9vfg7qAJWaD/ZHRw7NY9nCd+XOWQmRAkJytXPVmS4YBJWOPiyiQLpO7 vsXa6CsrAHg8g== From: Drew Fustini Date: Mon, 01 Jun 2026 13:35:58 -0700 Subject: [PATCH RFC v6 04/18] fs/resctrl: Add resctrl_is_membw() helper Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-4-baf00f50028a@kernel.org> References: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-0-baf00f50028a@kernel.org> In-Reply-To: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-0-baf00f50028a@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , Conor Dooley , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, Gong Shuai , Gong Shuai , liu.qingtao2@zte.com.cn, Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Rob Herring , Conor Dooley , Krzysztof Kozlowski , "Rafael J. Wysocki" , Len Brown , Robert Moore , Sunil V L , Drew Fustini , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Sebastian Andrzej Siewior , Clark Williams , Steven Rostedt , Jonathan Corbet Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org, linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, devicetree@vger.kernel.org, Paul Walmsley , Conor Dooley , linux-rt-devel@lists.linux.dev, linux-doc@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3572; i=fustini@kernel.org; h=from:subject:message-id; bh=AWRHihJSBi+LIrOoIsOzoxnsBG0+4NVU5YSaIMOxEs8=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTJvnX68MtA7IdD/cyz767HerOHxIhE6sfutTnEfs3oR mJ01wHrjlIWBjEuBlkxRZZNH/IuLPEK/bpg/ottMHNYmUCGMHBxCsBEgrYwMvzUmfE49KbQ7Iyv 0b+u21xhnyWd9+TlY6mvFv5hHfNnzqxmZDjwJKXw+hqerg8nAy8cKz+07eu6bTGbZyh7i1x3PMk 3qYkBAA== X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Four sites in fs/resctrl distinguish bandwidth resources (MBA, SMBA) from cache resources by explicit rid match: fs/resctrl/ctrlmondata.c parse_line() fs/resctrl/rdtgroup.c rdtgroup_mode_test_exclusive() fs/resctrl/rdtgroup.c rdtgroup_size_show() fs/resctrl/rdtgroup.c rdtgroup_init_alloc() Replace the open-coded MBA/SMBA tests with a single resctrl_is_membw() helper keyed on schema_fmt (RESCTRL_SCHEMA_RANGE). No functional change: every existing RESCTRL_SCHEMA_RANGE resource is MBA or SMBA today. This isolates fs/resctrl from the addition of further bandwidth resource types so the four call sites do not have to be updated for each new rid. Assisted-by: Claude:claude-opus-4-7 Signed-off-by: Drew Fustini --- fs/resctrl/ctrlmondata.c | 3 +-- fs/resctrl/internal.h | 2 ++ fs/resctrl/rdtgroup.c | 14 +++++++++----- 3 files changed, 12 insertions(+), 7 deletions(-) diff --git a/fs/resctrl/ctrlmondata.c b/fs/resctrl/ctrlmondata.c index 9a7dfc48cb2e..d9f052700941 100644 --- a/fs/resctrl/ctrlmondata.c +++ b/fs/resctrl/ctrlmondata.c @@ -245,8 +245,7 @@ static int parse_line(char *line, struct resctrl_schema= *s, if (WARN_ON_ONCE(!parse_ctrlval)) return -EINVAL; =20 - if (rdtgrp->mode =3D=3D RDT_MODE_PSEUDO_LOCKSETUP && - (r->rid =3D=3D RDT_RESOURCE_MBA || r->rid =3D=3D RDT_RESOURCE_SMBA)) { + if (rdtgrp->mode =3D=3D RDT_MODE_PSEUDO_LOCKSETUP && resctrl_is_membw(r))= { rdt_last_cmd_puts("Cannot pseudo-lock MBA resource\n"); return -EINVAL; } diff --git a/fs/resctrl/internal.h b/fs/resctrl/internal.h index 1a9b29119f88..76187987b2ee 100644 --- a/fs/resctrl/internal.h +++ b/fs/resctrl/internal.h @@ -397,6 +397,8 @@ void mbm_handle_overflow(struct work_struct *work); =20 bool is_mba_sc(struct rdt_resource *r); =20 +bool resctrl_is_membw(struct rdt_resource *r); + void cqm_setup_limbo_handler(struct rdt_l3_mon_domain *dom, unsigned long = delay_ms, int exclude_cpu); =20 diff --git a/fs/resctrl/rdtgroup.c b/fs/resctrl/rdtgroup.c index 5dfdaa6f9d8f..0f331bf5ce82 100644 --- a/fs/resctrl/rdtgroup.c +++ b/fs/resctrl/rdtgroup.c @@ -1412,7 +1412,7 @@ static bool rdtgroup_mode_test_exclusive(struct rdtgr= oup *rdtgrp) =20 list_for_each_entry(s, &resctrl_schema_all, list) { r =3D s->res; - if (r->rid =3D=3D RDT_RESOURCE_MBA || r->rid =3D=3D RDT_RESOURCE_SMBA) + if (resctrl_is_membw(r)) continue; has_cache =3D true; list_for_each_entry(d, &r->ctrl_domains, hdr.list) { @@ -1555,6 +1555,12 @@ bool is_mba_sc(struct rdt_resource *r) return r->membw.mba_sc; } =20 +/* RANGE schema is bandwidth (MBA/SMBA). BITMAP is cache. */ +bool resctrl_is_membw(struct rdt_resource *r) +{ + return r->schema_fmt =3D=3D RESCTRL_SCHEMA_RANGE; +} + /* * rdtgroup_size_show - Display size in bytes of allocated regions * @@ -1616,8 +1622,7 @@ static int rdtgroup_size_show(struct kernfs_open_file= *of, ctrl =3D resctrl_arch_get_config(r, d, closid, type); - if (r->rid =3D=3D RDT_RESOURCE_MBA || - r->rid =3D=3D RDT_RESOURCE_SMBA) + if (resctrl_is_membw(r)) size =3D ctrl; else size =3D rdtgroup_cbm_to_size(r, d, ctrl); @@ -3648,8 +3653,7 @@ static int rdtgroup_init_alloc(struct rdtgroup *rdtgr= p) =20 list_for_each_entry(s, &resctrl_schema_all, list) { r =3D s->res; - if (r->rid =3D=3D RDT_RESOURCE_MBA || - r->rid =3D=3D RDT_RESOURCE_SMBA) { + if (resctrl_is_membw(r)) { rdtgroup_init_mba(r, rdtgrp->closid); if (is_mba_sc(r)) continue; --=20 2.43.0 From nobody Mon Jun 8 05:29:11 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1922D3F789D; Mon, 1 Jun 2026 20:36:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780346188; cv=none; b=r4/aYGknZnfc1daOI0DDsMxu6PH4/EQC59wpZqwWvMMQrg57UgF9NQ6KrOJrkIUFadX/L3AAHpfELJ7Mv3S2EZ2ch2V2aW3NSckX4A6m3jLIaXe+D7ZBjQGzaTWX67vXXkGwNje8ArQw3ByyEeiDDB0gVF+rBSJH7VwMTMOcPfs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780346188; c=relaxed/simple; bh=5R/JdWFi++9znbUpG3cGFvBtrlKO+JDslGJA+1+iOLc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=B0aq+w2/emwhNNjUIpglO9xAS9vYOmX2F3aoIUPr52qIZW06Xhk9E7C802K386suMFYHzq/QR9i5h7oGHt7WOjVIdtluGvV4olvXhNBdLDXKhJ7mPTg/bISEk89Vcjqxum0tWWE9ipv47wuXGikEkLaERcSdQs6qq1xSdtESacc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=m3SVo7zy; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="m3SVo7zy" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1BE1E1F008A3; Mon, 1 Jun 2026 20:36:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1780346186; bh=f9ZOFiPohiYSKhbWWzIEk2xjvwSzBQ/tKoIQXjkNAxw=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=m3SVo7zyq96FMlVQkDyefmhThVvqpBHzYEwM01u/+hQQorVfnMQIJU0Tis2CFRaeC QIVEkTgLTtss2oupuozZKDtPnAMcNq8zePDPeGvD8ksvBalYIIXHA10w+u8gTam8G4 JAQ3cvFJKmwg0L3vUCUxJwazAZYYaXUroPdGSeN9P84OQFcaQIDtpJ6RQHUMr4Q2xK uuTEpUWKO7XP3JG/qrJRQlrfQ66drKDKVxQdKFPJseEqBOc5n+RUT97HqctFfL+Bx2 9HBetHTXHlWWgMHgMA72OT0io/s2GByTMz52JjsBQvnzkFuV2sgjrBDmZr7lSa8+El 3pEdX3lSUKNDg== From: Drew Fustini Date: Mon, 01 Jun 2026 13:35:59 -0700 Subject: [PATCH RFC v6 05/18] fs/resctrl: Add RDT_RESOURCE_MB_MIN and RDT_RESOURCE_MB_WGHT Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-5-baf00f50028a@kernel.org> References: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-0-baf00f50028a@kernel.org> In-Reply-To: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-0-baf00f50028a@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , Conor Dooley , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, Gong Shuai , Gong Shuai , liu.qingtao2@zte.com.cn, Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Rob Herring , Conor Dooley , Krzysztof Kozlowski , "Rafael J. Wysocki" , Len Brown , Robert Moore , Sunil V L , Drew Fustini , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Sebastian Andrzej Siewior , Clark Williams , Steven Rostedt , Jonathan Corbet Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org, linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, devicetree@vger.kernel.org, Paul Walmsley , Conor Dooley , linux-rt-devel@lists.linux.dev, linux-doc@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1643; i=fustini@kernel.org; h=from:subject:message-id; bh=5R/JdWFi++9znbUpG3cGFvBtrlKO+JDslGJA+1+iOLc=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTJvnWam3v/ImetyEH5AsFixXvqZ3++YV6yT2LF/ymfJ p1/2bJ0XUcpC4MYF4OsmCLLpg95F5Z4hX5dMP/FNpg5rEwgQxi4OAVgIr+vMPxmPb4qM2Z59kSF hqP2RsHVp6/P+Ma6wme/VmPcv6pyvg/vGBm2PPA/O+31e86133K6dTclNsue+bbfw+n95idC65k 0ZMRYAA== X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Introduce bandwidth controls which are semantically different from the throttle-based MB resource: - RDT_RESOURCE_MB_MIN: minimum reserved bandwidth - RDT_RESOURCE_MB_WGHT: weighted share of unreserved bandwidth Assisted-by: Claude:claude-opus-4-7 Signed-off-by: Drew Fustini --- fs/resctrl/rdtgroup.c | 4 +++- include/linux/resctrl.h | 2 ++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/fs/resctrl/rdtgroup.c b/fs/resctrl/rdtgroup.c index 0f331bf5ce82..02733b11e115 100644 --- a/fs/resctrl/rdtgroup.c +++ b/fs/resctrl/rdtgroup.c @@ -1555,7 +1555,7 @@ bool is_mba_sc(struct rdt_resource *r) return r->membw.mba_sc; } =20 -/* RANGE schema is bandwidth (MBA/SMBA). BITMAP is cache. */ +/* RANGE schema is bandwidth (MBA/SMBA/MB_MIN/MB_WGHT). BITMAP is cache. */ bool resctrl_is_membw(struct rdt_resource *r) { return r->schema_fmt =3D=3D RESCTRL_SCHEMA_RANGE; @@ -2402,6 +2402,8 @@ static unsigned long fflags_from_resource(struct rdt_= resource *r) return RFTYPE_RES_CACHE; case RDT_RESOURCE_MBA: case RDT_RESOURCE_SMBA: + case RDT_RESOURCE_MB_MIN: + case RDT_RESOURCE_MB_WGHT: return RFTYPE_RES_MB; case RDT_RESOURCE_PERF_PKG: return RFTYPE_RES_PERF_PKG; diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h index 006e57fd7ca5..9529ed0d1fdf 100644 --- a/include/linux/resctrl.h +++ b/include/linux/resctrl.h @@ -53,6 +53,8 @@ enum resctrl_res_level { RDT_RESOURCE_L2, RDT_RESOURCE_MBA, RDT_RESOURCE_SMBA, + RDT_RESOURCE_MB_MIN, + RDT_RESOURCE_MB_WGHT, RDT_RESOURCE_PERF_PKG, =20 /* Must be the last */ --=20 2.43.0 From nobody Mon Jun 8 05:29:11 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B5FCF37F002; Mon, 1 Jun 2026 20:36:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780346188; cv=none; b=OtKK+WjVW5jDjpxJqmH3SUfKGxDdQwSJv6/LWQDBmDEQpw4XhKHNVNWV9hRSQ+3JM+B4gFr/i+CXm0Ho79Y6MtAGHSmeCTGUQslvWJ8t6o9MmiBV3HPmuvbUfRuq1kDaEwdIyyWZYCUp7t9dPqcbQMR1z7kfy/RxuhDQ2wezTt4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780346188; c=relaxed/simple; bh=umPX9KI/Gk5be4QxBnpv0rW9Oy0Ozoiycv8rX5MjK6Y=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZmUjYuE+WQghouFw7IEpb2MWztnvzdmJ9GKu87RZKD3sCm4d7OJ+nymDpJhOMhvMzFjaF1m2d/y4cqv1YYrtYcR4j56hROiVDGi2OV//dShByn+TUhuwtCzET6xOI5HdEbvgwWnLHktFDybHyTOhyU4+lXJ1dJXrtCVyFuuLAGE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=IdM9AEMz; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="IdM9AEMz" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E7EC71F008A5; Mon, 1 Jun 2026 20:36:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1780346187; bh=bMpLloap6PiHKBmR2q+lkFW8XbOS+M/R8KIqzK/QRe8=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=IdM9AEMz5E5ImmoO2m5gDZ4DU4xHBhRRkMCrCSOBVEt/9OjvRP5aD4zTy/1kvNBgu AuN7tEt7FHvcksMKxRaNnZz2dYOBaTR95HeuXfQU6yK6ZT3MuMUhHGDIxH/tHWAgah KZd8AXXoZNQs4z+pkHiFeLZvv30gwHA2MfCrv3OLD0nIFyq9atgPgLeRF0MF628hbm nq71w5h6686v9pNmOTYTcCWeP7nl9RyELQ2WW5FRHhocacyObGfL/dsiivDGd+Zj5U da17UP5VWp/0j4GTunnmV8RszPCSQ+foGaot3B5F3KhISze6JmSUXb6Cw7Bsuuo/+4 TM3/m4u/4uVvQ== From: Drew Fustini Date: Mon, 01 Jun 2026 13:36:00 -0700 Subject: [PATCH RFC v6 06/18] fs/resctrl: Let bandwidth resources default to min_bw at reset Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-6-baf00f50028a@kernel.org> References: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-0-baf00f50028a@kernel.org> In-Reply-To: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-0-baf00f50028a@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , Conor Dooley , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, Gong Shuai , Gong Shuai , liu.qingtao2@zte.com.cn, Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Rob Herring , Conor Dooley , Krzysztof Kozlowski , "Rafael J. Wysocki" , Len Brown , Robert Moore , Sunil V L , Drew Fustini , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Sebastian Andrzej Siewior , Clark Williams , Steven Rostedt , Jonathan Corbet Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org, linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, devicetree@vger.kernel.org, Paul Walmsley , Conor Dooley , linux-rt-devel@lists.linux.dev, linux-doc@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2176; i=fustini@kernel.org; h=from:subject:message-id; bh=umPX9KI/Gk5be4QxBnpv0rW9Oy0Ozoiycv8rX5MjK6Y=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTJvnWSlbogxnP79dej/1bd9WIR37Ty8sHVDk2yYYd9N i++trzVsKOUhUGMi0FWTJFl04e8C0u8Qr8umP9iG8wcViaQIQxcnAIwkYOaDP9Us8xffjt+JEPb Izaz3MwuYWe1ApeG9f+LGWEl73y37/FkZFh1JvmK7ZXIpEXLNsdP3xXJ8czT1smrcse0ZI+Pctd ehbMDAA== X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Bandwidth resources reset to max_bw on group creation today, which is the right default for MBA and SMBA. However, it is the wrong default for hardware whose registers form a sum-constrained reservation: defaulting every new group to max_bw would immediately violate the sum on the first mkdir. When default_to_min is set, resctrl_get_default_ctrl() returns min_bw for the resource. The existing MBA and SMBA behavior is not changed. Assisted-by: Claude:claude-opus-4-7 Signed-off-by: Drew Fustini --- include/linux/resctrl.h | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h index 9529ed0d1fdf..bcbc166412ef 100644 --- a/include/linux/resctrl.h +++ b/include/linux/resctrl.h @@ -247,7 +247,13 @@ enum membw_throttle_mode { /** * struct resctrl_membw - Memory bandwidth allocation related data * @min_bw: Minimum memory bandwidth percentage user can request - * @max_bw: Maximum memory bandwidth value, used as the reset value + * @max_bw: Maximum memory bandwidth value a group can be + * configured with + * @default_to_min: When true, the default control value for new + * groups and reset is @min_bw instead of @max_bw. + * Drivers whose hardware enforces a sum constraint + * across groups (e.g. CBQRI MB_MIN) set this so + * mkdir does not overflow the sum. * @bw_gran: Granularity at which the memory bandwidth is allocated * @delay_linear: True if memory B/W delay is in linear scale * @arch_needs_linear: True if we can't configure non-linear resources @@ -259,6 +265,7 @@ enum membw_throttle_mode { struct resctrl_membw { u32 min_bw; u32 max_bw; + bool default_to_min; u32 bw_gran; u32 delay_linear; bool arch_needs_linear; @@ -405,7 +412,7 @@ static inline u32 resctrl_get_default_ctrl(struct rdt_r= esource *r) case RESCTRL_SCHEMA_BITMAP: return BIT_MASK(r->cache.cbm_len) - 1; case RESCTRL_SCHEMA_RANGE: - return r->membw.max_bw; + return r->membw.default_to_min ? r->membw.min_bw : r->membw.max_bw; } =20 return WARN_ON_ONCE(1); --=20 2.43.0 From nobody Mon Jun 8 05:29:11 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B5F333F9A11; Mon, 1 Jun 2026 20:36:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780346191; cv=none; b=E1n31/jWiB7GZo5f0hJiT1wkL8HTonU3H4iHp58ozJi5tP1mzTv+MSJin5NRDWFNhKwgdVd9m0f3sRjBCl158R5d8aB6CT2qV1HRnv4Z6mJ7Bw1AA6jQJy7stvrZ8g1UJmmXbrxj9+MiCm82IWzW1mCp7+AiQbyJC7ojSxjoRIg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780346191; c=relaxed/simple; bh=HUZuC2TN/EOt/MC9dmQMZrVkejIxug9FAD16P95rXgs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=eyISbp43OR/3b+tUWHQ1LAJNRVxOsB6qaxONc9G+WkhRBrl5MRu45VKO7i4sx5cOe7D3OzNNnII7rtMwgpDtHQwIt+BlTQX13Br564yWFY46U8gv3iTgUQQn0XXBlKwjd/BAjEtVvL/VLHCdJ347LvbdU6sLj+rbYe6ZO+taSQI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=K50UXJ02; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="K50UXJ02" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BB0A61F008A4; Mon, 1 Jun 2026 20:36:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1780346188; bh=8lL76ILh6Lvy3heVERwEx9T8OxPihh6iqbLX7I3sOwg=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=K50UXJ02HYroamEbB9O78L9IywJoHeDeEDtvn4TRBPlCSyH/P5plJi2N2lQYPUi43 S9Tw2cVO03W9GZKLlWI41lmV7tYjmZpYpaPt8omg3ZkcmRSGnbIbz0VCDdajuinNhC 5m1Zj8suiseaT6ZIPq3tfEkPaYxfybB1UfdeFebVdciLPt+uBy1t6mTVjV2GJdvvmN oCCUW3pp3FjHEwvYVCK9+6wFsKM1eDLLlMwNQD6h2DJbrrufDgTh66zT3D0dgP8WOF 5rjiaua7K/94sn3PTrHbRk1iUAS+krwe5tJjEIrT/nujcwBY9zLVcdm0wXG/Wk/sqq RlAMA3/F0yLpw== From: Drew Fustini Date: Mon, 01 Jun 2026 13:36:01 -0700 Subject: [PATCH RFC v6 07/18] riscv_cbqri: Add capacity controller probe and allocation device ops Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-7-baf00f50028a@kernel.org> References: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-0-baf00f50028a@kernel.org> In-Reply-To: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-0-baf00f50028a@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , Conor Dooley , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, Gong Shuai , Gong Shuai , liu.qingtao2@zte.com.cn, Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Rob Herring , Conor Dooley , Krzysztof Kozlowski , "Rafael J. Wysocki" , Len Brown , Robert Moore , Sunil V L , Drew Fustini , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Sebastian Andrzej Siewior , Clark Williams , Steven Rostedt , Jonathan Corbet Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org, linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, devicetree@vger.kernel.org, Paul Walmsley , Conor Dooley , linux-rt-devel@lists.linux.dev, linux-doc@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=28066; i=fustini@kernel.org; h=from:subject:message-id; bh=HUZuC2TN/EOt/MC9dmQMZrVkejIxug9FAD16P95rXgs=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTJvnU2i3eQaZ3oWXq648SpY/1xVhFn1xx3aVq74XCE8 MyY/xGuHaUsDGJcDLJiiiybPuRdWOIV+nXB/BfbYOawMoEMYeDiFICJ9J9lZGh04d1e3apadMRX yq0+cqrOPqv0Lfu8N8nL7vr2t2Sv3g+Gf0orxfZJlCm5z5U4kjR5b1e950GO73kn9Y2/WR7/+ft 6JwMA X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Add support for the RISC-V CBQRI capacity controller (CC). The firmware discovery layer is responsible for passing the cbqri_controller_info descriptor to riscv_cbqri_register_controller(). The driver resolves the cpumask so callers do not need the cacheinfo topology. AT-capable controllers with CDP off mirror the cbm into both DATA and CODE halves. Assisted-by: Claude:claude-opus-4-7 Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- MAINTAINERS | 3 + drivers/resctrl/Kconfig | 28 ++ drivers/resctrl/Makefile | 5 + drivers/resctrl/cbqri_devices.c | 567 +++++++++++++++++++++++++++++++++++= ++++ drivers/resctrl/cbqri_internal.h | 141 ++++++++++ include/linux/riscv_cbqri.h | 60 +++++ 6 files changed, 804 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e694fb2a22d2..24bdc04fea7a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -23024,6 +23024,9 @@ L: linux-riscv@lists.infradead.org S: Supported F: arch/riscv/include/asm/qos.h F: arch/riscv/kernel/qos.c +F: drivers/resctrl/cbqri_devices.c +F: drivers/resctrl/cbqri_internal.h +F: include/linux/riscv_cbqri.h =20 RISC-V RPMI AND MPXY DRIVERS M: Rahul Pathak diff --git a/drivers/resctrl/Kconfig b/drivers/resctrl/Kconfig index 672abea3b03c..d578bc7aed85 100644 --- a/drivers/resctrl/Kconfig +++ b/drivers/resctrl/Kconfig @@ -29,3 +29,31 @@ config ARM64_MPAM_RESCTRL_FS default y if ARM64_MPAM_DRIVER && RESCTRL_FS select RESCTRL_RMID_DEPENDS_ON_CLOSID select RESCTRL_ASSIGN_FIXED + +menuconfig RISCV_CBQRI_DRIVER + bool "RISC-V CBQRI driver" + depends on RISCV && RISCV_ISA_SSQOSID + help + Capacity and Bandwidth QoS Register Interface (CBQRI) driver + for RISC-V cache and memory-controller QoS resources. CBQRI + exposes capacity allocation, bandwidth reservation, weighted + bandwidth share, and per-MCID monitoring counters through the + resctrl filesystem at /sys/fs/resctrl when RESCTRL_FS is also + enabled. + + RISCV_ISA_SSQOSID provides the srmcfg CSR that tags each hart's + memory traffic with the RCID and MCID consumed by CBQRI + controllers. + +if RISCV_CBQRI_DRIVER + +config RISCV_CBQRI_DRIVER_DEBUG + bool "Enable debug messages from the CBQRI driver" + help + Say yes here to enable debug messages from the CBQRI driver. + + This adds pr_debug() output covering controller probe and + per-controller registration steps. Useful when bringing up a + new platform; otherwise leave disabled to avoid log noise. + +endif diff --git a/drivers/resctrl/Makefile b/drivers/resctrl/Makefile index 4f6d0e81f9b8..28085036d895 100644 --- a/drivers/resctrl/Makefile +++ b/drivers/resctrl/Makefile @@ -3,3 +3,8 @@ mpam-y +=3D mpam_devices.o mpam-$(CONFIG_ARM64_MPAM_RESCTRL_FS) +=3D mpam_resctrl.o =20 ccflags-$(CONFIG_ARM64_MPAM_DRIVER_DEBUG) +=3D -DDEBUG + +obj-$(CONFIG_RISCV_CBQRI_DRIVER) +=3D cbqri.o +cbqri-y +=3D cbqri_devices.o + +ccflags-$(CONFIG_RISCV_CBQRI_DRIVER_DEBUG) +=3D -DDEBUG diff --git a/drivers/resctrl/cbqri_devices.c b/drivers/resctrl/cbqri_device= s.c new file mode 100644 index 000000000000..65453e614a43 --- /dev/null +++ b/drivers/resctrl/cbqri_devices.c @@ -0,0 +1,567 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#define pr_fmt(fmt) "%s:%s: " fmt, KBUILD_MODNAME, __func__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "cbqri_internal.h" + +LIST_HEAD(cbqri_controllers); + +/* Set capacity block mask (cc_block_mask) */ +static void cbqri_set_cbm(struct cbqri_controller *ctrl, u64 cbm) +{ + iowrite64(cbm, ctrl->base + CBQRI_CC_BLOCK_MASK_OFF); +} + +static int cbqri_wait_busy_flag(struct cbqri_controller *ctrl, int reg_off= set, + u64 *regp) +{ + u64 reg; + int ret; + + /* + * Sleeping poll: caller holds ctrl->lock as a sleeping mutex, so + * 10us/1ms is safe under PREEMPT_RT. + */ + ret =3D readq_poll_timeout(ctrl->base + reg_offset, reg, + !FIELD_GET(CBQRI_CONTROL_REGISTERS_BUSY_MASK, reg), + 10, 1000); + if (ret) { + ctrl->faulted =3D true; + return ret; + } + ctrl->faulted =3D false; + if (regp) + *regp =3D reg; + return 0; +} + +/* + * Perform capacity allocation control operation on capacity controller. + * Caller must hold ctrl->lock. + */ +static int cbqri_cc_alloc_op(struct cbqri_controller *ctrl, int operation, + int rcid, enum cbqri_at at) +{ + int reg_offset =3D CBQRI_CC_ALLOC_CTL_OFF; + int status; + u64 reg; + + lockdep_assert_held(&ctrl->lock); + + if (cbqri_wait_busy_flag(ctrl, reg_offset, ®) < 0) { + pr_err_ratelimited("BUSY timeout before starting operation\n"); + return -EIO; + } + FIELD_MODIFY(CBQRI_CONTROL_REGISTERS_OP_MASK, ®, operation); + FIELD_MODIFY(CBQRI_CONTROL_REGISTERS_RCID_MASK, ®, rcid); + + /* + * CBQRI Table 1: AT 0=3DData, 1=3DCode. Program AT on controllers + * that report supports_alloc_at_code. On controllers that don't, + * AT is reserved-zero and the op acts on both halves. + */ + reg &=3D ~CBQRI_CONTROL_REGISTERS_AT_MASK; + if (ctrl->cc.supports_alloc_at_code) + reg |=3D FIELD_PREP(CBQRI_CONTROL_REGISTERS_AT_MASK, at); + + iowrite64(reg, ctrl->base + reg_offset); + + if (cbqri_wait_busy_flag(ctrl, reg_offset, ®) < 0) { + pr_err_ratelimited("BUSY timeout during operation\n"); + return -EIO; + } + + status =3D FIELD_GET(CBQRI_CONTROL_REGISTERS_STATUS_MASK, reg); + if (status !=3D CBQRI_CC_ALLOC_CTL_STATUS_SUCCESS) { + pr_err_ratelimited("operation %d failed: status=3D%d\n", operation, stat= us); + return -EIO; + } + + return 0; +} + +/* + * Apply a capacity block mask and verify via CONFIG_LIMIT + READ_LIMIT. + * + * AT-capable controllers with CDP off need a second CONFIG_LIMIT on the + * other AT half (the spec encodes AT only as 0=3DData / 1=3DCode, there is + * no "both halves" value). CDP-on issues separate per-type writes from + * resctrl, so a single CONFIG_LIMIT per call is correct. + */ +int cbqri_apply_cache_config(struct cbqri_controller *ctrl, u32 closid, + const struct cbqri_cc_config *cfg) +{ + bool need_at_mirror; + u64 saved_cbm =3D 0; + int err =3D 0; + u64 reg; + + mutex_lock(&ctrl->lock); + + need_at_mirror =3D ctrl->cc.supports_alloc_at_code && !cfg->cdp_enabled; + + /* + * Capture the cfg->at half CBM before any write so a partial + * AT-mirror failure can revert and keep the two halves consistent. + * Pre-clear cc_block_mask so a silent firmware no-op (status + * SUCCESS but staging not updated) shows as a zero readback + * rather than carrying stale data from a prior op. Mirrors the + * defensive pattern in cbqri_read_cache_config(). + */ + if (need_at_mirror) { + cbqri_set_cbm(ctrl, 0); + err =3D cbqri_cc_alloc_op(ctrl, CBQRI_CC_ALLOC_CTL_OP_READ_LIMIT, + closid, cfg->at); + if (err < 0) + goto out; + saved_cbm =3D ioread64(ctrl->base + CBQRI_CC_BLOCK_MASK_OFF); + } + + /* Set capacity block mask (cc_block_mask) */ + cbqri_set_cbm(ctrl, cfg->cbm); + + /* Capacity config limit operation for the AT half implied by cfg->at */ + err =3D cbqri_cc_alloc_op(ctrl, CBQRI_CC_ALLOC_CTL_OP_CONFIG_LIMIT, + closid, cfg->at); + if (err < 0) + goto out; + + /* + * CDP-off mirror: on AT-capable controllers, also program the + * other AT half with the same mask so the two halves stay in sync. + */ + if (need_at_mirror) { + enum cbqri_at other =3D (cfg->at =3D=3D CBQRI_AT_CODE) ? + CBQRI_AT_DATA : CBQRI_AT_CODE; + + cbqri_set_cbm(ctrl, cfg->cbm); + err =3D cbqri_cc_alloc_op(ctrl, + CBQRI_CC_ALLOC_CTL_OP_CONFIG_LIMIT, + closid, other); + if (err < 0) { + int rerr; + + /* + * Best-effort revert of the cfg->at half so the two + * halves stay in sync. A schemata read sees only one + * half, so silent divergence would otherwise report + * the new value as if the write had succeeded. + */ + cbqri_set_cbm(ctrl, saved_cbm); + rerr =3D cbqri_cc_alloc_op(ctrl, + CBQRI_CC_ALLOC_CTL_OP_CONFIG_LIMIT, + closid, cfg->at); + if (rerr < 0) + pr_err_ratelimited("AT-mirror revert failed (err=3D%d), AT halves dive= rged\n", + rerr); + goto out; + } + } + + /* Clear cc_block_mask before read limit to verify op works */ + cbqri_set_cbm(ctrl, 0); + + /* Perform a capacity read limit operation to verify blockmask */ + err =3D cbqri_cc_alloc_op(ctrl, CBQRI_CC_ALLOC_CTL_OP_READ_LIMIT, + closid, cfg->at); + if (err < 0) + goto out; + + /* + * Read capacity blockmask and narrow to u32 to match resctrl's CBM + * width. cbqri_probe_cc() rejects ncblks > 32 so the upper bits are + * reserved zero. + */ + reg =3D ioread64(ctrl->base + CBQRI_CC_BLOCK_MASK_OFF); + if (lower_32_bits(reg) !=3D cfg->cbm) { + pr_err_ratelimited("CBM verify mismatch (reg=3D%llx !=3D cbm=3D%llx)\n", + reg, cfg->cbm); + err =3D -EIO; + } + +out: + mutex_unlock(&ctrl->lock); + return err; +} + +/* + * Read the configured CBM for closid on the at half via READ_LIMIT. + * Pre-clears cc_block_mask before the op so a silent firmware no-op + * (status SUCCESS but staging not updated) is detectable in cbm_out. + */ +int cbqri_read_cache_config(struct cbqri_controller *ctrl, u32 closid, + enum cbqri_at at, u32 *cbm_out) +{ + int err; + + mutex_lock(&ctrl->lock); + cbqri_set_cbm(ctrl, 0); + err =3D cbqri_cc_alloc_op(ctrl, CBQRI_CC_ALLOC_CTL_OP_READ_LIMIT, closid,= at); + if (err =3D=3D 0) { + /* + * cc_block_mask is a 64-bit MMIO register. resctrl exposes the + * CBM as a u32. cbqri_probe_cc() rejects ncblks > 32 so the + * upper 32 bits are reserved zero by the spec. Narrow + * explicitly via lower_32_bits() so the assumption is visible + * at the read site. + */ + *cbm_out =3D lower_32_bits(ioread64(ctrl->base + CBQRI_CC_BLOCK_MASK_OFF= )); + } + mutex_unlock(&ctrl->lock); + return err; +} + +static int cbqri_probe_feature(struct cbqri_controller *ctrl, int reg_offs= et, + int operation, int *status, bool *access_type_supported) +{ + const u64 active_mask =3D CBQRI_CONTROL_REGISTERS_OP_MASK | + CBQRI_CONTROL_REGISTERS_AT_MASK | + CBQRI_CONTROL_REGISTERS_RCID_MASK | + CBQRI_MON_CTL_EVT_ID_MASK; + u64 reg, saved_reg; + int at; + + /* + * Default the output to false so the status=3D=3D0 (feature not + * implemented) path returns a deterministic value to the caller + * rather than leaving an uninitialized bool. + */ + *access_type_supported =3D false; + + /* Keep the initial register value to preserve the WPRI fields */ + reg =3D ioread64(ctrl->base + reg_offset); + saved_reg =3D reg; + + /* Drain any in-flight firmware op before issuing our own write. */ + if (cbqri_wait_busy_flag(ctrl, reg_offset, &saved_reg) < 0) { + pr_err("BUSY timeout before probe operation\n"); + return -EIO; + } + + /* + * Execute the requested operation with all active fields + * (OP/AT/RCID/EVT_ID) zeroed except OP itself. The same builder + * works for ALLOC_CTL and MON_CTL because every bit not in + * active_mask is WPRI and gets carried over from saved_reg. The + * AT and EVT_ID positions are reserved for the other register + * type, where writing zero is harmless. + */ + reg =3D (saved_reg & ~active_mask) | + FIELD_PREP(CBQRI_CONTROL_REGISTERS_OP_MASK, operation); + iowrite64(reg, ctrl->base + reg_offset); + if (cbqri_wait_busy_flag(ctrl, reg_offset, ®) < 0) { + pr_err_ratelimited("BUSY timeout during operation\n"); + return -EIO; + } + + /* Get the operation status */ + *status =3D FIELD_GET(CBQRI_CONTROL_REGISTERS_STATUS_MASK, reg); + + /* + * Check for the AT support if the register is implemented + * (if not, the status value will remain 0) + */ + if (*status !=3D 0) { + /* + * Re-issue operation with AT=3DCODE so the controller + * latches AT=3DCODE on supported hardware (or resets it to 0 + * on hardware that doesn't). OP must be a defined CBQRI op + * here. OP=3D0 is a no-op and would silently disable CDP. + */ + reg =3D (saved_reg & ~active_mask) | + FIELD_PREP(CBQRI_CONTROL_REGISTERS_OP_MASK, operation) | + FIELD_PREP(CBQRI_CONTROL_REGISTERS_AT_MASK, + CBQRI_CONTROL_REGISTERS_AT_CODE); + iowrite64(reg, ctrl->base + reg_offset); + if (cbqri_wait_busy_flag(ctrl, reg_offset, ®) < 0) { + pr_err("BUSY timeout setting AT field\n"); + return -EIO; + } + + /* + * If the AT field value has been reset to zero, + * then the AT support is not present + */ + at =3D FIELD_GET(CBQRI_CONTROL_REGISTERS_AT_MASK, reg); + if (at =3D=3D CBQRI_CONTROL_REGISTERS_AT_CODE) + *access_type_supported =3D true; + } + + /* + * Restore the original register value. + * Clear OP to avoid re-triggering the probe op. + */ + saved_reg &=3D ~CBQRI_CONTROL_REGISTERS_OP_MASK; + iowrite64(saved_reg, ctrl->base + reg_offset); + if (cbqri_wait_busy_flag(ctrl, reg_offset, NULL) < 0) { + pr_err("BUSY timeout restoring register value\n"); + return -EIO; + } + + return 0; +} + +static int cbqri_probe_cc(struct cbqri_controller *ctrl) +{ + int err, status; + u64 reg; + + reg =3D ioread64(ctrl->base + CBQRI_CC_CAPABILITIES_OFF); + if (reg =3D=3D 0) + return -ENODEV; + + ctrl->ver_minor =3D FIELD_GET(CBQRI_CC_CAPABILITIES_VER_MINOR_MASK, reg); + ctrl->ver_major =3D FIELD_GET(CBQRI_CC_CAPABILITIES_VER_MAJOR_MASK, reg); + ctrl->cc.ncblks =3D FIELD_GET(CBQRI_CC_CAPABILITIES_NCBLKS_MASK, reg); + + pr_debug("version=3D%d.%d ncblks=3D%d cache_level=3D%d\n", + ctrl->ver_major, ctrl->ver_minor, + ctrl->cc.ncblks, ctrl->cache.cache_level); + + /* + * NCBLKS =3D=3D 0 would divide-by-zero in the schemata math while + * ctrl->lock is held. + */ + if (!ctrl->cc.ncblks) { + pr_warn("CC at %pa has 0 capacity blocks, skipping\n", + &ctrl->addr); + return -ENODEV; + } + + if (ctrl->cc.ncblks > 32) { + pr_warn("CC at %pa has ncblks=3D%u > 32 (resctrl CBM is u32), skipping\n= ", + &ctrl->addr, ctrl->cc.ncblks); + return -ENODEV; + } + + /* + * Resolve cache_size via cacheinfo. cpus_read_lock satisfies + * lockdep_assert_cpus_held() inside get_cpu_cacheinfo_level(). If + * every cpu_mask member is offline, cache_size stays 0 and the + * controller cannot back occupancy monitoring. + */ + cpus_read_lock(); + if (!ctrl->cache.cache_size) { + int cpu =3D cpumask_first_and(&ctrl->cache.cpu_mask, cpu_online_mask); + + if (cpu < nr_cpu_ids) { + struct cacheinfo *ci; + + ci =3D get_cpu_cacheinfo_level(cpu, ctrl->cache.cache_level); + if (ci) + ctrl->cache.cache_size =3D ci->size; + } + } + cpus_read_unlock(); + + /* Probe allocation features */ + err =3D cbqri_probe_feature(ctrl, CBQRI_CC_ALLOC_CTL_OFF, + CBQRI_CC_ALLOC_CTL_OP_READ_LIMIT, + &status, &ctrl->cc.supports_alloc_at_code); + if (err) + return err; + + if (status =3D=3D CBQRI_CC_ALLOC_CTL_STATUS_SUCCESS) + ctrl->alloc_capable =3D true; + + return 0; +} + +static int cbqri_probe_controller(struct cbqri_controller *ctrl) +{ + int err; + + pr_debug("controller info: type=3D%d addr=3D%pa size=3D%pa max-rcid=3D%u = max-mcid=3D%u\n", + ctrl->type, &ctrl->addr, &ctrl->size, + ctrl->rcid_count, ctrl->mcid_count); + + if (!ctrl->addr) { + pr_warn("controller has invalid addr=3D0x0, skipping\n"); + return -EINVAL; + } + + if (ctrl->size < CBQRI_CTRL_MIN_REG_SPAN) { + pr_warn("controller at %pa: size %pa < minimum 0x%x, skipping\n", + &ctrl->addr, &ctrl->size, CBQRI_CTRL_MIN_REG_SPAN); + return -EINVAL; + } + + if (!request_mem_region(ctrl->addr, ctrl->size, "cbqri_controller")) { + pr_err("request_mem_region failed for %pa\n", &ctrl->addr); + return -EBUSY; + } + + ctrl->base =3D ioremap(ctrl->addr, ctrl->size); + if (!ctrl->base) { + pr_err("ioremap failed for %pa\n", &ctrl->addr); + err =3D -ENOMEM; + goto err_release; + } + + switch (ctrl->type) { + case CBQRI_CONTROLLER_TYPE_CAPACITY: + err =3D cbqri_probe_cc(ctrl); + break; + default: + pr_err("unknown controller type %d\n", ctrl->type); + err =3D -ENODEV; + break; + } + + if (err) + goto err_iounmap; + + return 0; + +err_iounmap: + iounmap(ctrl->base); + ctrl->base =3D NULL; +err_release: + release_mem_region(ctrl->addr, ctrl->size); + return err; +} + +void cbqri_controller_destroy(struct cbqri_controller *ctrl) +{ + /* + * cbqri_probe_controller() clears ctrl->base on its error paths and + * releases the mem region itself, so reach into both only when + * destroy is rolling back a successful probe. + */ + if (ctrl->base) { + iounmap(ctrl->base); + release_mem_region(ctrl->addr, ctrl->size); + } + kfree(ctrl); +} + +/* + * Roll back the most recent n successful riscv_cbqri_register_controller() + * calls. Discovery layers use this to undo partial registrations when a + * subsequent table entry turns out to be malformed and the whole parse mu= st + * abort. + * + * Caller serialization: this is intended for boot-time discovery (ACPI + * acpi_arch_init, future DT) which run single-threaded before late_initca= ll. + * No lock is taken. + */ +void riscv_cbqri_unregister_last(unsigned int n) +{ + while (n--) { + struct cbqri_controller *ctrl; + + if (list_empty(&cbqri_controllers)) + return; + ctrl =3D list_last_entry(&cbqri_controllers, + struct cbqri_controller, list); + list_del(&ctrl->list); + cbqri_controller_destroy(ctrl); + } +} + +/* + * Allocate, populate, and add to cbqri_controllers a fresh controller + * descriptor based on info supplied by a discovery layer (ACPI RQSC, + * future DT). Resolves the cpumask via PPTT (capacity) so callers do + * not need to know about cacheinfo topology. + */ +int riscv_cbqri_register_controller(const struct cbqri_controller_info *in= fo) +{ + struct cbqri_controller *ctrl; + int err; + + if (!info->addr) { + pr_warn("skipping controller with invalid addr=3D0x0\n"); + return -EINVAL; + } + + ctrl =3D kzalloc(sizeof(*ctrl), GFP_KERNEL); + if (!ctrl) + return -ENOMEM; + + mutex_init(&ctrl->lock); + + ctrl->addr =3D info->addr; + ctrl->size =3D info->size; + ctrl->type =3D info->type; + ctrl->rcid_count =3D info->rcid_count; + ctrl->mcid_count =3D info->mcid_count; + + /* + * SRMCFG encodes RCID in 12 bits. ACPI's acpi_parse_rqsc() already + * caps info->rcid_count at CBQRI_MAX_RCID (1024) so this is unreachable + * today, but a future DT discovery path or a malformed firmware table + * routed through a different validator could bypass that ceiling. + * Catch the violation here rather than silently truncating in every + * FIELD_PREP(SRMCFG_RCID_MASK, closid) on the schedule-in fast path. + */ + if (WARN_ON_ONCE(ctrl->rcid_count > FIELD_MAX(SRMCFG_RCID_MASK) + 1)) { + cbqri_controller_destroy(ctrl); + return -EINVAL; + } + + switch (info->type) { + case CBQRI_CONTROLLER_TYPE_CAPACITY: { + int level; + + ctrl->cache.cache_id =3D info->cache_id; + + level =3D find_acpi_cache_level_from_id(info->cache_id); + if (level < 0) { + pr_warn("Failed to resolve cache level for cache id 0x%x (%d), skipping= \n", + info->cache_id, level); + cbqri_controller_destroy(ctrl); + return level; + } + ctrl->cache.cache_level =3D level; + + /* + * cache_size stays at 0 here. cacheinfo is not populated + * yet at acpi_arch_init time. Filled lazily during probe + * via get_cpu_cacheinfo_level(). + */ + + err =3D acpi_pptt_get_cpumask_from_cache_id(info->cache_id, + &ctrl->cache.cpu_mask); + if (err) { + pr_warn("Failed to get cpumask for cache id 0x%x (%d), skipping\n", + info->cache_id, err); + cbqri_controller_destroy(ctrl); + return err; + } + break; + } + default: + pr_warn("controller at %pa: unknown type %u, skipping\n", + &ctrl->addr, info->type); + cbqri_controller_destroy(ctrl); + return -EINVAL; + } + + err =3D cbqri_probe_controller(ctrl); + if (err) { + cbqri_controller_destroy(ctrl); + return err; + } + + list_add_tail(&ctrl->list, &cbqri_controllers); + return 0; +} diff --git a/drivers/resctrl/cbqri_internal.h b/drivers/resctrl/cbqri_inter= nal.h new file mode 100644 index 000000000000..518955963403 --- /dev/null +++ b/drivers/resctrl/cbqri_internal.h @@ -0,0 +1,141 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _DRIVERS_RESCTRL_CBQRI_INTERNAL_H +#define _DRIVERS_RESCTRL_CBQRI_INTERNAL_H + +#include +#include +#include +#include +#include +#include + +/* Capacity Controller (CC) MMIO register offsets. */ +#define CBQRI_CC_CAPABILITIES_OFF 0 +#define CBQRI_CC_ALLOC_CTL_OFF 24 +#define CBQRI_CC_BLOCK_MASK_OFF 32 + +/* + * Smallest MMIO span the driver actually accesses: highest defined + * register offset (0x20) plus the 8-byte register width. Used by + * cbqri_probe_controller() to reject undersized firmware-supplied + * mappings before request_mem_region/ioremap, so a u64 access at + * BLOCK_MASK does not walk past the end of the mapping. + */ +#define CBQRI_CTRL_MIN_REG_SPAN 0x28u + +#define CBQRI_CC_CAPABILITIES_VER_MINOR_MASK GENMASK_ULL(3, 0) +#define CBQRI_CC_CAPABILITIES_VER_MAJOR_MASK GENMASK_ULL(7, 4) +#define CBQRI_CC_CAPABILITIES_NCBLKS_MASK GENMASK_ULL(23, 8) + +/* + * CC and BC control and mon registers are 64-bit. Keep every field mask + * GENMASK_ULL so FIELD_MODIFY() or ~mask on a u64 register never + * zero-extends a 32-bit mask and clobbers STATUS/BUSY/WPRI in bits 63:32 + * if RV32 support is added in the future. + */ +#define CBQRI_CONTROL_REGISTERS_OP_MASK GENMASK_ULL(4, 0) +#define CBQRI_CONTROL_REGISTERS_AT_MASK GENMASK_ULL(7, 5) +#define CBQRI_CONTROL_REGISTERS_AT_DATA 0 +#define CBQRI_CONTROL_REGISTERS_AT_CODE 1 +#define CBQRI_CONTROL_REGISTERS_RCID_MASK GENMASK_ULL(19, 8) +#define CBQRI_CONTROL_REGISTERS_STATUS_MASK GENMASK_ULL(38, 32) +#define CBQRI_CONTROL_REGISTERS_BUSY_MASK GENMASK_ULL(39, 39) + +#define CBQRI_CC_ALLOC_CTL_OP_CONFIG_LIMIT 1 +#define CBQRI_CC_ALLOC_CTL_OP_READ_LIMIT 2 +#define CBQRI_CC_ALLOC_CTL_STATUS_SUCCESS 1 + +/* mon_ctl field masks (CC and BC share an identical OP/MCID/EVT_ID/STATUS= layout) */ +#define CBQRI_MON_CTL_OP_MASK GENMASK_ULL(4, 0) +#define CBQRI_MON_CTL_MCID_MASK GENMASK_ULL(19, 8) +#define CBQRI_MON_CTL_EVT_ID_MASK GENMASK_ULL(27, 20) +#define CBQRI_MON_CTL_STATUS_MASK GENMASK_ULL(38, 32) +#define CBQRI_MON_CTL_STATUS_SUCCESS 1 + +/* Capacity Controller hardware capabilities */ +struct riscv_cbqri_capacity_caps { + u16 ncblks; + bool supports_alloc_at_code; +}; + +/** + * enum cbqri_at - capacity controller access type for CDP + * @CBQRI_AT_DATA: data access (CBQRI Table 1, AT=3D0) + * @CBQRI_AT_CODE: code access (CBQRI Table 1, AT=3D1) + * + * Selects between data and code halves on controllers that advertise + * supports_alloc_at_code. The resctrl glue maps from CDP_DATA / CDP_CODE + * to this enum at the boundary so cbqri_devices.c stays free of fs/resctrl + * types. + */ +enum cbqri_at { + CBQRI_AT_DATA =3D CBQRI_CONTROL_REGISTERS_AT_DATA, + CBQRI_AT_CODE =3D CBQRI_CONTROL_REGISTERS_AT_CODE, +}; + +/** + * struct cbqri_cc_config - desired capacity allocation state for one rcid + * @cbm: capacity block mask + * @at: AT half (data or code) the @cbm applies to + * @cdp_enabled: when false and the controller supports AT, mirror @cbm + * into the other AT half so both stay in sync + */ +struct cbqri_cc_config { + u64 cbm; + enum cbqri_at at; + bool cdp_enabled; +}; + +struct cbqri_controller { + void __iomem *base; + /* + * Serializes the write-then-poll-busy MMIO sequences on this + * controller. Each CBQRI op may busy-wait up to 1 ms on slow + * firmware, so use a sleeping mutex (paired with the sleeping + * readq_poll_timeout() in cbqri_wait_busy_flag()) to keep + * preemption enabled, which is required for PREEMPT_RT. + * All resctrl-arch entry points run in process context. + */ + struct mutex lock; + /* + * Set by cbqri_wait_busy_flag() on BUSY timeout, cleared on the + * next successful wait. Informational only, used for diagnostics. + */ + bool faulted; + + int ver_major; + int ver_minor; + + struct riscv_cbqri_capacity_caps cc; + + bool alloc_capable; + bool mon_capable; + + phys_addr_t addr; + phys_addr_t size; + enum cbqri_controller_type type; + u32 rcid_count; + u32 mcid_count; + + struct list_head list; + + struct cache_controller { + u32 cache_level; + u32 cache_size; /* in bytes */ + struct cpumask cpu_mask; + /* Unique Cache ID from the PPTT table's Cache Type Structure */ + u32 cache_id; + } cache; +}; + +extern struct list_head cbqri_controllers; + +void cbqri_controller_destroy(struct cbqri_controller *ctrl); + +int cbqri_apply_cache_config(struct cbqri_controller *ctrl, u32 closid, + const struct cbqri_cc_config *cfg); + +int cbqri_read_cache_config(struct cbqri_controller *ctrl, u32 closid, + enum cbqri_at at, u32 *cbm_out); + +#endif /* _DRIVERS_RESCTRL_CBQRI_INTERNAL_H */ diff --git a/include/linux/riscv_cbqri.h b/include/linux/riscv_cbqri.h new file mode 100644 index 000000000000..5863f0a65f6c --- /dev/null +++ b/include/linux/riscv_cbqri.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Public registration API for the RISC-V Capacity and Bandwidth QoS + * Register Interface (CBQRI) driver. Discovery layers (ACPI RQSC, future + * device tree) call riscv_cbqri_register_controller() to hand a controller + * descriptor to the driver, which owns all subsequent state. + */ +#ifndef _LINUX_RISCV_CBQRI_H +#define _LINUX_RISCV_CBQRI_H + +#include + +enum cbqri_controller_type { + CBQRI_CONTROLLER_TYPE_CAPACITY, + CBQRI_CONTROLLER_TYPE_BANDWIDTH, +}; + +/* Sanity caps on per-controller RCID/MCID counts from firmware */ +#define CBQRI_MAX_RCID 1024 +#define CBQRI_MAX_MCID 1024 + +/** + * struct cbqri_controller_info - registration descriptor + * @addr: MMIO base address of the controller's register interface + * @size: size of the MMIO region + * @type: capacity or bandwidth controller + * @rcid_count: number of supported RCIDs (per RQSC table) + * @mcid_count: number of supported MCIDs (per RQSC table) + * @cache_id: PPTT cache id. Only meaningful for CAPACITY controllers + * @prox_dom: SRAT proximity domain. Only meaningful for BANDWIDTH + * controllers + * + * Discovery layers populate one of @cache_id / @prox_dom according to + * @type. The CBQRI driver resolves the matching cpumask internally so + * callers do not need to know about cacheinfo/NUMA topology. + */ +struct cbqri_controller_info { + phys_addr_t addr; + phys_addr_t size; + enum cbqri_controller_type type; + u32 rcid_count; + u32 mcid_count; + u32 cache_id; + u32 prox_dom; +}; + +#if IS_ENABLED(CONFIG_RISCV_CBQRI_DRIVER) +int riscv_cbqri_register_controller(const struct cbqri_controller_info *in= fo); +void riscv_cbqri_unregister_last(unsigned int n); +#else +static inline int +riscv_cbqri_register_controller(const struct cbqri_controller_info *info) +{ + return -ENODEV; +} + +static inline void riscv_cbqri_unregister_last(unsigned int n) { } +#endif + +#endif /* _LINUX_RISCV_CBQRI_H */ --=20 2.43.0 From nobody Mon Jun 8 05:29:11 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D8D63FADE0; Mon, 1 Jun 2026 20:36:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780346192; cv=none; b=SwJFAsXuO5NEwC72oj/idxpqrvh1D5YCBhGXfVo2iOHsmrj4rITDdbYwZWXzqt+t5U61zpSqC9iHuJb+od1AF0V4nI/B1zveQjNtJy+sBfCft9RLIldrNFzPS2ddV7AW1CQXldN/LXi7Z9aiHAkW6wgxWUnm2Ts4TbCQQ/9bGj4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780346192; c=relaxed/simple; bh=6pGb65kUi8C4rTI8Gu7TEGZMX7qYRHql0RDoSYaXCBA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=SeDzNmNWOINq2y8vMRE4MLg7KanjcMGtfqjipYEfpoJNzhLXGme575qotgf8Wcj/D6fC49QJ0HM/U07w8/9qfaEUDF8CaYj11cWPBnRSOyF8YX5QV3QCeGYUpD9zZLsqC22FrrgMe3yrV+UJppf8P7hFp3BycJ9zyEBSH1X8JOc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Q/CK1X2r; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Q/CK1X2r" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BA3FF1F008A2; Mon, 1 Jun 2026 20:36:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1780346189; bh=rEo6Boe1f4U6J69bplZaagznip1xGYS4k0AxEWh7bSg=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=Q/CK1X2rY8jP1eiaXjNZK1292cWzD9n1bNUfa14c8m7WoBei4nTvGz0HznSYPOYpg bVm4FdFr8x3rL1Kl4btvZU5HXxXwYhQr8dY+DUT/bzxFm47W12O26x+u0+F5Zx9IST B6mAVOpNCxnHemCuCoHlCCD/GvGXDxO8qIa02Cd0lU08/WFh+PH/QksYsaMW4QrBT+ vgW5exUG9rmwxiKZS04Mu4NZu/sK0n0kjUJOmWXibmp2fRLan1avSfQ79xdeKBkWAA WHCPtLxCVj/6kq7DRWbNWQhUcJc5ijBAuT64wQ7OcXGQjVjsDV9Ub9KJg4M1KOWh5N av/5/GoNon42A== From: Drew Fustini Date: Mon, 01 Jun 2026 13:36:02 -0700 Subject: [PATCH RFC v6 08/18] riscv_cbqri: Add capacity controller monitoring device ops Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-8-baf00f50028a@kernel.org> References: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-0-baf00f50028a@kernel.org> In-Reply-To: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-0-baf00f50028a@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , Conor Dooley , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, Gong Shuai , Gong Shuai , liu.qingtao2@zte.com.cn, Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Rob Herring , Conor Dooley , Krzysztof Kozlowski , "Rafael J. Wysocki" , Len Brown , Robert Moore , Sunil V L , Drew Fustini , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Sebastian Andrzej Siewior , Clark Williams , Steven Rostedt , Jonathan Corbet Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org, linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, devicetree@vger.kernel.org, Paul Walmsley , Conor Dooley , linux-rt-devel@lists.linux.dev, linux-doc@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=9666; i=fustini@kernel.org; h=from:subject:message-id; bh=6pGb65kUi8C4rTI8Gu7TEGZMX7qYRHql0RDoSYaXCBA=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTJvnXe9+mSpW1VwpGCF8t+67FJ3FCacuoAR1wW2+Ug5 UCP+UsPd5SyMIhxMciKKbJs+pB3YYlX6NcF819sg5nDygQyhIGLUwAmcv8YI8M27bXHp1vMUJ90 4N1LwQB1DefyGRNqS+fPe6bH0XdPupuD4Z9GUusE8b0Gn9Y2WS7eLP3FpLTpVPn7TVcOFMYVFxY sWMICAA== X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Add capacity monitoring operations. cbqri_init_mon_counters() pre-arms every MCID with the Occupancy event so a subsequent READ_COUNTER just snapshots the live counter without re-configuring the slot. cbqri_probe_cc() leaves ctrl->mon_capable false when cacheinfo has not given a non-zero cache_size, since the byte conversion would be meaningless. cbqri_mon_op() takes a reg_offset and serves both capacity and bandwidth mon_ctl registers as they share an identical layout. Assisted-by: Claude:claude-opus-4-7 Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- drivers/resctrl/cbqri_devices.c | 124 ++++++++++++++++++++++++++++++++++-= ---- drivers/resctrl/cbqri_internal.h | 14 +++++ 2 files changed, 124 insertions(+), 14 deletions(-) diff --git a/drivers/resctrl/cbqri_devices.c b/drivers/resctrl/cbqri_device= s.c index 65453e614a43..c44bc50c31ba 100644 --- a/drivers/resctrl/cbqri_devices.c +++ b/drivers/resctrl/cbqri_devices.c @@ -98,6 +98,43 @@ static int cbqri_cc_alloc_op(struct cbqri_controller *ct= rl, int operation, return 0; } =20 +/* + * Issue a monitoring op on a CC or BC controller's mon_ctl register at + * reg_offset (CBQRI_CC_MON_CTL_OFF or CBQRI_BC_MON_CTL_OFF). The CC and + * BC mon_ctl registers share an identical OP/MCID/EVT_ID/STATUS layout, so + * one helper covers both. Caller must hold ctrl->lock. + */ +int cbqri_mon_op(struct cbqri_controller *ctrl, int reg_offset, + int operation, int mcid, int evt_id, u64 *out_reg) +{ + u64 reg; + + lockdep_assert_held(&ctrl->lock); + + if (cbqri_wait_busy_flag(ctrl, reg_offset, ®) < 0) { + pr_err_ratelimited("BUSY timeout before starting operation\n"); + return -EIO; + } + FIELD_MODIFY(CBQRI_MON_CTL_OP_MASK, ®, operation); + FIELD_MODIFY(CBQRI_MON_CTL_MCID_MASK, ®, mcid); + FIELD_MODIFY(CBQRI_MON_CTL_EVT_ID_MASK, ®, evt_id); + iowrite64(reg, ctrl->base + reg_offset); + + if (cbqri_wait_busy_flag(ctrl, reg_offset, ®) < 0) { + pr_err_ratelimited("BUSY timeout\n"); + return -EIO; + } + + if (FIELD_GET(CBQRI_MON_CTL_STATUS_MASK, reg) !=3D + CBQRI_MON_CTL_STATUS_SUCCESS) + return -EIO; + + if (out_reg) + *out_reg =3D reg; + + return 0; +} + /* * Apply a capacity block mask and verify via CONFIG_LIMIT + READ_LIMIT. * @@ -230,7 +267,8 @@ int cbqri_read_cache_config(struct cbqri_controller *ct= rl, u32 closid, } =20 static int cbqri_probe_feature(struct cbqri_controller *ctrl, int reg_offs= et, - int operation, int *status, bool *access_type_supported) + int operation, int evt_id, int *status, + bool *access_type_supported) { const u64 active_mask =3D CBQRI_CONTROL_REGISTERS_OP_MASK | CBQRI_CONTROL_REGISTERS_AT_MASK | @@ -242,9 +280,11 @@ static int cbqri_probe_feature(struct cbqri_controller= *ctrl, int reg_offset, /* * Default the output to false so the status=3D=3D0 (feature not * implemented) path returns a deterministic value to the caller - * rather than leaving an uninitialized bool. + * rather than leaving an uninitialized bool. mon_ctl probes pass + * NULL: the register has no AT field, so the AT probe is skipped. */ - *access_type_supported =3D false; + if (access_type_supported) + *access_type_supported =3D false; =20 /* Keep the initial register value to preserve the WPRI fields */ reg =3D ioread64(ctrl->base + reg_offset); @@ -257,15 +297,14 @@ static int cbqri_probe_feature(struct cbqri_controlle= r *ctrl, int reg_offset, } =20 /* - * Execute the requested operation with all active fields - * (OP/AT/RCID/EVT_ID) zeroed except OP itself. The same builder - * works for ALLOC_CTL and MON_CTL because every bit not in - * active_mask is WPRI and gets carried over from saved_reg. The - * AT and EVT_ID positions are reserved for the other register - * type, where writing zero is harmless. + * Execute the requested operation with the active fields + * (OP/AT/RCID/EVT_ID) cleared, then set OP and, for mon_ctl, the + * probe-safe evt_id. WPRI bits outside active_mask carry over from + * saved_reg. alloc_ctl callers pass evt_id 0. */ reg =3D (saved_reg & ~active_mask) | - FIELD_PREP(CBQRI_CONTROL_REGISTERS_OP_MASK, operation); + FIELD_PREP(CBQRI_CONTROL_REGISTERS_OP_MASK, operation) | + FIELD_PREP(CBQRI_MON_CTL_EVT_ID_MASK, evt_id); iowrite64(reg, ctrl->base + reg_offset); if (cbqri_wait_busy_flag(ctrl, reg_offset, ®) < 0) { pr_err_ratelimited("BUSY timeout during operation\n"); @@ -276,10 +315,11 @@ static int cbqri_probe_feature(struct cbqri_controlle= r *ctrl, int reg_offset, *status =3D FIELD_GET(CBQRI_CONTROL_REGISTERS_STATUS_MASK, reg); =20 /* - * Check for the AT support if the register is implemented - * (if not, the status value will remain 0) + * Probe AT support only on alloc_ctl registers (mon_ctl has no AT + * field, so access_type_supported is NULL there). Skipped when the + * register is unimplemented (status stays 0). */ - if (*status !=3D 0) { + if (access_type_supported && *status !=3D 0) { /* * Re-issue operation with AT=3DCODE so the controller * latches AT=3DCODE on supported hardware (or resets it to 0 @@ -372,9 +412,31 @@ static int cbqri_probe_cc(struct cbqri_controller *ctr= l) } cpus_read_unlock(); =20 + /* Probe monitoring features */ + err =3D cbqri_probe_feature(ctrl, CBQRI_CC_MON_CTL_OFF, + CBQRI_CC_MON_CTL_OP_CONFIG_EVENT, + CBQRI_CC_EVT_ID_NONE, &status, NULL); + if (err) + return err; + + if (status =3D=3D CBQRI_MON_CTL_STATUS_SUCCESS) { + /* + * Occupancy is reported to userspace in bytes, computed as + * cache_size * counter / ncblks by the resctrl glue. If + * cacheinfo has no cache_size, leave mon_capable false so + * the file is not exposed at all rather than silently + * returning 0. + */ + if (!ctrl->cache.cache_size) + pr_debug("CC @%pa: cache_size unknown, occupancy monitoring disabled\n", + &ctrl->addr); + else + ctrl->mon_capable =3D true; + } + /* Probe allocation features */ err =3D cbqri_probe_feature(ctrl, CBQRI_CC_ALLOC_CTL_OFF, - CBQRI_CC_ALLOC_CTL_OP_READ_LIMIT, + CBQRI_CC_ALLOC_CTL_OP_READ_LIMIT, 0, &status, &ctrl->cc.supports_alloc_at_code); if (err) return err; @@ -439,6 +501,28 @@ static int cbqri_probe_controller(struct cbqri_control= ler *ctrl) return err; } =20 +/* + * Pre-arm every MCID with the Occupancy event so a subsequent READ_COUNTER + * just snapshots the live counter rather than re-configuring the slot. + * Called once per CC during resctrl-side cpuhp online for the L3 monitori= ng + * domain. + */ +int cbqri_init_mon_counters(struct cbqri_controller *ctrl) +{ + int i, err; + + for (i =3D 0; i < ctrl->mcid_count; i++) { + mutex_lock(&ctrl->lock); + err =3D cbqri_mon_op(ctrl, CBQRI_CC_MON_CTL_OFF, + CBQRI_CC_MON_CTL_OP_CONFIG_EVENT, + i, CBQRI_CC_EVT_ID_OCCUPANCY, NULL); + mutex_unlock(&ctrl->lock); + if (err) + return err; + } + return 0; +} + void cbqri_controller_destroy(struct cbqri_controller *ctrl) { /* @@ -518,6 +602,18 @@ int riscv_cbqri_register_controller(const struct cbqri= _controller_info *info) return -EINVAL; } =20 + /* + * mon_ctl encodes MCID in 12 bits. acpi_parse_rqsc() caps + * info->mcid_count at CBQRI_MAX_MCID (1024), but a future discovery + * path could bypass that. Reject an out-of-range count so + * cbqri_init_mon_counters() iterates a trusted bound and no MCID + * aliases another slot through FIELD_MODIFY(MON_CTL_MCID_MASK). + */ + if (WARN_ON_ONCE(ctrl->mcid_count > FIELD_MAX(CBQRI_MON_CTL_MCID_MASK) + = 1)) { + cbqri_controller_destroy(ctrl); + return -EINVAL; + } + switch (info->type) { case CBQRI_CONTROLLER_TYPE_CAPACITY: { int level; diff --git a/drivers/resctrl/cbqri_internal.h b/drivers/resctrl/cbqri_inter= nal.h index 518955963403..1d2007a0c15b 100644 --- a/drivers/resctrl/cbqri_internal.h +++ b/drivers/resctrl/cbqri_internal.h @@ -11,6 +11,8 @@ =20 /* Capacity Controller (CC) MMIO register offsets. */ #define CBQRI_CC_CAPABILITIES_OFF 0 +#define CBQRI_CC_MON_CTL_OFF 8 +#define CBQRI_CC_MON_CTL_VAL_OFF 16 #define CBQRI_CC_ALLOC_CTL_OFF 24 #define CBQRI_CC_BLOCK_MASK_OFF 32 =20 @@ -45,6 +47,9 @@ #define CBQRI_CC_ALLOC_CTL_OP_READ_LIMIT 2 #define CBQRI_CC_ALLOC_CTL_STATUS_SUCCESS 1 =20 +#define CBQRI_CC_MON_CTL_OP_CONFIG_EVENT 1 +#define CBQRI_CC_MON_CTL_OP_READ_COUNTER 2 + /* mon_ctl field masks (CC and BC share an identical OP/MCID/EVT_ID/STATUS= layout) */ #define CBQRI_MON_CTL_OP_MASK GENMASK_ULL(4, 0) #define CBQRI_MON_CTL_MCID_MASK GENMASK_ULL(19, 8) @@ -52,6 +57,10 @@ #define CBQRI_MON_CTL_STATUS_MASK GENMASK_ULL(38, 32) #define CBQRI_MON_CTL_STATUS_SUCCESS 1 =20 +/* Capacity usage monitoring event IDs (CBQRI spec Table 4) */ +#define CBQRI_CC_EVT_ID_NONE 0 +#define CBQRI_CC_EVT_ID_OCCUPANCY 1 + /* Capacity Controller hardware capabilities */ struct riscv_cbqri_capacity_caps { u16 ncblks; @@ -138,4 +147,9 @@ int cbqri_apply_cache_config(struct cbqri_controller *c= trl, u32 closid, int cbqri_read_cache_config(struct cbqri_controller *ctrl, u32 closid, enum cbqri_at at, u32 *cbm_out); =20 +int cbqri_mon_op(struct cbqri_controller *ctrl, int reg_offset, + int operation, int mcid, int evt_id, u64 *out_reg); + +int cbqri_init_mon_counters(struct cbqri_controller *ctrl); + #endif /* _DRIVERS_RESCTRL_CBQRI_INTERNAL_H */ --=20 2.43.0 From nobody Mon Jun 8 05:29:11 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B1F193FB075; Mon, 1 Jun 2026 20:36:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780346193; cv=none; b=PUaGD/q0xogszllchHBJ3dBQAbN6tkcL7pT9fBOSxljXiCfeh2Fdl+2M8beRVuW0XHcRssgENTR1C1w1od84QdIEfdHPSW/7+99NFUGNiaNt1V4+ce9k/epwG97AkbQ4mT6NrxFRXy3HxCs0R3RBvjXNR8YaRUQ3sev9u8n6r44= ARC-Message-Signature: i=1; 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b=meFJ8vucPB6eMdwhgjnC6fjExavgEKbR+0cjAYJxrM4DjMoGb/QuDpC61MnHt92n9 VSbiNrLCPoQWtabGEjukkp5otULvrill9oc6pzz+OpsIfuSXdhHpYB5/hw0MBV97Uu +hvTmsOYd/91jqxMbUyGy0ylnXdYvnrurDcA0hswWjiXz0nQud8fPXSDtJIpDMKIvE hjJClJzNncNypCl0GjNjmoc7fQZJkgqA/UN7DN/cxnW7EZHhfIIqAGBlc4gP1a4LJU 5fVikyUA+ctpDCR7njpT3+J4a1gnuOQIA8MY5qPByiSvxOLS/fCw39668qNrwelqd9 QygfM3S4SV0aA== From: Drew Fustini Date: Mon, 01 Jun 2026 13:36:03 -0700 Subject: [PATCH RFC v6 09/18] riscv_cbqri: Add bandwidth controller probe and allocation device ops Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-9-baf00f50028a@kernel.org> References: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-0-baf00f50028a@kernel.org> In-Reply-To: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-0-baf00f50028a@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , Conor Dooley , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, Gong Shuai , Gong Shuai , liu.qingtao2@zte.com.cn, Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Rob Herring , Conor Dooley , Krzysztof Kozlowski , "Rafael J. Wysocki" , Len Brown , Robert Moore , Sunil V L , Drew Fustini , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Sebastian Andrzej Siewior , Clark Williams , Steven Rostedt , Jonathan Corbet Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org, linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, devicetree@vger.kernel.org, Paul Walmsley , Conor Dooley , linux-rt-devel@lists.linux.dev, linux-doc@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=21221; i=fustini@kernel.org; h=from:subject:message-id; bh=DUk9uYSQmnJgbKJP/PtpcwFxWEQxB9eEmQQq2rcrZnY=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTJvnW2crs7t2NGs+ShiQ8K7VcwOHY6PKj+1fg88/rN+ Ia5OcGCHaUsDGJcDLJiiiybPuRdWOIV+nXB/BfbYOawMoEMYeDiFICJvGBh+J+09uBy090Lovae T46Syr7fftN42ZLSBYes2878NHhj0W7A8M9Y6sdctmgVXrNpJjzRC1kL9LJvfWVelBMo5pV9xMA zlgcA X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Add support for CBQRI bandwidth controller (BC) discovery and the two BC allocation control knobs. Rbwb is the number of reserved bandwidth blocks per RCID. Mweight is the weighted share per RCID of the remaining unreserved bandwidth. Both fields share the bc_bw_alloc register, so cbqri_apply_bc_field() seeds both halves from per-RCID software caches (rbwb_cache and mweight_cache) on every CONFIG_LIMIT. The caches are the authoritative source of the unmodified field, which sidesteps a silent READ_LIMIT no-op leaking stale data from a prior RCID. After CONFIG_LIMIT, the caller writes a sentinel to the target field and reads back via READ_LIMIT to verify hardware accepted the write. The cache is updated only after verify succeeds. mweight_cache is seeded to FIELD_MAX at probe so the first MB_MIN domain init does not commit Mweight=3D0 (per CBQRI 4.5, a hard cap that disallows opportunistic bandwidth) before the subsequent MB_WGHT init catches up. cbqri_apply_rbwb() enforces the spec-mandated sum(Rbwb) <=3D MRBWB invariant from rbwb_cache rather than per-RCID READ_LIMIT round-trips, which would cost up to 1 ms each while holding the mutex. cbqri_apply_mweight_config() rejects values that would truncate against the 8-bit MWEIGHT_MASK at entry. Assisted-by: Claude:claude-opus-4-7 Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- drivers/resctrl/cbqri_devices.c | 416 +++++++++++++++++++++++++++++++++++= ++++ drivers/resctrl/cbqri_internal.h | 57 +++++- 2 files changed, 472 insertions(+), 1 deletion(-) diff --git a/drivers/resctrl/cbqri_devices.c b/drivers/resctrl/cbqri_device= s.c index c44bc50c31ba..6093706b1ec4 100644 --- a/drivers/resctrl/cbqri_devices.c +++ b/drivers/resctrl/cbqri_devices.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -30,6 +31,63 @@ static void cbqri_set_cbm(struct cbqri_controller *ctrl,= u64 cbm) iowrite64(cbm, ctrl->base + CBQRI_CC_BLOCK_MASK_OFF); } =20 +/* Set the Rbwb (reserved bandwidth blocks) field in bc_bw_alloc */ +static void cbqri_set_rbwb(struct cbqri_controller *ctrl, u64 rbwb) +{ + u64 reg; + + reg =3D ioread64(ctrl->base + CBQRI_BC_BW_ALLOC_OFF); + FIELD_MODIFY(CBQRI_CONTROL_REGISTERS_RBWB_MASK, ®, rbwb); + iowrite64(reg, ctrl->base + CBQRI_BC_BW_ALLOC_OFF); +} + +/* Get the Rbwb (reserved bandwidth blocks) field in bc_bw_alloc */ +static u64 cbqri_get_rbwb(struct cbqri_controller *ctrl) +{ + u64 reg; + + reg =3D ioread64(ctrl->base + CBQRI_BC_BW_ALLOC_OFF); + return FIELD_GET(CBQRI_CONTROL_REGISTERS_RBWB_MASK, reg); +} + +/* Set the Mweight (opportunistic weight) field in bc_bw_alloc */ +static void cbqri_set_mweight(struct cbqri_controller *ctrl, u64 mweight) +{ + u64 reg; + + reg =3D ioread64(ctrl->base + CBQRI_BC_BW_ALLOC_OFF); + FIELD_MODIFY(CBQRI_CONTROL_REGISTERS_MWEIGHT_MASK, ®, mweight); + iowrite64(reg, ctrl->base + CBQRI_BC_BW_ALLOC_OFF); +} + +/* Get the Mweight (opportunistic weight) field in bc_bw_alloc */ +static u64 cbqri_get_mweight(struct cbqri_controller *ctrl) +{ + u64 reg; + + reg =3D ioread64(ctrl->base + CBQRI_BC_BW_ALLOC_OFF); + return FIELD_GET(CBQRI_CONTROL_REGISTERS_MWEIGHT_MASK, reg); +} + +/* + * Stage both fields of bc_bw_alloc in one read-modify-write so the staging + * register is consistent after a single MMIO write. + */ +static void cbqri_set_bc_bw_alloc(struct cbqri_controller *ctrl, + u64 rbwb, u64 mweight) +{ + u64 reg =3D ioread64(ctrl->base + CBQRI_BC_BW_ALLOC_OFF); + + FIELD_MODIFY(CBQRI_CONTROL_REGISTERS_RBWB_MASK, ®, rbwb); + FIELD_MODIFY(CBQRI_CONTROL_REGISTERS_MWEIGHT_MASK, ®, mweight); + iowrite64(reg, ctrl->base + CBQRI_BC_BW_ALLOC_OFF); +} + +enum cbqri_bc_field { + CBQRI_BC_FIELD_RBWB, + CBQRI_BC_FIELD_MWEIGHT, +}; + static int cbqri_wait_busy_flag(struct cbqri_controller *ctrl, int reg_off= set, u64 *regp) { @@ -135,6 +193,42 @@ int cbqri_mon_op(struct cbqri_controller *ctrl, int re= g_offset, return 0; } =20 +/* + * Perform bandwidth allocation control operation on bandwidth controller. + * Caller must hold ctrl->lock. + */ +static int cbqri_bc_alloc_op(struct cbqri_controller *ctrl, int operation,= int rcid) +{ + int reg_offset =3D CBQRI_BC_ALLOC_CTL_OFF; + int status; + u64 reg; + + lockdep_assert_held(&ctrl->lock); + + if (cbqri_wait_busy_flag(ctrl, reg_offset, ®) < 0) { + pr_err_ratelimited("BUSY timeout before starting operation\n"); + return -EIO; + } + FIELD_MODIFY(CBQRI_CONTROL_REGISTERS_OP_MASK, ®, operation); + FIELD_MODIFY(CBQRI_CONTROL_REGISTERS_RCID_MASK, ®, rcid); + reg &=3D ~CBQRI_CONTROL_REGISTERS_AT_MASK; + iowrite64(reg, ctrl->base + reg_offset); + + if (cbqri_wait_busy_flag(ctrl, reg_offset, ®) < 0) { + pr_err_ratelimited("BUSY timeout during operation\n"); + return -EIO; + } + + status =3D FIELD_GET(CBQRI_CONTROL_REGISTERS_STATUS_MASK, reg); + if (status !=3D CBQRI_BC_ALLOC_CTL_STATUS_SUCCESS) { + pr_err_ratelimited("BC alloc op %d failed: status=3D%d\n", + operation, status); + return -EIO; + } + + return 0; +} + /* * Apply a capacity block mask and verify via CONFIG_LIMIT + READ_LIMIT. * @@ -266,6 +360,189 @@ int cbqri_read_cache_config(struct cbqri_controller *= ctrl, u32 closid, return err; } =20 +/* + * Apply a per-RCID update to one field (Rbwb or Mweight) of bc_bw_alloc. + * bc_bw_alloc packs both fields, so both halves are seeded from the + * authoritative software caches before CONFIG_LIMIT. This avoids the + * silent READ_LIMIT no-op window where stale data from a prior op's + * RCID could leak into the unmodified field. The verify step uses an + * inverted-value sentinel to confirm hardware accepted the target field. + * + * Caller must hold ctrl->lock. + */ +static int cbqri_apply_bc_field(struct cbqri_controller *ctrl, u32 closid, + enum cbqri_bc_field field, u64 val) +{ + u64 rbwb =3D ctrl->rbwb_cache[closid]; + u64 mweight =3D ctrl->mweight_cache[closid]; + u64 readback; + int ret; + + lockdep_assert_held(&ctrl->lock); + + if (field =3D=3D CBQRI_BC_FIELD_RBWB) + rbwb =3D val; + else + mweight =3D val; + + /* + * Wait for BUSY=3D0 before staging. A read-modify-write to the + * bc_bw_alloc staging register while an op is in flight can corrupt + * the unmodified field. + */ + if (cbqri_wait_busy_flag(ctrl, CBQRI_BC_ALLOC_CTL_OFF, NULL) < 0) { + pr_err_ratelimited("BUSY timeout before staging bc_bw_alloc\n"); + return -EIO; + } + + cbqri_set_bc_bw_alloc(ctrl, rbwb, mweight); + + ret =3D cbqri_bc_alloc_op(ctrl, CBQRI_BC_ALLOC_CTL_OP_CONFIG_LIMIT, closi= d); + if (ret < 0) + return ret; + + /* + * Pre-write a sentinel that cannot equal val to the target field + * so a silent READ_LIMIT (status SUCCESS but no staging update) + * is detectable in the readback. ~val truncated to the field + * width cannot equal val. + */ + if (field =3D=3D CBQRI_BC_FIELD_RBWB) + cbqri_set_rbwb(ctrl, ~val); + else + cbqri_set_mweight(ctrl, ~val); + + ret =3D cbqri_bc_alloc_op(ctrl, CBQRI_BC_ALLOC_CTL_OP_READ_LIMIT, closid); + if (ret < 0) + return ret; + + readback =3D (field =3D=3D CBQRI_BC_FIELD_RBWB) ? + cbqri_get_rbwb(ctrl) : cbqri_get_mweight(ctrl); + if (readback !=3D val) { + pr_err_ratelimited("BC field verify mismatch (reg=3D0x%llx !=3D val=3D%l= lu)\n", + readback, val); + return -EIO; + } + + /* Hardware confirmed to hold val. Update the authoritative cache. */ + if (field =3D=3D CBQRI_BC_FIELD_RBWB) + ctrl->rbwb_cache[closid] =3D rbwb; + else + ctrl->mweight_cache[closid] =3D mweight; + + return 0; +} + +/* + * Apply an Rbwb update for closid, optionally enforcing CBQRI section 4.5 + * sum(Rbwb) <=3D MRBWB. check_sum=3Dfalse is used by coordinated init/res= et + * walks where intermediate sums may transiently exceed MRBWB. + */ +int cbqri_apply_rbwb(struct cbqri_controller *ctrl, u32 closid, + u64 rbwb, bool check_sum) +{ + u32 i; + int ret; + + if (rbwb > U16_MAX) + return -EINVAL; + + mutex_lock(&ctrl->lock); + + if (check_sum && rbwb > 0) { + u64 sum =3D rbwb; + + for (i =3D 0; i < ctrl->rcid_count; i++) { + if (i =3D=3D closid) + continue; + sum +=3D ctrl->rbwb_cache[i]; + } + if (sum > ctrl->bc.mrbwb) { + pr_err_ratelimited("RBWB sum %llu exceeds MRBWB %u\n", + sum, ctrl->bc.mrbwb); + ret =3D -EINVAL; + goto out; + } + } + + ret =3D cbqri_apply_bc_field(ctrl, closid, CBQRI_BC_FIELD_RBWB, rbwb); +out: + mutex_unlock(&ctrl->lock); + return ret; +} + +int cbqri_apply_mweight_config(struct cbqri_controller *ctrl, u32 closid, + u64 mweight) +{ + int ret; + + if (mweight > FIELD_MAX(CBQRI_CONTROL_REGISTERS_MWEIGHT_MASK)) + return -EINVAL; + + mutex_lock(&ctrl->lock); + ret =3D cbqri_apply_bc_field(ctrl, closid, CBQRI_BC_FIELD_MWEIGHT, mweigh= t); + mutex_unlock(&ctrl->lock); + return ret; +} + +/* + * Read the Rbwb (reserved bandwidth blocks) for closid via READ_LIMIT. + */ +int cbqri_read_rbwb(struct cbqri_controller *ctrl, u32 closid, u64 *rbwb_o= ut) +{ + u8 mweight_sentinel =3D ~ctrl->mweight_cache[closid]; + int err; + + mutex_lock(&ctrl->lock); + + /* + * Stage a sentinel into the unread Mweight field. A silent + * READ_LIMIT no-op (status SUCCESS but staging not refreshed) leaves + * the sentinel in place, while a real read overwrites Mweight with + * the hardware value, which differs from the inverted cache sentinel. + */ + cbqri_set_bc_bw_alloc(ctrl, ctrl->rbwb_cache[closid], mweight_sentinel); + err =3D cbqri_bc_alloc_op(ctrl, CBQRI_BC_ALLOC_CTL_OP_READ_LIMIT, closid); + if (err =3D=3D 0) { + if (cbqri_get_mweight(ctrl) =3D=3D mweight_sentinel) { + pr_err_ratelimited("Rbwb READ_LIMIT did not update staging\n"); + err =3D -EIO; + } else { + *rbwb_out =3D cbqri_get_rbwb(ctrl); + } + } + mutex_unlock(&ctrl->lock); + return err; +} + +/* + * Read the Mweight (opportunistic weight) for closid via READ_LIMIT. + */ +int cbqri_read_mweight(struct cbqri_controller *ctrl, u32 closid, u64 *mwe= ight_out) +{ + u16 rbwb_sentinel =3D ~ctrl->rbwb_cache[closid]; + int err; + + mutex_lock(&ctrl->lock); + + /* + * Stage a sentinel into the unread Rbwb field so a silent READ_LIMIT + * no-op is detectable, mirroring cbqri_read_rbwb(). + */ + cbqri_set_bc_bw_alloc(ctrl, rbwb_sentinel, ctrl->mweight_cache[closid]); + err =3D cbqri_bc_alloc_op(ctrl, CBQRI_BC_ALLOC_CTL_OP_READ_LIMIT, closid); + if (err =3D=3D 0) { + if (cbqri_get_rbwb(ctrl) =3D=3D rbwb_sentinel) { + pr_err_ratelimited("Mweight READ_LIMIT did not update staging\n"); + err =3D -EIO; + } else { + *mweight_out =3D cbqri_get_mweight(ctrl); + } + } + mutex_unlock(&ctrl->lock); + return err; +} + static int cbqri_probe_feature(struct cbqri_controller *ctrl, int reg_offs= et, int operation, int evt_id, int *status, bool *access_type_supported) @@ -447,6 +724,108 @@ static int cbqri_probe_cc(struct cbqri_controller *ct= rl) return 0; } =20 +static int cbqri_probe_bc(struct cbqri_controller *ctrl) +{ + int err, status; + u32 i; + u64 reg; + + reg =3D ioread64(ctrl->base + CBQRI_BC_CAPABILITIES_OFF); + if (reg =3D=3D 0) + return -ENODEV; + + ctrl->ver_minor =3D FIELD_GET(CBQRI_BC_CAPABILITIES_VER_MINOR_MASK, reg); + ctrl->ver_major =3D FIELD_GET(CBQRI_BC_CAPABILITIES_VER_MAJOR_MASK, reg); + ctrl->bc.nbwblks =3D FIELD_GET(CBQRI_BC_CAPABILITIES_NBWBLKS_MASK, reg); + ctrl->bc.mrbwb =3D FIELD_GET(CBQRI_BC_CAPABILITIES_MRBWB_MASK, reg); + + if (!ctrl->bc.nbwblks) { + pr_err("bandwidth controller has nbwblks=3D0\n"); + return -EINVAL; + } + + if (!ctrl->rcid_count) { + pr_err("bandwidth controller has rcid_count=3D0\n"); + return -EINVAL; + } + + /* + * Reset seeds RCID 0 with mrbwb - (rcid_count - 1). Reject a + * controller that would underflow that arithmetic. + */ + if (ctrl->bc.mrbwb < ctrl->rcid_count) { + pr_err("bandwidth controller has mrbwb=3D%u < rcid_count=3D%u, rejecting= \n", + ctrl->bc.mrbwb, ctrl->rcid_count); + return -EINVAL; + } + + pr_debug("version=3D%d.%d nbwblks=3D%d mrbwb=3D%d\n", + ctrl->ver_major, ctrl->ver_minor, + ctrl->bc.nbwblks, ctrl->bc.mrbwb); + + /* Probe monitoring features */ + err =3D cbqri_probe_feature(ctrl, CBQRI_BC_MON_CTL_OFF, + CBQRI_BC_MON_CTL_OP_READ_COUNTER, 0, + &status, NULL); + if (err) + return err; + + if (status =3D=3D CBQRI_MON_CTL_STATUS_SUCCESS) + ctrl->mon_capable =3D true; + + /* Probe allocation features */ + err =3D cbqri_probe_feature(ctrl, CBQRI_BC_ALLOC_CTL_OFF, + CBQRI_BC_ALLOC_CTL_OP_READ_LIMIT, 0, + &status, &ctrl->bc.supports_alloc_at_code); + if (err) + return err; + + if (status =3D=3D CBQRI_BC_ALLOC_CTL_STATUS_SUCCESS) { + ctrl->alloc_capable =3D true; + + /* + * Per-RCID Rbwb and Mweight caches. The caches feed both + * fields of bc_bw_alloc on every apply so the staging + * register reflects authoritative software state, sidestepping + * silent READ_LIMIT no-op corruption of the unmodified field. + * rbwb_cache also lets cbqri_apply_rbwb() validate + * sum(Rbwb) <=3D MRBWB without re-reading every RCID. + */ + ctrl->rbwb_cache =3D kcalloc(ctrl->rcid_count, + sizeof(*ctrl->rbwb_cache), + GFP_KERNEL); + if (!ctrl->rbwb_cache) + return -ENOMEM; + + ctrl->mweight_cache =3D kcalloc(ctrl->rcid_count, + sizeof(*ctrl->mweight_cache), + GFP_KERNEL); + if (!ctrl->mweight_cache) { + kfree(ctrl->rbwb_cache); + ctrl->rbwb_cache =3D NULL; + return -ENOMEM; + } + + /* + * Seed mweight to the maximum, matching the resctrl-side + * MB_WGHT default. cbqri_apply_bc_field() reads both halves + * of bc_bw_alloc from the caches on every CONFIG_LIMIT, so + * the first MB_MIN domain init (which writes Rbwb) would + * otherwise commit Mweight=3D0 to every RCID. Per CBQRI 4.5 + * a weight of 0 implies the configured limit is a hard + * limit and the use of unused or non-reserved bandwidth + * is not allowed, which starves every RCID of opportunistic + * bandwidth until the subsequent MB_WGHT domain init + * catches up. + */ + for (i =3D 0; i < ctrl->rcid_count; i++) + ctrl->mweight_cache[i] =3D + FIELD_MAX(CBQRI_CONTROL_REGISTERS_MWEIGHT_MASK); + } + + return 0; +} + static int cbqri_probe_controller(struct cbqri_controller *ctrl) { int err; @@ -482,6 +861,9 @@ static int cbqri_probe_controller(struct cbqri_controll= er *ctrl) case CBQRI_CONTROLLER_TYPE_CAPACITY: err =3D cbqri_probe_cc(ctrl); break; + case CBQRI_CONTROLLER_TYPE_BANDWIDTH: + err =3D cbqri_probe_bc(ctrl); + break; default: pr_err("unknown controller type %d\n", ctrl->type); err =3D -ENODEV; @@ -534,6 +916,8 @@ void cbqri_controller_destroy(struct cbqri_controller *= ctrl) iounmap(ctrl->base); release_mem_region(ctrl->addr, ctrl->size); } + kfree(ctrl->mweight_cache); + kfree(ctrl->rbwb_cache); kfree(ctrl); } =20 @@ -645,6 +1029,38 @@ int riscv_cbqri_register_controller(const struct cbqr= i_controller_info *info) } break; } + case CBQRI_CONTROLLER_TYPE_BANDWIDTH: { + struct cbqri_controller *other; + int node_id; + + ctrl->mem.prox_dom =3D info->prox_dom; + node_id =3D pxm_to_node(info->prox_dom); + if (node_id =3D=3D NUMA_NO_NODE) { + pr_warn("controller at %pa: proximity domain %u has no NUMA node, skipp= ing\n", + &ctrl->addr, info->prox_dom); + cbqri_controller_destroy(ctrl); + return -ENODEV; + } + /* + * cbqri_resctrl_dom tracks a single hw_ctrl per domain, so a + * second BC sharing the same proximity domain would be + * silently dropped when the resctrl glue resolves the cpu to + * an existing domain. Reject the duplicate at register time + * to keep the failure mode visible. + */ + list_for_each_entry(other, &cbqri_controllers, list) { + if (other->type !=3D CBQRI_CONTROLLER_TYPE_BANDWIDTH) + continue; + if (other->mem.prox_dom !=3D info->prox_dom) + continue; + pr_warn("controller at %pa: proximity domain %u already claimed by %pa,= skipping\n", + &ctrl->addr, info->prox_dom, &other->addr); + cbqri_controller_destroy(ctrl); + return -EEXIST; + } + cpumask_copy(&ctrl->mem.cpu_mask, cpumask_of_node(node_id)); + break; + } default: pr_warn("controller at %pa: unknown type %u, skipping\n", &ctrl->addr, info->type); diff --git a/drivers/resctrl/cbqri_internal.h b/drivers/resctrl/cbqri_inter= nal.h index 1d2007a0c15b..4f806689d503 100644 --- a/drivers/resctrl/cbqri_internal.h +++ b/drivers/resctrl/cbqri_internal.h @@ -9,13 +9,21 @@ #include #include =20 -/* Capacity Controller (CC) MMIO register offsets. */ +/* + * Capacity Controller (CC) and Bandwidth Controller (BC) MMIO register of= fsets. + */ #define CBQRI_CC_CAPABILITIES_OFF 0 #define CBQRI_CC_MON_CTL_OFF 8 #define CBQRI_CC_MON_CTL_VAL_OFF 16 #define CBQRI_CC_ALLOC_CTL_OFF 24 #define CBQRI_CC_BLOCK_MASK_OFF 32 =20 +#define CBQRI_BC_CAPABILITIES_OFF 0 +#define CBQRI_BC_MON_CTL_OFF 8 +#define CBQRI_BC_MON_CTR_VAL_OFF 16 +#define CBQRI_BC_ALLOC_CTL_OFF 24 +#define CBQRI_BC_BW_ALLOC_OFF 32 + /* * Smallest MMIO span the driver actually accesses: highest defined * register offset (0x20) plus the 8-byte register width. Used by @@ -29,6 +37,11 @@ #define CBQRI_CC_CAPABILITIES_VER_MAJOR_MASK GENMASK_ULL(7, 4) #define CBQRI_CC_CAPABILITIES_NCBLKS_MASK GENMASK_ULL(23, 8) =20 +#define CBQRI_BC_CAPABILITIES_VER_MINOR_MASK GENMASK_ULL(3, 0) +#define CBQRI_BC_CAPABILITIES_VER_MAJOR_MASK GENMASK_ULL(7, 4) +#define CBQRI_BC_CAPABILITIES_NBWBLKS_MASK GENMASK_ULL(23, 8) +#define CBQRI_BC_CAPABILITIES_MRBWB_MASK GENMASK_ULL(47, 32) + /* * CC and BC control and mon registers are 64-bit. Keep every field mask * GENMASK_ULL so FIELD_MODIFY() or ~mask on a u64 register never @@ -42,14 +55,22 @@ #define CBQRI_CONTROL_REGISTERS_RCID_MASK GENMASK_ULL(19, 8) #define CBQRI_CONTROL_REGISTERS_STATUS_MASK GENMASK_ULL(38, 32) #define CBQRI_CONTROL_REGISTERS_BUSY_MASK GENMASK_ULL(39, 39) +#define CBQRI_CONTROL_REGISTERS_RBWB_MASK GENMASK_ULL(15, 0) +#define CBQRI_CONTROL_REGISTERS_MWEIGHT_MASK GENMASK_ULL(27, 20) =20 #define CBQRI_CC_ALLOC_CTL_OP_CONFIG_LIMIT 1 #define CBQRI_CC_ALLOC_CTL_OP_READ_LIMIT 2 #define CBQRI_CC_ALLOC_CTL_STATUS_SUCCESS 1 =20 +#define CBQRI_BC_ALLOC_CTL_OP_CONFIG_LIMIT 1 +#define CBQRI_BC_ALLOC_CTL_OP_READ_LIMIT 2 +#define CBQRI_BC_ALLOC_CTL_STATUS_SUCCESS 1 + #define CBQRI_CC_MON_CTL_OP_CONFIG_EVENT 1 #define CBQRI_CC_MON_CTL_OP_READ_COUNTER 2 =20 +#define CBQRI_BC_MON_CTL_OP_READ_COUNTER 2 + /* mon_ctl field masks (CC and BC share an identical OP/MCID/EVT_ID/STATUS= layout) */ #define CBQRI_MON_CTL_OP_MASK GENMASK_ULL(4, 0) #define CBQRI_MON_CTL_MCID_MASK GENMASK_ULL(19, 8) @@ -67,6 +88,14 @@ struct riscv_cbqri_capacity_caps { bool supports_alloc_at_code; }; =20 +/* Bandwidth Controller hardware capabilities */ +struct riscv_cbqri_bandwidth_caps { + u16 nbwblks; /* number of bandwidth blocks */ + u16 mrbwb; /* max reserved bw blocks */ + + bool supports_alloc_at_code; +}; + /** * enum cbqri_at - capacity controller access type for CDP * @CBQRI_AT_DATA: data access (CBQRI Table 1, AT=3D0) @@ -115,6 +144,7 @@ struct cbqri_controller { int ver_major; int ver_minor; =20 + struct riscv_cbqri_bandwidth_caps bc; struct riscv_cbqri_capacity_caps cc; =20 bool alloc_capable; @@ -126,6 +156,15 @@ struct cbqri_controller { u32 rcid_count; u32 mcid_count; =20 + /* + * Per-RCID cache of the most recent Rbwb / Mweight values applied + * via CONFIG_LIMIT. bc_bw_alloc packs both fields into one register, + * so cbqri_apply_bc_field() seeds both halves from the authoritative + * cache before CONFIG_LIMIT. + */ + u16 *rbwb_cache; + u8 *mweight_cache; + struct list_head list; =20 struct cache_controller { @@ -135,6 +174,12 @@ struct cbqri_controller { /* Unique Cache ID from the PPTT table's Cache Type Structure */ u32 cache_id; } cache; + + struct mem_controller { + /* Proximity Domain from SRAT table Memory Affinity Controller */ + u32 prox_dom; + struct cpumask cpu_mask; + } mem; }; =20 extern struct list_head cbqri_controllers; @@ -152,4 +197,14 @@ int cbqri_mon_op(struct cbqri_controller *ctrl, int re= g_offset, =20 int cbqri_init_mon_counters(struct cbqri_controller *ctrl); =20 +int cbqri_apply_rbwb(struct cbqri_controller *ctrl, u32 closid, + u64 rbwb, bool check_sum); + +int cbqri_apply_mweight_config(struct cbqri_controller *ctrl, u32 closid, + u64 mweight); + +int cbqri_read_rbwb(struct cbqri_controller *ctrl, u32 closid, u64 *rbwb_o= ut); + +int cbqri_read_mweight(struct cbqri_controller *ctrl, u32 closid, u64 *mwe= ight_out); + #endif /* _DRIVERS_RESCTRL_CBQRI_INTERNAL_H */ --=20 2.43.0 From nobody Mon Jun 8 05:29:11 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3F5EA3FB7DE; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="OXF9eawG" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 748441F008A6; Mon, 1 Jun 2026 20:36:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1780346191; bh=Mx+5fk1zL6sWbwK39Q+LQcpcli107HYns+HIsrXaf2o=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=OXF9eawGDGKdJtAaMPyuzdalCJuSYmleQUiS8tImVeJt9ncOAPsvcjVWvIiJJ8Wpi uf8BQmSv2UmxEDXoBUJJ8rAZ7oS88ycApIc/c/wryqH2qYrERF0U3SyseaYMu5KrU4 wApJq2Jv94b1hkfE4zj4M2kP8IApOQkUqNe8d8gGrwp7/e1Osya8uTOzJy3v3IVPTh EJxifSGu6Rxg0iwghHU8t9q3rRFd2++GQfSP6+u2sGfv4QSZTwAuPxdB6UonwLVmhW 0oQwxGZ/iv+3FzhnyFiDda91KW+bHRbPZ+9bWNxGK92D7ivwUPviQUxFCFPZr99Do/ /x5yhQlF3x3Ug== From: Drew Fustini Date: Mon, 01 Jun 2026 13:36:04 -0700 Subject: [PATCH RFC v6 10/18] riscv_cbqri: Add bandwidth controller monitoring device ops Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-10-baf00f50028a@kernel.org> References: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-0-baf00f50028a@kernel.org> In-Reply-To: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-0-baf00f50028a@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , Conor Dooley , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, Gong Shuai , Gong Shuai , liu.qingtao2@zte.com.cn, Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Rob Herring , Conor Dooley , Krzysztof Kozlowski , "Rafael J. Wysocki" , Len Brown , Robert Moore , Sunil V L , Drew Fustini , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Sebastian Andrzej Siewior , Clark Williams , Steven Rostedt , Jonathan Corbet Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org, linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, devicetree@vger.kernel.org, Paul Walmsley , Conor Dooley , linux-rt-devel@lists.linux.dev, linux-doc@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=6428; i=fustini@kernel.org; h=from:subject:message-id; bh=PJiKrbbQTgFTzCgn1gatNQ+Ncv3hgYYMnVZK/XK1Z28=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTJvnVmTPv9Y7XerLg3X4Ns5ropJ5YKH3C/tY5tAfeCh vPzo1+JdZSyMIhxMciKKbJs+pB3YYlX6NcF819sg5nDygQyhIGLUwAmMv07w2823dNSAV8+Pj2p /Gjdl0ilo+u4BF+IdvBo/XIq0yk+tNSA4Q+/etB1v+NXjFT5p1wykWCWDHh66VlnpkW70ZtTUpz Nt5kA X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Add the BC monitoring primitives. cbqri_init_bc_mon_counters() pre-arms each MCID with the TOTAL_READ_WRITE event and allocates the per-MCID software accumulator (struct cbqri_bc_mon_state) so subsequent reads can extend the 62-bit hardware counter to the 64-bit byte total resctrl expects. cbqri_bc_mon_overflow() recovers a single-wrap delta. The OVF bit signals multi-wrap and is the caller's concern. cbqri_find_only_mon_bc() returns NULL when zero or more than one mon-capable BC is present. A BC's counter can only accurately back L3 mbm_total_bytes when every memory request flows through that BC. Assisted-by: Claude:claude-opus-4-7 Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- drivers/resctrl/cbqri_devices.c | 75 ++++++++++++++++++++++++++++++++++++= ++++ drivers/resctrl/cbqri_internal.h | 37 ++++++++++++++++++++ 2 files changed, 112 insertions(+) diff --git a/drivers/resctrl/cbqri_devices.c b/drivers/resctrl/cbqri_device= s.c index 6093706b1ec4..b1a6ce35042a 100644 --- a/drivers/resctrl/cbqri_devices.c +++ b/drivers/resctrl/cbqri_devices.c @@ -905,6 +905,80 @@ int cbqri_init_mon_counters(struct cbqri_controller *c= trl) return 0; } =20 +/* + * 62-bit BC counter delta. Inputs must be pre-masked to + * CBQRI_BC_MON_CTR_VAL_CTR_MASK. The shift promotes the modular + * subtraction into 64-bit so a single wrap (cur < prev) yields the + * correct delta. Multi-wrap is handled by the caller via the + * hardware OVF bit (CBQRI 4.3). This function only needs to recover + * from at most one wrap. + */ +u64 cbqri_bc_mon_overflow(u64 prev_ctr, u64 cur_ctr) +{ + const unsigned int shift =3D 64 - 62; + u64 chunks =3D (cur_ctr << shift) - (prev_ctr << shift); + + return chunks >> shift; +} + +/* + * Allocate the per-MCID software accumulator and pre-arm every MCID + * with TOTAL_READ_WRITE so subsequent reads just snapshot the live + * counter. + * + * Caller responsibility: serialize concurrent invocations on the same + * single mon-capable BC (cbqri_resctrl uses cbqri_domain_list_lock for + * this). + */ +int cbqri_init_bc_mon_counters(struct cbqri_controller *bc) +{ + int i, err; + + if (bc->mbm_total_states) + return 0; + + bc->mbm_total_states =3D kcalloc(bc->mcid_count, + sizeof(*bc->mbm_total_states), + GFP_KERNEL); + if (!bc->mbm_total_states) + return -ENOMEM; + + for (i =3D 0; i < bc->mcid_count; i++) { + mutex_lock(&bc->lock); + err =3D cbqri_mon_op(bc, CBQRI_BC_MON_CTL_OFF, + CBQRI_BC_MON_CTL_OP_CONFIG_EVENT, + i, CBQRI_BC_EVT_ID_TOTAL_READ_WRITE, NULL); + mutex_unlock(&bc->lock); + if (err) { + kfree(bc->mbm_total_states); + bc->mbm_total_states =3D NULL; + return err; + } + } + return 0; +} + +/* + * Return the single mon-capable BC, NULL if zero or more than one. BC + * counters can only accurately surface as L3 mbm_total_bytes if every mem= ory + * request flows through the same BC. + */ +struct cbqri_controller *cbqri_find_only_mon_bc(void) +{ + struct cbqri_controller *ctrl, *only_bc =3D NULL; + + list_for_each_entry(ctrl, &cbqri_controllers, list) { + if (ctrl->type !=3D CBQRI_CONTROLLER_TYPE_BANDWIDTH) + continue; + if (!ctrl->mon_capable) + continue; + if (only_bc) + return NULL; + only_bc =3D ctrl; + } + return only_bc; +} + void cbqri_controller_destroy(struct cbqri_controller *ctrl) { /* @@ -916,6 +990,7 @@ void cbqri_controller_destroy(struct cbqri_controller *= ctrl) iounmap(ctrl->base); release_mem_region(ctrl->addr, ctrl->size); } + kfree(ctrl->mbm_total_states); kfree(ctrl->mweight_cache); kfree(ctrl->rbwb_cache); kfree(ctrl); diff --git a/drivers/resctrl/cbqri_internal.h b/drivers/resctrl/cbqri_inter= nal.h index 4f806689d503..68a40f846f40 100644 --- a/drivers/resctrl/cbqri_internal.h +++ b/drivers/resctrl/cbqri_internal.h @@ -69,8 +69,17 @@ #define CBQRI_CC_MON_CTL_OP_CONFIG_EVENT 1 #define CBQRI_CC_MON_CTL_OP_READ_COUNTER 2 =20 +#define CBQRI_BC_MON_CTL_OP_CONFIG_EVENT 1 #define CBQRI_BC_MON_CTL_OP_READ_COUNTER 2 =20 +/* Bandwidth usage monitoring event IDs (CBQRI spec Table 10) */ +#define CBQRI_BC_EVT_ID_TOTAL_READ_WRITE 1 + +/* bc_mon_ctr_val layout (CBQRI spec section 4.3, Figure 7) */ +#define CBQRI_BC_MON_CTR_VAL_CTR_MASK GENMASK_ULL(61, 0) +#define CBQRI_BC_MON_CTR_VAL_INVALID BIT_ULL(62) +#define CBQRI_BC_MON_CTR_VAL_OVF BIT_ULL(63) + /* mon_ctl field masks (CC and BC share an identical OP/MCID/EVT_ID/STATUS= layout) */ #define CBQRI_MON_CTL_OP_MASK GENMASK_ULL(4, 0) #define CBQRI_MON_CTL_MCID_MASK GENMASK_ULL(19, 8) @@ -96,6 +105,19 @@ struct riscv_cbqri_bandwidth_caps { bool supports_alloc_at_code; }; =20 +/** + * struct cbqri_bc_mon_state - per-MCID software accumulator for BC bandwi= dth + * @prev_ctr: previous 62-bit hardware snapshot (already masked to CTR fie= ld) + * @chunks: accumulated 64-bit byte total across hardware wraparounds + * + * Updated in resctrl_arch_rmid_read() under cbqri_controller::lock and + * zeroed by resctrl_arch_reset_rmid(). + */ +struct cbqri_bc_mon_state { + u64 prev_ctr; + u64 chunks; +}; + /** * enum cbqri_at - capacity controller access type for CDP * @CBQRI_AT_DATA: data access (CBQRI Table 1, AT=3D0) @@ -165,6 +187,15 @@ struct cbqri_controller { u16 *rbwb_cache; u8 *mweight_cache; =20 + /* + * Per-MCID 64-bit software accumulator for the BC's mbm_total_bytes + * event. Allocated by cbqri_init_bc_mon_counters() when this BC is + * paired with an L3 monitoring domain, sized by ->mcid_count. NULL + * on capacity controllers and on BCs that are not mon-paired. + * Protected by ->lock along with the surrounding MMIO sequence. + */ + struct cbqri_bc_mon_state *mbm_total_states; + struct list_head list; =20 struct cache_controller { @@ -207,4 +238,10 @@ int cbqri_read_rbwb(struct cbqri_controller *ctrl, u32= closid, u64 *rbwb_out); =20 int cbqri_read_mweight(struct cbqri_controller *ctrl, u32 closid, u64 *mwe= ight_out); =20 +u64 cbqri_bc_mon_overflow(u64 prev_ctr, u64 cur_ctr); + +int cbqri_init_bc_mon_counters(struct cbqri_controller *bc); + +struct cbqri_controller *cbqri_find_only_mon_bc(void); + #endif /* _DRIVERS_RESCTRL_CBQRI_INTERNAL_H */ --=20 2.43.0 From nobody Mon Jun 8 05:29:11 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 18F583FBEA2; Mon, 1 Jun 2026 20:36:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780346194; cv=none; b=iqEyGlSWx7wXVCUtjG6Va4XStAgPtFp0zNREy8/I1a62jlmlMH1vlTGb243PfS2HGHfh4PlS13n/y+iGOZDsnsRBdoSuUy4GEoamZCZETf9eG7GJcrY+r5Dxui/PkCC8/H52dxPrKt1sPb2Dpvbl2YYDYwYkLUnIUKQFMsazh8w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780346194; c=relaxed/simple; bh=BUQFXTa0I6vLX30BP8etjML8itzDlkQdpKSZUwFby6E=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KFJHIXkFMPll1UgikXqJnTZ28DwJEp/CDRlXe2dh9tX9b/Jx8HDrXOkilwSw8pQ3ma4sxUTKzo3WCcVtYXs3flfa+yw7mrPAAhxNiwQCyA2i+USwrGrMr8W5w+JD4jCkiZtjG+vHUtXsB2osFVQBqByV3KUs91QEP8zG5z43Nxc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=be+9yFKB; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="be+9yFKB" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4335F1F008A7; Mon, 1 Jun 2026 20:36:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1780346192; bh=9vBRs1mSGVNvPR6xjocFKftpd4+Zjp+FACjvhq14Wq4=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=be+9yFKB4xMSMnOWGa9vkl4HpsV1rdM+Vj6ExSguyyBgwqW5z7YsAfCMGS9qGGd1T abJJHHOzceP8DzbxtO1dh2Y2KmHKkxankV886ENt95GQV41F0oTerW+88k7zoZ1EGm 62jW5IM0pUgc/hI+nIHwR+6DlVOwokR9EjOij7oq6C/foKikRPVkQH+8epTavqKoDj OBTymHAbMYW8h89oH6zzcElA3V+F+/aYOX8X/dEEeZvMQB2yQCll14X8D2IMXXXoCK qINatc/RT6Flm+4F5ocWkl80HZIovjDL82Wm5FGTIwXSTVLr2WwNQnYaEfSkLFy1wz O5sDPu4cpBrdw== From: Drew Fustini Date: Mon, 01 Jun 2026 13:36:05 -0700 Subject: [PATCH RFC v6 11/18] riscv_cbqri: resctrl: Add cache allocation via capacity block mask Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-11-baf00f50028a@kernel.org> References: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-0-baf00f50028a@kernel.org> In-Reply-To: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-0-baf00f50028a@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , Conor Dooley , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, Gong Shuai , Gong Shuai , liu.qingtao2@zte.com.cn, Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Rob Herring , Conor Dooley , Krzysztof Kozlowski , "Rafael J. Wysocki" , Len Brown , Robert Moore , Sunil V L , Drew Fustini , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Sebastian Andrzej Siewior , Clark Williams , Steven Rostedt , Jonathan Corbet Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org, linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, devicetree@vger.kernel.org, Paul Walmsley , Conor Dooley , linux-rt-devel@lists.linux.dev, linux-doc@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=29327; i=fustini@kernel.org; h=from:subject:message-id; bh=BUQFXTa0I6vLX30BP8etjML8itzDlkQdpKSZUwFby6E=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTJvnUOW91YclH6s/IlfhWRO8yXkuzNNba21n2d6dzCN +tQVZhoRykLgxgXg6yYIsumD3kXlniFfl0w/8U2mDmsTCBDGLg4BWAiUy4zMlzIcVM+9ji+TyCy nfMSc0ayQB53lFH+MdYLM79tnmSoZ8zIsHCm73v2zG+H+g8t/ayw9NPGf5ybI4TdeK798nhkHr7 4BDMA X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Wire CBQRI capacity controllers into resctrl as RDT_RESOURCE_L2 and RDT_RESOURCE_L3 schemata. Mismatched CC caps at the same cache level are treated as a fatal configuration error since fs/resctrl exposes a single per-rid cap set. Domains are created lazily in the cpuhp online callback so cpu_mask reflects only currently online CPUs. Assisted-by: Claude:claude-opus-4-7 Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- MAINTAINERS | 2 + arch/riscv/Kconfig | 1 + arch/riscv/include/asm/resctrl.h | 152 ++++++++ drivers/resctrl/Kconfig | 4 + drivers/resctrl/Makefile | 1 + drivers/resctrl/cbqri_resctrl.c | 777 +++++++++++++++++++++++++++++++++++= ++++ 6 files changed, 937 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 24bdc04fea7a..7821dd5159cb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -23023,9 +23023,11 @@ R: yunhui cui L: linux-riscv@lists.infradead.org S: Supported F: arch/riscv/include/asm/qos.h +F: arch/riscv/include/asm/resctrl.h F: arch/riscv/kernel/qos.c F: drivers/resctrl/cbqri_devices.c F: drivers/resctrl/cbqri_internal.h +F: drivers/resctrl/cbqri_resctrl.c F: include/linux/riscv_cbqri.h =20 RISC-V RPMI AND MPXY DRIVERS diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 6abbb21f3a0d..390353a6153a 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -595,6 +595,7 @@ config RISCV_ISA_SSQOSID bool "Ssqosid extension support for supervisor mode Quality of Service ID" depends on 64BIT default n + select ARCH_HAS_CPU_RESCTRL help Adds support for the Ssqosid ISA extension (Supervisor-mode Quality of Service ID). diff --git a/arch/riscv/include/asm/resctrl.h b/arch/riscv/include/asm/resc= trl.h new file mode 100644 index 000000000000..282b5b59e3ee --- /dev/null +++ b/arch/riscv/include/asm/resctrl.h @@ -0,0 +1,152 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _ASM_RISCV_RESCTRL_H +#define _ASM_RISCV_RESCTRL_H + +#include +#include +#include + +#include + +struct rdt_resource; + +/* + * Sentinel "no CLOSID assigned" used by resctrl_arch_rmid_idx_decode(). + * fs/resctrl treats this opaquely. CBQRI uses MCID directly as the linear + * rmid index, so closid is unused on decode. + */ +#define RISCV_RESCTRL_EMPTY_CLOSID ((u32)~0) + +/* + * Terminology mapping between x86 (Intel RDT/AMD QoS) and RISC-V: + * + * CLOSID on x86 is RCID on RISC-V + * RMID on x86 is MCID on RISC-V + * CDP on x86 is AT (access type) on RISC-V + * + * Each fast-path arch entry point below is the RISC-V realization of the + * generic contract documented in . Comments here describe + * only the RISC-V-specific behavior (srmcfg encoding, CBQRI controller + * lookup, MCID-as-index policy). + */ + +/** + * resctrl_arch_alloc_capable() - any CBQRI controller exposes resctrl all= oc + * + * Returns true once at least one CBQRI controller has successfully probed= for + * a resctrl-exposed allocation feature (cache capacity or memory bandwidt= h). + * Only meaningful after cbqri_resctrl_setup() runs at late_initcall. + */ +bool resctrl_arch_alloc_capable(void); + +/** + * resctrl_arch_mon_capable() - any CBQRI controller exposes resctrl monit= oring + * + * Returns true once at least one CBQRI controller has successfully probed= a + * monitoring event wired through resctrl (L3 occupancy or L3 mbm_total_by= tes). + */ +bool resctrl_arch_mon_capable(void); + +/** + * resctrl_arch_rmid_idx_encode() - encode (RCID, MCID) into a linear index + * @closid: RCID (resource control id) + * @rmid: MCID (monitoring counter id) + * + * RISC-V uses MCID directly as the linear index into per-RMID arrays + * managed by fs/resctrl, since CBQRI controllers admit any MCID for any + * RCID. closid is unused here. CDP is encoded via the AT field on each + * CBQRI op rather than via the index. + */ +u32 resctrl_arch_rmid_idx_encode(u32 closid, u32 rmid); + +/** + * resctrl_arch_rmid_idx_decode() - inverse of resctrl_arch_rmid_idx_encod= e() + * @idx: linear index + * @closid: out: always RISCV_RESCTRL_EMPTY_CLOSID + * @rmid: out: the MCID that @idx encodes + */ +void resctrl_arch_rmid_idx_decode(u32 idx, u32 *closid, u32 *rmid); + +/** + * resctrl_arch_set_cpu_default_closid_rmid() - install per-CPU srmcfg def= ault + * @cpu: CPU number + * @closid: RCID to use when no task is matched + * @rmid: MCID to use when no task is matched + * + * Sets the per-CPU cpu_srmcfg_default so __switch_to_srmcfg() can fall ba= ck + * to the CPU's default RCID/MCID for default-group tasks (those whose + * thread.srmcfg encodes to 0, i.e. closid =3D=3D RESCTRL_RESERVED_CLOSID = and + * rmid =3D=3D RESCTRL_RESERVED_RMID). Implements resctrl allocation rule 2 + * ("CPU default") on RISC-V. + */ +void resctrl_arch_set_cpu_default_closid_rmid(int cpu, u32 closid, u32 rmi= d); + +/** + * resctrl_arch_sched_in() - context-switch hook to install task RCID/MCID + * @tsk: the task being scheduled in + * + * Called from finish_task_switch() to write tsk->thread.srmcfg into the + * srmcfg CSR. Tasks tagged with RISCV_RESCTRL_EMPTY_CLOSID inherit the + * per-CPU default set via resctrl_arch_set_cpu_default_closid_rmid(). + */ +void resctrl_arch_sched_in(struct task_struct *tsk); + +/** + * resctrl_arch_set_closid_rmid() - tag a task with an RCID/MCID + * @tsk: task to tag + * @closid: RCID to install + * @rmid: MCID to install + * + * Updates tsk->thread.srmcfg with the encoded (RCID, MCID) pair. The new + * value takes effect on the next resctrl_arch_sched_in() for this task. + */ +void resctrl_arch_set_closid_rmid(struct task_struct *tsk, u32 closid, u32= rmid); + +/** + * resctrl_arch_match_closid() - test whether a task carries a given RCID + * @tsk: task + * @closid: RCID + */ +bool resctrl_arch_match_closid(struct task_struct *tsk, u32 closid); + +/** + * resctrl_arch_match_rmid() - test whether a task carries a given (RCID, = MCID) + * @tsk: task + * @closid: RCID + * @rmid: MCID + */ +bool resctrl_arch_match_rmid(struct task_struct *tsk, u32 closid, u32 rmid= ); + +/** + * resctrl_arch_mon_ctx_alloc() - allocate per-monitor-event arch context + * @r: resctrl resource being monitored + * @evtid: which monitor event needs context + * + * Returns an opaque pointer that resctrl_arch_rmid_read() can use to find= the + * CBQRI controller backing this event. CBQRI's BC bandwidth context is + * keyed off the resource's L3 monitoring domain rather than per-event sta= te, + * so this implementation returns NULL. + */ +void *resctrl_arch_mon_ctx_alloc(struct rdt_resource *r, enum resctrl_even= t_id evtid); + +/** + * resctrl_arch_mon_ctx_free() - release context returned by mon_ctx_alloc= () + * @r: resctrl resource + * @evtid: monitor event id + * @arch_mon_ctx: pointer returned by resctrl_arch_mon_ctx_alloc() + */ +void resctrl_arch_mon_ctx_free(struct rdt_resource *r, enum resctrl_event_= id evtid, + void *arch_mon_ctx); + +static inline unsigned int resctrl_arch_round_mon_val(unsigned int val) +{ + return val; +} + +/* Not needed for RISC-V */ +static inline void resctrl_arch_enable_mon(void) { } +static inline void resctrl_arch_disable_mon(void) { } +static inline void resctrl_arch_enable_alloc(void) { } +static inline void resctrl_arch_disable_alloc(void) { } + +#endif /* _ASM_RISCV_RESCTRL_H */ diff --git a/drivers/resctrl/Kconfig b/drivers/resctrl/Kconfig index d578bc7aed85..732aae26f8f8 100644 --- a/drivers/resctrl/Kconfig +++ b/drivers/resctrl/Kconfig @@ -57,3 +57,7 @@ config RISCV_CBQRI_DRIVER_DEBUG new platform; otherwise leave disabled to avoid log noise. =20 endif + +config RISCV_CBQRI_RESCTRL_FS + bool + default y if RISCV_CBQRI_DRIVER && RESCTRL_FS diff --git a/drivers/resctrl/Makefile b/drivers/resctrl/Makefile index 28085036d895..ed737b4461b9 100644 --- a/drivers/resctrl/Makefile +++ b/drivers/resctrl/Makefile @@ -6,5 +6,6 @@ ccflags-$(CONFIG_ARM64_MPAM_DRIVER_DEBUG) +=3D -DDEBUG =20 obj-$(CONFIG_RISCV_CBQRI_DRIVER) +=3D cbqri.o cbqri-y +=3D cbqri_devices.o +cbqri-$(CONFIG_RISCV_CBQRI_RESCTRL_FS) +=3D cbqri_resctrl.o =20 ccflags-$(CONFIG_RISCV_CBQRI_DRIVER_DEBUG) +=3D -DDEBUG diff --git a/drivers/resctrl/cbqri_resctrl.c b/drivers/resctrl/cbqri_resctr= l.c new file mode 100644 index 000000000000..fb6d82aa3ffc --- /dev/null +++ b/drivers/resctrl/cbqri_resctrl.c @@ -0,0 +1,777 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#define pr_fmt(fmt) "%s:%s: " fmt, KBUILD_MODNAME, __func__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "cbqri_internal.h" + +struct cbqri_resctrl_res { + struct cbqri_controller *ctrl; + struct rdt_resource resctrl_res; + bool cdp_enabled; +}; + +struct cbqri_resctrl_dom { + struct rdt_ctrl_domain resctrl_ctrl_dom; + struct cbqri_controller *hw_ctrl; +}; + +static struct cbqri_resctrl_res cbqri_resctrl_resources[RDT_NUM_RESOURCES]; + +static bool exposed_alloc_capable; + +/* Protects ctrl_domain list mutations across CPU hotplug. */ +static DEFINE_MUTEX(cbqri_domain_list_lock); + +static struct rdt_ctrl_domain * +cbqri_find_ctrl_domain(struct list_head *h, int id) +{ + struct rdt_domain_hdr *hdr =3D resctrl_find_domain(h, id, NULL); + + return hdr ? container_of(hdr, struct rdt_ctrl_domain, hdr) : NULL; +} + +static int cbqri_apply_cache_config_dom(struct cbqri_resctrl_dom *hw_dom, + struct rdt_resource *r, + u32 closid, enum resctrl_conf_type t, + u64 cbm) +{ + struct cbqri_resctrl_res *hw_res =3D + container_of(r, struct cbqri_resctrl_res, resctrl_res); + struct cbqri_cc_config cfg =3D { + .cbm =3D cbm, + .at =3D (t =3D=3D CDP_CODE) ? CBQRI_AT_CODE : CBQRI_AT_DATA, + .cdp_enabled =3D hw_res->cdp_enabled, + }; + + return cbqri_apply_cache_config(hw_dom->hw_ctrl, closid, &cfg); +} + +bool resctrl_arch_alloc_capable(void) +{ + return exposed_alloc_capable; +} + +bool resctrl_arch_mon_capable(void) +{ + return false; +} + +bool resctrl_arch_get_cdp_enabled(enum resctrl_res_level rid) +{ + if (rid !=3D RDT_RESOURCE_L2 && rid !=3D RDT_RESOURCE_L3) + return false; + return cbqri_resctrl_resources[rid].cdp_enabled; +} + +int resctrl_arch_set_cdp_enabled(enum resctrl_res_level rid, bool enable) +{ + struct cbqri_resctrl_res *cbqri_res; + + if (rid !=3D RDT_RESOURCE_L2 && rid !=3D RDT_RESOURCE_L3) + return -ENODEV; + + cbqri_res =3D &cbqri_resctrl_resources[rid]; + if (!cbqri_res->resctrl_res.cdp_capable) + return -ENODEV; + + cbqri_res->cdp_enabled =3D enable; + return 0; +} + +struct rdt_resource *resctrl_arch_get_resource(enum resctrl_res_level l) +{ + if (l >=3D RDT_NUM_RESOURCES) + return NULL; + + return &cbqri_resctrl_resources[l].resctrl_res; +} + +/* + * fs/resctrl unconditionally references the symbols below before checking + * mon_capable. They are stubs for features CBQRI does not yet support. + */ +bool resctrl_arch_is_evt_configurable(enum resctrl_event_id evt) +{ + return false; +} + +void *resctrl_arch_mon_ctx_alloc(struct rdt_resource *r, + enum resctrl_event_id evtid) +{ + return NULL; +} + +void resctrl_arch_mon_ctx_free(struct rdt_resource *r, + enum resctrl_event_id evtid, void *arch_mon_ctx) +{ +} + +void resctrl_arch_config_cntr(struct rdt_resource *r, struct rdt_l3_mon_do= main *d, + enum resctrl_event_id evtid, u32 rmid, u32 closid, + u32 cntr_id, bool assign) +{ +} + +int resctrl_arch_cntr_read(struct rdt_resource *r, struct rdt_l3_mon_domai= n *d, + u32 unused, u32 rmid, int cntr_id, + enum resctrl_event_id eventid, u64 *val) +{ + return -EOPNOTSUPP; +} + +bool resctrl_arch_mbm_cntr_assign_enabled(struct rdt_resource *r) +{ + return false; +} + +int resctrl_arch_mbm_cntr_assign_set(struct rdt_resource *r, bool enable) +{ + return -EOPNOTSUPP; +} + +void resctrl_arch_reset_cntr(struct rdt_resource *r, struct rdt_l3_mon_dom= ain *d, + u32 unused, u32 rmid, int cntr_id, + enum resctrl_event_id eventid) +{ +} + +bool resctrl_arch_get_io_alloc_enabled(struct rdt_resource *r) +{ + return false; +} + +int resctrl_arch_io_alloc_enable(struct rdt_resource *r, bool enable) +{ + return -EOPNOTSUPP; +} + +void resctrl_arch_mon_event_config_read(void *info) +{ +} + +void resctrl_arch_mon_event_config_write(void *info) +{ +} + +void resctrl_arch_reset_rmid_all(struct rdt_resource *r, struct rdt_l3_mon= _domain *d) +{ +} + +void resctrl_arch_reset_rmid(struct rdt_resource *r, struct rdt_l3_mon_dom= ain *d, + u32 unused, u32 rmid, enum resctrl_event_id eventid) +{ +} + +int resctrl_arch_rmid_read(struct rdt_resource *r, struct rdt_domain_hdr *= hdr, + u32 closid, u32 rmid, enum resctrl_event_id eventid, + void *arch_priv, u64 *val, void *arch_mon_ctx) +{ + return -ENODATA; +} + +/* + * Note about terminology between x86 (Intel RDT/AMD QoS) and RISC-V: + * CLOSID on x86 is RCID on RISC-V + * RMID on x86 is MCID on RISC-V + */ +u32 resctrl_arch_get_num_closid(struct rdt_resource *res) +{ + struct cbqri_resctrl_res *hw_res; + + hw_res =3D container_of(res, struct cbqri_resctrl_res, resctrl_res); + + if (!hw_res->ctrl) + return 0; + + return hw_res->ctrl->rcid_count; +} + +u32 resctrl_arch_system_num_rmid_idx(void) +{ + return 1; +} + +u32 resctrl_arch_rmid_idx_encode(u32 closid, u32 rmid) +{ + return rmid; +} + +void resctrl_arch_rmid_idx_decode(u32 idx, u32 *closid, u32 *rmid) +{ + *closid =3D RISCV_RESCTRL_EMPTY_CLOSID; + *rmid =3D idx; +} + +void resctrl_arch_set_cpu_default_closid_rmid(int cpu, u32 closid, u32 rmi= d) +{ + u32 srmcfg =3D FIELD_PREP(SRMCFG_RCID_MASK, closid) | + FIELD_PREP(SRMCFG_MCID_MASK, rmid); + + WRITE_ONCE(per_cpu(cpu_srmcfg_default, cpu), srmcfg); +} + +void resctrl_arch_sched_in(struct task_struct *tsk) +{ + __switch_to_srmcfg(tsk); +} + +void resctrl_arch_set_closid_rmid(struct task_struct *tsk, u32 closid, u32= rmid) +{ + u32 srmcfg =3D FIELD_PREP(SRMCFG_RCID_MASK, closid) | + FIELD_PREP(SRMCFG_MCID_MASK, rmid); + + WRITE_ONCE(tsk->thread.srmcfg, srmcfg); +} + +void resctrl_arch_sync_cpu_closid_rmid(void *info) +{ + struct resctrl_cpu_defaults *r =3D info; + + lockdep_assert_preemption_disabled(); + + if (r) { + resctrl_arch_set_cpu_default_closid_rmid(smp_processor_id(), + r->closid, r->rmid); + } + + resctrl_arch_sched_in(current); +} + +bool resctrl_arch_match_closid(struct task_struct *tsk, u32 closid) +{ + return FIELD_GET(SRMCFG_RCID_MASK, READ_ONCE(tsk->thread.srmcfg)) =3D=3D = closid; +} + +bool resctrl_arch_match_rmid(struct task_struct *tsk, u32 closid, u32 rmid) +{ + return FIELD_GET(SRMCFG_MCID_MASK, READ_ONCE(tsk->thread.srmcfg)) =3D=3D = rmid; +} + +void resctrl_arch_pre_mount(void) +{ + /* All controllers discovered at boot via late_initcall. Nothing to do. */ +} + +int resctrl_arch_update_one(struct rdt_resource *r, struct rdt_ctrl_domain= *d, + u32 closid, enum resctrl_conf_type t, u32 cfg_val) +{ + struct cbqri_resctrl_dom *dom; + + dom =3D container_of(d, struct cbqri_resctrl_dom, resctrl_ctrl_dom); + + if (!r->alloc_capable) + return -EINVAL; + + switch (r->rid) { + case RDT_RESOURCE_L2: + case RDT_RESOURCE_L3: + return cbqri_apply_cache_config_dom(dom, r, closid, t, cfg_val); + default: + return -EINVAL; + } +} + +int resctrl_arch_update_domains(struct rdt_resource *r, u32 closid) +{ + struct resctrl_staged_config *cfg; + enum resctrl_conf_type t; + struct rdt_ctrl_domain *d; + int err =3D 0; + + /* Walking r->ctrl_domains, ensure it can't race with cpuhp */ + lockdep_assert_cpus_held(); + + list_for_each_entry(d, &r->ctrl_domains, hdr.list) { + for (t =3D 0; t < CDP_NUM_TYPES; t++) { + cfg =3D &d->staged_config[t]; + if (!cfg->have_new_ctrl) + continue; + err =3D resctrl_arch_update_one(r, d, closid, t, cfg->new_ctrl); + if (err) + return err; + } + } + return err; +} + +u32 resctrl_arch_get_config(struct rdt_resource *r, struct rdt_ctrl_domain= *d, + u32 closid, enum resctrl_conf_type type) +{ + struct cbqri_resctrl_dom *hw_dom; + struct cbqri_controller *ctrl; + enum cbqri_at at; + u32 val; + int err; + + hw_dom =3D container_of(d, struct cbqri_resctrl_dom, resctrl_ctrl_dom); + ctrl =3D hw_dom->hw_ctrl; + val =3D resctrl_get_default_ctrl(r); + + if (!r->alloc_capable) + return val; + + switch (r->rid) { + case RDT_RESOURCE_L2: + case RDT_RESOURCE_L3: + at =3D (type =3D=3D CDP_CODE) ? CBQRI_AT_CODE : CBQRI_AT_DATA; + err =3D cbqri_read_cache_config(ctrl, closid, at, &val); + if (err < 0) + val =3D resctrl_get_default_ctrl(r); + break; + default: + break; + } + + return val; +} + +void resctrl_arch_reset_all_ctrls(struct rdt_resource *r) +{ + struct cbqri_resctrl_res *hw_res; + struct rdt_ctrl_domain *d; + enum resctrl_conf_type t; + u32 default_ctrl; + int i; + + lockdep_assert_cpus_held(); + + hw_res =3D container_of(r, struct cbqri_resctrl_res, resctrl_res); + default_ctrl =3D resctrl_get_default_ctrl(r); + + if (!hw_res->ctrl) + return; + + list_for_each_entry(d, &r->ctrl_domains, hdr.list) { + for (i =3D 0; i < hw_res->ctrl->rcid_count; i++) { + for (t =3D 0; t < CDP_NUM_TYPES; t++) { + int rerr; + + rerr =3D resctrl_arch_update_one(r, d, i, t, default_ctrl); + if (rerr) + pr_err_ratelimited("rid=3D%d reset RCID %u type %u failed (%d)\n", + r->rid, i, t, rerr); + } + } + } +} + +static struct rdt_ctrl_domain *cbqri_new_domain(struct cbqri_controller *c= trl) +{ + struct cbqri_resctrl_dom *hw_dom; + struct rdt_ctrl_domain *domain; + + hw_dom =3D kzalloc_obj(*hw_dom, GFP_KERNEL); + if (!hw_dom) + return NULL; + + hw_dom->hw_ctrl =3D ctrl; + domain =3D &hw_dom->resctrl_ctrl_dom; + + INIT_LIST_HEAD(&domain->hdr.list); + + return domain; +} + +static int cbqri_init_domain_ctrlval(struct rdt_resource *r, struct rdt_ct= rl_domain *d) +{ + struct cbqri_resctrl_res *hw_res; + enum resctrl_conf_type t; + int err =3D 0; + int i; + + hw_res =3D container_of(r, struct cbqri_resctrl_res, resctrl_res); + + for (i =3D 0; i < hw_res->ctrl->rcid_count; i++) { + /* + * Seed both DATA and CODE staged slots so a later mount + * with -o cdp does not see stale CODE values. + * On non-AT controllers cbqri_cc_alloc_op() masks AT to 0 + * so all three iterations land on the same hardware state. + * The redundant writes are harmless. + */ + for (t =3D 0; t < CDP_NUM_TYPES; t++) { + err =3D resctrl_arch_update_one(r, d, i, t, + resctrl_get_default_ctrl(r)); + if (err) + return err; + } + } + return 0; +} + +/* + * Walk cbqri_controllers and pick one capacity controller (CC) per cache + * level (L2/L3) to back the corresponding RDT_RESOURCE_L*. When more than + * one CC sits at the same level (e.g. one per socket), they must agree on + * rcid_count / ncblks / alloc_capable. A mismatch is fatal because resctrl + * exposes a single set of caps per rid. The first matching controller win= s. + */ +static int cbqri_resctrl_pick_caches(void) +{ + struct cbqri_controller *ctrl; + + list_for_each_entry(ctrl, &cbqri_controllers, list) { + struct cbqri_resctrl_res *cbqri_res; + enum resctrl_res_level rid; + + if (ctrl->type !=3D CBQRI_CONTROLLER_TYPE_CAPACITY) + continue; + if (!ctrl->alloc_capable) { + if (ctrl->mon_capable) + pr_warn_once("CC @%pa: monitor-only controllers aren't supported\n", + &ctrl->addr); + continue; + } + + if (ctrl->cache.cache_level =3D=3D 2) { + rid =3D RDT_RESOURCE_L2; + } else if (ctrl->cache.cache_level =3D=3D 3) { + rid =3D RDT_RESOURCE_L3; + } else { + pr_err("unknown cache level %d\n", + ctrl->cache.cache_level); + return -ENODEV; + } + + cbqri_res =3D &cbqri_resctrl_resources[rid]; + if (cbqri_res->ctrl) { + /* + * CCs at the same cache level must agree on every cap + * resctrl exposes globally. Reject mismatches at pick + * time so the inconsistency is visible at boot. + */ + if (cbqri_res->ctrl->rcid_count !=3D ctrl->rcid_count || + cbqri_res->ctrl->cc.ncblks !=3D ctrl->cc.ncblks || + cbqri_res->ctrl->cc.supports_alloc_at_code !=3D + ctrl->cc.supports_alloc_at_code || + cbqri_res->ctrl->alloc_capable !=3D ctrl->alloc_capable) { + pr_err("L%d controllers have mismatched capabilities\n", + ctrl->cache.cache_level); + return -EINVAL; + } + continue; + } + + cbqri_res->ctrl =3D ctrl; + } + + return 0; +} + +/* + * Fill the rdt_resource fields for one picked rid. An rid with no picked + * controller is left untouched so it stays out of resctrl_arch_get_resour= ce(). + */ +static int cbqri_resctrl_control_init(struct cbqri_resctrl_res *cbqri_res) +{ + struct cbqri_controller *ctrl =3D cbqri_res->ctrl; + struct rdt_resource *res =3D &cbqri_res->resctrl_res; + + if (!ctrl) + return 0; + + switch (res->rid) { + case RDT_RESOURCE_L2: + case RDT_RESOURCE_L3: + res->name =3D (res->rid =3D=3D RDT_RESOURCE_L2) ? "L2" : "L3"; + res->schema_fmt =3D RESCTRL_SCHEMA_BITMAP; + res->ctrl_scope =3D (res->rid =3D=3D RDT_RESOURCE_L2) ? + RESCTRL_L2_CACHE : RESCTRL_L3_CACHE; + res->cache.cbm_len =3D ctrl->cc.ncblks; + res->cache.shareable_bits =3D 0; + res->cache.min_cbm_bits =3D 1; + res->cache.arch_has_sparse_bitmasks =3D false; + res->cdp_capable =3D ctrl->cc.supports_alloc_at_code; + res->alloc_capable =3D ctrl->alloc_capable; + INIT_LIST_HEAD(&res->ctrl_domains); + INIT_LIST_HEAD(&res->mon_domains); + break; + default: + break; + } + + return 0; +} + +static void cbqri_resctrl_accumulate_caps(void) +{ + int rid; + + for (rid =3D 0; rid < RDT_NUM_RESOURCES; rid++) { + struct cbqri_resctrl_res *hw_res =3D &cbqri_resctrl_resources[rid]; + + if (!hw_res->ctrl) + continue; + if (hw_res->ctrl->alloc_capable) + exposed_alloc_capable =3D true; + } +} + +/* + * Create, list-insert, and online a fresh ctrl_domain backing ctrl on + * resource res, seeded with cpu and identified by dom_id. Caller must + * hold cbqri_domain_list_lock and must have already verified that no + * existing ctrl_domain on res carries this id. + */ +static struct rdt_ctrl_domain *cbqri_create_ctrl_domain(struct cbqri_contr= oller *ctrl, + struct rdt_resource *res, + unsigned int cpu, int dom_id) +{ + struct rdt_ctrl_domain *domain; + struct list_head *pos =3D NULL; + int err; + + domain =3D cbqri_new_domain(ctrl); + if (!domain) + return ERR_PTR(-ENOMEM); + + cpumask_set_cpu(cpu, &domain->hdr.cpu_mask); + domain->hdr.id =3D dom_id; + domain->hdr.type =3D RESCTRL_CTRL_DOMAIN; + + err =3D cbqri_init_domain_ctrlval(res, domain); + if (err) { + kfree(container_of(domain, struct cbqri_resctrl_dom, + resctrl_ctrl_dom)); + return ERR_PTR(err); + } + + /* Insert sorted by id so user-visible ordering is deterministic. */ + resctrl_find_domain(&res->ctrl_domains, dom_id, &pos); + list_add_tail(&domain->hdr.list, pos); + + resctrl_online_ctrl_domain(res, domain); + + return domain; +} + +static int cbqri_attach_cpu_to_cap_ctrl(struct cbqri_controller *ctrl, + unsigned int cpu) +{ + struct cbqri_resctrl_res *hw_res; + struct rdt_ctrl_domain *domain; + struct rdt_resource *res; + int dom_id; + + if (ctrl->cache.cache_level =3D=3D 2) + hw_res =3D &cbqri_resctrl_resources[RDT_RESOURCE_L2]; + else if (ctrl->cache.cache_level =3D=3D 3) + hw_res =3D &cbqri_resctrl_resources[RDT_RESOURCE_L3]; + else + return 0; + + if (!hw_res->ctrl) + return 0; + + res =3D &hw_res->resctrl_res; + dom_id =3D ctrl->cache.cache_id; + + domain =3D cbqri_find_ctrl_domain(&res->ctrl_domains, dom_id); + if (domain) { + cpumask_set_cpu(cpu, &domain->hdr.cpu_mask); + return 0; + } + + domain =3D cbqri_create_ctrl_domain(ctrl, res, cpu, dom_id); + if (IS_ERR(domain)) + return PTR_ERR(domain); + + return 0; +} + +static void cbqri_detach_cpu_from_ctrl_domains(struct rdt_resource *res, + unsigned int cpu) +{ + struct rdt_ctrl_domain *domain, *tmp; + + list_for_each_entry_safe(domain, tmp, &res->ctrl_domains, hdr.list) { + if (!cpumask_test_cpu(cpu, &domain->hdr.cpu_mask)) + continue; + cpumask_clear_cpu(cpu, &domain->hdr.cpu_mask); + if (cpumask_empty(&domain->hdr.cpu_mask)) { + resctrl_offline_ctrl_domain(res, domain); + list_del(&domain->hdr.list); + kfree(container_of(domain, struct cbqri_resctrl_dom, + resctrl_ctrl_dom)); + } + } +} + +/* + * Remove a CPU from every domain it was attached to. The per-resource + * detach helpers act only when the CPU is set in a domain's mask, so this + * is idempotent and undoes a partial online attach as well as a full + * offline. Caller holds cbqri_domain_list_lock. + */ +static void cbqri_detach_cpu_from_all_ctrls(unsigned int cpu) +{ + int rid; + + lockdep_assert_held(&cbqri_domain_list_lock); + + for (rid =3D 0; rid < RDT_NUM_RESOURCES; rid++) { + struct cbqri_resctrl_res *hw_res =3D &cbqri_resctrl_resources[rid]; + + if (!hw_res->ctrl) + continue; + cbqri_detach_cpu_from_ctrl_domains(&hw_res->resctrl_res, cpu); + } +} + +/* + * Attach a CPU to every controller that claims it. On failure, detach the + * CPU from everything attached so far: the cpuhp core does not run this + * state's offline teardown when its startup fails, so a partial attach + * would otherwise leak into the domain cpu_masks. Caller holds + * cbqri_domain_list_lock. + */ +static int cbqri_attach_cpu_to_all_ctrls(unsigned int cpu) +{ + struct cbqri_controller *ctrl; + int err =3D 0; + + lockdep_assert_held(&cbqri_domain_list_lock); + + list_for_each_entry(ctrl, &cbqri_controllers, list) { + if (ctrl->type !=3D CBQRI_CONTROLLER_TYPE_CAPACITY) + continue; + if (!cpumask_test_cpu(cpu, &ctrl->cache.cpu_mask)) + continue; + if (!ctrl->alloc_capable) + continue; + + err =3D cbqri_attach_cpu_to_cap_ctrl(ctrl, cpu); + if (err) { + cbqri_detach_cpu_from_all_ctrls(cpu); + break; + } + } + + return err; +} + +static bool cbqri_resctrl_inited; + +static void cbqri_resctrl_teardown(void) +{ + int rid; + + if (!cbqri_resctrl_inited) + return; + + resctrl_exit(); + + for (rid =3D 0; rid < RDT_NUM_RESOURCES; rid++) { + struct cbqri_resctrl_res *hw_res =3D &cbqri_resctrl_resources[rid]; + + hw_res->ctrl =3D NULL; + hw_res->cdp_enabled =3D false; + } + exposed_alloc_capable =3D false; + cbqri_resctrl_inited =3D false; +} + +static int cbqri_resctrl_setup(void) +{ + int rid; + int err; + + for (rid =3D 0; rid < RDT_NUM_RESOURCES; rid++) + cbqri_resctrl_resources[rid].resctrl_res.rid =3D rid; + + err =3D cbqri_resctrl_pick_caches(); + if (err) + return err; + + for (rid =3D 0; rid < RDT_NUM_RESOURCES; rid++) { + err =3D cbqri_resctrl_control_init(&cbqri_resctrl_resources[rid]); + if (err) + return err; + } + + cbqri_resctrl_accumulate_caps(); + + if (!exposed_alloc_capable) { + pr_debug("no resctrl-capable CBQRI controllers found\n"); + return -ENODEV; + } + + err =3D resctrl_init(); + if (err) + return err; + + cbqri_resctrl_inited =3D true; + return 0; +} + +static int cbqri_resctrl_online_cpu(unsigned int cpu) +{ + int err; + + mutex_lock(&cbqri_domain_list_lock); + err =3D cbqri_attach_cpu_to_all_ctrls(cpu); + mutex_unlock(&cbqri_domain_list_lock); + if (err) + return err; + + /* + * Seed the per-CPU default RCID/MCID to the reserved (0, 0) pair and + * notify the resctrl core so it tracks this CPU in the default group. + * Mirrors x86 resctrl_arch_online_cpu(). + */ + resctrl_arch_set_cpu_default_closid_rmid(cpu, 0, 0); + resctrl_online_cpu(cpu); + return 0; +} + +static int cbqri_resctrl_offline_cpu(unsigned int cpu) +{ + resctrl_offline_cpu(cpu); + + mutex_lock(&cbqri_domain_list_lock); + cbqri_detach_cpu_from_all_ctrls(cpu); + mutex_unlock(&cbqri_domain_list_lock); + return 0; +} + +/* Saved cpuhp slot from cpuhp_setup_state() for symmetric removal. */ +static enum cpuhp_state cbqri_cpuhp_state; + +static int __init cbqri_arch_late_init(void) +{ + int err; + + if (!riscv_isa_extension_available(NULL, SSQOSID)) + return -ENODEV; + + err =3D cbqri_resctrl_setup(); + if (err) + return err; + + err =3D cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "cbqri:online", + cbqri_resctrl_online_cpu, + cbqri_resctrl_offline_cpu); + if (err < 0) { + cbqri_resctrl_teardown(); + return err; + } + cbqri_cpuhp_state =3D err; + + return 0; +} +late_initcall(cbqri_arch_late_init); --=20 2.43.0 From nobody Mon Jun 8 05:29:11 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E34B73F65E0; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FqFDzxu7" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1E5CC1F00A01; Mon, 1 Jun 2026 20:36:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1780346192; bh=ExeO4pgSdUF010kVTEBC1O84msec/XDSsHQ4MfdpSGE=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=FqFDzxu7/T6I/uNql61JLjy4BfB6zGAOoNv/ctgfNBiz+g6DHsWpVod0lplC381sf imIl3y3+XbBwuwzpJ9FYlWcy9AG+wDbOLzk+Qz7PinbZTi0yNDKxs/a+TcNA0GiDlB pj4YtMG9Gvj7mgzkwy8HSYzf+MaONfxnU5QCw/2qxpNdujc2YMmYCmaPyVM2uBpV2f fTbHlrx8ef2SCMf8hwfeEiEtAlD+iQkQQSTuNrTCOUqSH7J4MxYj28i9BmyZPm5VI8 SINC0/OLt1FQal9AlGxDCbGWsWV2VBOys329Iv2oz38Xt9HSvuKHvwg08iljPsBkBB uTgeUZFWKOBgA== From: Drew Fustini Date: Mon, 01 Jun 2026 13:36:06 -0700 Subject: [PATCH RFC v6 12/18] riscv_cbqri: resctrl: Add L3 cache occupancy monitoring Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-12-baf00f50028a@kernel.org> References: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-0-baf00f50028a@kernel.org> In-Reply-To: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-0-baf00f50028a@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , Conor Dooley , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, Gong Shuai , Gong Shuai , liu.qingtao2@zte.com.cn, Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Rob Herring , Conor Dooley , Krzysztof Kozlowski , "Rafael J. Wysocki" , Len Brown , Robert Moore , Sunil V L , Drew Fustini , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Sebastian Andrzej Siewior , Clark Williams , Steven Rostedt , Jonathan Corbet Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org, linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, devicetree@vger.kernel.org, Paul Walmsley , Conor Dooley , linux-rt-devel@lists.linux.dev, linux-doc@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=13890; i=fustini@kernel.org; h=from:subject:message-id; bh=TDq5aUaYu2V9OHkOb5NqMyBoroO1Wj/vn9YtYWOCSsg=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTJvnVW35gqpBebwGWSOXmp6qIJBse9kvju3H38oo2Xa clp7vO8HaUsDGJcDLJiiiybPuRdWOIV+nXB/BfbYOawMoEMYeDiFICJiPoxMjzsmeu8bx+D6JYe 3r2sepK2V6caLp+c3HtCKfd56PwFpi6MDBtdnN6HX9wcmi8X873A7smDG85F56+31xT/3LaochF DNg8A X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Expose QOS_L3_OCCUP_EVENT_ID so userspace can read per-MCID llc_occupancy. The result is converted from capacity blocks to bytes using cache_size and ncblks. Each MCID is armed once with the Occupancy event by cbqri_init_mon_counters() and free runs thereafter. The resctrl core only reads occupancy on the limbo recycle path and never resets it, so resctrl_arch_reset_rmid() and resctrl_arch_reset_rmid_all() have no per-rmid software state to clear. The L3 mon_domain is created lazily on the first CPU of a cache_id and linked to the paired ctrl_domain. Assisted-by: Claude:claude-opus-4-7 Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- drivers/resctrl/cbqri_resctrl.c | 286 ++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 274 insertions(+), 12 deletions(-) diff --git a/drivers/resctrl/cbqri_resctrl.c b/drivers/resctrl/cbqri_resctr= l.c index fb6d82aa3ffc..f379058b0114 100644 --- a/drivers/resctrl/cbqri_resctrl.c +++ b/drivers/resctrl/cbqri_resctrl.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -33,6 +34,10 @@ struct cbqri_resctrl_dom { static struct cbqri_resctrl_res cbqri_resctrl_resources[RDT_NUM_RESOURCES]; =20 static bool exposed_alloc_capable; +static bool exposed_mon_capable; + +/* Used by resctrl_arch_system_num_rmid_idx(). Narrowed by accumulate_caps= . */ +static u32 max_rmid =3D U32_MAX; =20 /* Protects ctrl_domain list mutations across CPU hotplug. */ static DEFINE_MUTEX(cbqri_domain_list_lock); @@ -45,6 +50,14 @@ cbqri_find_ctrl_domain(struct list_head *h, int id) return hdr ? container_of(hdr, struct rdt_ctrl_domain, hdr) : NULL; } =20 +static struct rdt_l3_mon_domain * +cbqri_find_l3_mon_domain(struct list_head *h, int id) +{ + struct rdt_domain_hdr *hdr =3D resctrl_find_domain(h, id, NULL); + + return hdr ? container_of(hdr, struct rdt_l3_mon_domain, hdr) : NULL; +} + static int cbqri_apply_cache_config_dom(struct cbqri_resctrl_dom *hw_dom, struct rdt_resource *r, u32 closid, enum resctrl_conf_type t, @@ -68,7 +81,7 @@ bool resctrl_arch_alloc_capable(void) =20 bool resctrl_arch_mon_capable(void) { - return false; + return exposed_mon_capable; } =20 bool resctrl_arch_get_cdp_enabled(enum resctrl_res_level rid) @@ -168,20 +181,89 @@ void resctrl_arch_mon_event_config_write(void *info) { } =20 -void resctrl_arch_reset_rmid_all(struct rdt_resource *r, struct rdt_l3_mon= _domain *d) +void resctrl_arch_reset_rmid(struct rdt_resource *r, struct rdt_l3_mon_dom= ain *d, + u32 unused, u32 rmid, enum resctrl_event_id eventid) { + /* + * Occupancy MCIDs are armed once by cbqri_init_mon_counters() and + * free run thereafter. The core only reads occupancy on the limbo + * recycle path, never resets it, so there is no per-rmid software + * state to clear here. + */ } =20 -void resctrl_arch_reset_rmid(struct rdt_resource *r, struct rdt_l3_mon_dom= ain *d, - u32 unused, u32 rmid, enum resctrl_event_id eventid) +void resctrl_arch_reset_rmid_all(struct rdt_resource *r, struct rdt_l3_mon= _domain *d) { + /* Occupancy counters free run, so there is no state to reset. */ } =20 int resctrl_arch_rmid_read(struct rdt_resource *r, struct rdt_domain_hdr *= hdr, u32 closid, u32 rmid, enum resctrl_event_id eventid, void *arch_priv, u64 *val, void *arch_mon_ctx) { - return -ENODATA; + struct cbqri_resctrl_dom *hw_dom; + struct cbqri_controller *ctrl; + struct rdt_ctrl_domain *d; + u64 ctr_val; + int err =3D 0; + + resctrl_arch_rmid_read_context_check(); + + /* + * cbqri_mon_op() takes ctrl->lock sleeping mutex and polls + * BUSY for up to 1 ms, neither of which is safe under + * irqs_disabled(). + */ + if (irqs_disabled()) + return -EIO; + + /* + * cbqri_domain_list_lock serialises the list walk against + * cbqri_detach_cpu_from_ctrl_domains(). + */ + mutex_lock(&cbqri_domain_list_lock); + + switch (eventid) { + case QOS_L3_OCCUP_EVENT_ID: + d =3D cbqri_find_ctrl_domain(&r->ctrl_domains, hdr->id); + if (!d) { + err =3D -ENOENT; + break; + } + + hw_dom =3D container_of(d, struct cbqri_resctrl_dom, resctrl_ctrl_dom); + ctrl =3D hw_dom->hw_ctrl; + + mutex_lock(&ctrl->lock); + + /* + * MCIDs are armed with Occupancy once at init and free run. + * Pass EVT_ID explicitly as the CBQRI spec does not guarantee + * sticky-last-configured-event for READ_COUNTER. + */ + err =3D cbqri_mon_op(ctrl, CBQRI_CC_MON_CTL_OFF, + CBQRI_CC_MON_CTL_OP_READ_COUNTER, + rmid, CBQRI_CC_EVT_ID_OCCUPANCY, NULL); + if (!err) { + ctr_val =3D ioread64(ctrl->base + CBQRI_CC_MON_CTL_VAL_OFF); + + /* + * Capacity blocks to bytes. Multiply before divide + * so a non-power-of-2 ncblks doesn't truncate. + */ + *val =3D (u64)ctrl->cache.cache_size * ctr_val / + ctrl->cc.ncblks; + } + mutex_unlock(&ctrl->lock); + break; + + default: + err =3D -EINVAL; + break; + } + + mutex_unlock(&cbqri_domain_list_lock); + return err; } =20 /* @@ -203,7 +285,7 @@ u32 resctrl_arch_get_num_closid(struct rdt_resource *re= s) =20 u32 resctrl_arch_system_num_rmid_idx(void) { - return 1; + return max_rmid; } =20 u32 resctrl_arch_rmid_idx_encode(u32 closid, u32 rmid) @@ -500,6 +582,13 @@ static int cbqri_resctrl_control_init(struct cbqri_res= ctrl_res *cbqri_res) res->alloc_capable =3D ctrl->alloc_capable; INIT_LIST_HEAD(&res->ctrl_domains); INIT_LIST_HEAD(&res->mon_domains); + + if (ctrl->mon_capable && res->rid =3D=3D RDT_RESOURCE_L3) { + res->mon_scope =3D RESCTRL_L3_CACHE; + resctrl_enable_mon_event(QOS_L3_OCCUP_EVENT_ID, + false, 0, NULL); + res->mon_capable =3D true; + } break; default: break; @@ -510,6 +599,7 @@ static int cbqri_resctrl_control_init(struct cbqri_resc= trl_res *cbqri_res) =20 static void cbqri_resctrl_accumulate_caps(void) { + struct cbqri_controller *l3_ctrl; int rid; =20 for (rid =3D 0; rid < RDT_NUM_RESOURCES; rid++) { @@ -519,7 +609,30 @@ static void cbqri_resctrl_accumulate_caps(void) continue; if (hw_res->ctrl->alloc_capable) exposed_alloc_capable =3D true; + if (hw_res->ctrl->mon_capable) + exposed_mon_capable =3D true; + } + + /* + * Narrow max_rmid against the picked occupancy source (the L3 CC) + * only. A mon-capable controller that is not exposed as a counter + * source must not clamp the rmid space. + */ + l3_ctrl =3D cbqri_resctrl_resources[RDT_RESOURCE_L3].ctrl; + if (l3_ctrl && l3_ctrl->mon_capable) + max_rmid =3D min(max_rmid, l3_ctrl->mcid_count); + + if (!exposed_mon_capable) { + max_rmid =3D 1; + return; } + + /* + * num_rmid is the user-visible bound for the L3 monitoring rmid + * space. Track max_rmid (the picked-source minimum) so userspace is + * not told more RMIDs than can be allocated. + */ + cbqri_resctrl_resources[RDT_RESOURCE_L3].resctrl_res.mon.num_rmid =3D max= _rmid; } =20 /* @@ -560,13 +673,89 @@ static struct rdt_ctrl_domain *cbqri_create_ctrl_doma= in(struct cbqri_controller return domain; } =20 +static int cbqri_attach_cpu_to_l3_mon(struct cbqri_controller *ctrl, + struct rdt_resource *res, unsigned int cpu) +{ + struct rdt_l3_mon_domain *mon_dom; + struct rdt_ctrl_domain *ctrl_dom; + struct list_head *mon_pos =3D NULL; + int dom_id =3D ctrl->cache.cache_id; + int err; + + lockdep_assert_held(&cbqri_domain_list_lock); + + mon_dom =3D cbqri_find_l3_mon_domain(&res->mon_domains, dom_id); + if (mon_dom) { + cpumask_set_cpu(cpu, &mon_dom->hdr.cpu_mask); + return 0; + } + + ctrl_dom =3D cbqri_find_ctrl_domain(&res->ctrl_domains, dom_id); + if (!ctrl_dom) { + pr_err("L3 mon attach for cpu %u: no ctrl_domain id %d\n", + cpu, dom_id); + return -EINVAL; + } + + mon_dom =3D kzalloc_obj(*mon_dom, GFP_KERNEL); + if (!mon_dom) + return -ENOMEM; + + mon_dom->hdr.id =3D dom_id; + mon_dom->hdr.type =3D RESCTRL_MON_DOMAIN; + mon_dom->hdr.rid =3D RDT_RESOURCE_L3; + cpumask_set_cpu(cpu, &mon_dom->hdr.cpu_mask); + INIT_LIST_HEAD(&mon_dom->hdr.list); + + if (resctrl_find_domain(&res->mon_domains, dom_id, &mon_pos)) { + pr_err("duplicate L3 mon_domain id %d\n", dom_id); + err =3D -EEXIST; + goto err_free; + } + if (mon_pos) + list_add_tail(&mon_dom->hdr.list, mon_pos); + else + list_add_tail(&mon_dom->hdr.list, &res->mon_domains); + + err =3D resctrl_online_mon_domain(res, &mon_dom->hdr); + if (err) + goto err_listdel; + + err =3D cbqri_init_mon_counters(ctrl); + if (err) + goto err_offline; + + return 0; + +err_offline: + /* + * cancel_delayed_work avoids deadlocking against the cqm_limbo + * worker which takes cpus_read_lock while this hotplug callback + * already holds cpus_write_lock. mbm_over is only + * INIT_DELAYED_WORK'd when MBM_TOTAL was enabled, so gate the + * cancel on the same condition to avoid touching a zeroed work + * struct. + */ + cancel_delayed_work(&mon_dom->cqm_limbo); + if (resctrl_is_mon_event_enabled(QOS_L3_MBM_TOTAL_EVENT_ID)) + cancel_delayed_work(&mon_dom->mbm_over); + resctrl_offline_mon_domain(res, &mon_dom->hdr); +err_listdel: + list_del(&mon_dom->hdr.list); +err_free: + kfree(mon_dom); + return err; +} + static int cbqri_attach_cpu_to_cap_ctrl(struct cbqri_controller *ctrl, unsigned int cpu) { struct cbqri_resctrl_res *hw_res; struct rdt_ctrl_domain *domain; struct rdt_resource *res; + bool new_domain =3D false; int dom_id; + int err; =20 if (ctrl->cache.cache_level =3D=3D 2) hw_res =3D &cbqri_resctrl_resources[RDT_RESOURCE_L2]; @@ -584,14 +773,68 @@ static int cbqri_attach_cpu_to_cap_ctrl(struct cbqri_= controller *ctrl, domain =3D cbqri_find_ctrl_domain(&res->ctrl_domains, dom_id); if (domain) { cpumask_set_cpu(cpu, &domain->hdr.cpu_mask); - return 0; + } else { + domain =3D cbqri_create_ctrl_domain(ctrl, res, cpu, dom_id); + if (IS_ERR(domain)) + return PTR_ERR(domain); + new_domain =3D true; } =20 - domain =3D cbqri_create_ctrl_domain(ctrl, res, cpu, dom_id); - if (IS_ERR(domain)) - return PTR_ERR(domain); + if (ctrl->mon_capable && ctrl->cache.cache_level =3D=3D 3) { + err =3D cbqri_attach_cpu_to_l3_mon(ctrl, res, cpu); + if (err) + goto err_undo_ctrl_dom; + } =20 return 0; + +err_undo_ctrl_dom: + /* + * The cpuhp core only rolls back states that successfully ran their + * startup. The L3 mon attach failure happens inside this state's + * startup, so its own offline callback is not invoked. Undo the + * cpumask_set and, if this attach created the ctrl_domain, tear it + * down so a retry sees a clean slate. + */ + cpumask_clear_cpu(cpu, &domain->hdr.cpu_mask); + if (new_domain) { + resctrl_offline_ctrl_domain(res, domain); + list_del(&domain->hdr.list); + kfree(container_of(domain, struct cbqri_resctrl_dom, + resctrl_ctrl_dom)); + } + return err; +} + +static void cbqri_detach_cpu_from_l3_mon(struct rdt_resource *res, + unsigned int cpu) +{ + struct rdt_l3_mon_domain *mon_dom, *tmp; + + lockdep_assert_held(&cbqri_domain_list_lock); + + list_for_each_entry_safe(mon_dom, tmp, &res->mon_domains, hdr.list) { + if (!cpumask_test_cpu(cpu, &mon_dom->hdr.cpu_mask)) + continue; + cpumask_clear_cpu(cpu, &mon_dom->hdr.cpu_mask); + if (cpumask_empty(&mon_dom->hdr.cpu_mask)) { + /* + * This runs as a cpuhp offline callback under + * cpus_write_lock. The cqm_limbo and mbm_over workers + * take cpus_read_lock before touching a domain, so + * neither can run or re-queue here. A non-sync cancel + * thus reliably dequeues any pending work before kfree, + * and cancel_delayed_work_sync() would instead deadlock + * against that cpus_read_lock. + */ + cancel_delayed_work(&mon_dom->cqm_limbo); + if (resctrl_is_mon_event_enabled(QOS_L3_MBM_TOTAL_EVENT_ID)) + cancel_delayed_work(&mon_dom->mbm_over); + resctrl_offline_mon_domain(res, &mon_dom->hdr); + list_del(&mon_dom->hdr.list); + kfree(mon_dom); + } + } } =20 static void cbqri_detach_cpu_from_ctrl_domains(struct rdt_resource *res, @@ -630,6 +873,8 @@ static void cbqri_detach_cpu_from_all_ctrls(unsigned in= t cpu) if (!hw_res->ctrl) continue; cbqri_detach_cpu_from_ctrl_domains(&hw_res->resctrl_res, cpu); + if (rid =3D=3D RDT_RESOURCE_L3 && hw_res->ctrl->mon_capable) + cbqri_detach_cpu_from_l3_mon(&hw_res->resctrl_res, cpu); } } =20 @@ -683,6 +928,8 @@ static void cbqri_resctrl_teardown(void) hw_res->cdp_enabled =3D false; } exposed_alloc_capable =3D false; + exposed_mon_capable =3D false; + max_rmid =3D U32_MAX; cbqri_resctrl_inited =3D false; } =20 @@ -706,14 +953,29 @@ static int cbqri_resctrl_setup(void) =20 cbqri_resctrl_accumulate_caps(); =20 - if (!exposed_alloc_capable) { + if (!exposed_alloc_capable && !exposed_mon_capable) { pr_debug("no resctrl-capable CBQRI controllers found\n"); return -ENODEV; } =20 err =3D resctrl_init(); - if (err) + if (err) { + /* + * resctrl_init() failed before we set cbqri_resctrl_inited, + * so cbqri_resctrl_teardown() would no-op. Roll back the + * exposed_*_capable flags and the resource picks directly + * so resctrl_arch_alloc_capable() / _mon_capable() do not + * lie to callers after this returns. + */ + for (rid =3D 0; rid < RDT_NUM_RESOURCES; rid++) { + cbqri_resctrl_resources[rid].ctrl =3D NULL; + cbqri_resctrl_resources[rid].cdp_enabled =3D false; + } + exposed_alloc_capable =3D false; + exposed_mon_capable =3D false; + max_rmid =3D U32_MAX; return err; + } =20 cbqri_resctrl_inited =3D true; return 0; --=20 2.43.0 From nobody Mon Jun 8 05:29:11 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF0093FCB22; Mon, 1 Jun 2026 20:36:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780346195; cv=none; b=D0l2f60AE3Nmd9nMyEFqp2DlFXPz43j8PQSG0HhEAM2/E0aj0NBIhkBRkNdmh2rm72Hb4nXFBUYCtympfVSEy5zbJ2YRWSV5QjeBcTyps6ea/HhUjMX58+oSXBS7VqjqwsIpI1FCQLhFEjvyv5kn+9qvIYa4B4jlIpIfC0p5j8M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780346195; c=relaxed/simple; bh=Vd7FTyDoPXSVqpeMVe2i7AEgBBOuyeoGDUMVwp3ktKw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ITa07Ucshm/4eUhbNn4Ga1VAQ0Iglv93UZq1X4ewzTeGhHlf0fwci/kR+eoLLEsNlAbtEN9kq/uC6jnouEJmxHD9twFQWk+PQs6egJExn6XUhegrOsTDLJKv+HLAPUEy1QpuW8pZ68CiEdoHduII5IthI5QwIb6npGIiChhgIH4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WKOo6Dxi; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WKOo6Dxi" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E77DF1F008A2; Mon, 1 Jun 2026 20:36:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1780346193; bh=lWCNgIop9Qt5yfOtgz+epfIATOfjedxUHQRs5gpk3e0=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=WKOo6DxiIJVHHW/BdwO2m4vYkGaOOFzn8i1M6vhULhDzMJDUJpmSkZxqUDbfJrsjs juTnCKb5zKGLYgu7hl8R09HEmyPw2QYGd3fIwSamPzggdLfP57cK95Knd4sp99Lcsn yzlAkznuy/Na1aaBC+dB8bYu2yZX9qzFwuU4tDWivdud11Pw73M1Finksy+ftI8Oe+ nLUitaA6btDR4FlaTXhuxa1SMXzpw3Rer5HUpd9gcwjiZyFBTUef5MN20x8L4A055w uvnPpF4boarscMi9KAeaUPd9JT8cYylmxuspQto/uNb2An2SnfVyfuVJlaXTYHcq2m zq6tw/LF7a2Kw== From: Drew Fustini Date: Mon, 01 Jun 2026 13:36:07 -0700 Subject: [PATCH RFC v6 13/18] riscv_cbqri: resctrl: Add MB_MIN bandwidth allocation via Rbwb Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-13-baf00f50028a@kernel.org> References: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-0-baf00f50028a@kernel.org> In-Reply-To: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-0-baf00f50028a@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , Conor Dooley , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, Gong Shuai , Gong Shuai , liu.qingtao2@zte.com.cn, Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Rob Herring , Conor Dooley , Krzysztof Kozlowski , "Rafael J. Wysocki" , Len Brown , Robert Moore , Sunil V L , Drew Fustini , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Sebastian Andrzej Siewior , Clark Williams , Steven Rostedt , Jonathan Corbet Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org, linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, devicetree@vger.kernel.org, Paul Walmsley , Conor Dooley , linux-rt-devel@lists.linux.dev, linux-doc@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=10711; i=fustini@kernel.org; h=from:subject:message-id; bh=Vd7FTyDoPXSVqpeMVe2i7AEgBBOuyeoGDUMVwp3ktKw=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTJvnU5L5HfsEcxU1GNr8+E+cW9J1Ic4bk797ZskwiV/ S1ytNiio5SFQYyLQVZMkWXTh7wLS7xCvy6Y/2IbzBxWJpAhDFycAjCRC2GMDFO77h96sIupt3OO aNO55/OfnZl7esn7mR3ezBJXeh9KcRxgZPgWZ/n3dlPtBkEnX9u/2ZK/ovoknEpy9ka9MfiroOr 5jhkA X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Add bandwidth allocation through Rbwb (reserved bandwidth blocks) exposed as the MB_MIN resource. Rbwb's sum constraint does not fit MBA's percentage cap, so MB_MIN lands as a new RDT_RESOURCE_* rather than masquerading as MBA. The sum(Rbwb) <=3D MRBWB (max resv bw blocks) invariant from the CBQRI spec is enforced at schemata-write time using a per-RCID software cache under ctrl->lock. -EINVAL on overflow, matching the existing schemata-write rejection convention. Reset gives RCID 0 the remaining MRBWB budget after reserving 1 block per other RCID. default_to_min=3Dtrue on MB_MIN so mkdir cannot overflow the sum constraint. Assisted-by: Claude:claude-opus-4-7 Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- drivers/resctrl/cbqri_resctrl.c | 219 ++++++++++++++++++++++++++++++++++++= ---- 1 file changed, 197 insertions(+), 22 deletions(-) diff --git a/drivers/resctrl/cbqri_resctrl.c b/drivers/resctrl/cbqri_resctr= l.c index f379058b0114..1d312004b07d 100644 --- a/drivers/resctrl/cbqri_resctrl.c +++ b/drivers/resctrl/cbqri_resctrl.c @@ -363,6 +363,9 @@ int resctrl_arch_update_one(struct rdt_resource *r, str= uct rdt_ctrl_domain *d, case RDT_RESOURCE_L2: case RDT_RESOURCE_L3: return cbqri_apply_cache_config_dom(dom, r, closid, t, cfg_val); + case RDT_RESOURCE_MB_MIN: + /* sum(Rbwb) <=3D MRBWB validation runs inside cbqri_apply_rbwb(). */ + return cbqri_apply_rbwb(dom->hw_ctrl, closid, cfg_val, true); default: return -EINVAL; } @@ -415,6 +418,14 @@ u32 resctrl_arch_get_config(struct rdt_resource *r, st= ruct rdt_ctrl_domain *d, if (err < 0) val =3D resctrl_get_default_ctrl(r); break; + case RDT_RESOURCE_MB_MIN: { + u64 rbwb; + + err =3D cbqri_read_rbwb(ctrl, closid, &rbwb); + if (err =3D=3D 0) + val =3D (u32)rbwb; + break; + } default: break; } @@ -422,9 +433,22 @@ u32 resctrl_arch_get_config(struct rdt_resource *r, st= ruct rdt_ctrl_domain *d, return val; } =20 +/* + * RCID 0 carries the remaining MRBWB after every other RCID is seeded with + * the minimum Rbwb of 1. cbqri_probe_bc() rejects a bandwidth controller + * with mrbwb < rcid_count, so this subtraction cannot underflow. + */ +static u64 cbqri_rcid0_rbwb(struct cbqri_controller *ctrl) +{ + if (WARN_ON_ONCE(ctrl->bc.mrbwb < ctrl->rcid_count)) + return 1; + return ctrl->bc.mrbwb - (ctrl->rcid_count - 1); +} + void resctrl_arch_reset_all_ctrls(struct rdt_resource *r) { struct cbqri_resctrl_res *hw_res; + struct cbqri_resctrl_dom *dom; struct rdt_ctrl_domain *d; enum resctrl_conf_type t; u32 default_ctrl; @@ -439,15 +463,41 @@ void resctrl_arch_reset_all_ctrls(struct rdt_resource= *r) return; =20 list_for_each_entry(d, &r->ctrl_domains, hdr.list) { - for (i =3D 0; i < hw_res->ctrl->rcid_count; i++) { - for (t =3D 0; t < CDP_NUM_TYPES; t++) { + dom =3D container_of(d, struct cbqri_resctrl_dom, + resctrl_ctrl_dom); + + switch (r->rid) { + case RDT_RESOURCE_MB_MIN: + /* + * CBQRI section 4.5: Rbwb >=3D 1, sum(Rbwb) <=3D MRBWB. + * Walk N-1..1 first so RCID 0 lands last with the + * remaining budget. + */ + for (i =3D 0; i < hw_res->ctrl->rcid_count; i++) { + u32 rcid =3D (i + 1) % hw_res->ctrl->rcid_count; + u64 rbwb =3D (rcid =3D=3D 0) ? + cbqri_rcid0_rbwb(dom->hw_ctrl) : 1; int rerr; =20 - rerr =3D resctrl_arch_update_one(r, d, i, t, default_ctrl); + rerr =3D cbqri_apply_rbwb(dom->hw_ctrl, rcid, rbwb, false); if (rerr) - pr_err_ratelimited("rid=3D%d reset RCID %u type %u failed (%d)\n", - r->rid, i, t, rerr); + pr_err_ratelimited("RBWB reset RCID %u failed (%d)\n", + rcid, rerr); + } + break; + default: + for (i =3D 0; i < hw_res->ctrl->rcid_count; i++) { + for (t =3D 0; t < CDP_NUM_TYPES; t++) { + int rerr; + + rerr =3D resctrl_arch_update_one(r, d, i, t, + default_ctrl); + if (rerr) + pr_err_ratelimited("rid=3D%d reset RCID %u type %u failed (%d)\n", + r->rid, i, t, rerr); + } } + break; } } } @@ -472,26 +522,51 @@ static struct rdt_ctrl_domain *cbqri_new_domain(struc= t cbqri_controller *ctrl) static int cbqri_init_domain_ctrlval(struct rdt_resource *r, struct rdt_ct= rl_domain *d) { struct cbqri_resctrl_res *hw_res; + struct cbqri_resctrl_dom *dom; enum resctrl_conf_type t; int err =3D 0; + u64 rbwb; int i; =20 hw_res =3D container_of(r, struct cbqri_resctrl_res, resctrl_res); + dom =3D container_of(d, struct cbqri_resctrl_dom, resctrl_ctrl_dom); =20 for (i =3D 0; i < hw_res->ctrl->rcid_count; i++) { /* - * Seed both DATA and CODE staged slots so a later mount - * with -o cdp does not see stale CODE values. - * On non-AT controllers cbqri_cc_alloc_op() masks AT to 0 - * so all three iterations land on the same hardware state. - * The redundant writes are harmless. + * For MB_MIN walk, RCIDs 1..N-1 then RCID 0 last so the sum + * doesn't exceed MRBWB during the walk. */ - for (t =3D 0; t < CDP_NUM_TYPES; t++) { - err =3D resctrl_arch_update_one(r, d, i, t, - resctrl_get_default_ctrl(r)); - if (err) - return err; + u32 rcid =3D (r->rid =3D=3D RDT_RESOURCE_MB_MIN) ? + ((i + 1) % hw_res->ctrl->rcid_count) : i; + + switch (r->rid) { + case RDT_RESOURCE_MB_MIN: + /* + * CBQRI section 4.5: Rbwb >=3D 1, sum(Rbwb) <=3D MRBWB. + * RCID 0 takes the remaining budget. + */ + rbwb =3D (rcid =3D=3D 0) ? cbqri_rcid0_rbwb(dom->hw_ctrl) : 1; + + err =3D cbqri_apply_rbwb(dom->hw_ctrl, rcid, rbwb, false); + break; + default: + /* + * Seed both DATA and CODE staged slots so a later + * mount with -o cdp does not see stale CODE values. + * On non-AT controllers cbqri_cc_alloc_op() masks + * AT to 0, so all three iterations land on the same + * hardware state. The redundant writes are harmless. + */ + for (t =3D 0; t < CDP_NUM_TYPES; t++) { + err =3D resctrl_arch_update_one(r, d, i, t, + resctrl_get_default_ctrl(r)); + if (err) + break; + } + break; } + if (err) + return err; } return 0; } @@ -590,6 +665,31 @@ static int cbqri_resctrl_control_init(struct cbqri_res= ctrl_res *cbqri_res) res->mon_capable =3D true; } break; + + case RDT_RESOURCE_MB_MIN: + res->name =3D "MB_MIN"; + res->schema_fmt =3D RESCTRL_SCHEMA_RANGE; + /* + * resctrl requires a cache scope for MBA-style domains. + * Use L3 as a proxy until the resctrl supports non-cache + * scopes for bandwidth resources. + */ + res->ctrl_scope =3D RESCTRL_L3_CACHE; + /* Rbwb is an integer block count, not a percentage. No MBA delay_linear= . */ + res->membw.throttle_mode =3D THREAD_THROTTLE_UNDEFINED; + res->membw.min_bw =3D 1; + res->membw.max_bw =3D ctrl->bc.mrbwb; + res->membw.bw_gran =3D 1; + /* + * CBQRI section 4.5 caps sum(Rbwb) <=3D MRBWB. Default new + * groups to min_bw so mkdir cannot overflow that sum. + */ + res->membw.default_to_min =3D true; + res->alloc_capable =3D ctrl->alloc_capable; + INIT_LIST_HEAD(&res->ctrl_domains); + INIT_LIST_HEAD(&res->mon_domains); + break; + default: break; } @@ -597,6 +697,36 @@ static int cbqri_resctrl_control_init(struct cbqri_res= ctrl_res *cbqri_res) return 0; } =20 +/* + * Pick one BC to back MB_MIN. Multiple BCs must agree on rcid_count + * and mrbwb. Mismatch is fatal because resctrl exposes a single set + * of caps per rid. + */ +static int cbqri_resctrl_pick_bw_alloc(void) +{ + struct cbqri_resctrl_res *mb_min =3D &cbqri_resctrl_resources[RDT_RESOURC= E_MB_MIN]; + struct cbqri_controller *ctrl; + + list_for_each_entry(ctrl, &cbqri_controllers, list) { + if (ctrl->type !=3D CBQRI_CONTROLLER_TYPE_BANDWIDTH) + continue; + if (!ctrl->alloc_capable) + continue; + + if (mb_min->ctrl) { + if (mb_min->ctrl->rcid_count !=3D ctrl->rcid_count || + mb_min->ctrl->bc.mrbwb !=3D ctrl->bc.mrbwb) { + pr_err("BW controllers have mismatched capabilities\n"); + return -EINVAL; + } + continue; + } + + mb_min->ctrl =3D ctrl; + } + + return 0; +} static void cbqri_resctrl_accumulate_caps(void) { struct cbqri_controller *l3_ctrl; @@ -806,6 +936,37 @@ static int cbqri_attach_cpu_to_cap_ctrl(struct cbqri_c= ontroller *ctrl, return err; } =20 +static int cbqri_attach_cpu_to_one_bw_res(struct cbqri_controller *ctrl, + enum resctrl_res_level rid, + unsigned int cpu) +{ + struct cbqri_resctrl_res *hw_res =3D &cbqri_resctrl_resources[rid]; + struct rdt_resource *res =3D &hw_res->resctrl_res; + struct rdt_ctrl_domain *domain; + int dom_id =3D ctrl->mem.prox_dom; + + if (!hw_res->ctrl) + return 0; + + domain =3D cbqri_find_ctrl_domain(&res->ctrl_domains, dom_id); + if (domain) { + cpumask_set_cpu(cpu, &domain->hdr.cpu_mask); + return 0; + } + + domain =3D cbqri_create_ctrl_domain(ctrl, res, cpu, dom_id); + if (IS_ERR(domain)) + return PTR_ERR(domain); + + return 0; +} + +static int cbqri_attach_cpu_to_bw_ctrl(struct cbqri_controller *ctrl, + unsigned int cpu) +{ + return cbqri_attach_cpu_to_one_bw_res(ctrl, RDT_RESOURCE_MB_MIN, cpu); +} + static void cbqri_detach_cpu_from_l3_mon(struct rdt_resource *res, unsigned int cpu) { @@ -893,14 +1054,24 @@ static int cbqri_attach_cpu_to_all_ctrls(unsigned in= t cpu) lockdep_assert_held(&cbqri_domain_list_lock); =20 list_for_each_entry(ctrl, &cbqri_controllers, list) { - if (ctrl->type !=3D CBQRI_CONTROLLER_TYPE_CAPACITY) - continue; - if (!cpumask_test_cpu(cpu, &ctrl->cache.cpu_mask)) - continue; - if (!ctrl->alloc_capable) + switch (ctrl->type) { + case CBQRI_CONTROLLER_TYPE_CAPACITY: + if (!cpumask_test_cpu(cpu, &ctrl->cache.cpu_mask)) + continue; + if (!ctrl->alloc_capable) + continue; + err =3D cbqri_attach_cpu_to_cap_ctrl(ctrl, cpu); + break; + case CBQRI_CONTROLLER_TYPE_BANDWIDTH: + if (!cpumask_test_cpu(cpu, &ctrl->mem.cpu_mask)) + continue; + if (!ctrl->alloc_capable) + continue; + err =3D cbqri_attach_cpu_to_bw_ctrl(ctrl, cpu); + break; + default: continue; - - err =3D cbqri_attach_cpu_to_cap_ctrl(ctrl, cpu); + } if (err) { cbqri_detach_cpu_from_all_ctrls(cpu); break; @@ -945,6 +1116,10 @@ static int cbqri_resctrl_setup(void) if (err) return err; =20 + err =3D cbqri_resctrl_pick_bw_alloc(); + if (err) + return err; + for (rid =3D 0; rid < RDT_NUM_RESOURCES; rid++) { err =3D cbqri_resctrl_control_init(&cbqri_resctrl_resources[rid]); if (err) --=20 2.43.0 From nobody Mon Jun 8 05:29:11 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 915F13FD133; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-14-baf00f50028a@kernel.org> References: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-0-baf00f50028a@kernel.org> In-Reply-To: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-0-baf00f50028a@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , Conor Dooley , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, Gong Shuai , Gong Shuai , liu.qingtao2@zte.com.cn, Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Rob Herring , Conor Dooley , Krzysztof Kozlowski , "Rafael J. Wysocki" , Len Brown , Robert Moore , Sunil V L , Drew Fustini , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Sebastian Andrzej Siewior , Clark Williams , Steven Rostedt , Jonathan Corbet Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org, linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, devicetree@vger.kernel.org, Paul Walmsley , Conor Dooley , linux-rt-devel@lists.linux.dev, linux-doc@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=6210; i=fustini@kernel.org; h=from:subject:message-id; bh=iGmU2buwnXjB4e9q+wmO+AF3FTtZ91gPnMFZh5ljUS0=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTJvnW50enmE3yv+UTkya5LOWs2Rr7ms52wX4BrVonbL mbfX/YGHaUsDGJcDLJiiiybPuRdWOIV+nXB/BfbYOawMoEMYeDiFICJvMtmZLhWs2Yq24KJN3VO Pi1Niz1Q25++Qipzj4RXYjZ30evtk94x/M9dLejvIOH94A5T2MYpNfG18wt0a85xfV749m67ovU RAUYA X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Add bandwidth allocation through Mweight (shared weight for unreserved bandwidth) exposed as the MB_WGHT resource. Mweight has no MBA equivalent, so it lands as a new RDT_RESOURCE_*. Mweight is an integer in [0, 255]. A value of 0 disables work- conserving sharing for the group, capping its bandwidth at the MB_MIN reservation. Values 1..255 compete for the leftover pool in proportion to the weight. The same BC backs both MB_MIN and MB_WGHT and bc_bw_alloc packs Rbwb and Mweight in one register. cbqri_attach_cpu_to_bw_ctrl() attaches both rids to the picked BC. Reset gives every RCID the new-group default (max_bw =3D 255) for equal opportunistic shares. Assisted-by: Claude:claude-opus-4-7 Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- drivers/resctrl/cbqri_resctrl.c | 90 +++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 86 insertions(+), 4 deletions(-) diff --git a/drivers/resctrl/cbqri_resctrl.c b/drivers/resctrl/cbqri_resctr= l.c index 1d312004b07d..14b955eb7949 100644 --- a/drivers/resctrl/cbqri_resctrl.c +++ b/drivers/resctrl/cbqri_resctrl.c @@ -366,6 +366,8 @@ int resctrl_arch_update_one(struct rdt_resource *r, str= uct rdt_ctrl_domain *d, case RDT_RESOURCE_MB_MIN: /* sum(Rbwb) <=3D MRBWB validation runs inside cbqri_apply_rbwb(). */ return cbqri_apply_rbwb(dom->hw_ctrl, closid, cfg_val, true); + case RDT_RESOURCE_MB_WGHT: + return cbqri_apply_mweight_config(dom->hw_ctrl, closid, cfg_val); default: return -EINVAL; } @@ -426,6 +428,14 @@ u32 resctrl_arch_get_config(struct rdt_resource *r, st= ruct rdt_ctrl_domain *d, val =3D (u32)rbwb; break; } + case RDT_RESOURCE_MB_WGHT: { + u64 mweight; + + err =3D cbqri_read_mweight(ctrl, closid, &mweight); + if (err =3D=3D 0) + val =3D (u32)mweight; + break; + } default: break; } @@ -485,6 +495,18 @@ void resctrl_arch_reset_all_ctrls(struct rdt_resource = *r) rcid, rerr); } break; + case RDT_RESOURCE_MB_WGHT: + /* All RCIDs start at max weight (the new-group default). */ + for (i =3D 0; i < hw_res->ctrl->rcid_count; i++) { + int rerr; + + rerr =3D cbqri_apply_mweight_config(dom->hw_ctrl, i, + default_ctrl); + if (rerr) + pr_err_ratelimited("Mweight reset RCID %u failed (%d)\n", + i, rerr); + } + break; default: for (i =3D 0; i < hw_res->ctrl->rcid_count; i++) { for (t =3D 0; t < CDP_NUM_TYPES; t++) { @@ -549,6 +571,11 @@ static int cbqri_init_domain_ctrlval(struct rdt_resour= ce *r, struct rdt_ctrl_dom =20 err =3D cbqri_apply_rbwb(dom->hw_ctrl, rcid, rbwb, false); break; + case RDT_RESOURCE_MB_WGHT: + /* Match the new-group default: equal weights across RCIDs. */ + err =3D cbqri_apply_mweight_config(dom->hw_ctrl, i, + resctrl_get_default_ctrl(r)); + break; default: /* * Seed both DATA and CODE staged slots so a later @@ -690,6 +717,25 @@ static int cbqri_resctrl_control_init(struct cbqri_res= ctrl_res *cbqri_res) INIT_LIST_HEAD(&res->mon_domains); break; =20 + case RDT_RESOURCE_MB_WGHT: + res->name =3D "MB_WGHT"; + res->schema_fmt =3D RESCTRL_SCHEMA_RANGE; + res->ctrl_scope =3D RESCTRL_L3_CACHE; + /* Mweight is a dimensionless ratio. No delay/linear concept. */ + res->membw.throttle_mode =3D THREAD_THROTTLE_UNDEFINED; + /* + * CBQRI section 4.5: Mweight is 0-255 (0 disables + * work-conserving). No sum constraint, so leave + * default_to_min false. Groups default to max_bw. + */ + res->membw.min_bw =3D 0; + res->membw.max_bw =3D 255; + res->membw.bw_gran =3D 1; + res->alloc_capable =3D ctrl->alloc_capable; + INIT_LIST_HEAD(&res->ctrl_domains); + INIT_LIST_HEAD(&res->mon_domains); + break; + default: break; } @@ -698,13 +744,12 @@ static int cbqri_resctrl_control_init(struct cbqri_re= sctrl_res *cbqri_res) } =20 /* - * Pick one BC to back MB_MIN. Multiple BCs must agree on rcid_count - * and mrbwb. Mismatch is fatal because resctrl exposes a single set - * of caps per rid. + * Pick one BC to back both MB_MIN and MB_WGHT. */ static int cbqri_resctrl_pick_bw_alloc(void) { struct cbqri_resctrl_res *mb_min =3D &cbqri_resctrl_resources[RDT_RESOURC= E_MB_MIN]; + struct cbqri_resctrl_res *mb_wght =3D &cbqri_resctrl_resources[RDT_RESOUR= CE_MB_WGHT]; struct cbqri_controller *ctrl; =20 list_for_each_entry(ctrl, &cbqri_controllers, list) { @@ -723,6 +768,7 @@ static int cbqri_resctrl_pick_bw_alloc(void) } =20 mb_min->ctrl =3D ctrl; + mb_wght->ctrl =3D ctrl; } =20 return 0; @@ -961,10 +1007,46 @@ static int cbqri_attach_cpu_to_one_bw_res(struct cbq= ri_controller *ctrl, return 0; } =20 +static void cbqri_detach_cpu_from_one_bw_res(struct cbqri_controller *ctrl, + enum resctrl_res_level rid, + unsigned int cpu) +{ + struct cbqri_resctrl_res *hw_res =3D &cbqri_resctrl_resources[rid]; + struct rdt_resource *res =3D &hw_res->resctrl_res; + struct rdt_ctrl_domain *domain; + int dom_id =3D ctrl->mem.prox_dom; + + lockdep_assert_held(&cbqri_domain_list_lock); + + if (!hw_res->ctrl) + return; + + domain =3D cbqri_find_ctrl_domain(&res->ctrl_domains, dom_id); + if (!domain || !cpumask_test_cpu(cpu, &domain->hdr.cpu_mask)) + return; + + cpumask_clear_cpu(cpu, &domain->hdr.cpu_mask); + if (cpumask_empty(&domain->hdr.cpu_mask)) { + resctrl_offline_ctrl_domain(res, domain); + list_del(&domain->hdr.list); + kfree(container_of(domain, struct cbqri_resctrl_dom, + resctrl_ctrl_dom)); + } +} + static int cbqri_attach_cpu_to_bw_ctrl(struct cbqri_controller *ctrl, unsigned int cpu) { - return cbqri_attach_cpu_to_one_bw_res(ctrl, RDT_RESOURCE_MB_MIN, cpu); + int err; + + err =3D cbqri_attach_cpu_to_one_bw_res(ctrl, RDT_RESOURCE_MB_MIN, cpu); + if (err) + return err; + + err =3D cbqri_attach_cpu_to_one_bw_res(ctrl, RDT_RESOURCE_MB_WGHT, cpu); + if (err) + cbqri_detach_cpu_from_one_bw_res(ctrl, RDT_RESOURCE_MB_MIN, cpu); + return err; } =20 static void cbqri_detach_cpu_from_l3_mon(struct rdt_resource *res, --=20 2.43.0 From nobody Mon Jun 8 05:29:11 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 995C43FCB2F; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-15-baf00f50028a@kernel.org> References: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-0-baf00f50028a@kernel.org> In-Reply-To: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-0-baf00f50028a@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , Conor Dooley , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, Gong Shuai , Gong Shuai , liu.qingtao2@zte.com.cn, Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Rob Herring , Conor Dooley , Krzysztof Kozlowski , "Rafael J. Wysocki" , Len Brown , Robert Moore , Sunil V L , Drew Fustini , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Sebastian Andrzej Siewior , Clark Williams , Steven Rostedt , Jonathan Corbet Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org, linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, devicetree@vger.kernel.org, Paul Walmsley , Conor Dooley , linux-rt-devel@lists.linux.dev, linux-doc@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=10593; i=fustini@kernel.org; h=from:subject:message-id; bh=Y0XxVCH1oI0OHqCclMlaz+iRYbQWNxAWz1RLz5vRgmM=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTJvnUxLlNyk3yxZpPxml/yx8+kb1OfyOe+M+ZrN+M5w ekdemv9O0pZGMS4GGTFFFk2fci7sMQr9OuC+S+2wcxhZQIZwsDFKQATsTJk+F8/+eC856k3FwtO /FNenFK9RqA3QclHa/98hoTG1/wdE5cy/C8qstudYNpe0t10zv4QX0xnzLLAtFK35a8OCYtFPM7 8wAMA X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Expose CBQRI bandwidth controller's combined read+write counter as the L3 mbm_total_bytes event. A software accumulator keeps the 64-bit byte total monotonic across the 62-bit hardware counter wrap. mbm_local_bytes is not supported because the CBQRI spec has no way to distinguish total versus local. mbm_total_bytes is enabled only when the platform exposes exactly one mon-capable bandwidth controller and exactly one L3 domain. Pairing a single BC with multiple L3 domains would let standard userspace tools overcount system bandwidth by summing the same counter across domains. Assisted-by: Claude:claude-opus-4-7 Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- drivers/resctrl/cbqri_resctrl.c | 232 ++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 228 insertions(+), 4 deletions(-) diff --git a/drivers/resctrl/cbqri_resctrl.c b/drivers/resctrl/cbqri_resctr= l.c index 14b955eb7949..efd75d241122 100644 --- a/drivers/resctrl/cbqri_resctrl.c +++ b/drivers/resctrl/cbqri_resctrl.c @@ -29,6 +29,13 @@ struct cbqri_resctrl_res { struct cbqri_resctrl_dom { struct rdt_ctrl_domain resctrl_ctrl_dom; struct cbqri_controller *hw_ctrl; + /* + * For an L3 capacity controller paired with a bandwidth controller + * of matching topology, paired_bc caches that BC so mbm_total_bytes + * reads / resets don't have to walk cbqri_controllers on every hit. + * NULL for non-L3 domains and L3s without a paired BC. + */ + struct cbqri_controller *paired_bc; }; =20 static struct cbqri_resctrl_res cbqri_resctrl_resources[RDT_NUM_RESOURCES]; @@ -184,17 +191,67 @@ void resctrl_arch_mon_event_config_write(void *info) void resctrl_arch_reset_rmid(struct rdt_resource *r, struct rdt_l3_mon_dom= ain *d, u32 unused, u32 rmid, enum resctrl_event_id eventid) { + struct cbqri_resctrl_dom *hw_dom; + struct rdt_ctrl_domain *cd; + + if (irqs_disabled()) + return; + + mutex_lock(&cbqri_domain_list_lock); + /* * Occupancy MCIDs are armed once by cbqri_init_mon_counters() and - * free run thereafter. The core only reads occupancy on the limbo - * recycle path, never resets it, so there is no per-rmid software - * state to clear here. + * free run thereafter, so only mbm_total_bytes needs a per-rmid reset. */ + switch (eventid) { + case QOS_L3_MBM_TOTAL_EVENT_ID: { + struct cbqri_controller *bc; + + cd =3D cbqri_find_ctrl_domain(&r->ctrl_domains, d->hdr.id); + if (!cd) + break; + hw_dom =3D container_of(cd, struct cbqri_resctrl_dom, resctrl_ctrl_dom); + bc =3D hw_dom->paired_bc; + if (!bc) + break; + if (WARN_ON_ONCE(!bc->mbm_total_states)) + break; + if (rmid >=3D bc->mcid_count) + break; + + mutex_lock(&bc->lock); + /* + * CONFIG_EVENT both resets and re-arms. Skip the accumulator + * memset on failure. A stale hardware counter X with + * prev_ctr=3D0 would inject overflow(0, X) on the next read. + */ + if (!cbqri_mon_op(bc, CBQRI_BC_MON_CTL_OFF, + CBQRI_BC_MON_CTL_OP_CONFIG_EVENT, rmid, + CBQRI_BC_EVT_ID_TOTAL_READ_WRITE, NULL)) + memset(&bc->mbm_total_states[rmid], 0, + sizeof(*bc->mbm_total_states)); + mutex_unlock(&bc->lock); + break; + } + + default: + break; + } + + mutex_unlock(&cbqri_domain_list_lock); } =20 void resctrl_arch_reset_rmid_all(struct rdt_resource *r, struct rdt_l3_mon= _domain *d) { - /* Occupancy counters free run, so there is no state to reset. */ + int i; + + /* + * Occupancy counters free run and need no reset; only the + * mbm_total_bytes accumulators are cleared. Bound by max_rmid + * (system-wide minimum mcid_count). + */ + for (i =3D 0; i < max_rmid; i++) + resctrl_arch_reset_rmid(r, d, 0, i, QOS_L3_MBM_TOTAL_EVENT_ID); } =20 int resctrl_arch_rmid_read(struct rdt_resource *r, struct rdt_domain_hdr *= hdr, @@ -257,6 +314,82 @@ int resctrl_arch_rmid_read(struct rdt_resource *r, str= uct rdt_domain_hdr *hdr, mutex_unlock(&ctrl->lock); break; =20 + case QOS_L3_MBM_TOTAL_EVENT_ID: { + struct cbqri_controller *bc; + + /* + * The L3 monitoring domain's id is the L3 cache id. The + * matching ctrl domain's hw_dom->paired_bc was cached at + * add time to avoid walking cbqri_controllers on every read. + */ + d =3D cbqri_find_ctrl_domain(&r->ctrl_domains, hdr->id); + if (!d) { + err =3D -ENOENT; + break; + } + hw_dom =3D container_of(d, struct cbqri_resctrl_dom, resctrl_ctrl_dom); + bc =3D hw_dom->paired_bc; + if (!bc) { + err =3D -ENOENT; + break; + } + if (WARN_ON_ONCE(!bc->mbm_total_states)) { + err =3D -EIO; + break; + } + if (rmid >=3D bc->mcid_count) { + err =3D -ERANGE; + break; + } + + mutex_lock(&bc->lock); + /* Pass EVT_ID explicitly. Same reason as the CC path above. */ + err =3D cbqri_mon_op(bc, CBQRI_BC_MON_CTL_OFF, + CBQRI_BC_MON_CTL_OP_READ_COUNTER, rmid, + CBQRI_BC_EVT_ID_TOTAL_READ_WRITE, NULL); + if (err) + goto out_bc; + + ctr_val =3D ioread64(bc->base + CBQRI_BC_MON_CTR_VAL_OFF); + + if (ctr_val & CBQRI_BC_MON_CTR_VAL_INVALID) { + /* + * Return the last good total and leave prev_ctr so + * the next valid sample resumes from there. + */ + *val =3D bc->mbm_total_states[rmid].chunks; + } else if (ctr_val & CBQRI_BC_MON_CTR_VAL_OVF) { + /* + * OVF is sticky until next CONFIG_EVENT. + * cbqri_bc_mon_overflow() can recover at most + * one wrap. With OVF set, the count is unknown, + * so re-arm and re-anchor prev_ctr=3D0. + */ + struct cbqri_bc_mon_state *s =3D &bc->mbm_total_states[rmid]; + + pr_warn_ratelimited("BC@%pa MCID %u: bandwidth counter overflow\n", + &bc->addr, rmid); + err =3D cbqri_mon_op(bc, CBQRI_BC_MON_CTL_OFF, + CBQRI_BC_MON_CTL_OP_CONFIG_EVENT, rmid, + CBQRI_BC_EVT_ID_TOTAL_READ_WRITE, NULL); + if (err) + goto out_bc; + + s->prev_ctr =3D 0; + *val =3D s->chunks; + } else { + struct cbqri_bc_mon_state *s =3D &bc->mbm_total_states[rmid]; + u64 cur =3D ctr_val & CBQRI_BC_MON_CTR_VAL_CTR_MASK; + + s->chunks +=3D cbqri_bc_mon_overflow(s->prev_ctr, cur); + s->prev_ctr =3D cur; + *val =3D s->chunks; + } +out_bc: + mutex_unlock(&bc->lock); + break; + } + default: err =3D -EINVAL; break; @@ -773,6 +906,61 @@ static int cbqri_resctrl_pick_bw_alloc(void) =20 return 0; } + +/* + * Enable mbm_total_bytes when the system exposes exactly one mon-capable + * bandwidth controller and exactly one L3 cache. Pairing a single BC with + * multiple L3 domains would let userspace overcount system bandwidth by a + * factor equal to the L3 domain count. resctrl_is_mon_event_enabled() then + * gates the BC pairing and rmid-space accounting. L3 occupancy is enabled + * by cbqri_resctrl_control_init(). + */ +static void cbqri_resctrl_pick_counters(void) +{ + struct cbqri_resctrl_res *l3 =3D &cbqri_resctrl_resources[RDT_RESOURCE_L3= ]; + struct cbqri_controller *ctrl, *prev; + unsigned int l3_count =3D 0; + + /* Count distinct L3 cache_ids */ + list_for_each_entry(ctrl, &cbqri_controllers, list) { + bool seen =3D false; + + if (ctrl->type !=3D CBQRI_CONTROLLER_TYPE_CAPACITY) + continue; + if (ctrl->cache.cache_level !=3D 3) + continue; + + list_for_each_entry(prev, &cbqri_controllers, list) { + if (prev =3D=3D ctrl) + break; + if (prev->type !=3D CBQRI_CONTROLLER_TYPE_CAPACITY) + continue; + if (prev->cache.cache_level !=3D 3) + continue; + if (prev->cache.cache_id =3D=3D ctrl->cache.cache_id) { + seen =3D true; + break; + } + } + if (!seen) + l3_count++; + } + + if (l3_count > 1) { + pr_warn_once("multiple L3 domains (%u) detected. mbm_total_bytes disable= d\n", + l3_count); + return; + } + + /* + * mbm_total_bytes is surfaced on the L3 monitoring domain, so it + * needs a mon-capable L3 cache controller as well as a single + * mon-capable bandwidth controller. + */ + if (l3->ctrl && l3->ctrl->mon_capable && cbqri_find_only_mon_bc()) + resctrl_enable_mon_event(QOS_L3_MBM_TOTAL_EVENT_ID, false, 0, NULL); +} + static void cbqri_resctrl_accumulate_caps(void) { struct cbqri_controller *l3_ctrl; @@ -798,6 +986,18 @@ static void cbqri_resctrl_accumulate_caps(void) if (l3_ctrl && l3_ctrl->mon_capable) max_rmid =3D min(max_rmid, l3_ctrl->mcid_count); =20 + /* + * When mbm_total_bytes is enabled, the paired BC is a second counter + * source, so clamp against its mcid_count too. A BC left unpicked + * because mbm_total_bytes is disabled must not clamp it. + */ + if (resctrl_is_mon_event_enabled(QOS_L3_MBM_TOTAL_EVENT_ID)) { + struct cbqri_controller *bc =3D cbqri_find_only_mon_bc(); + + if (bc) + max_rmid =3D min(max_rmid, bc->mcid_count); + } + if (!exposed_mon_capable) { max_rmid =3D 1; return; @@ -854,6 +1054,7 @@ static int cbqri_attach_cpu_to_l3_mon(struct cbqri_con= troller *ctrl, { struct rdt_l3_mon_domain *mon_dom; struct rdt_ctrl_domain *ctrl_dom; + struct cbqri_resctrl_dom *hw_dom; struct list_head *mon_pos =3D NULL; int dom_id =3D ctrl->cache.cache_id; int err; @@ -893,6 +1094,27 @@ static int cbqri_attach_cpu_to_l3_mon(struct cbqri_co= ntroller *ctrl, else list_add_tail(&mon_dom->hdr.list, &res->mon_domains); =20 + /* + * Pair this L3 domain with the system's mon-capable BC and + * initialise the BC's per-MCID software accumulators before + * resctrl_online_mon_domain() exposes the domain to userspace. + * A concurrent sysfs read of mbm_total_bytes between online and + * BC init would otherwise pass the !bc->mbm_total_states check + * with a half-initialised pointer. + */ + hw_dom =3D container_of(ctrl_dom, struct cbqri_resctrl_dom, resctrl_ctrl_= dom); + + if (resctrl_is_mon_event_enabled(QOS_L3_MBM_TOTAL_EVENT_ID)) + hw_dom->paired_bc =3D cbqri_find_only_mon_bc(); + if (hw_dom->paired_bc) { + err =3D cbqri_init_bc_mon_counters(hw_dom->paired_bc); + if (err) { + pr_err("BC @%pa: mon init failed (%d)\n", &hw_dom->paired_bc->addr, err= ); + hw_dom->paired_bc =3D NULL; + goto err_listdel; + } + } + err =3D resctrl_online_mon_domain(res, &mon_dom->hdr); if (err) goto err_listdel; @@ -1202,6 +1424,8 @@ static int cbqri_resctrl_setup(void) if (err) return err; =20 + cbqri_resctrl_pick_counters(); + for (rid =3D 0; rid < RDT_NUM_RESOURCES; rid++) { err =3D cbqri_resctrl_control_init(&cbqri_resctrl_resources[rid]); if (err) --=20 2.43.0 From nobody Mon Jun 8 05:29:11 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7002A3FE66C; Mon, 1 Jun 2026 20:36:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 1 Jun 2026 20:36:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1780346196; bh=mTwwl+ig+fjJ0sELrhOzw5k5khRQRR/9+wVPF6kCj4I=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=gJTT7vLPU4zZnX8MnBUpUg7DnP8Gw3cbMJA/yE9dAjwRlgBvq6fIxvTWOLUmoQzSx mEYqGmHv9Ii9kpr8q1DlXWgt9ahqj1iAmvNL0/Dc2CC6bGxcdKAXj1IbW9iWFS0DCn rcxCSOik56cE65ESRwMV1JX2/eEMDnNkEejAfbYcWtNKWTdAH1X4WZ1V92fIIvqVj9 +d1k1PDuEHyEsKwqiwdDbXp68/ZqY0b2KEbWc10ZITb3NV2NB7mcbDR3ZTv40hdvau t3p0iy/I+oWJmqVJlmeg7E/I6n7OdTZRMOtuRwBMe3PksLYVR4ttTJdLQtCx2arVs6 mlQ1/jq0wlsVg== From: Drew Fustini Date: Mon, 01 Jun 2026 13:36:10 -0700 Subject: [PATCH RFC v6 16/18] ACPI: RISC-V: Parse RISC-V Quality of Service Controller (RQSC) table Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-16-baf00f50028a@kernel.org> References: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-0-baf00f50028a@kernel.org> In-Reply-To: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-0-baf00f50028a@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , Conor Dooley , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, Gong Shuai , Gong Shuai , liu.qingtao2@zte.com.cn, Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Rob Herring , Conor Dooley , Krzysztof Kozlowski , "Rafael J. Wysocki" , Len Brown , Robert Moore , Sunil V L , Drew Fustini , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Sebastian Andrzej Siewior , Clark Williams , Steven Rostedt , Jonathan Corbet Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org, linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, devicetree@vger.kernel.org, Paul Walmsley , Conor Dooley , linux-rt-devel@lists.linux.dev, linux-doc@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=11871; i=fustini@kernel.org; h=from:subject:message-id; bh=wQO5+pAF5VjZ/zebqBozq+z2BXVrC/YcBMlOHb+h3/g=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTJvnVZI3Fk5W15+e4SMR5ZeX6P13FLDSJXMJj/XLI9Z 9LrtCrmjlIWBjEuBlkxRZZNH/IuLPEK/bpg/ottMHNYmUCGMHBxCsBEXuYy/JVj31r1dBnLhP8e VYt/zW89EfdxQlRvTPHm8hStvCvuD6YwMixxUCmTe/j0evMc38RHptve+SeX17x5IFU0/bjl6Ud Md7gA X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Add a parser for the ACPI RQSC table, which describes the CBQRI controllers in a system. For each table entry, populate a cbqri_controller_info descriptor and hand it to the CBQRI driver via riscv_cbqri_register_controller(). The driver owns all subsequent state, including cpumask resolution at cbqri_resctrl_setup() time. Link: https://github.com/riscv-non-isa/riscv-rqsc/blob/main/src/ Link: https://github.com/riscv-non-isa/riscv-cbqri/releases/tag/v1.0 Assisted-by: Claude:claude-opus-4-7 Signed-off-by: Drew Fustini --- MAINTAINERS | 2 + arch/riscv/include/asm/acpi.h | 10 +++ drivers/acpi/riscv/Makefile | 1 + drivers/acpi/riscv/rqsc.c | 202 ++++++++++++++++++++++++++++++++++++++= ++++ drivers/acpi/riscv/rqsc.h | 66 ++++++++++++++ 5 files changed, 281 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 7821dd5159cb..eab31c7b5e91 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -23025,6 +23025,8 @@ S: Supported F: arch/riscv/include/asm/qos.h F: arch/riscv/include/asm/resctrl.h F: arch/riscv/kernel/qos.c +F: drivers/acpi/riscv/rqsc.c +F: drivers/acpi/riscv/rqsc.h F: drivers/resctrl/cbqri_devices.c F: drivers/resctrl/cbqri_internal.h F: drivers/resctrl/cbqri_resctrl.c diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h index 26ab37c171bc..3cfd0102085e 100644 --- a/arch/riscv/include/asm/acpi.h +++ b/arch/riscv/include/asm/acpi.h @@ -67,6 +67,16 @@ int acpi_get_riscv_isa(struct acpi_table_header *table, =20 void acpi_get_cbo_block_size(struct acpi_table_header *table, u32 *cbom_si= ze, u32 *cboz_size, u32 *cbop_size); + +#ifdef CONFIG_RISCV_CBQRI_DRIVER +int __init acpi_parse_rqsc(struct acpi_table_header *table); +#else +static inline int acpi_parse_rqsc(struct acpi_table_header *table) +{ + return -EINVAL; +} +#endif /* CONFIG_RISCV_CBQRI_DRIVER */ + #else static inline void acpi_init_rintc_map(void) { } static inline struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu) diff --git a/drivers/acpi/riscv/Makefile b/drivers/acpi/riscv/Makefile index 1284a076fa88..77f8f0101b7e 100644 --- a/drivers/acpi/riscv/Makefile +++ b/drivers/acpi/riscv/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only obj-y +=3D rhct.o init.o irq.o +obj-$(CONFIG_RISCV_CBQRI_DRIVER) +=3D rqsc.o obj-$(CONFIG_ACPI_PROCESSOR_IDLE) +=3D cpuidle.o obj-$(CONFIG_ACPI_CPPC_LIB) +=3D cppc.o obj-$(CONFIG_ACPI_RIMT) +=3D rimt.o diff --git a/drivers/acpi/riscv/rqsc.c b/drivers/acpi/riscv/rqsc.c new file mode 100644 index 000000000000..1b1ae2e353a5 --- /dev/null +++ b/drivers/acpi/riscv/rqsc.c @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#define pr_fmt(fmt) "ACPI: RQSC: " fmt + +#include +#include +#include + +#include "rqsc.h" + +#define CBQRI_CTRL_SIZE 0x1000 + +int __init acpi_parse_rqsc(struct acpi_table_header *table) +{ + struct acpi_table_rqsc *rqsc =3D (struct acpi_table_rqsc *)table; + struct acpi_rqsc_node *end, *node; + int num_controllers =3D 0; + + /* + * Reject revisions newer than this parser was written against. A + * future revision could extend the fixed RQSC header before the + * first node, which would shift the resource subtables and cause the + * sizeof(*node)-based offset below to point into the wrong place. + */ + if (rqsc->header.revision !=3D ACPI_RQSC_REVISION) { + pr_err("RQSC table revision %u, expected %u, aborting\n", + rqsc->header.revision, ACPI_RQSC_REVISION); + return -EINVAL; + } + + /* Reject tables shorter than the fixed RQSC header. */ + if (rqsc->header.length < sizeof(struct acpi_table_rqsc)) { + pr_err("RQSC table truncated: length %u < %zu, aborting\n", + rqsc->header.length, sizeof(struct acpi_table_rqsc)); + return -EINVAL; + } + + end =3D ACPI_ADD_PTR(struct acpi_rqsc_node, rqsc, rqsc->header.length); + + for (node =3D ACPI_ADD_PTR(struct acpi_rqsc_node, rqsc, + sizeof(struct acpi_table_rqsc)); + node < end; + node =3D ACPI_ADD_PTR(struct acpi_rqsc_node, node, node->length) + ) { + const struct acpi_rqsc_resource *res0; + struct cbqri_controller_info info =3D {}; + int ret; + + if ((void *)node + sizeof(*node) > (void *)end) { + pr_err("truncated entry at end of table, aborting\n"); + riscv_cbqri_unregister_last(num_controllers); + return -EINVAL; + } + + if (node->length < sizeof(*node)) { + pr_err("malformed RQSC entry: length %u < %zu, aborting\n", + node->length, sizeof(*node)); + riscv_cbqri_unregister_last(num_controllers); + return -EINVAL; + } + + /* + * Without this check, a node whose length claims to extend + * past the end of the table would advance the loop cursor + * past 'end' and silently terminate. Flag the corruption + * explicitly so a malformed firmware table cannot truncate + * the controller list without noise. + */ + if ((void *)node + node->length > (void *)end) { + pr_err("RQSC entry length %u overruns table end, aborting\n", + node->length); + riscv_cbqri_unregister_last(num_controllers); + return -EINVAL; + } + + /* GAS must describe system memory. ioremap() consumes it later. */ + if (node->reg.space_id !=3D ACPI_ADR_SPACE_SYSTEM_MEMORY) { + pr_warn("controller has unsupported address space_id=3D%u, skipping\n", + node->reg.space_id); + continue; + } + + if (!node->reg.address) { + pr_warn("controller has zero address, skipping\n"); + continue; + } + + info.type =3D node->type; + /* RQSC section 2 Table 2: 12-byte GAS-format register interface address= */ + info.addr =3D node->reg.address; + info.size =3D CBQRI_CTRL_SIZE; + info.rcid_count =3D node->rcid; + info.mcid_count =3D node->mcid; + + /* See CBQRI_MAX_RCID/MCID in for the rationale. */ + if (info.rcid_count > CBQRI_MAX_RCID) { + pr_warn("controller at %pa: rcid_count %u exceeds CBQRI_MAX_RCID %u, sk= ipping\n", + &info.addr, info.rcid_count, CBQRI_MAX_RCID); + continue; + } + + if (info.mcid_count > CBQRI_MAX_MCID) { + pr_warn("controller at %pa: mcid_count %u exceeds CBQRI_MAX_MCID %u, sk= ipping\n", + &info.addr, info.mcid_count, CBQRI_MAX_MCID); + continue; + } + + /* + * RQSC Table 2: at least one of RCID Count or MCID Count must be non-ze= ro. + */ + if (!info.rcid_count && !info.mcid_count) { + pr_warn("controller at %pa: both rcid_count and mcid_count are zero, sk= ipping\n", + &info.addr); + continue; + } + + if (node->nres =3D=3D 0) { + pr_warn("controller at %pa has no resource descriptors, skipping\n", + &info.addr); + continue; + } + + /* + * Resources follow the node header in-line. Only res[0] is + * consumed. Bound it against end before reading its prefix so + * a table that ends partway through a resource subtable is + * rejected rather than read past the mapping. + */ + res0 =3D (const struct acpi_rqsc_resource *) + ((const u8 *)node + sizeof(*node)); + if ((void *)res0 + sizeof(*res0) > (void *)end || + node->length < sizeof(*node) + sizeof(*res0) || + res0->length < sizeof(*res0)) { + pr_warn("controller at %pa: node too short for resource descriptor, ski= pping\n", + &info.addr); + continue; + } + + if (node->nres > 1) + pr_warn("controller at %pa has %u resource descriptors, using first\n", + &info.addr, node->nres); + + /* + * id1 is u64 but it is used for cache_id and prox_dom + * which are only u32. Reject rather than truncate, so a + * too large id is not silently mapped to the wrong PPTT + * entry or NUMA node. + */ + if (res0->id1 > U32_MAX) { + pr_warn("controller at %pa: id1 0x%llx exceeds u32, skipping\n", + &info.addr, res0->id1); + continue; + } + + /* + * Pair the QoS controller type with the resource descriptor + * fields that index id1. RQSC Table 4 defines the mapping: + * Capacity controller indexes a Processor Cache via PPTT + * cache_id, a Bandwidth controller indexes a Memory Range + * via SRAT proximity domain. Mismatched pairings (e.g. a + * CC whose first resource is Memory) would otherwise route + * id1 into the wrong downstream lookup. + */ + switch (info.type) { + case CBQRI_CONTROLLER_TYPE_CAPACITY: + if (res0->type !=3D ACPI_RQSC_RESOURCE_TYPE_CACHE || + res0->id_type !=3D ACPI_RQSC_RESOURCE_ID_TYPE_PROCESSOR_CACHE) { + pr_warn("CC at %pa: resource type=3D%u id_type=3D%u not (cache, proces= sor cache), skipping\n", + &info.addr, res0->type, res0->id_type); + continue; + } + info.cache_id =3D (u32)res0->id1; + break; + case CBQRI_CONTROLLER_TYPE_BANDWIDTH: + if (res0->type !=3D ACPI_RQSC_RESOURCE_TYPE_MEMORY || + res0->id_type !=3D ACPI_RQSC_RESOURCE_ID_TYPE_MEMORY_RANGE) { + pr_warn("BC at %pa: resource type=3D%u id_type=3D%u not (memory, memor= y range), skipping\n", + &info.addr, res0->type, res0->id_type); + continue; + } + info.prox_dom =3D (u32)res0->id1; + break; + default: + pr_warn("controller at %pa: unknown type %u, skipping\n", + &info.addr, info.type); + continue; + } + + pr_debug("registering controller type=3D%u addr=3D%pa rcid=3D%u mcid=3D%= u\n", + info.type, &info.addr, info.rcid_count, info.mcid_count); + + ret =3D riscv_cbqri_register_controller(&info); + if (ret =3D=3D 0) + num_controllers++; + else + pr_warn("controller at %pa: registration failed (%d), skipping\n", + &info.addr, ret); + } + + pr_info("found %d CBQRI controllers\n", num_controllers); + return 0; +} diff --git a/drivers/acpi/riscv/rqsc.h b/drivers/acpi/riscv/rqsc.h new file mode 100644 index 000000000000..fa0d96e267e1 --- /dev/null +++ b/drivers/acpi/riscv/rqsc.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Local definitions for the RISC-V Quality of Service Controller (RQSC) + * ACPI table. Will move to ACPICA's include/acpi/actbl2.h once the spec + * is ratified. + */ +#ifndef _DRIVERS_ACPI_RISCV_RQSC_H +#define _DRIVERS_ACPI_RISCV_RQSC_H + +#include +#include + +#define ACPI_SIG_RQSC "RQSC" /* RISC-V Quality of Service Controller */ + +/* RQSC Table 1: current revision number. */ +#define ACPI_RQSC_REVISION 1 + +/* RQSC Table 4: Resource Type values for acpi_rqsc_resource.type. */ +#define ACPI_RQSC_RESOURCE_TYPE_CACHE 0 +#define ACPI_RQSC_RESOURCE_TYPE_MEMORY 1 + +/* RQSC Table 4: Resource ID Type values for .id_type. */ +#define ACPI_RQSC_RESOURCE_ID_TYPE_PROCESSOR_CACHE 0 +#define ACPI_RQSC_RESOURCE_ID_TYPE_MEMORY_RANGE 1 +#define ACPI_RQSC_RESOURCE_ID_TYPE_MEMORY_SIDE_CACHE 2 +#define ACPI_RQSC_RESOURCE_ID_TYPE_ACPI_DEVICE 3 +#define ACPI_RQSC_RESOURCE_ID_TYPE_PCI_DEVICE 4 + +/* + * Byte-packed: u64 id1 would otherwise pad to 8-byte alignment and inflate + * sizeof(*res) from the spec's 20 bytes to 24, mis-sizing resource subtab= les. + */ +struct acpi_rqsc_resource { + u8 type; + u8 resv; + u16 length; + u16 flags; + u8 resv2; + u8 id_type; + u64 id1; + u32 id2; +} __packed; + +struct acpi_rqsc_node { + u8 type; + u8 resv; + u16 length; + /* RQSC section 2 Table 2: 12-byte GAS-format register interface address = */ + struct acpi_generic_address reg; + u16 rcid; + u16 mcid; + u16 flags; + u16 nres; + /* + * Followed by nres acpi_rqsc_resource subtables. Walk them via + * each resource's own length field so a future RQSC revision that + * extends the resource layout cannot misalign older parsers. + */ +} __packed; + +struct acpi_table_rqsc { + struct acpi_table_header header; /* Common ACPI table header */ + u32 num; +} __packed; + +#endif /* _DRIVERS_ACPI_RISCV_RQSC_H */ --=20 2.43.0 From nobody Mon Jun 8 05:29:11 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C7573FF8B3; Mon, 1 Jun 2026 20:36:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780346199; cv=none; b=bJmnFoFi6hlZXRiEqp9l8BjIA7lCYtN4tYfhi9qUJYhoo/VBu0wktuuTqc4h6X2qdAeO8BkIyt+oCwUcMbkIbNzKkNjB+/rbYhZjsbK7zdmqJHLPLXdTHkzxQywRJtkJ7haaz5jnbZHG822zx/seFnQja8lk+SpVY4SVWjYeZJQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780346199; c=relaxed/simple; bh=J9k+kdxn9VBh2gcTNNCv4EIpVuWkTdzFDdzbka+fNg8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YnDatMSO2uSFiBpp43ANarmIGkac7wMf1r+2OR+uwbnWwd08Nj4CJV9m4ztwtjvmsZIV2sxcVCDimTWixQq49LiDcOGaY/aIvB8G4l4ME7pL3i+le3kyzy600soUx5cGH8gAU3VDpBvpJJPLZ82AGEIgdv0w3qXTO8x6ot/GyDE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=EjEVZgO5; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="EjEVZgO5" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6FE861F008A2; Mon, 1 Jun 2026 20:36:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1780346197; bh=6zw1YkJkBQFnyL3MGMXlh5Ks8e9UJTAJTqAov2MLs5U=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=EjEVZgO5AQLGfNQ7aScZUx87ZdJYswihpQzcWMZZQuPlhoi2tnoB0KR1PPb0j6Iqj wr+l/gIFy2z9I+lRYHbmulwPxQETmhnJ1q7nE3DT7NhbwQR9t8IbRjJ/CBjZ8hFcuV Hrmr/5VmiDL+bwWxMK3oQcMos3FwHFVsDYo6FW9gFIR+2PfZk9vMcUV84N1LF+KFYm 51NZzD9koISz6UXrmyViqNr0tQYW7eC/zow9Zrdqe8m1W9ISr/APConh2pjVZYBTc4 xJo4B6gvth0JVcq1pgGCsys3XFJrXRLmDASaOUUNI2BjW1m/Rwjig12G4Cr4zo+fp7 lDsjJL23LGBKg== From: Drew Fustini Date: Mon, 01 Jun 2026 13:36:11 -0700 Subject: [PATCH RFC v6 17/18] ACPI: RISC-V: Add support for RISC-V Quality of Service Controller (RQSC) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-17-baf00f50028a@kernel.org> References: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-0-baf00f50028a@kernel.org> In-Reply-To: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-0-baf00f50028a@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , Conor Dooley , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, Gong Shuai , Gong Shuai , liu.qingtao2@zte.com.cn, Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Rob Herring , Conor Dooley , Krzysztof Kozlowski , "Rafael J. Wysocki" , Len Brown , Robert Moore , Sunil V L , Drew Fustini , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Sebastian Andrzej Siewior , Clark Williams , Steven Rostedt , Jonathan Corbet Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org, linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, devicetree@vger.kernel.org, Paul Walmsley , Conor Dooley , linux-rt-devel@lists.linux.dev, linux-doc@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1706; i=fustini@kernel.org; h=from:subject:message-id; bh=J9k+kdxn9VBh2gcTNNCv4EIpVuWkTdzFDdzbka+fNg8=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTJvnW5EnBOVuGM9dw7i1t+JossSmJa3bls+hyV5zZia xw+PDfK7ihlYRDjYpAVU2TZ9CHvwhKv0K8L5r/YBjOHlQlkCAMXpwBMhOUqI8MFLenMt4F71tQv WjeNX+H1iXdX0u1W9/rO2tN3e9NZDYsCRoZNPLI1KXeC9J+mn7NZJiib31hRsN64LXFrs8eVc3O EfzAAAA== X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Call acpi_parse_rqsc() from acpi_arch_init() to discover CBQRI controllers when an RQSC table is present. Gate on CONFIG_RISCV_CBQRI_DRIVER rather than CONFIG_RISCV_ISA_SSQOSID so a kernel built with the ISA extension but without the driver (e.g. RESCTRL_FS=3Dn) does not walk the table and print a misleading "found 0 CBQRI controllers" line on every boot. Link: https://github.com/riscv-non-isa/riscv-cbqri/releases/tag/v1.0 Link: https://github.com/riscv-non-isa/riscv-rqsc/blob/main/src/ Assisted-by: Claude:claude-opus-4-7 Signed-off-by: Drew Fustini --- drivers/acpi/riscv/init.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/acpi/riscv/init.c b/drivers/acpi/riscv/init.c index 7c00f7995e86..129ebfae28be 100644 --- a/drivers/acpi/riscv/init.c +++ b/drivers/acpi/riscv/init.c @@ -5,11 +5,32 @@ */ =20 #include +#include #include "init.h" +#include "rqsc.h" =20 void __init acpi_arch_init(void) { riscv_acpi_init_gsi_mapping(); + if (IS_ENABLED(CONFIG_ACPI_RIMT)) riscv_acpi_rimt_init(); + + if (IS_ENABLED(CONFIG_RISCV_CBQRI_DRIVER)) { + struct acpi_table_header *rqsc __free(acpi_put_table) =3D NULL; + acpi_status status =3D acpi_get_table(ACPI_SIG_RQSC, 0, &rqsc); + + if (status =3D=3D AE_NOT_FOUND) { + /* RQSC is optional. Silence on systems without it. */ + } else if (ACPI_FAILURE(status)) { + pr_err("RQSC: failed to get table: %s\n", + acpi_format_exception(status)); + } else { + int rc =3D acpi_parse_rqsc(rqsc); + + if (rc < 0) + pr_err("RQSC: failed to parse table: %d\n", + rc); + } + } } --=20 2.43.0 From nobody Mon Jun 8 05:29:11 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 307DD3FFAC7; Mon, 1 Jun 2026 20:36:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780346199; cv=none; b=J/NfsARvJao8q0i6LFG8ac4mJeQsn17v/oKnCXEOkTZQVTJNIRGVBIGjCw6zkvcLZkoS7b/7U3S21lv/D6iKdGkfG73UU2ZMDPHbpFMpdIbYYNcyuW1NVpuRUu9bh3CrJVMlX21Eyw4YFchRYOVZj1HLPPXHqHA3rLvRou1Vl8I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780346199; c=relaxed/simple; bh=6CzKXhV0tXNwm1l8Ur8ud/xHZoolzjjof2zwrYxGHkE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=TiKkr78PS6ovIvMeRb338xlFMKs3ZIjwsR9SsxerGn7aQp3DjjMy7ADLheKhNbHEpfbjQ+BMd0soywGri9zZuO1QPSwPvXFrtVc5X6y/150ICYaGiiZxM1KioC7KGmWk+oZSbS8HZ0qP+TILMrsLBEzjBlp4+a+G+HSj/ZMwjxg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Nl8wTyX/; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Nl8wTyX/" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4C8091F008A7; Mon, 1 Jun 2026 20:36:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1780346198; bh=U+t+EwaLSa9WOo0VEMTYqUakFDohqsI+NxBxDSmeLYo=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=Nl8wTyX/3fAHjM6xCDMCVHOCu3oJDWI+XRy1KZ9PvBnAqA4duBLSFcYQDXfH8LR3H bmr/vkHgcmqlGVOPXOH7eCHLUrkofOuec9XEdAucwtz9xqZZHwYBth838JWjM42WrF hRyA0hrHdvjTHSOwxDgjgflVsYBo75+Aupt/ay78vbAlWMnIJOnE8VIhCaoYlBKxcH o8pRHP/gexjsttym3kyDtl8ZOM5k3lxZ1P95y0xEcdjTjfVFiPAHMIbFv+ZHgEkHDv bM5jqFFfnUwjVLqNNStE9Sj4Yz0MjpUbRO5wwoFjBHhzrUAiD4jQtHRYj2dzZ60Xjk vKo/0wGjioQwg== From: Drew Fustini Date: Mon, 01 Jun 2026 13:36:12 -0700 Subject: [PATCH RFC v6 18/18] riscv: enable resctrl filesystem for Ssqosid Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-18-baf00f50028a@kernel.org> References: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-0-baf00f50028a@kernel.org> In-Reply-To: <20260601-ssqosid-cbqri-rqsc-v7-0-v6-0-baf00f50028a@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , Conor Dooley , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, Gong Shuai , Gong Shuai , liu.qingtao2@zte.com.cn, Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Rob Herring , Conor Dooley , Krzysztof Kozlowski , "Rafael J. Wysocki" , Len Brown , Robert Moore , Sunil V L , Drew Fustini , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Sebastian Andrzej Siewior , Clark Williams , Steven Rostedt , Jonathan Corbet Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org, linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, devicetree@vger.kernel.org, Paul Walmsley , Conor Dooley , linux-rt-devel@lists.linux.dev, linux-doc@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=876; i=fustini@kernel.org; h=from:subject:message-id; bh=6CzKXhV0tXNwm1l8Ur8ud/xHZoolzjjof2zwrYxGHkE=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTJvnV52Za3ouVAzL3ilwppM5c5a08te3++5curp5eER TanbI9k6ShlYRDjYpAVU2TZ9CHvwhKv0K8L5r/YBjOHlQlkCAMXpwBMJOcGI0NvgXDqtYmLhE+G LVeYFdfqNWG+hJJ60TZPI6Nn2yMPnLNj+F8Q/2LCVN7dmtezuZ7369SkzJZ9d4PD4dLsk+rvZk8 yEmYEAA== X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 RISCV_ISA_SSQOSID selects RISCV_CBQRI_DRIVER unconditionally. The resctrl filesystem integration is gated separately by RISCV_CBQRI_RESCTRL_FS, a silent option that defaults to y when both RISCV_CBQRI_DRIVER and RESCTRL_FS are enabled. Enabling the resctrl filesystem itself stays a user choice via the standard fs/Kconfig MISC_FILESYSTEMS menu. Signed-off-by: Drew Fustini --- arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 390353a6153a..dd65248df117 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -596,6 +596,7 @@ config RISCV_ISA_SSQOSID depends on 64BIT default n select ARCH_HAS_CPU_RESCTRL + select RISCV_CBQRI_DRIVER help Adds support for the Ssqosid ISA extension (Supervisor-mode Quality of Service ID). --=20 2.43.0