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Mon, 01 Jun 2026 03:26:34 -0700 (PDT) From: Yong-Xuan Wang Date: Mon, 01 Jun 2026 03:26:22 -0700 Subject: [PATCH v5 1/5] KVM: RISC-V: SBI FWFT: Mark vCPU CSRs dirty after setting feature value Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260601-kvm-get_reg_list-v2-v5-1-415d08a2813b@sifive.com> References: <20260601-kvm-get_reg_list-v2-v5-0-415d08a2813b@sifive.com> In-Reply-To: <20260601-kvm-get_reg_list-v2-v5-0-415d08a2813b@sifive.com> To: Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Cl=C3=A9ment_L=C3=A9ger?= , Andrew Jones , Paolo Bonzini , Shuah Khan Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, zong.li@sifive.com, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, inochiama@gmail.com, Yong-Xuan Wang X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780309592; l=970; i=yongxuan.wang@sifive.com; s=20260424; h=from:subject:message-id; bh=XMF0XSIyNuy4j6kTqZpEJUq1eyLTItJ7528vJLaFCY0=; b=i4mw/AFm7VlveGu7MUnkidG4GqKblWsIvDKpDapvBtMbjsymQ2BViwqrFhpQVOJj/B8/0HHfM 1eIuk0srt6vBTpBQi2sl9VIkC6pNQBVnanp9bwOiLrdd6aUCUVh1h+H X-Developer-Key: i=yongxuan.wang@sifive.com; a=ed25519; pk=+8NCHB1ZJvZthQAmZspOAaqjo+/snaW8mFSiDx45HxY= Mark the vCPU CSRs as dirty after successfully setting an FWFT feature value. FWFT features may modify CSRs (e.g., pointer masking modifies henvcfg.PMM), and failing to mark them dirty can lead to the guest observing stale CSR state after vCPU scheduling or migration. Fixes: 1323a5cfe52c ("KVM: riscv: Skip CSR restore if VCPU is reloaded on t= he same core") Signed-off-by: Yong-Xuan Wang Reviewed-by: Anup Patel --- arch/riscv/kvm/vcpu_sbi_fwft.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/kvm/vcpu_sbi_fwft.c b/arch/riscv/kvm/vcpu_sbi_fwft.c index 2eab15339694..5e4aafb0cbf1 100644 --- a/arch/riscv/kvm/vcpu_sbi_fwft.c +++ b/arch/riscv/kvm/vcpu_sbi_fwft.c @@ -521,6 +521,7 @@ static int kvm_sbi_ext_fwft_set_reg(struct kvm_vcpu *vc= pu, unsigned long reg_num break; case 2: ret =3D conf->feature->set(vcpu, conf, true, value); + vcpu->arch.csr_dirty =3D true; break; default: return -ENOENT; --=20 2.43.7 From nobody Mon Jun 8 06:39:40 2026 Received: from mail-dy1-f169.google.com (mail-dy1-f169.google.com [74.125.82.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF2F239B481 for ; Mon, 1 Jun 2026 10:26:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 01 Jun 2026 03:26:36 -0700 (PDT) Received: from sw07.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-304ed5b9be7sm8176001eec.27.2026.06.01.03.26.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jun 2026 03:26:35 -0700 (PDT) From: Yong-Xuan Wang Date: Mon, 01 Jun 2026 03:26:23 -0700 Subject: [PATCH v5 2/5] KVM: RISC-V: SBI FWFT: Add optional init() callback for hardware probing Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260601-kvm-get_reg_list-v2-v5-2-415d08a2813b@sifive.com> References: <20260601-kvm-get_reg_list-v2-v5-0-415d08a2813b@sifive.com> In-Reply-To: <20260601-kvm-get_reg_list-v2-v5-0-415d08a2813b@sifive.com> To: Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Cl=C3=A9ment_L=C3=A9ger?= , Andrew Jones , Paolo Bonzini , Shuah Khan Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, zong.li@sifive.com, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, inochiama@gmail.com, Yong-Xuan Wang X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780309592; l=3443; i=yongxuan.wang@sifive.com; s=20260424; h=from:subject:message-id; bh=TXFt0DFSQdnCviWDHonLXEXWuSs4TELoJXTKnRITfIM=; b=qcEndV2CiUSg4lgHuYRsd5aA3etrfjNCxq7IkheXcAXYBJk1dZaQuK988NbgWu4xRLQDpVAvG BP0vZ9jMc8fAsWp8ehTJPS9CV54ctGBCq+yHf0goiUICI38bbjxLzLD X-Developer-Key: i=yongxuan.wang@sifive.com; a=ed25519; pk=+8NCHB1ZJvZthQAmZspOAaqjo+/snaW8mFSiDx45HxY= Add an optional init() callback to separate one-time hardware probing from runtime availability checks. For pointer masking, this allows probing supported PMM lengths during initialization while checking ISA extension availability at runtime. Fix try_to_set_pmm() to restore the previous HENVCFG.PMM value after probing, preventing side effects from hardware detection. Add preemption protection to ensure CSR probe sequences complete atomically on the same CPU. Fixes: 6f576fc0aeb9 ("RISC-V: KVM: Add support for SBI_FWFT_POINTER_MASKING= _PMLEN") Signed-off-by: Yong-Xuan Wang Reviewed-by: Anup Patel --- arch/riscv/kvm/vcpu_sbi_fwft.c | 33 +++++++++++++++++++++++++++++---- 1 file changed, 29 insertions(+), 4 deletions(-) diff --git a/arch/riscv/kvm/vcpu_sbi_fwft.c b/arch/riscv/kvm/vcpu_sbi_fwft.c index 5e4aafb0cbf1..aee951f2b8e6 100644 --- a/arch/riscv/kvm/vcpu_sbi_fwft.c +++ b/arch/riscv/kvm/vcpu_sbi_fwft.c @@ -35,6 +35,16 @@ struct kvm_sbi_fwft_feature { */ bool (*supported)(struct kvm_vcpu *vcpu); =20 + /** + * @init: Probe and initialize the feature on the vcpu + * + * This callback is optional. If provided, it will be called during + * vcpu initialization to probe the feature availability and perform + * any necessary initialization. Returns true if the feature is supported + * and initialized successfully, false otherwise. + */ + bool (*init)(struct kvm_vcpu *vcpu); + /** * @reset: Reset the feature value irrespective whether feature is suppor= ted or not * @@ -131,19 +141,30 @@ static long kvm_sbi_fwft_get_misaligned_delegation(st= ruct kvm_vcpu *vcpu, =20 static bool try_to_set_pmm(unsigned long value) { + unsigned long prev; + bool ret; + + prev =3D csr_read_clear(CSR_HENVCFG, ENVCFG_PMM); csr_set(CSR_HENVCFG, value); - return (csr_read_clear(CSR_HENVCFG, ENVCFG_PMM) & ENVCFG_PMM) =3D=3D valu= e; + ret =3D (csr_read_clear(CSR_HENVCFG, ENVCFG_PMM) & ENVCFG_PMM) =3D=3D val= ue; + csr_write(CSR_HENVCFG, prev); + + return ret; } =20 static bool kvm_sbi_fwft_pointer_masking_pmlen_supported(struct kvm_vcpu *= vcpu) { - struct kvm_sbi_fwft *fwft =3D vcpu_to_fwft(vcpu); + return riscv_isa_extension_available(vcpu->arch.isa, SMNPM); +} =20 - if (!riscv_isa_extension_available(vcpu->arch.isa, SMNPM)) - return false; +static bool kvm_sbi_fwft_pointer_masking_pmlen_init(struct kvm_vcpu *vcpu) +{ + struct kvm_sbi_fwft *fwft =3D vcpu_to_fwft(vcpu); =20 + preempt_disable(); fwft->have_vs_pmlen_7 =3D try_to_set_pmm(ENVCFG_PMM_PMLEN_7); fwft->have_vs_pmlen_16 =3D try_to_set_pmm(ENVCFG_PMM_PMLEN_16); + preempt_enable(); =20 return fwft->have_vs_pmlen_7 || fwft->have_vs_pmlen_16; } @@ -231,6 +252,7 @@ static const struct kvm_sbi_fwft_feature features[] =3D= { .first_reg_num =3D offsetof(struct kvm_riscv_sbi_fwft, pointer_masking.e= nable) / sizeof(unsigned long), .supported =3D kvm_sbi_fwft_pointer_masking_pmlen_supported, + .init =3D kvm_sbi_fwft_pointer_masking_pmlen_init, .reset =3D kvm_sbi_fwft_reset_pointer_masking_pmlen, .set =3D kvm_sbi_fwft_set_pointer_masking_pmlen, .get =3D kvm_sbi_fwft_get_pointer_masking_pmlen, @@ -365,6 +387,9 @@ static int kvm_sbi_ext_fwft_init(struct kvm_vcpu *vcpu) else conf->supported =3D true; =20 + if (conf->supported && feature->init) + conf->supported =3D feature->init(vcpu); + conf->enabled =3D conf->supported; conf->feature =3D feature; } --=20 2.43.7 From nobody Mon Jun 8 06:39:40 2026 Received: from mail-dy1-f170.google.com (mail-dy1-f170.google.com [74.125.82.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ABCFD39BFE6 for ; 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Mon, 01 Jun 2026 03:26:37 -0700 (PDT) Received: from sw07.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-304ed5b9be7sm8176001eec.27.2026.06.01.03.26.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jun 2026 03:26:37 -0700 (PDT) From: Yong-Xuan Wang Date: Mon, 01 Jun 2026 03:26:24 -0700 Subject: [PATCH v5 3/5] KVM: RISC-V: SBI FWFT: Fix stale feature exposure after runtime extension changes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260601-kvm-get_reg_list-v2-v5-3-415d08a2813b@sifive.com> References: <20260601-kvm-get_reg_list-v2-v5-0-415d08a2813b@sifive.com> In-Reply-To: <20260601-kvm-get_reg_list-v2-v5-0-415d08a2813b@sifive.com> To: Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Cl=C3=A9ment_L=C3=A9ger?= , Andrew Jones , Paolo Bonzini , Shuah Khan Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, zong.li@sifive.com, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, inochiama@gmail.com, Yong-Xuan Wang X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780309592; l=3662; i=yongxuan.wang@sifive.com; s=20260424; h=from:subject:message-id; bh=gfnczZN+h+rWjSUF0BJooFipVgVWUQb9pSCmrwwRlAE=; b=+qL9SVI0RXfE0tqzldQtvBLEC2mHZjs6gsmQCiAjT050VaVqPB7Gkj9XL3XjEOBKONYsNXAwg xUJ+NRYAep7D+DmPqqrsPG6bSMojxfLyj5wI5WYNqJxBrI1Z/pit3jK X-Developer-Key: i=yongxuan.wang@sifive.com; a=ed25519; pk=+8NCHB1ZJvZthQAmZspOAaqjo+/snaW8mFSiDx45HxY= Fix a bug where FWFT features could be incorrectly exposed to guests after userspace disables their dependent ISA extensions at runtime. The 'supported' field in kvm_sbi_fwft_config was set once during vCPU initialization based on the initial hardware/extension availability. However, when userspace subsequently disables ISA extensions via the KVM ONE_REG interface, the 'supported' field was not updated. This caused the following issues: 1. FWFT features would remain visible and accessible to guests even after their prerequisite ISA extensions were disabled 2. Guests could configure FWFT features that depend on disabled extensions, leading to undefined behavior 3. The static 'supported' flag and the dynamic supported() callback could disagree about feature availability The fix introduces a two-layer checking mechanism: 1. Add an optional init() callback to the kvm_sbi_fwft_feature structure for features that require hardware probing during initialization. This separates the one-time hardware detection logic from the runtime availability check. 2. Add runtime checks in all FWFT-related functions that call feature->supported(vcpu) if the callback exists. This ensures feature availability is re-evaluated based on the current ISA extension state. This approach maintains the cached 'supported' field for initialization- time decisions while ensuring runtime availability is always determined by the current vCPU configuration, not initialization-time snapshots. Fixes: 6b72fd170592 ("RISC-V: KVM: add support for FWFT SBI extension") Signed-off-by: Yong-Xuan Wang Reviewed-by: Anup Patel --- arch/riscv/kvm/vcpu_sbi_fwft.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/riscv/kvm/vcpu_sbi_fwft.c b/arch/riscv/kvm/vcpu_sbi_fwft.c index aee951f2b8e6..ab39ac464ffd 100644 --- a/arch/riscv/kvm/vcpu_sbi_fwft.c +++ b/arch/riscv/kvm/vcpu_sbi_fwft.c @@ -303,6 +303,8 @@ static int kvm_fwft_get_feature(struct kvm_vcpu *vcpu, = u32 feature, =20 if (!tconf->supported || !tconf->enabled) return SBI_ERR_NOT_SUPPORTED; + else if (tconf->feature->supported && !tconf->feature->supported(vcpu)) + return SBI_ERR_NOT_SUPPORTED; =20 *conf =3D tconf; =20 @@ -433,6 +435,8 @@ static unsigned long kvm_sbi_ext_fwft_get_reg_count(str= uct kvm_vcpu *vcpu) conf =3D kvm_sbi_fwft_get_config(vcpu, feature->id); if (!conf || !conf->supported) continue; + else if (conf->feature->supported && !conf->feature->supported(vcpu)) + continue; =20 ret++; } @@ -455,6 +459,8 @@ static int kvm_sbi_ext_fwft_get_reg_id(struct kvm_vcpu = *vcpu, int index, u64 *re conf =3D kvm_sbi_fwft_get_config(vcpu, feature->id); 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a=ed25519-sha256; t=1780309592; l=6365; i=yongxuan.wang@sifive.com; s=20260424; h=from:subject:message-id; bh=FNI4e0Y9g5FK2/4DBzvxjuh05HswRPQCPmugp/FnJwg=; b=9IbSqErsPynCglrgkwjMA+Pn1UvkzsbZQo8VRzxpAFxO8XIbhoiVwTbVc3LpOqgcnBdJpW6yM vbRg2ZdmJawDzqD0fAyIWeBXDsk5lPW5Koi53Bg5UxxEJo3heBn0AMo X-Developer-Key: i=yongxuan.wang@sifive.com; a=ed25519; pk=+8NCHB1ZJvZthQAmZspOAaqjo+/snaW8mFSiDx45HxY= Refactor the get-reg-list test to use unified sublist macros for ISA and SBI extensions, eliminating code duplication and improving maintainability. Previously, each extension had its own hand-coded sublist definition (e.g., SUBLIST_ZICBOM, SUBLIST_AIA, etc.) and the config structures repeated the same pattern. This made the code verbose and error-prone. Signed-off-by: Yong-Xuan Wang Reviewed-by: Anup Patel --- tools/testing/selftests/kvm/riscv/get-reg-list.c | 78 +++++++++-----------= ---- 1 file changed, 28 insertions(+), 50 deletions(-) diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testi= ng/selftests/kvm/riscv/get-reg-list.c index 8d6fdb5d38b8..5033c09201ef 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -1013,7 +1013,7 @@ static __u64 fp_d_regs[] =3D { }; =20 /* Define a default vector registers with length. This will be overwritten= at runtime */ -static __u64 vector_regs[] =3D { +static __u64 v_regs[] =3D { KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV= _VECTOR_CSR_REG(vstart), KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV= _VECTOR_CSR_REG(vl), KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV= _VECTOR_CSR_REG(vtype), @@ -1057,37 +1057,17 @@ static __u64 vector_regs[] =3D { #define SUBLIST_BASE \ {"base", .regs =3D base_regs, .regs_n =3D ARRAY_SIZE(base_regs), \ .skips_set =3D base_skips_set, .skips_set_n =3D ARRAY_SIZE(base_skips_se= t),} -#define SUBLIST_SBI_BASE \ - {"sbi-base", .feature_type =3D VCPU_FEATURE_SBI_EXT, .feature =3D KVM_RIS= CV_SBI_EXT_V01, \ - .regs =3D sbi_base_regs, .regs_n =3D ARRAY_SIZE(sbi_base_regs),} -#define SUBLIST_SBI_STA \ - {"sbi-sta", .feature_type =3D VCPU_FEATURE_SBI_EXT, .feature =3D KVM_RISC= V_SBI_EXT_STA, \ - .regs =3D sbi_sta_regs, .regs_n =3D ARRAY_SIZE(sbi_sta_regs),} -#define SUBLIST_SBI_FWFT \ - {"sbi-fwft", .feature_type =3D VCPU_FEATURE_SBI_EXT, .feature =3D KVM_RIS= CV_SBI_EXT_FWFT, \ - .regs =3D sbi_fwft_regs, .regs_n =3D ARRAY_SIZE(sbi_fwft_regs),} -#define SUBLIST_ZICBOM \ - {"zicbom", .feature =3D KVM_RISCV_ISA_EXT_ZICBOM, .regs =3D zicbom_regs, = .regs_n =3D ARRAY_SIZE(zicbom_regs),} -#define SUBLIST_ZICBOP \ - {"zicbop", .feature =3D KVM_RISCV_ISA_EXT_ZICBOP, .regs =3D zicbop_regs, = .regs_n =3D ARRAY_SIZE(zicbop_regs),} -#define SUBLIST_ZICBOZ \ - {"zicboz", .feature =3D KVM_RISCV_ISA_EXT_ZICBOZ, .regs =3D zicboz_regs, = .regs_n =3D ARRAY_SIZE(zicboz_regs),} -#define SUBLIST_AIA \ - {"aia", .feature =3D KVM_RISCV_ISA_EXT_SSAIA, .regs =3D aia_regs, .regs_n= =3D ARRAY_SIZE(aia_regs),} -#define SUBLIST_SMSTATEEN \ - {"smstateen", .feature =3D KVM_RISCV_ISA_EXT_SMSTATEEN, .regs =3D smstate= en_regs, .regs_n =3D ARRAY_SIZE(smstateen_regs),} -#define SUBLIST_FP_F \ - {"fp_f", .feature =3D KVM_RISCV_ISA_EXT_F, .regs =3D fp_f_regs, \ - .regs_n =3D ARRAY_SIZE(fp_f_regs),} -#define SUBLIST_FP_D \ - {"fp_d", .feature =3D KVM_RISCV_ISA_EXT_D, .regs =3D fp_d_regs, \ - .regs_n =3D ARRAY_SIZE(fp_d_regs),} - -#define SUBLIST_V \ - {"v", .feature =3D KVM_RISCV_ISA_EXT_V, .regs =3D vector_regs, .regs_n = =3D ARRAY_SIZE(vector_regs),} + +#define SUBLIST_ISA(ext, extu) \ + { \ + .name =3D #ext, \ + .feature =3D KVM_RISCV_ISA_EXT_##extu, \ + .regs =3D ext##_regs, \ + .regs_n =3D ARRAY_SIZE(ext##_regs), \ + } =20 #define KVM_ISA_EXT_SIMPLE_CONFIG(ext, extu) \ -static __u64 regs_##ext[] =3D { \ +static __u64 ext##_regs[] =3D { \ KVM_REG_RISCV | KVM_REG_SIZE_ULONG | \ KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | \ KVM_RISCV_ISA_EXT_##extu, \ @@ -1095,18 +1075,22 @@ static __u64 regs_##ext[] =3D { \ static struct vcpu_reg_list config_##ext =3D { \ .sublists =3D { \ SUBLIST_BASE, \ - { \ - .name =3D #ext, \ - .feature =3D KVM_RISCV_ISA_EXT_##extu, \ - .regs =3D regs_##ext, \ - .regs_n =3D ARRAY_SIZE(regs_##ext), \ - }, \ + SUBLIST_ISA(ext, extu), \ {0}, \ }, \ } \ =20 +#define SUBLIST_SBI(ext, extu) \ + { \ + .name =3D "sbi-"#ext, \ + .feature_type =3D VCPU_FEATURE_SBI_EXT, \ + .feature =3D KVM_RISCV_SBI_EXT_##extu, \ + .regs =3D sbi_##ext##_regs, \ + .regs_n =3D ARRAY_SIZE(sbi_##ext##_regs), \ + } + #define KVM_SBI_EXT_SIMPLE_CONFIG(ext, extu) \ -static __u64 regs_sbi_##ext[] =3D { \ +static __u64 sbi_##ext##_regs[] =3D { \ KVM_REG_RISCV | KVM_REG_SIZE_ULONG | \ KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | \ KVM_RISCV_SBI_EXT_##extu, \ @@ -1114,13 +1098,7 @@ static __u64 regs_sbi_##ext[] =3D { \ static struct vcpu_reg_list config_sbi_##ext =3D { \ .sublists =3D { \ SUBLIST_BASE, \ - { \ - .name =3D "sbi-"#ext, \ - .feature_type =3D VCPU_FEATURE_SBI_EXT, \ - .feature =3D KVM_RISCV_SBI_EXT_##extu, \ - .regs =3D regs_sbi_##ext, \ - .regs_n =3D ARRAY_SIZE(regs_sbi_##ext), \ - }, \ + SUBLIST_SBI(ext, extu), \ {0}, \ }, \ } \ @@ -1129,7 +1107,7 @@ static struct vcpu_reg_list config_sbi_##ext =3D { \ static struct vcpu_reg_list config_##ext =3D { \ .sublists =3D { \ SUBLIST_BASE, \ - SUBLIST_##extu, \ + SUBLIST_ISA(ext, extu), \ {0}, \ }, \ } \ @@ -1138,14 +1116,14 @@ static struct vcpu_reg_list config_##ext =3D { \ static struct vcpu_reg_list config_sbi_##ext =3D { \ .sublists =3D { \ SUBLIST_BASE, \ - SUBLIST_SBI_##extu, \ + SUBLIST_SBI(ext, extu), \ {0}, \ }, \ } \ =20 /* Note: The below list is alphabetically sorted. */ =20 -KVM_SBI_EXT_SUBLIST_CONFIG(base, BASE); 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a=ed25519-sha256; t=1780309592; l=6157; i=yongxuan.wang@sifive.com; s=20260424; h=from:subject:message-id; bh=dvopGRgDaRky18g/xnQDE1UFxOqmLWbk1vHTjPzPMBI=; b=Olw29Tmd5roLVBLWWP49d+h5thdSBlPI0OZxQt2vjWmCkx7EuWs1TdMjVMOQKpouSKkjMyimr wTecLpqPhRoCpumKzUBuxJhFUA60FQQDmUile8JquKjB1uNad5HoPnR X-Developer-Key: i=yongxuan.wang@sifive.com; a=ed25519; pk=+8NCHB1ZJvZthQAmZspOAaqjo+/snaW8mFSiDx45HxY= Divide the monolithic SBI FWFT (Firmware Features) register list into separate sublists, each testing a specific FWFT feature independently with proper dependency checking. Previously, all FWFT features were tested together in a single sublist. This caused issues because: 1. Not all FWFT features are available on all platforms 2. Some features depend on specific ISA extensions (e.g., pointer_masking requires Smnpm) 3. Tests would fail if any single feature was unavailable Add the feature-specific SBI FWFT sublists with the following improvements: - Add check_fwft_feature() helper to verify FWFT feature availability at runtime - Update filter_reg() to handle per-feature FWFT register filtering Signed-off-by: Yong-Xuan Wang Reviewed-by: Anup Patel --- tools/testing/selftests/kvm/riscv/get-reg-list.c | 60 ++++++++++++++++++++= ++-- 1 file changed, 57 insertions(+), 3 deletions(-) diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testi= ng/selftests/kvm/riscv/get-reg-list.c index 5033c09201ef..cb86cb6b3635 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -27,6 +27,7 @@ enum { }; =20 static bool isa_ext_cant_disable[KVM_RISCV_ISA_EXT_MAX]; +static bool sbi_ext_enabled[KVM_RISCV_SBI_EXT_MAX]; =20 bool filter_reg(__u64 reg) { @@ -149,6 +150,14 @@ bool filter_reg(__u64 reg) case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_RE= G(iprio1h): case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_RE= G(iprio2h): return isa_ext_cant_disable[KVM_RISCV_ISA_EXT_SSAIA]; + /* + * FWFT misaligned delegation registers are always visible when the SBI F= WFT + * extension is enable and the host supports the misaligned delegation. + */ + case KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI= _FWFT_REG(misaligned_deleg.enable): + case KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI= _FWFT_REG(misaligned_deleg.flags): + case KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI= _FWFT_REG(misaligned_deleg.value): + return sbi_ext_enabled[KVM_RISCV_SBI_EXT_FWFT]; default: break; } @@ -193,6 +202,27 @@ static int override_vector_reg_size(struct kvm_vcpu *v= cpu, struct vcpu_reg_subli return 0; } =20 +void check_fwft_feature(struct kvm_vcpu *vcpu, struct vcpu_reg_sublist *s,= u64 feature) +{ + unsigned long value; + int rc; + + /* Enable SBI FWFT extension so that we can check the supported register = */ + rc =3D __vcpu_set_reg(vcpu, feature, 1); + if (rc) + return; + + for (int i =3D 0; i < s->regs_n; i++) { + if ((s->regs[i] & KVM_REG_RISCV_TYPE_MASK) =3D=3D KVM_REG_RISCV_SBI_STAT= E) { + rc =3D __vcpu_get_reg(vcpu, s->regs[i], &value); + __TEST_REQUIRE(!rc, "%s not available, skipping tests", s->name); + } + } + + /* We should assert if disabling failed here while enabling succeeded bef= ore */ + vcpu_set_reg(vcpu, feature, 0); +} + void finalize_vcpu(struct kvm_vcpu *vcpu, struct vcpu_reg_list *c) { unsigned long isa_ext_state[KVM_RISCV_ISA_EXT_MAX] =3D { 0 }; @@ -235,6 +265,9 @@ void finalize_vcpu(struct kvm_vcpu *vcpu, struct vcpu_r= eg_list *c) break; case VCPU_FEATURE_SBI_EXT: feature =3D RISCV_SBI_EXT_REG(s->feature); + if (s->feature =3D=3D KVM_RISCV_SBI_EXT_FWFT) + check_fwft_feature(vcpu, s, feature); + sbi_ext_enabled[s->feature] =3D true; break; default: TEST_FAIL("Unknown feature type"); @@ -897,11 +930,15 @@ static __u64 sbi_sta_regs[] =3D { KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_STA | KVM_REG_RISCV_SBI_STA_REG(shmem_hi), }; =20 -static __u64 sbi_fwft_regs[] =3D { +static __u64 sbi_fwft_misaligned_deleg_regs[] =3D { KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISC= V_SBI_SINGLE | KVM_RISCV_SBI_EXT_FWFT, KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.enable), KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.flags), KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.value), +}; + +static __u64 sbi_fwft_pointer_masking_regs[] =3D { + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISC= V_SBI_SINGLE | KVM_RISCV_SBI_EXT_FWFT, KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.enable), KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.flags), KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.value), @@ -1129,7 +1166,6 @@ KVM_SBI_EXT_SIMPLE_CONFIG(pmu, PMU); KVM_SBI_EXT_SIMPLE_CONFIG(dbcn, DBCN); KVM_SBI_EXT_SIMPLE_CONFIG(susp, SUSP); KVM_SBI_EXT_SIMPLE_CONFIG(mpxy, MPXY); -KVM_SBI_EXT_SUBLIST_CONFIG(fwft, FWFT); =20 KVM_ISA_EXT_SUBLIST_CONFIG(aia, SSAIA); KVM_ISA_EXT_SUBLIST_CONFIG(fp_f, F); @@ -1206,6 +1242,23 @@ KVM_ISA_EXT_SIMPLE_CONFIG(zvksed, ZVKSED); KVM_ISA_EXT_SIMPLE_CONFIG(zvksh, ZVKSH); KVM_ISA_EXT_SIMPLE_CONFIG(zvkt, ZVKT); =20 +static struct vcpu_reg_list config_sbi_fwft_misaligned_deleg =3D { + .sublists =3D { + SUBLIST_BASE, + SUBLIST_SBI(fwft_misaligned_deleg, FWFT), + {0}, + }, +}; + +static struct vcpu_reg_list config_sbi_fwft_pointer_masking =3D { + .sublists =3D { + SUBLIST_BASE, + SUBLIST_ISA(smnpm, SMNPM), + SUBLIST_SBI(fwft_pointer_masking, FWFT), + {0}, + }, +}; + struct vcpu_reg_list *vcpu_configs[] =3D { &config_sbi_base, &config_sbi_sta, @@ -1213,7 +1266,8 @@ struct vcpu_reg_list *vcpu_configs[] =3D { &config_sbi_dbcn, &config_sbi_susp, &config_sbi_mpxy, - &config_sbi_fwft, + &config_sbi_fwft_misaligned_deleg, + &config_sbi_fwft_pointer_masking, &config_aia, &config_fp_f, &config_fp_d, --=20 2.43.7