From nobody Mon Jun 8 08:30:34 2026 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D3F643242BA for ; Sun, 31 May 2026 09:27:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780219641; cv=none; b=eI9pwvgudC0sWtf/ll87lMHqpeM0FyVrzykIom6/aKDvvqizpCb26lGhaFk3X+XbtrzE1qHZh/0GwNhXO+DpRLG9jzZqMuAefg0CTowB+aGkFAGRLjbzxRMGbvVb7arrgf3LE/mqJLopk/KLG5r0sX3e2S/Lp30WPBFG9iUcGMo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780219641; c=relaxed/simple; bh=OWSx1MMpR9qIKeq9ksKpLzpLKLA05SSYFkqxHQGQPB4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ArspJVqONFkUVkZD+V5YiMaNcVC9lkxrMZFSnQkQ1v3cNGRh1VGx6Hd2WXyxjEUsV071fvDt+uOWBS+wDqRrF20vn9YStkGEFmm9NV54ph2HZqd5/TNmwo1yinmZMekHdnaMK3ab8XxMgd4sVYp3KYpDJzzTnh0WiJeJ5KgmoyA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=XP+vYEEN; arc=none smtp.client-ip=209.85.128.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="XP+vYEEN" Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-4904c1ce4c1so99126615e9.3 for ; Sun, 31 May 2026 02:27:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1780219638; x=1780824438; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/yV5eCV14Q3TCkUmPIb/jJ+sajPZ6JHRE3L068KeT1Q=; b=XP+vYEENUxcCcvVgsgwSMgOwHzAmOjyVZrFSiTJj55xaULwMHHEAkEYDJcnjOit11p iZB8cHglVy9RwBVV6LDuI4oFke3GoJ0iuoAd+pRbJpC3vk5A5a7rWOti/UYgA9waaLeq tzydxqojoSLncwppmcywgix9vGiSnn1ndigZxQIuDk/EEKObc3kqa56+ySpqnlRinnhU A90f1wV/f1ue9ErC/8zY+80bzYiJVfB1jxxs1jncbCvz4iiDtd3F81+q6swLSHPnvRXl aSSmtfW9k6eSOQ4j5j3O/6ek8rtAfpBZ3pOFkHB29inzSV7dpGMtbRVsy+BEwJm+4RIO I70Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1780219638; x=1780824438; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=/yV5eCV14Q3TCkUmPIb/jJ+sajPZ6JHRE3L068KeT1Q=; b=ley4ns8gk3abiZFkxdcBTChLL/fElbSyOL23VG7Zrx1kCzEetAL88Obbm1HW3p8fzR 05hNEK7yImKFUUkV8mJm9FUCzm8dJjhe+/vlmrTDT5HQ5RgVEM2y/x3dMJsum3RnI7Nd rL3raSporJMOID9qi2C99c99Xxi0AY14mRg1yqLLBZIakP0J2+xtgbTjJ4KNCDiLrsao EvyzgcMechYAgbLlB2Wy9JLVQnrr5uZTZKPxfNHfC9ZwUMU6a3NvJGbRhTYqxTLGxwzN dsdltzHG/urLCRQOb4Qdd1qwHQ1cb6ErHeBKS1XEyCetjOuY2l7A4TlDIbmryw2MTe2Q 7Jow== X-Forwarded-Encrypted: i=1; AFNElJ/OnEJLVJ10pUsM/072NMPkj28oS8avpxTAM2Qon1gF3HWyY903go9v+Ygd+dTAPSdMu5S8+bQQGUaqKUs=@vger.kernel.org X-Gm-Message-State: AOJu0YwE7xRK+lPzC7L/MjUhIvWN4gFDqB+isjFa6OpzwFgW8f3Tvu+f 8uawhQG/Q1a21RpvO9sOzRMXBsSecFNO+1FJsr5s8bSyflL/uh8H0Sv+ X-Gm-Gg: Acq92OFctwRNaRMs9MU4H43GCOz+qrgl/kGMG6c6Z2wdp4Li9bafSOGnT7AQpzKGOB/ uu0wc6wC/QHVATjl+MXMRt+XjKf93v0kLeNONIf/yxw1Ftz1BeW+463RgJmnYYYNiznEzzzKAy3 fzniy2GArVQH15rfKdWl3QN6rjHpL9sMqeRnzr8levhoINLQruUMQR9LZRm6FzXCa1uQYBZkfHG dwZ1mcGwptMvDP0B9AsqRumZ5zuczrJ3fDzJr6ZieDVcLtoJI67M7B9pSyHusRZYoGCKdc6TLRW oJzrACx23j8al2aTGIqE4zTCiIgFP8a2RRSFhOoEkZoTwGvimJU3/1dQvBIWCT6LrbT144Lvw94 Xf80PkueVb5oQHvamvudB9rnCZa6pE5J5drq2O/m2zyiF8lbMI9XsRJavcRW2ArVmKHW9ThAxa0 7PAl9PqB9m7cBqLD9nsgT/N7c= X-Received: by 2002:a05:600c:4f05:b0:490:50e8:45c3 with SMTP id 5b1f17b1804b1-490a28cf434mr119706925e9.0.1780219638142; Sun, 31 May 2026 02:27:18 -0700 (PDT) Received: from xeon ([188.163.112.61]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4909c0e8c1bsm68462675e9.3.2026.05.31.02.27.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 May 2026 02:27:17 -0700 (PDT) From: Svyatoslav Ryhel To: Prashant Gaikwad , Michael Turquette , Stephen Boyd , Thierry Reding , Thierry Reding , Jonathan Hunter , Mikko Perttunen , Svyatoslav Ryhel Cc: linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 1/1 RESEND v2] clk: tegra: set up proper EMC clock implementation for Tegra114 Date: Sun, 31 May 2026 12:26:53 +0300 Message-ID: <20260531092653.12589-2-clamor95@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260531092653.12589-1-clamor95@gmail.com> References: <20260531092653.12589-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove current emc and emc_mux clocks and replace them with the proper EMC clock implementation for correct EMC driver support. Acked-by: Thierry Reding Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen --- drivers/clk/tegra/clk-tegra114.c | 39 ++++++++++++++++++++------------ 1 file changed, 25 insertions(+), 14 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra= 114.c index 8bde72aa5e68..853ef707654a 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -622,10 +622,6 @@ static const char *mux_plld_out0_plld2_out0[] =3D { }; #define mux_plld_out0_plld2_out0_idx NULL =20 -static const char *mux_pllmcp_clkm[] =3D { - "pll_m_out0", "pll_c_out0", "pll_p_out0", "clk_m", "pll_m_ud", -}; - static const struct clk_div_table pll_re_div_table[] =3D { { .val =3D 0, .div =3D 1 }, { .val =3D 1, .div =3D 2 }, @@ -672,7 +668,6 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __= initdata =3D { [tegra_clk_csi] =3D { .dt_id =3D TEGRA114_CLK_CSI, .present =3D true }, [tegra_clk_i2c2] =3D { .dt_id =3D TEGRA114_CLK_I2C2, .present =3D true }, [tegra_clk_uartc] =3D { .dt_id =3D TEGRA114_CLK_UARTC, .present =3D true = }, - [tegra_clk_emc] =3D { .dt_id =3D TEGRA114_CLK_EMC, .present =3D true }, [tegra_clk_usb2] =3D { .dt_id =3D TEGRA114_CLK_USB2, .present =3D true }, [tegra_clk_usb3] =3D { .dt_id =3D TEGRA114_CLK_USB3, .present =3D true }, [tegra_clk_vde_8] =3D { .dt_id =3D TEGRA114_CLK_VDE, .present =3D true }, @@ -1048,14 +1043,7 @@ static __init void tegra114_periph_clk_init(void __i= omem *clk_base, 0, 82, periph_clk_enb_refcnt); clks[TEGRA114_CLK_DSIB] =3D clk; =20 - /* emc mux */ - clk =3D clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, - ARRAY_SIZE(mux_pllmcp_clkm), - CLK_SET_RATE_NO_REPARENT, - clk_base + CLK_SOURCE_EMC, - 29, 3, 0, &emc_lock); - - clk =3D tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC, + clk =3D tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC, &emc_lock); clks[TEGRA114_CLK_MC] =3D clk; =20 @@ -1321,6 +1309,26 @@ static int tegra114_reset_deassert(unsigned long id) return 0; } =20 +static struct clk *tegra114_clk_src_onecell_get(struct of_phandle_args *cl= kspec, + void *data) +{ + struct clk_hw *hw; + struct clk *clk; + + clk =3D of_clk_src_onecell_get(clkspec, data); + if (IS_ERR(clk)) + return clk; + + hw =3D __clk_get_hw(clk); + + if (clkspec->args[0] =3D=3D TEGRA114_CLK_EMC) { + if (!tegra124_clk_emc_driver_available(hw)) + return ERR_PTR(-EPROBE_DEFER); + } + + return clk; +} + static void __init tegra114_clock_init(struct device_node *np) { struct device_node *node; @@ -1368,7 +1376,10 @@ static void __init tegra114_clock_init(struct device= _node *np) tegra_init_special_resets(1, tegra114_reset_assert, tegra114_reset_deassert); =20 - tegra_add_of_provider(np, of_clk_src_onecell_get); + tegra_add_of_provider(np, tegra114_clk_src_onecell_get); + clks[TEGRA114_CLK_EMC] =3D tegra124_clk_register_emc(clk_base, np, + &emc_lock); + tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); =20 tegra_clk_apply_init_table =3D tegra114_clock_apply_init_table; --=20 2.51.0