From nobody Mon Jun 8 08:30:46 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3DA892FFF89; Sun, 31 May 2026 13:08:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780232893; cv=none; b=eb6K9+cHPC4cFnHND7znENvkRHtNnAYUNwSqW0LSCRyyLcxFXJcoD61srnH2uCqO7r9suFwjk0akBqz4PYa/efAvi4PCXUM6EioNLX7VsCz/yYN/XeQYOeOLzYnnshsg7vbR0+moZ76HwJ24CammsPxXDI0B4W+ZZEkrXiGnmkc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780232893; c=relaxed/simple; bh=WOHap0PMuhNX1jbsZv5OuNbW6B9ccA62w6TZvxd2zIo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=LT3ElyHs0xL5/IFCva2fkqf6f6tmq02eyY20wprgZzqnVsO+3up8Zmm1VmYTw0hXZvehMmjOkh8wokxXIMsLXRlLLsH/8UnQ/hjHlqbJ2oGRU5oTn+MPjqpyI3ysQuxreYIk88P+EN+P/oPy7NlbFmTRyUQs+yDSxbMPeBj0t54= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=AHduGVIV; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="AHduGVIV" Received: by smtp.kernel.org (Postfix) with ESMTPS id C1590C2BCF4; Sun, 31 May 2026 13:08:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1780232892; bh=WOHap0PMuhNX1jbsZv5OuNbW6B9ccA62w6TZvxd2zIo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=AHduGVIVDXiRRJF11/Sqo6Zj3+ZkaIMp8R61xM4ojb9NyplaOAi6PGS/NpLLvsYTa Ba9X9XKf7Pf303DCFmseDBYHryLTDzQ0n5lhzfg8aAWBGZfaPyd0gwjTqllnvKyWGk LdmQZoKQtfy8sshWRkbP5BJVJK9wYawwzMvAbyB1pLgTaJZg65iTcq78zloCVyTEoa cfYnTfzs8pAWbeWOoK5RV1whYEVrx53+LUv73HKytdqtxAHWA2Lpy5U/0JTVMJTiCB N3VRC4fq5XtBbQOI7kDExv/b8bFWfauzwdcYwsHbNlquyjvs+TJOYSj0uBm0x7GLLW ZzOzusO5vOoNA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id ADA7FCD6E53; Sun, 31 May 2026 13:08:12 +0000 (UTC) From: David Heidelberg via B4 Relay Date: Sun, 31 May 2026 15:08:09 +0200 Subject: [PATCH WIP v5 1/9] media: qcom: camss: csiphy: Introduce PHY configuration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260531-qcom-cphy-v5-1-6be0f62b4d65@ixit.cz> References: <20260531-qcom-cphy-v5-0-6be0f62b4d65@ixit.cz> In-Reply-To: <20260531-qcom-cphy-v5-0-6be0f62b4d65@ixit.cz> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Luca Weiss , Petr Hodina , Casey Connolly , "Dr. Git" , Cory Keitz , Loic Poulain Cc: Konrad Dybcio , Joel Selvaraj , Kieran Bingham , Sakari Ailus , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2338; i=david@ixit.cz; h=from:subject:message-id; bh=TdL92ydT0RSn4nXWxC1lDtEnuvLw0RCXQb+vqbcUxZw=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBqHDK6wtFEBz2O6Kq/yf2dnhUqWk4pgHemgv/3G 21Xeo1J03+JAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCahwyugAKCRBgAj/E00kg clgXD/9Ywx0xMj6zvgMQec3E/GnYdHljbdPgEj3RLVpgjVaZe+kLLUAbsQxLh1ADPT0DOwkscD/ W7WUfLbFUYBVfUhwdd4W2GiEzNJmOJR9UV9Wl7nMNFRZUPR37J0DEpnrZ7H1PdLbPcemiE7XKCr d4tCHrJIoElHv9jbvBSD17WrewzWZ5xvQzYB54wehZKgTatnVERAPqKc9j0ZXH4uM3RJhShmq6+ 3GakdO2MF7bdmjCCEtJ5htKrSAWVzQEJcgLc0zb5hpBIo0PGjwjI7TAHoKNGeHnYKGfnnZHHIP5 frdUSI6awzHl+9z/XMGx/irWSnhtqCqxAgSl3hKLDS1bD3ZRSlomfF19iNL7lSZG+GJlcbaYrRs x90rtBjIReajO/Ges6GTwW03euqd8WQFfdOx7lvht5QWQ8G0am8+pFMJzC7Srip5zBgDuPETFTo Y5Mjz7HE4SLfSYyqv9dczdauI7kN+gR3AhLeDgJ78m4/Pwovp1uZloL6YDTIPZ2oD83y1CtWR1J CLZRU+GvKN5z2Srb85YzTqi8lJUxvWeQYrYvqAuipbRbcPtW/G3forPwNbxm6HzOketZjwn4dLl qS8ycb/rxYsI22C1Shci3g58DJWo7/jj04Af3+snbtBgJks38Qjq3txff0gwVwCt4d57HObciss WzL2T0ps0hyyeBQ== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg Read PHY configuration from the device-tree bus-type and save it into the csiphy structure for later use. For C-PHY, skip clock line configuration, as there is none. Acked-by: Cory Keitz Signed-off-by: David Heidelberg Reviewed-by: Bryan O'Donoghue --- drivers/media/platform/qcom/camss/camss-csiphy.h | 2 ++ drivers/media/platform/qcom/camss/camss.c | 8 ++++++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.h b/drivers/med= ia/platform/qcom/camss/camss-csiphy.h index 9d9657b82f748..2ebb307be18ba 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy.h +++ b/drivers/media/platform/qcom/camss/camss-csiphy.h @@ -25,21 +25,23 @@ =20 struct csiphy_lane { u8 pos; u8 pol; }; =20 /** * struct csiphy_lanes_cfg - CSIPHY lanes configuration + * @phy_cfg: interface selection (C-PHY or D-PHY) * @num_data: number of data lanes * @data: data lanes configuration * @clk: clock lane configuration (only for D-PHY) */ struct csiphy_lanes_cfg { + enum v4l2_mbus_type phy_cfg; int num_data; struct csiphy_lane *data; struct csiphy_lane clk; }; =20 struct csiphy_csi2_cfg { struct csiphy_lanes_cfg lane_cfg; }; diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index 2123f6388e3d7..072c428e25166 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -4761,19 +4761,23 @@ static int camss_parse_endpoint_node(struct device = *dev, if (vep.bus_type !=3D V4L2_MBUS_CSI2_DPHY) { dev_err(dev, "Unsupported bus type %d\n", vep.bus_type); return -EINVAL; } =20 csd->interface.csiphy_id =3D vep.base.port; =20 mipi_csi2 =3D &vep.bus.mipi_csi2; - lncfg->clk.pos =3D mipi_csi2->clock_lane; - lncfg->clk.pol =3D mipi_csi2->lane_polarities[0]; lncfg->num_data =3D mipi_csi2->num_data_lanes; + lncfg->phy_cfg =3D vep.bus_type; + + if (lncfg->phy_cfg !=3D V4L2_MBUS_CSI2_CPHY) { + lncfg->clk.pos =3D mipi_csi2->clock_lane; + lncfg->clk.pol =3D mipi_csi2->lane_polarities[0]; + } =20 lncfg->data =3D devm_kcalloc(dev, lncfg->num_data, sizeof(*lncfg->data), GFP_KERNEL); if (!lncfg->data) return -ENOMEM; =20 for (i =3D 0; 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Sun, 31 May 2026 13:08:12 +0000 (UTC) From: David Heidelberg via B4 Relay Date: Sun, 31 May 2026 15:08:10 +0200 Subject: [PATCH WIP v5 2/9] media: qcom: camss: csiphy-3ph: Use odd bits for configuring C-PHY lanes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260531-qcom-cphy-v5-2-6be0f62b4d65@ixit.cz> References: <20260531-qcom-cphy-v5-0-6be0f62b4d65@ixit.cz> In-Reply-To: <20260531-qcom-cphy-v5-0-6be0f62b4d65@ixit.cz> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Luca Weiss , Petr Hodina , Casey Connolly , "Dr. Git" , Cory Keitz , Loic Poulain Cc: Konrad Dybcio , Joel Selvaraj , Kieran Bingham , Sakari Ailus , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg So far, only D-PHY mode was supported, which uses even bits when enabling or masking lanes. For C-PHY configuration, the hardware instead requires using the odd bits. Since there can be unrecognized configuration allow returning failure. Reviewed-by: Bryan O'Donoghue Acked-by: Cory Keitz Signed-off-by: David Heidelberg Reviewed-by: Bryan O'Donoghue --- .../platform/qcom/camss/camss-csiphy-2ph-1-0.c | 8 ++-- .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 49 +++++++++++++++++-= ---- drivers/media/platform/qcom/camss/camss-csiphy.c | 5 +-- drivers/media/platform/qcom/camss/camss-csiphy.h | 6 +-- 4 files changed, 48 insertions(+), 20 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c b/dri= vers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c index 9d67e7fa6366a..bb4b91f69616b 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c @@ -89,19 +89,19 @@ static u8 csiphy_settle_cnt_calc(s64 link_freq, u32 tim= er_clk_rate) t_hs_settle =3D (t_hs_prepare_max + t_hs_prepare_zero_min) / 2; =20 timer_period =3D div_u64(1000000000000LL, timer_clk_rate); settle_cnt =3D t_hs_settle / timer_period - 1; =20 return settle_cnt; } =20 -static void csiphy_lanes_enable(struct csiphy_device *csiphy, - struct csiphy_config *cfg, - s64 link_freq, u8 lane_mask) +static int csiphy_lanes_enable(struct csiphy_device *csiphy, + struct csiphy_config *cfg, + s64 link_freq, u8 lane_mask) { struct csiphy_lanes_cfg *c =3D &cfg->csi2->lane_cfg; u8 settle_cnt; u8 val, l =3D 0; int i =3D 0; =20 settle_cnt =3D csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate); =20 @@ -127,16 +127,18 @@ static void csiphy_lanes_enable(struct csiphy_device = *csiphy, CAMSS_CSI_PHY_LNn_CFG2(l)); writel_relaxed(settle_cnt, csiphy->base + CAMSS_CSI_PHY_LNn_CFG3(l)); writel_relaxed(0x3f, csiphy->base + CAMSS_CSI_PHY_INTERRUPT_MASKn(l)); writel_relaxed(0x3f, csiphy->base + CAMSS_CSI_PHY_INTERRUPT_CLEARn(l)); } + + return 0; } =20 static void csiphy_lanes_disable(struct csiphy_device *csiphy, struct csiphy_config *cfg) { struct csiphy_lanes_cfg *c =3D &cfg->csi2->lane_cfg; u8 l =3D 0; int i =3D 0; diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/dri= vers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index dac8d2ecf7995..d4624417a7424 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -9,16 +9,17 @@ */ =20 #include "camss.h" #include "camss-csiphy.h" =20 #include #include #include +#include =20 #define CSIPHY_3PH_LNn_CFG1(n) (0x000 + 0x100 * (n)) #define CSIPHY_3PH_LNn_CFG1_SWI_REC_DLY_PRG (BIT(7) | BIT(6)) #define CSIPHY_3PH_LNn_CFG2(n) (0x004 + 0x100 * (n)) #define CSIPHY_3PH_LNn_CFG2_LP_REC_EN_INT BIT(3) #define CSIPHY_3PH_LNn_CFG3(n) (0x008 + 0x100 * (n)) #define CSIPHY_3PH_LNn_CFG4(n) (0x00c + 0x100 * (n)) #define CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS 0xa4 @@ -1108,23 +1109,32 @@ static void csiphy_gen2_config_lanes(struct csiphy_= device *csiphy, writel_relaxed(val, csiphy->base + r->reg_addr); if (r->delay_us) udelay(r->delay_us); } } =20 static u8 csiphy_get_lane_mask(struct csiphy_lanes_cfg *lane_cfg) { - u8 lane_mask; - int i; + u8 lane_mask =3D 0; =20 - lane_mask =3D CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE; + switch (lane_cfg->phy_cfg) { + case V4L2_MBUS_CSI2_CPHY: + for (int i =3D 0; i < lane_cfg->num_data; i++) + lane_mask |=3D BIT(lane_cfg->data[i].pos + 1); + break; + case V4L2_MBUS_CSI2_DPHY: + lane_mask =3D CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE; =20 - for (i =3D 0; i < lane_cfg->num_data; i++) - lane_mask |=3D 1 << lane_cfg->data[i].pos; + for (int i =3D 0; i < lane_cfg->num_data; i++) + lane_mask |=3D BIT(lane_cfg->data[i].pos); + break; + default: + break; + } =20 return lane_mask; } =20 static bool csiphy_is_gen2(u32 version) { bool ret =3D false; =20 @@ -1143,31 +1153,46 @@ static bool csiphy_is_gen2(u32 version) case CAMSS_X1E80100: ret =3D true; break; } =20 return ret; } =20 -static void csiphy_lanes_enable(struct csiphy_device *csiphy, - struct csiphy_config *cfg, - s64 link_freq, u8 lane_mask) +static int csiphy_lanes_enable(struct csiphy_device *csiphy, + struct csiphy_config *cfg, + s64 link_freq, u8 lane_mask) { + struct device *dev =3D csiphy->camss->dev; struct csiphy_lanes_cfg *c =3D &cfg->csi2->lane_cfg; struct csiphy_device_regs *regs =3D csiphy->regs; u8 settle_cnt; u8 val; int i; =20 settle_cnt =3D csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate); =20 - val =3D CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE; - for (i =3D 0; i < c->num_data; i++) - val |=3D BIT(c->data[i].pos * 2); + val =3D 0; + + switch (c->phy_cfg) { + case V4L2_MBUS_CSI2_CPHY: + for (i =3D 0; i < c->num_data; i++) + val |=3D BIT((c->data[i].pos * 2) + 1); + break; + case V4L2_MBUS_CSI2_DPHY: + val =3D CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE; + + for (i =3D 0; i < c->num_data; i++) + val |=3D BIT(c->data[i].pos * 2); + break; + default: + dev_err(dev, "Unsupported bus type %d\n", c->phy_cfg); + return -EINVAL; + } =20 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 5)); =20 val =3D CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B; writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 6)); =20 @@ -1184,16 +1209,18 @@ static void csiphy_lanes_enable(struct csiphy_devic= e *csiphy, else csiphy_gen1_config_lanes(csiphy, cfg, settle_cnt); =20 /* IRQ_MASK registers - disable all interrupts */ for (i =3D 11; i < 22; i++) { writel_relaxed(0, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, i)); } + + return 0; } =20 static void csiphy_lanes_disable(struct csiphy_device *csiphy, struct csiphy_config *cfg) { struct csiphy_device_regs *regs =3D csiphy->regs; =20 writel_relaxed(0, csiphy->base + diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.c b/drivers/med= ia/platform/qcom/camss/camss-csiphy.c index 539ac4888b608..ec0dc9d31b585 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy.c @@ -260,16 +260,17 @@ static int csiphy_set_power(struct v4l2_subdev *sd, i= nt on) * Helper function to enable streaming on CSIPHY module. * Main configuration of CSIPHY module is also done here. * * Return 0 on success or a negative error code otherwise */ static int csiphy_stream_on(struct csiphy_device *csiphy) { struct csiphy_config *cfg =3D &csiphy->cfg; + const struct csiphy_hw_ops *ops =3D csiphy->res->hw_ops; s64 link_freq; u8 lane_mask =3D csiphy->res->hw_ops->get_lane_mask(&cfg->csi2->lane_cfg); u8 bpp =3D csiphy_get_bpp(csiphy->res->formats->formats, csiphy->res->for= mats->nformats, csiphy->fmt[MSM_CSIPHY_PAD_SINK].code); u8 num_lanes =3D csiphy->cfg.csi2->lane_cfg.num_data; u8 val; =20 link_freq =3D camss_get_link_freq(&csiphy->subdev.entity, bpp, num_lanes); @@ -290,19 +291,17 @@ static int csiphy_stream_on(struct csiphy_device *csi= phy) val |=3D cfg->csid_id; } writel_relaxed(val, csiphy->base_clk_mux); =20 /* Enforce reg write ordering between clk mux & lane enabling */ wmb(); } =20 - csiphy->res->hw_ops->lanes_enable(csiphy, cfg, link_freq, lane_mask); - - return 0; + return ops->lanes_enable(csiphy, cfg, link_freq, lane_mask); } =20 /* * csiphy_stream_off - Disable streaming on CSIPHY module * @csiphy: CSIPHY device * * Helper function to disable streaming on CSIPHY module */ diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.h b/drivers/med= ia/platform/qcom/camss/camss-csiphy.h index 2ebb307be18ba..42f0134635316 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy.h +++ b/drivers/media/platform/qcom/camss/camss-csiphy.h @@ -70,19 +70,19 @@ struct csiphy_hw_ops { * @lane_cfg - CSI2 lane configuration * * Return lane mask */ u8 (*get_lane_mask)(struct csiphy_lanes_cfg *lane_cfg); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260531-qcom-cphy-v5-3-6be0f62b4d65@ixit.cz> References: <20260531-qcom-cphy-v5-0-6be0f62b4d65@ixit.cz> In-Reply-To: <20260531-qcom-cphy-v5-0-6be0f62b4d65@ixit.cz> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Luca Weiss , Petr Hodina , Casey Connolly , "Dr. Git" , Cory Keitz , Loic Poulain Cc: Konrad Dybcio , Joel Selvaraj , Kieran Bingham , Sakari Ailus , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=3063; i=david@ixit.cz; h=from:subject:message-id; bh=S/NCEpJ9Qg9rdkYHEby0/Ggz1JWYH66XExTkL5xCQFM=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBqHDK6kmjsncTUzeO54xthml2IZ3U2SQw3iaus6 QSkGp0N+cWJAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCahwyugAKCRBgAj/E00kg cqmGEAChdf28mfhJCEHaxSqPEAwexYTrK/Ebkt0A7/hrBavJYvh+4G+6tEliJunghAi03i25tiB WGxu8Efa6Hkej9Cr94uoVOSbDRnVy7DaNR4BJh983oT9qspzEXHCZMgbH29Bn/ZUzUnGbk+IGdm Xt9Iv7u3KbgAqY1hzGrQE2voUSz8DSYtXaj2cli7da037gu5wtgQIifYR/ENBhF+B8uREdMp1ws HeTO8OWq/bkp8nly2sXd/LgmLux4OehiKMpLfFHYxt+hsozinXHaIBziTq6MYRWBxysrUpbDiWq WxpaWZycifJin2QanBEjCTx3UON4+KUXB5afxqbetqcVdtbvyAjnryXM8topDvQyJEhkqOgdcMt WjX2mpo65N1c+zsPQG1b4khb+pd4ToaUNff7rpsR4K4p7eGli61KDeo0T/JjteILQo/1XIR9pRa nE4mPjj328P7CkjrkrRfRga7dopVl+5gkwUVZDkm4jNUKFrb8tsVq485e+AQePnxU8wk56EqxIg MJoj1jOmnR2sJkuAmO+pD+tokOfQkQIvs8p5Uyi3LT9GCn752sBvhpiTYQKURuS6KiiKobc/m5m oPX3mqnz+agBeA2eUOPJfsgG9VIOdfhbPw1K76DrCeeToJUtc8HHEx06DrYmbw/zevhXh4DSbDq iEQT0p3uQyFJEZg== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg Inherit C-PHY information from CSIPHY, so we can configure CSID properly. CSI2_RX_CFG0_PHY_TYPE_SEL must be set to 1, when C-PHY mode is used. Reviewed-by: Bryan O'Donoghue Acked-by: Cory Keitz Signed-off-by: David Heidelberg --- drivers/media/platform/qcom/camss/camss-csid-gen2.c | 1 + drivers/media/platform/qcom/camss/camss-csid.c | 1 + drivers/media/platform/qcom/camss/camss-csid.h | 1 + 3 files changed, 3 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen2.c b/drivers/= media/platform/qcom/camss/camss-csid-gen2.c index eadcb2f7e3aaa..52ef730b10553 100644 --- a/drivers/media/platform/qcom/camss/camss-csid-gen2.c +++ b/drivers/media/platform/qcom/camss/camss-csid-gen2.c @@ -178,16 +178,17 @@ static void __csid_configure_rx(struct csid_device *c= sid, int val; =20 if (!lane_cnt) lane_cnt =3D 4; =20 val =3D (lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES; val |=3D phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL; val |=3D phy->csiphy_id << CSI2_RX_CFG0_PHY_NUM_SEL; + val |=3D csid->phy.cphy << CSI2_RX_CFG0_PHY_TYPE_SEL; writel_relaxed(val, csid->base + CSID_CSI2_RX_CFG0); =20 val =3D 1 << CSI2_RX_CFG1_PACKET_ECC_CORRECTION_EN; if (vc > 3) val |=3D 1 << CSI2_RX_CFG1_VC_MODE; val |=3D 1 << CSI2_RX_CFG1_MISR_EN; writel_relaxed(val, csid->base + CSID_CSI2_RX_CFG1); } diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media= /platform/qcom/camss/camss-csid.c index 48459b46a981b..8d5c872f84ed5 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.c +++ b/drivers/media/platform/qcom/camss/camss-csid.c @@ -1286,16 +1286,17 @@ static int csid_link_setup(struct media_entity *ent= ity, /* do no allow a link from CSIPHY to CSID */ if (!csiphy->cfg.csi2) return -EPERM; =20 csid->phy.csiphy_id =3D csiphy->id; =20 lane_cfg =3D &csiphy->cfg.csi2->lane_cfg; csid->phy.lane_cnt =3D lane_cfg->num_data; + csid->phy.cphy =3D (lane_cfg->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY); csid->phy.lane_assign =3D csid_get_lane_assign(lane_cfg, lane_cfg->num_= data); csid->tpg_linked =3D false; } } /* Decide which virtual channels to enable based on which source pads are= enabled */ if (local->flags & MEDIA_PAD_FL_SOURCE) { struct v4l2_subdev *sd =3D media_entity_to_v4l2_subdev(entity); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260531-qcom-cphy-v5-4-6be0f62b4d65@ixit.cz> References: <20260531-qcom-cphy-v5-0-6be0f62b4d65@ixit.cz> In-Reply-To: <20260531-qcom-cphy-v5-0-6be0f62b4d65@ixit.cz> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Luca Weiss , Petr Hodina , Casey Connolly , "Dr. Git" , Cory Keitz , Loic Poulain Cc: Konrad Dybcio , Joel Selvaraj , Kieran Bingham , Sakari Ailus , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=5950; i=david@ixit.cz; h=from:subject:message-id; bh=dWOt5dZdmn593tye85C2/K4nGj/PKk/cJpue2OmW62I=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBqHDK6Fksemqu0EcgXqA2yZFBAkKkR8QedjRCQV t/wvPhPSF6JAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCahwyugAKCRBgAj/E00kg cr2hD/9uz2KhHVk7XvMkm8LPSzWoiyfrony7/e1Qc9dtiudlrMu/7VE3mnBNJS/d0f38zGyimf4 CUFOO+GXhv0HkSgnu7FDgHb21t688y5V/V114lrMAtwMkrqMfAwNdDT5FIzwVTdVjdIpJPo6rmc i3T3+cOlU34hjWMIeo6EeNw3380S6HqLJEMCNXIliU5wIxz9PQlyh5NaerLgUG/vHymgSD2EzJq GRTgwZ4dMenul4ELPhseF8JK0owvSPav4ZGzY/9fD6ldHdbCKEHQKc0oFtrnHgYJfYF9HJZOKYz JfUzL/fyuRnXJNFUT9Tn94QSmCmI0WKJpl/lN9rf1t+GhfBBpZcidOH47EgXb3Dy9klBBrxQtAC fqFhFr6uitE6OD3vS2HYwZizWo1ekIHJIf6MN8E91tHGl/C1kvc6SeBOhd6VMOFQYD7FuHqbwDs L8FeZir0utKnatTbb6HS/hHhYqEnFZrZTnqDh/+221NmpFSFZTQMxx+wRRPiI8SmsoMUamf81LG NBCEi5dSpL64rIx1fzRtS5ndYMYQJjYczXBdsV1zuP4Ab+xBJRwhwDTFqxpKny9+G9mcmUlpwPI lr7Q/arfCwvARaQhqGZwurXuMqka2TD/JN4Ltc4hsiMCeikQCldROsx/UinhmgFcSr2W7883+NB Yc66quhVvHJcePg== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg The lanes must not be initialized before the driver has access to the lane configuration, as it depends on whether D-PHY or C-PHY mode is in use. Move the lane initialization to csiphy_lanes_enable which is called when the configuration structures are available. Co-developed-by: Petr Hodina Signed-off-by: Petr Hodina Signed-off-by: David Heidelberg --- .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 133 +++++++++++++++--= ---- 1 file changed, 95 insertions(+), 38 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/dri= vers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index d4624417a7424..8bcba6107471f 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -1164,16 +1164,110 @@ static int csiphy_lanes_enable(struct csiphy_devic= e *csiphy, { struct device *dev =3D csiphy->camss->dev; struct csiphy_lanes_cfg *c =3D &cfg->csi2->lane_cfg; struct csiphy_device_regs *regs =3D csiphy->regs; u8 settle_cnt; u8 val; int i; =20 + switch (csiphy->camss->res->version) { + case CAMSS_845: + if (c->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY) { + regs->lane_regs =3D NULL; + regs->lane_array_size =3D 0; + } else { + regs->lane_regs =3D &lane_regs_sdm845[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sdm845); + } + break; + case CAMSS_2290: + case CAMSS_6150: + if (c->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY) { + regs->lane_regs =3D NULL; + regs->lane_array_size =3D 0; + } else { + regs->lane_regs =3D &lane_regs_qcm2290[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_qcm2290); + } + break; + case CAMSS_6350: + if (c->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY) { + regs->lane_regs =3D NULL; + regs->lane_array_size =3D 0; + } else { + regs->lane_regs =3D &lane_regs_sm6350[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm6350); + } + break; + case CAMSS_7280: + case CAMSS_8250: + if (c->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY) { + regs->lane_regs =3D NULL; + regs->lane_array_size =3D 0; + } else { + regs->lane_regs =3D &lane_regs_sm8250[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm8250); + } + break; + case CAMSS_8280XP: + if (c->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY) { + regs->lane_regs =3D NULL; + regs->lane_array_size =3D 0; + } else { + regs->lane_regs =3D &lane_regs_sc8280xp[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sc8280xp); + } + break; + case CAMSS_X1E80100: + if (c->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY) { + regs->lane_regs =3D NULL; + regs->lane_array_size =3D 0; + } else { + regs->lane_regs =3D &lane_regs_x1e80100[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_x1e80100); + } + break; + case CAMSS_8550: + if (c->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY) { + regs->lane_regs =3D NULL; + regs->lane_array_size =3D 0; + } else { + regs->lane_regs =3D &lane_regs_sm8550[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm8550); + } + break; + case CAMSS_8650: + if (c->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY) { + regs->lane_regs =3D NULL; + regs->lane_array_size =3D 0; + } else { + regs->lane_regs =3D &lane_regs_sm8650[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm8650); + } + break; + case CAMSS_8300: + case CAMSS_8775P: + if (c->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY) { + regs->lane_regs =3D NULL; + regs->lane_array_size =3D 0; + } else { + regs->lane_regs =3D &lane_regs_sa8775p[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sa8775p); + } + break; + default: + break; + } + + if (!regs->lane_regs && c->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY) { + dev_err(dev, "Missing lane_regs definition for C-PHY\n"); + return -EINVAL; + } + settle_cnt =3D csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate); =20 val =3D 0; =20 switch (c->phy_cfg) { case V4L2_MBUS_CSI2_CPHY: for (i =3D 0; i < c->num_data; i++) val |=3D BIT((c->data[i].pos * 2) + 1); @@ -1235,63 +1329,26 @@ static int csiphy_init(struct csiphy_device *csiphy) struct device *dev =3D csiphy->camss->dev; struct csiphy_device_regs *regs; =20 regs =3D devm_kmalloc(dev, sizeof(*regs), GFP_KERNEL); if (!regs) return -ENOMEM; =20 csiphy->regs =3D regs; - regs->offset =3D 0x800; regs->common_status_offset =3D 0xb0; =20 switch (csiphy->camss->res->version) { - case CAMSS_845: - regs->lane_regs =3D &lane_regs_sdm845[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sdm845); - break; - case CAMSS_2290: - case CAMSS_6150: - regs->lane_regs =3D &lane_regs_qcm2290[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_qcm2290); - break; - case CAMSS_6350: - regs->lane_regs =3D &lane_regs_sm6350[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm6350); - break; - case CAMSS_7280: - case CAMSS_8250: - regs->lane_regs =3D &lane_regs_sm8250[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm8250); - break; - case CAMSS_8280XP: - regs->lane_regs =3D &lane_regs_sc8280xp[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sc8280xp); - break; case CAMSS_X1E80100: - regs->lane_regs =3D &lane_regs_x1e80100[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_x1e80100); - regs->offset =3D 0x1000; - break; case CAMSS_8550: - regs->lane_regs =3D &lane_regs_sm8550[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm8550); - regs->offset =3D 0x1000; - break; case CAMSS_8650: - regs->lane_regs =3D &lane_regs_sm8650[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm8650); regs->offset =3D 0x1000; break; - case CAMSS_8300: - case CAMSS_8775P: - regs->lane_regs =3D &lane_regs_sa8775p[0]; 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Sun, 31 May 2026 13:08:12 +0000 (UTC) From: David Heidelberg via B4 Relay Date: Sun, 31 May 2026 15:08:13 +0200 Subject: [PATCH WIP v5 5/9] media: qcom: camss: csiphy-3ph: Add Gen2 v1.1 MIPI CSI-2 C-PHY init Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260531-qcom-cphy-v5-5-6be0f62b4d65@ixit.cz> References: <20260531-qcom-cphy-v5-0-6be0f62b4d65@ixit.cz> In-Reply-To: <20260531-qcom-cphy-v5-0-6be0f62b4d65@ixit.cz> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Luca Weiss , Petr Hodina , Casey Connolly , "Dr. Git" , Cory Keitz , Loic Poulain Cc: Konrad Dybcio , Joel Selvaraj , Kieran Bingham , Sakari Ailus , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: Casey Connolly Add a PHY configuration sequence for the sdm845 which uses a Qualcomm Gen 2 version 1.1 CSI-2 PHY. The PHY can be configured as two phase or three phase in C-PHY or D-PHY mode. This configuration supports three-phase C-PHY mode. Signed-off-by: Casey Connolly Acked-by: Cory Keitz Reviewed-by: Vladimir Zapolskiy Reviewed-by: Bryan O'Donoghue Co-developed-by: David Heidelberg Signed-off-by: David Heidelberg --- .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 70 ++++++++++++++++++= +++- 1 file changed, 68 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/dri= vers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index 8bcba6107471f..d837fcf7cd2f0 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -141,16 +141,17 @@ csiphy_lane_regs lane_regs_sa8775p[] =3D { {0x0460, 0xFD, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0464, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x065C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0660, 0xFD, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, }; =20 /* GEN2 1.0 2PH */ +/* 5 entries: clock + 4 lanes */ static const struct csiphy_lane_regs lane_regs_sdm845[] =3D { {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS}, @@ -215,16 +216,81 @@ csiphy_lane_regs lane_regs_sdm845[] =3D { {0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, {0x060C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0660, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, }; =20 +/* GEN2 1.0 3PH */ +/* 3 entries: 3 lanes (C-PHY) */ +static const struct +csiphy_lane_regs lane_regs_sdm845_3ph[] =3D { + {0x015c, 0x43, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0168, 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x016c, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0104, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x010c, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0108, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0114, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0150, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0118, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x011c, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0120, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0124, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0128, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x012c, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0144, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0160, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x01cc, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0164, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x01dc, 0x51, 0x00, CSIPHY_DEFAULT_PARAMS}, + + {0x035c, 0x43, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0368, 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x036c, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0304, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x030c, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0308, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0314, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0350, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0318, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x031c, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0320, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0324, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0328, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x032c, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0344, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0360, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x03cc, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0364, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x03dc, 0x51, 0x00, CSIPHY_DEFAULT_PARAMS}, + + {0x055c, 0x43, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0568, 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x056c, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0504, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x050c, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0508, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0514, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0550, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0518, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x051c, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0520, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0524, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0528, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x052c, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0544, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0560, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x05cc, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0564, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x05dc, 0x51, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + /* GEN2 1.1 2PH */ static const struct csiphy_lane_regs lane_regs_sc8280xp[] =3D { {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -1167,18 +1233,18 @@ static int csiphy_lanes_enable(struct csiphy_device= *csiphy, struct csiphy_device_regs *regs =3D csiphy->regs; u8 settle_cnt; u8 val; int i; =20 switch (csiphy->camss->res->version) { case CAMSS_845: if (c->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY) { - regs->lane_regs =3D NULL; - regs->lane_array_size =3D 0; + regs->lane_regs =3D &lane_regs_sdm845_3ph[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sdm845_3ph); } else { regs->lane_regs =3D &lane_regs_sdm845[0]; regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sdm845); } break; case CAMSS_2290: case CAMSS_6150: if (c->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY) { --=20 2.53.0 From nobody Mon Jun 8 08:30:46 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68E873859DF; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260531-qcom-cphy-v5-6-6be0f62b4d65@ixit.cz> References: <20260531-qcom-cphy-v5-0-6be0f62b4d65@ixit.cz> In-Reply-To: <20260531-qcom-cphy-v5-0-6be0f62b4d65@ixit.cz> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Luca Weiss , Petr Hodina , Casey Connolly , "Dr. Git" , Cory Keitz , Loic Poulain Cc: Konrad Dybcio , Joel Selvaraj , Kieran Bingham , Sakari Ailus , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=3860; i=david@ixit.cz; h=from:subject:message-id; bh=0qnzO19xgIcmqRH00F7JZkTLiVzhMJPwNn5Ze/smDMg=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBqHDK6Aocv0y3fmQKDsNuU7KhsS73Z27PMgXREc bZnIQfthTGJAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCahwyugAKCRBgAj/E00kg cqS1D/9wia8qwdNFo+dAuRruNuNxrNdaH94pjH//ZQiGd3m/fS8pMIgDvMlBidzHKoJ4Vy3OjkK pPxkvK2UE4y9Wsw8LxBnopM8jFHHoBOc6c9i+5uICvkZ9hrgeS0V1Y7YFTEJFk4P0bpfnu1rrUH IK0srEazKnxySZrsGAJIr8AN4Qv6J+19JZVq9dhRdckTMMiGrfRggtpaWE61irijR27WON/lvEg DkXlXCmIHmONxwSp0yLJz4Wd45EYnrMzeiIa8yrO5y3TF6EO5SQp7ztwH1tcP8ocS9S1KgkIqFd TVv8YdTkK8lutC6FY7pw34TLcDqe7PJJZn2fN+ohlnhDY6Mf+zmX0b2LukWUQRIXC/yC5p4czCf o2zvBgX2I99KUOhyeyRj1HALVQ7FalrU+xTMJ+sxoBetfuKyoH7YC+I11hLGVsRPN6nmN/gfqoI zpsvJo98m4kaHVQ6IhPqMzjK+etYgnffmPPC0WI55VaV6hwXAnpiL2K07IfW5OWzdWGMcKR5wHY v81GXW/H4yLSvE067fvBT2Dy7hxpkFhDG7gTyNjjEdV61lK2xUhH9zFG1pZ51erq8vjRhw6c1Ue z2xpgzDZEWgR8eqCS1UYD/6jUoyZ9sNVKrcWUqnFopNp14GbdhW2qTf8YbnXjCWso4TuP44rIKc QKRJaYuu3ltIslg== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg These values should improve C-PHY behaviour. Should match most recent Qualcomm code. Acked-by: Cory Keitz Suggested-by: Konrad Dybcio Signed-off-by: David Heidelberg --- .../media/platform/qcom/camss/camss-csiphy-3ph-1-0.c | 18 +++++++++-----= ---- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/dri= vers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index d837fcf7cd2f0..9a0f009c033bb 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -220,19 +220,19 @@ csiphy_lane_regs lane_regs_sdm845[] =3D { {0x0660, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, }; =20 /* GEN2 1.0 3PH */ /* 3 entries: 3 lanes (C-PHY) */ static const struct csiphy_lane_regs lane_regs_sdm845_3ph[] =3D { - {0x015c, 0x43, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0168, 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x016c, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x015c, 0x63, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0168, 0xac, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x016c, 0xa5, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0104, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x010c, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, {0x0108, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, {0x0114, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0150, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0118, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x011c, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0120, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -240,19 +240,19 @@ csiphy_lane_regs lane_regs_sdm845_3ph[] =3D { {0x0128, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x012c, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0144, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0160, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x01cc, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0164, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x01dc, 0x51, 0x00, CSIPHY_DEFAULT_PARAMS}, =20 - {0x035c, 0x43, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0368, 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x036c, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x035c, 0x63, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0368, 0xac, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x036c, 0xa5, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0304, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x030c, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, {0x0308, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, {0x0314, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0350, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0318, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x031c, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0320, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -260,19 +260,19 @@ csiphy_lane_regs lane_regs_sdm845_3ph[] =3D { {0x0328, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x032c, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0344, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0360, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x03cc, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0364, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x03dc, 0x51, 0x00, CSIPHY_DEFAULT_PARAMS}, =20 - {0x055c, 0x43, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0568, 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x056c, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x055c, 0x63, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0568, 0xac, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x056c, 0xa5, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0504, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x050c, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, {0x0508, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, {0x0514, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0550, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0518, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x051c, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0520, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, --=20 2.53.0 From nobody Mon Jun 8 08:30:46 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 67463382F01; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260531-qcom-cphy-v5-7-6be0f62b4d65@ixit.cz> References: <20260531-qcom-cphy-v5-0-6be0f62b4d65@ixit.cz> In-Reply-To: <20260531-qcom-cphy-v5-0-6be0f62b4d65@ixit.cz> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Luca Weiss , Petr Hodina , Casey Connolly , "Dr. Git" , Cory Keitz , Loic Poulain Cc: Konrad Dybcio , Joel Selvaraj , Kieran Bingham , Sakari Ailus , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=7307; i=david@ixit.cz; h=from:subject:message-id; bh=jjaD19AveXiWEpDTFtLOGJEDdbec9HAdKlKWc98YVL4=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBqHDK6M0V6RjsfWzJ/M8nlehadYbXDH4ailnyhF CA77q33R1GJAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCahwyugAKCRBgAj/E00kg cvNFD/99AEtQIbYGC/9uFzbZ6UqZt18bKv5efOr1y64iAaCxSYoJGoUuz/P8lwnzjkxYe94KXMV Ca3f3vEQRGup3XlXQZcU8cSwwwwwx+kG4gnzV6DRmwrnuAop9qaV1ZRXUbmQu8wkFi/80DNEdRE eFCNe8LchHEkH/DhYub65S0YDuRtgs+kjGJ3B4uET3dvsNWY18q5nPKjxvU/PdkONOmkJlGRfeU v01YtexVjCs7IMlzPv5ezUuKn8+tBQBSaNTCIVW4TLul4L0OvZ9xXg7MyWu1PfqsaYS6+9UAi5X Dc9TvDIpscNxgwWF8MiMe0bOPZFA9OqL9ZqllHClethxrEKxKiLHu69LGgYh35YC+2HhXBlOG7t ZOpcslYNMI11Lj5SyCEclgFUYtOXtL7DMgy4qGu0JDeIPBQ/4Lq07SWCLEAybjFuUo0A9prFPIJ Gya/8RcR3ed1CPWhaCnoDD7mytOYLie6S8AgBIKE1Nr7fTDFxOyPtLTUVFHa0J/M8JOcTnAqGKi mb8JsrOvndalqiBooJIpjbGNwSxy5Xk08zkxdHIXRRhg3zvnNpwdLJckhmC3hKDctC+m9vHcJYo x9z6bw+1MvdbmapXCTrZw5XXaTsQw01AHgzPEBFo3+C0W69KtAM8/FxN/xREXIesJrxjn0po+Ol izZCktS34ZqekpQ== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: Luca Weiss Add a PHY configuration sequence for the sm8250 which uses a Qualcomm Gen 2 version 1.2.1 CSI-2 PHY. The PHY can be configured as two phase or three phase in C-PHY or D-PHY mode. This configuration supports three-phase C-PHY mode. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Reviewed-by: Bryan O'Donoghue Acked-by: Cory Keitz Signed-off-by: David Heidelberg --- .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 111 +++++++++++++++++= +++- 1 file changed, 109 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/dri= vers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index 9a0f009c033bb..081060026975c 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -665,16 +665,123 @@ csiphy_lane_regs lane_regs_qcm2290[] =3D { {0x0608, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, {0x060C, 0xff, 0x00, CSIPHY_DNP_PARAMS}, {0x0610, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0638, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0660, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0664, 0x3f, 0x00, CSIPHY_DEFAULT_PARAMS}, }; =20 +/* GEN2 1.2.1 3PH */ +/* 3 entries: 3 lanes (C-PHY) */ +static const struct +csiphy_lane_regs lane_regs_sm8250_3ph[] =3D { + {0x0990, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0994, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0998, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0990, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0994, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0998, 0x1a, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x098c, 0xaf, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x015c, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0168, 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0104, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x010c, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0108, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0114, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0150, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0188, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x018c, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0190, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0118, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x011c, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0120, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0124, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0128, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x012c, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0160, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x01cc, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x01dc, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0984, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0988, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0980, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x09ac, 0x35, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x09b0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x0e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + + {0x0a90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0a94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0a98, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0a90, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0a94, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0a98, 0x1a, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0a8c, 0xaf, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x035c, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0368, 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0304, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x030c, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0308, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0314, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0350, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0388, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x038c, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0390, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0318, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x031c, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0320, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0324, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0328, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x032c, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0360, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x03cc, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x03dc, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0a84, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0a88, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0a80, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0aac, 0x35, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0ab0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x0e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + + {0x0b90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0b94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0b98, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0b90, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0b94, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0b98, 0x1a, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0b8c, 0xaf, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x055c, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0568, 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0504, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x050c, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0508, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0514, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0550, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0588, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x058c, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0590, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0518, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x051c, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0520, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0524, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0528, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x052c, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0560, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x05cc, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x05dc, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0b84, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0b88, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0b80, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0bac, 0x35, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0bb0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x0e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + /* GEN2 2.1.2 2PH DPHY mode */ static const struct csiphy_lane_regs lane_regs_sm8550[] =3D { {0x0E90, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0E98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0E94, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS}, {0x00A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0090, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -1262,18 +1369,18 @@ static int csiphy_lanes_enable(struct csiphy_device= *csiphy, } else { regs->lane_regs =3D &lane_regs_sm6350[0]; regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm6350); } break; case CAMSS_7280: case CAMSS_8250: if (c->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY) { - regs->lane_regs =3D NULL; - regs->lane_array_size =3D 0; + regs->lane_regs =3D &lane_regs_sm8250_3ph[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm8250_3ph); } else { regs->lane_regs =3D &lane_regs_sm8250[0]; regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm8250); } break; case CAMSS_8280XP: if (c->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY) { regs->lane_regs =3D NULL; --=20 2.53.0 From nobody Mon Jun 8 08:30:46 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client 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smtp.lore.kernel.org (Postfix) with ESMTP id 19546CD6E5D; Sun, 31 May 2026 13:08:13 +0000 (UTC) From: David Heidelberg via B4 Relay Date: Sun, 31 May 2026 15:08:16 +0200 Subject: [PATCH WIP v5 8/9] media: qcom: camss: Account for C-PHY when calculating link frequency Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260531-qcom-cphy-v5-8-6be0f62b4d65@ixit.cz> References: <20260531-qcom-cphy-v5-0-6be0f62b4d65@ixit.cz> In-Reply-To: <20260531-qcom-cphy-v5-0-6be0f62b4d65@ixit.cz> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Luca Weiss , Petr Hodina , Casey Connolly , "Dr. Git" , Cory Keitz , Loic Poulain Cc: Konrad Dybcio , Joel Selvaraj , Kieran Bingham , Sakari Ailus , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=7513; i=david@ixit.cz; h=from:subject:message-id; bh=VfLsah7RMKW8BXaupqjSf+xkoWPRRbvrrl6O72OO1HM=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBqHDK6CYOhkdRZEuqsnJmobHtNhM6tSuROXOEVK ow8GWYfRrSJAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCahwyugAKCRBgAj/E00kg cnUhEADLWZtMQh8OQun0BUQdi9l5YUZAQEkd8tOG5700/WCi2knrXCTHlef+7VA62eEPAmTMdAk hVbCxMqnydQLh+i9QW0VfIHBElMImnJwX4dF43NXlPUtWNI8L2J/h1fKah3rsd02YpX/5NN//PX XLqpOgJZkipqf5STy4zYPEEV0rUPU5Yclj5yt3J+6Z+WqnhcCRxMDKF8bS4M3Bx7fWUFsSg8aj5 dojmtK4Sz1u7jy7tWl1dWNdWaMt3odl7cBb3xx59AE1DfHKdkAtL4E/xmJVl/hTlLCXbA+FC4cM pDLMpELengdxCb2jZtaK/1HCv+CyHyXsTPY74E3bVGxcC67NikzSphWkoHx1LJjPFdqWCs76h24 Iy1lNShBY+w7qfn5QoQRgWke62HIj+uvwySSV1dcUd+UwkfWrGyoWnrIovb8GY8Nm8qi67C3MZ2 QYhW4Sr00hQ4OknACDVbEACMsNe26FgysJeve44opW64My/lewCBKIDZE4VdKYvKbXAkM9eqZAJ WWK4WZgS6buzfFmRTD7S7rPqJ4xFQipIItSym2Vrx0wekBoR516hCdtcw895Gw0m8OOY917FjB1 2xwPy4MQTDbInsZSIarJ4cbbn6clpiAWGLqbnsC/WDjhkOWZ/cdsDGHI4jSOl5gUIFpKuUyD2im TrJabUFRYawC/bQ== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg Ensure that the link frequency divider correctly accounts for C-PHY operation. The divider differs between D-PHY and C-PHY, as described in the MIPI CSI-2 specification. For more details, see: https://docs.kernel.org/driver-api/media/tx-rx.html#pixel-rate Suggested-by: Sakari Ailus Acked-by: Cory Keitz Tested-by: Cory Keitz Reviewed-by: Bryan O'Donoghue Signed-off-by: David Heidelberg --- drivers/media/platform/qcom/camss/camss-csid.c | 7 +++++-- drivers/media/platform/qcom/camss/camss-csiphy.c | 6 ++---- drivers/media/platform/qcom/camss/camss.c | 18 +++++++++++++++--- drivers/media/platform/qcom/camss/camss.h | 2 +- 4 files changed, 23 insertions(+), 10 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media= /platform/qcom/camss/camss-csid.c index 8d5c872f84ed5..594f280a455ed 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.c +++ b/drivers/media/platform/qcom/camss/camss-csid.c @@ -534,25 +534,28 @@ const struct csid_format_info *csid_get_fmt_entry(con= st struct csid_format_info =20 /* * csid_set_clock_rates - Calculate and set clock rates on CSID module * @csiphy: CSID device */ static int csid_set_clock_rates(struct csid_device *csid) { struct device *dev =3D csid->camss->dev; + struct csiphy_device *csiphy =3D &csid->camss->csiphy[csid->phy.csiphy_id= ]; + struct csiphy_lanes_cfg *lane_cfg =3D &csiphy->cfg.csi2->lane_cfg; const struct csid_format_info *fmt; + s64 link_freq; int i, j; int ret; =20 fmt =3D csid_get_fmt_entry(csid->res->formats->formats, csid->res->format= s->nformats, csid->fmt[MSM_CSIPHY_PAD_SINK].code); - link_freq =3D camss_get_link_freq(&csid->subdev.entity, fmt->bpp, - csid->phy.lane_cnt); + + link_freq =3D camss_get_link_freq(&csid->subdev.entity, fmt->bpp, lane_cf= g); if (link_freq < 0) link_freq =3D 0; =20 for (i =3D 0; i < csid->nclocks; i++) { struct camss_clock *clock =3D &csid->clock[i]; =20 if (!strcmp(clock->name, "csi0") || !strcmp(clock->name, "csi1") || diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.c b/drivers/med= ia/platform/qcom/camss/camss-csiphy.c index ec0dc9d31b585..cd16743858d6a 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy.c @@ -138,19 +138,18 @@ static int csiphy_set_clock_rates(struct csiphy_devic= e *csiphy) { struct device *dev =3D csiphy->camss->dev; s64 link_freq; int i, j; int ret; =20 u8 bpp =3D csiphy_get_bpp(csiphy->res->formats->formats, csiphy->res->for= mats->nformats, csiphy->fmt[MSM_CSIPHY_PAD_SINK].code); - u8 num_lanes =3D csiphy->cfg.csi2->lane_cfg.num_data; =20 - link_freq =3D camss_get_link_freq(&csiphy->subdev.entity, bpp, num_lanes); + link_freq =3D camss_get_link_freq(&csiphy->subdev.entity, bpp, &csiphy->c= fg.csi2->lane_cfg); if (link_freq < 0) link_freq =3D 0; =20 for (i =3D 0; i < csiphy->nclocks; i++) { struct camss_clock *clock =3D &csiphy->clock[i]; =20 if (csiphy->rate_set[i]) { u64 min_rate =3D link_freq / 4; @@ -265,20 +264,19 @@ static int csiphy_set_power(struct v4l2_subdev *sd, i= nt on) static int csiphy_stream_on(struct csiphy_device *csiphy) { struct csiphy_config *cfg =3D &csiphy->cfg; const struct csiphy_hw_ops *ops =3D csiphy->res->hw_ops; s64 link_freq; u8 lane_mask =3D csiphy->res->hw_ops->get_lane_mask(&cfg->csi2->lane_cfg); u8 bpp =3D csiphy_get_bpp(csiphy->res->formats->formats, csiphy->res->for= mats->nformats, csiphy->fmt[MSM_CSIPHY_PAD_SINK].code); - u8 num_lanes =3D csiphy->cfg.csi2->lane_cfg.num_data; u8 val; =20 - link_freq =3D camss_get_link_freq(&csiphy->subdev.entity, bpp, num_lanes); + link_freq =3D camss_get_link_freq(&csiphy->subdev.entity, bpp, &csiphy->c= fg.csi2->lane_cfg); =20 if (link_freq < 0) { dev_err(csiphy->camss->dev, "Cannot get CSI2 transmitter's link frequency\n"); return -EINVAL; } =20 if (csiphy->base_clk_mux) { diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index 072c428e25166..db4e14a84a95f 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -27,16 +27,24 @@ #include #include =20 #include "camss.h" =20 #define CAMSS_CLOCK_MARGIN_NUMERATOR 105 #define CAMSS_CLOCK_MARGIN_DENOMINATOR 100 =20 +/* + * C-PHY encodes data by 16/7 ~ 2.28 bits/symbol + * D-PHY doesn't encode data, thus 16/16 =3D 1 b/s + */ +#define CAMSS_COMMON_PHY_DIVIDENT 16 +#define CAMSS_CPHY_DIVISOR 7 +#define CAMSS_DPHY_DIVISOR 16 + static const struct parent_dev_ops vfe_parent_dev_ops; =20 static const struct camss_subdev_resources csiphy_res_8x16[] =3D { /* CSIPHY0 */ { .regulators =3D {}, .clock =3D { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer" }, .clock_rate =3D { { 0 }, @@ -4618,30 +4626,34 @@ struct media_pad *camss_find_sensor_pad(struct medi= a_entity *entity) return pad; } } =20 /** * camss_get_link_freq - Get link frequency from sensor * @entity: Media entity in the current pipeline * @bpp: Number of bits per pixel for the current format - * @lanes: Number of lanes in the link to the sensor + * @lane_cfg: CSI2 lane configuration * * Return link frequency on success or a negative error code otherwise */ s64 camss_get_link_freq(struct media_entity *entity, unsigned int bpp, - unsigned int lanes) + struct csiphy_lanes_cfg *lane_cfg) { struct media_pad *sensor_pad; + u8 num_lanes =3D lane_cfg->num_data; + bool cphy =3D lane_cfg->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY; + unsigned int div =3D num_lanes * 2 * (cphy ? CAMSS_CPHY_DIVISOR : + CAMSS_DPHY_DIVISOR); =20 sensor_pad =3D camss_find_sensor_pad(entity); if (!sensor_pad) return -ENODEV; =20 - return v4l2_get_link_freq(sensor_pad, bpp, 2 * lanes); + return v4l2_get_link_freq(sensor_pad, CAMSS_COMMON_PHY_DIVIDENT * bpp, di= v); } =20 /* * camss_get_pixel_clock - Get pixel clock rate from sensor * @entity: Media entity in the current pipeline * @pixel_clock: Received pixel clock value * * Return 0 on success or a negative error code otherwise diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/plat= form/qcom/camss/camss.h index 93d691c8ac63b..d65a9b62f7e66 100644 --- a/drivers/media/platform/qcom/camss/camss.h +++ b/drivers/media/platform/qcom/camss/camss.h @@ -164,17 +164,17 @@ struct parent_dev_ops { }; =20 void camss_add_clock_margin(u64 *rate); int camss_enable_clocks(int nclocks, struct camss_clock *clock, struct device *dev); void camss_disable_clocks(int nclocks, struct camss_clock *clock); struct media_pad *camss_find_sensor_pad(struct media_entity *entity); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260531-qcom-cphy-v5-9-6be0f62b4d65@ixit.cz> References: <20260531-qcom-cphy-v5-0-6be0f62b4d65@ixit.cz> In-Reply-To: <20260531-qcom-cphy-v5-0-6be0f62b4d65@ixit.cz> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Luca Weiss , Petr Hodina , Casey Connolly , "Dr. Git" , Cory Keitz , Loic Poulain Cc: Konrad Dybcio , Joel Selvaraj , Kieran Bingham , Sakari Ailus , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1302; i=david@ixit.cz; h=from:subject:message-id; bh=WvoNxYtj1sUqw5yG8DzYK/GGXWIIvs0AM/cwzkoEgMc=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBqHDK7hetDp3vpxAgr4G++P32MskYK9DBrT6G+E ieQj3Kp836JAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCahwyuwAKCRBgAj/E00kg cvLkEACoPbM3rHce6UNhOnbN21d16SIVm2/tEsCQ6HAQSHnk2g4pLTKDTpHx5ADRalvzxRcadQj NnVSG5Q5raIopmCDix57N6IvHIdQABB+1FXb1wW8gn1ud3y9NztmfqkudKK9nJZTYThVyTZeaYP yrQJ4RugQRq+empnvLaYvb+AdU6TmVfZsaHPeNhZWUg5mapcbqKptRGnVNoa7hIc6h5YqsPWbws rJ40CPuQo9F3ZIs83eSquk8JhispxoP21Pv3ZUl2gJOFNIvrBBdBsepKe6JyigBn6xKKGBxSf4T Ht0lA4nIRyW0ek5atq3r0yYZXcxYb8N9EypVM5/a/UU6jQrhDf9QaR8NrNGyZjtvfNiIvuaxI2g hziMF9uC1/6VjZ2lEAQrs3Au89Zi2VvIaImrc1FTGkjbWIn2YajVPH3c+6CK0jTi9Ng45g8qu/l rGd01odrkNhhl0VlknYLKDmb1ogqrOMXyH81DdRPCVHedYh6LepEnpVWPzIbNOm/RUUSNT8PfXQ wASPAwvJv4JHiGmiOSAqVCC3LcuHnfBgR1Konyhec1+i9wMhKA69dkuoh48RmNuzmrxVYuvgN4j DSRRub7fyszqqwf3rPf2QAlYB3aDIWd5ntxHbqMCQ20KjJsbvI/vn9n+IM48cy5Wr96t8gMw30H iCIffkhdq+yxLdA== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg After all the changes done we can now safely enable C-PHY for a SoC where it's available. Acked-by: Cory Keitz Signed-off-by: David Heidelberg Reviewed-by: Bryan O'Donoghue --- drivers/media/platform/qcom/camss/camss.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index db4e14a84a95f..555c53343a1e9 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -4761,21 +4761,21 @@ static int camss_parse_endpoint_node(struct device = *dev, struct v4l2_fwnode_endpoint vep =3D { { 0 } }; unsigned int i; int ret; =20 ret =3D v4l2_fwnode_endpoint_parse(ep, &vep); if (ret) return ret; =20 - /* - * Most SoCs support both D-PHY and C-PHY standards, but currently only - * D-PHY is supported in the driver. - */ - if (vep.bus_type !=3D V4L2_MBUS_CSI2_DPHY) { + switch (vep.bus_type) { + case V4L2_MBUS_CSI2_CPHY: + case V4L2_MBUS_CSI2_DPHY: + break; + default: dev_err(dev, "Unsupported bus type %d\n", vep.bus_type); return -EINVAL; } =20 csd->interface.csiphy_id =3D vep.base.port; =20 mipi_csi2 =3D &vep.bus.mipi_csi2; lncfg->num_data =3D mipi_csi2->num_data_lanes; --=20 2.53.0